diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2015-05-27 18:44:32 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2015-05-27 18:44:32 +0000 |
| commit | 5a5ac124e1efaf208671f01c46edb15f29ed2a0b (patch) | |
| tree | a6140557876943cdd800ee997c9317283394b22c /lib/Target/MSP430/MSP430ISelDAGToDAG.cpp | |
| parent | f03b5bed27d0d2eafd68562ce14f8b5e3f1f0801 (diff) | |
Notes
Diffstat (limited to 'lib/Target/MSP430/MSP430ISelDAGToDAG.cpp')
| -rw-r--r-- | lib/Target/MSP430/MSP430ISelDAGToDAG.cpp | 25 |
1 files changed, 10 insertions, 15 deletions
diff --git a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp index 81c176b8262d5..5ce5013d898c9 100644 --- a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp +++ b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -92,14 +92,9 @@ namespace { /// namespace { class MSP430DAGToDAGISel : public SelectionDAGISel { - const MSP430TargetLowering &Lowering; - const MSP430Subtarget &Subtarget; - public: MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel) - : SelectionDAGISel(TM, OptLevel), - Lowering(*TM.getSubtargetImpl()->getTargetLowering()), - Subtarget(*TM.getSubtargetImpl()) {} + : SelectionDAGISel(TM, OptLevel) {} const char *getPassName() const override { return "MSP430 DAG->DAG Pattern Instruction Selection"; @@ -109,7 +104,7 @@ namespace { bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM); bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM); - bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, + bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) override; // Include the pieces autogenerated from the target description. @@ -279,18 +274,18 @@ bool MSP430DAGToDAGISel::SelectAddr(SDValue N, Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0, 0/*AM.SymbolFlags*/); else - Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i16); + Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(N), MVT::i16); return true; } bool MSP430DAGToDAGISel:: -SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, +SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) { SDValue Op0, Op1; - switch (ConstraintCode) { + switch (ConstraintID) { default: return true; - case 'm': // memory + case InlineAsm::Constraint_m: // memory if (!SelectAddr(Op, Op0, Op1)) return true; break; @@ -406,10 +401,10 @@ SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) { int FI = cast<FrameIndexSDNode>(Node)->getIndex(); SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16); if (Node->hasOneUse()) - return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16, - TFI, CurDAG->getTargetConstant(0, MVT::i16)); - return CurDAG->getMachineNode(MSP430::ADD16ri, dl, MVT::i16, - TFI, CurDAG->getTargetConstant(0, MVT::i16)); + return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16, TFI, + CurDAG->getTargetConstant(0, dl, MVT::i16)); + return CurDAG->getMachineNode(MSP430::ADD16ri, dl, MVT::i16, TFI, + CurDAG->getTargetConstant(0, dl, MVT::i16)); } case ISD::LOAD: if (SDNode *ResNode = SelectIndexedLoad(Node)) |
