diff options
| author | Emmanuel Vadot <manu@FreeBSD.org> | 2018-11-10 20:44:37 +0000 |
|---|---|---|
| committer | Emmanuel Vadot <manu@FreeBSD.org> | 2018-11-10 20:44:37 +0000 |
| commit | 0bf7de3125ed8dcfbeaa112994b25101fa9b96c6 (patch) | |
| tree | ae8484d3cc1ff07575b83cc7a4592c9a33bd1dcc /src/arm/r8a7791.dtsi | |
| parent | c4fc09e238494b428e1e0abfd881425a86d8bfe7 (diff) | |
Notes
Diffstat (limited to 'src/arm/r8a7791.dtsi')
| -rw-r--r-- | src/arm/r8a7791.dtsi | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/src/arm/r8a7791.dtsi b/src/arm/r8a7791.dtsi index 6e1dd7ad7bd64..991ac6feedd5b 100644 --- a/src/arm/r8a7791.dtsi +++ b/src/arm/r8a7791.dtsi @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a7791 SoC * * Copyright (C) 2013-2015 Renesas Electronics Corporation * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/clock/r8a7791-cpg-mssr.h> @@ -78,11 +75,11 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1500000000>; - voltage-tolerance = <1>; /* 1% */ clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; - clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7791_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ /* kHz - uV - OPPs unknown yet */ operating-points = <1500000 1000000>, @@ -101,6 +98,16 @@ clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; power-domains = <&sysc R8A7791_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; }; L2_CA15: cache-controller-0 { |