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authorJohn Baldwin <jhb@FreeBSD.org>2005-12-05 22:09:30 +0000
committerJohn Baldwin <jhb@FreeBSD.org>2005-12-05 22:09:30 +0000
commit5ae84c09e7dffb4ca52406ec1bbe6d98d51a47d2 (patch)
tree0c3d127b2c2dac80169bcb1af8ce629eaa621376 /sys/amd64/isa
parent48c8cbcb8225b03f45ef847a47659e04f6404af7 (diff)
Notes
Diffstat (limited to 'sys/amd64/isa')
-rw-r--r--sys/amd64/isa/atpic.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/sys/amd64/isa/atpic.c b/sys/amd64/isa/atpic.c
index 9cc6969e5b0eb..88d461f4a2d33 100644
--- a/sys/amd64/isa/atpic.c
+++ b/sys/amd64/isa/atpic.c
@@ -453,6 +453,21 @@ atpic_init(void *dummy __unused)
struct atpic_intsrc *ai;
int i;
+ /*
+ * If any of the ISA IRQs have an interrupt source already, then
+ * assume that the APICs are being used and don't register any
+ * of our interrupt sources. This makes sure we don't accidentally
+ * use mixed mode. The "accidental" use could otherwise occur on
+ * machines that route the ACPI SCI interrupt to a different ISA
+ * IRQ (at least one machines routes it to IRQ 13) thus disabling
+ * that APIC ISA routing and allowing the ATPIC source for that IRQ
+ * to leak through. We used to depend on this feature for routing
+ * IRQ0 via mixed mode, but now we don't use mixed mode at all.
+ */
+ for (i = 0; i < NUM_ISA_IRQS; i++)
+ if (intr_lookup_source(i) != NULL)
+ return;
+
/* Loop through all interrupt sources and add them. */
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
if (i == ICU_SLAVEID)