14 files changed, 3273 insertions, 0 deletions

diff --git a/sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m b/sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m
new file mode 100644
index 0000000000000..0ecaba5b19870
--- /dev/null
+++ b/sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m
@@ -0,0 +1,46 @@
+#-
+# Copyright (c) 2016 Landon Fuller <landon@landonf.org>
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# $FreeBSD$
+
+#include <sys/types.h>
+#include <sys/bus.h>
+
+#include <dev/bhnd/bhnd.h>
+#include <dev/bhnd/nvram/bhnd_nvram.h>
+
+INTERFACE bhnd_chipc;
+
+#
+# bhnd(4) ChipCommon interface.
+#
+
+/**
+ * Return the preferred NVRAM data source.
+ *
+ * @param dev A bhnd(4) ChipCommon device.
+ */
+METHOD bhnd_nvram_src_t nvram_src {
+	device_t dev;
+}
\ No newline at end of file
diff --git a/sys/dev/bhnd/cores/chipc/chipc.c b/sys/dev/bhnd/cores/chipc/chipc.c
new file mode 100644
index 0000000000000..f47a8f2bdc755
--- /dev/null
+++ b/sys/dev/bhnd/cores/chipc/chipc.c
@@ -0,0 +1,319 @@
+/*-
+ * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Broadcom ChipCommon driver.
+ * 
+ * With the exception of some very early chipsets, the ChipCommon core
+ * has been included in all HND SoCs and chipsets based on the siba(4) 
+ * and bcma(4) interconnects, providing a common interface to chipset 
+ * identification, bus enumeration, UARTs, clocks, watchdog interrupts, GPIO, 
+ * flash, etc.
+ */
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+#include <sys/systm.h>
+
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/bhnd/bhnd.h>
+
+#include "chipcreg.h"
+#include "chipcvar.h"
+
+devclass_t bhnd_chipc_devclass;	/**< bhnd(4) chipcommon device class */
+
+static const struct resource_spec chipc_rspec[CHIPC_MAX_RSPEC] = {
+	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
+	{ -1, -1, 0 }
+};
+
+/* Supported device identifiers */
+static const struct chipc_device {
+	uint16_t	 device;
+} chipc_devices[] = {
+	{ BHND_COREID_CC },
+	{ BHND_COREID_INVALID }
+};
+
+/* Device quirks table */
+static struct bhnd_device_quirk chipc_quirks[] = {
+	BHND_QUIRK_HWREV_RANGE	(0,	21,	CHIPC_QUIRK_ALWAYS_HAS_SPROM),
+	BHND_QUIRK_HWREV_EQ	(22,		CHIPC_QUIRK_SPROM_CHECK_CST_R22),
+	BHND_QUIRK_HWREV_RANGE	(23,	31,	CHIPC_QUIRK_SPROM_CHECK_CST_R23),
+	BHND_QUIRK_HWREV_GTE	(35,		CHIPC_QUIRK_SUPPORTS_NFLASH),
+	BHND_QUIRK_HWREV_END
+};
+
+/* quirk and capability flag convenience macros */
+#define	CHIPC_QUIRK(_sc, _name)	\
+    ((_sc)->quirks & CHIPC_QUIRK_ ## _name)
+    
+#define CHIPC_CAP(_sc, _name)	\
+    ((_sc)->caps & CHIPC_ ## _name)
+
+#define	CHIPC_ASSERT_QUIRK(_sc, name)	\
+    KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set"))
+
+#define	CHIPC_ASSERT_CAP(_sc, name)	\
+    KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set"))    
+
+static int
+chipc_probe(device_t dev)
+{
+	const struct chipc_device	*id;
+
+	for (id = chipc_devices; id->device != BHND_COREID_INVALID; id++)
+	{
+		if (bhnd_get_vendor(dev) == BHND_MFGID_BCM &&
+		    bhnd_get_device(dev) == id->device)
+		{
+			bhnd_set_generic_core_desc(dev);
+			return (BUS_PROBE_DEFAULT);
+		}
+	}
+
+	return (ENXIO);
+}
+
+static int
+chipc_attach(device_t dev)
+{
+	struct bhnd_device_quirk	*dq;
+	struct chipc_softc		*sc;
+	bhnd_addr_t			 enum_addr;
+	uint32_t			 ccid_reg;
+	uint8_t				 chip_type;
+	int				 error;
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+
+	/* Allocate bus resources */
+	memcpy(sc->rspec, chipc_rspec, sizeof(sc->rspec));
+	if ((error = bhnd_alloc_resources(dev, sc->rspec, sc->res)))
+		return (error);
+
+	sc->core = sc->res[0];
+	
+	/* Fetch our chipset identification data */
+	ccid_reg = bhnd_bus_read_4(sc->core, CHIPC_ID);
+	chip_type = CHIPC_GET_ATTR(ccid_reg, ID_BUS);
+
+	switch (chip_type) {
+	case BHND_CHIPTYPE_SIBA:
+		/* enumeration space starts at the ChipCommon register base. */
+		enum_addr = rman_get_start(sc->core->res);
+		break;
+	case BHND_CHIPTYPE_BCMA:
+	case BHND_CHIPTYPE_BCMA_ALT:
+		enum_addr = bhnd_bus_read_4(sc->core, CHIPC_EROMPTR);
+		break;
+	default:
+		device_printf(dev, "unsupported chip type %hhu\n", chip_type);
+		error = ENODEV;
+		goto cleanup;
+	}
+
+	sc->ccid = bhnd_parse_chipid(ccid_reg, enum_addr);
+
+	/* Fetch capability and status register values */
+	sc->caps = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES);
+	sc->cst = bhnd_bus_read_4(sc->core, CHIPC_CHIPST);
+
+	/* Populate the set of applicable quirk flags */
+	sc->quirks = 0;
+	for (dq = chipc_quirks; dq->quirks != 0; dq++) {
+		if (bhnd_hwrev_matches(bhnd_get_hwrev(dev), &dq->hwrev))
+			sc->quirks |= dq->quirks;
+	};
+
+	// TODO
+	switch (bhnd_chipc_nvram_src(dev)) {
+	case BHND_NVRAM_SRC_CIS:
+		device_printf(dev, "NVRAM source: CIS\n");
+		break;
+	case BHND_NVRAM_SRC_SPROM:
+		device_printf(dev, "NVRAM source: SPROM\n");
+		break;
+	case BHND_NVRAM_SRC_OTP:
+		device_printf(dev, "NVRAM source: OTP\n");
+		break;
+	case BHND_NVRAM_SRC_NFLASH:
+		device_printf(dev, "NVRAM source: NFLASH\n");
+		break;
+	case BHND_NVRAM_SRC_NONE:
+		device_printf(dev, "NVRAM source: NONE\n");
+		break;
+	}
+
+	return (0);
+	
+cleanup:
+	bhnd_release_resources(dev, sc->rspec, sc->res);
+	return (error);
+}
+
+static int
+chipc_detach(device_t dev)
+{
+	struct chipc_softc	*sc;
+
+	sc = device_get_softc(dev);
+	bhnd_release_resources(dev, sc->rspec, sc->res);
+
+	return (0);
+}
+
+static int
+chipc_suspend(device_t dev)
+{
+	return (0);
+}
+
+static int
+chipc_resume(device_t dev)
+{
+	return (0);
+}
+
+/**
+ * Use device-specific ChipStatus flags to determine the preferred NVRAM
+ * data source.
+ */
+static bhnd_nvram_src_t
+chipc_nvram_src_chipst(struct chipc_softc *sc)
+{
+	uint8_t		nvram_sel;
+
+	CHIPC_ASSERT_QUIRK(sc, SPROM_CHECK_CHIPST);
+
+	if (CHIPC_QUIRK(sc, SPROM_CHECK_CST_R22)) {
+		// TODO: On these devices, the official driver code always
+		// assumes SPROM availability if CHIPC_CST_OTP_SEL is not
+		// set; we must review against the actual behavior of our
+		// BCM4312 hardware
+		nvram_sel = CHIPC_GET_ATTR(sc->cst, CST_SPROM_OTP_SEL_R22);
+	} else if (CHIPC_QUIRK(sc, SPROM_CHECK_CST_R23)) {
+		nvram_sel = CHIPC_GET_ATTR(sc->cst, CST_SPROM_OTP_SEL_R23);
+	} else {
+		panic("invalid CST OTP/SPROM chipc quirk flags");
+	}
+	device_printf(sc->dev, "querying chipst for 0x%x, 0x%x\n", sc->ccid.chip_id, sc->cst);
+
+	switch (nvram_sel) {
+	case CHIPC_CST_DEFCIS_SEL:
+		return (BHND_NVRAM_SRC_CIS);
+
+	case CHIPC_CST_SPROM_SEL:
+	case CHIPC_CST_OTP_PWRDN:
+		return (BHND_NVRAM_SRC_SPROM);
+
+	case CHIPC_CST_OTP_SEL:
+		return (BHND_NVRAM_SRC_OTP);
+
+	default:
+		device_printf(sc->dev, "unrecognized OTP/SPROM type 0x%hhx",
+		    nvram_sel);
+		return (BHND_NVRAM_SRC_NONE);
+	}
+}
+
+/**
+ * Determine the preferred NVRAM data source.
+ */
+static bhnd_nvram_src_t
+chipc_nvram_src(device_t dev)
+{
+	struct chipc_softc	*sc;
+	uint32_t		 srom_ctrl;
+
+	sc = device_get_softc(dev);
+
+	/* Very early devices always included a SPROM */
+	if (CHIPC_QUIRK(sc, ALWAYS_HAS_SPROM))
+		return (BHND_NVRAM_SRC_SPROM);
+
+	/* Most other early devices require checking ChipStatus flags */
+	if (CHIPC_QUIRK(sc, SPROM_CHECK_CHIPST))
+		return (chipc_nvram_src_chipst(sc));
+
+	/*
+	 * Later chipset revisions standardized the NVRAM capability flags and
+	 * register interfaces.
+	 * 
+	 * We check for hardware presence in order of precedence. For example,
+	 * SPROM is is always used in preference to internal OTP if found.
+	 */
+	if (CHIPC_CAP(sc, CAP_SPROM)) {
+		srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL);
+		if (srom_ctrl & CHIPC_SRC_PRESENT)
+			return (BHND_NVRAM_SRC_SPROM);
+	}
+
+	/* Check for OTP */
+	if (CHIPC_CAP(sc, CAP_OTP_SIZE))
+		return (BHND_NVRAM_SRC_OTP);
+
+	/*
+	 * Finally, Northstar chipsets (and possibly other chipsets?) support
+	 * external NAND flash. 
+	 */
+	if (CHIPC_QUIRK(sc, SUPPORTS_NFLASH) && CHIPC_CAP(sc, CAP_NFLASH))
+		return (BHND_NVRAM_SRC_NFLASH);
+
+	/* No NVRAM hardware capability declared */
+	return (BHND_NVRAM_SRC_NONE);
+}
+
+static device_method_t chipc_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		chipc_probe),
+	DEVMETHOD(device_attach,	chipc_attach),
+	DEVMETHOD(device_detach,	chipc_detach),
+	DEVMETHOD(device_suspend,	chipc_suspend),
+	DEVMETHOD(device_resume,	chipc_resume),
+	
+	/* ChipCommon interface */
+	DEVMETHOD(bhnd_chipc_nvram_src,	chipc_nvram_src),
+
+	DEVMETHOD_END
+};
+
+DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc));
+DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0);
+MODULE_VERSION(bhnd_chipc, 1);
diff --git a/sys/dev/bhnd/cores/chipc/chipc.h b/sys/dev/bhnd/cores/chipc/chipc.h
new file mode 100644
index 0000000000000..2757f7965c765
--- /dev/null
+++ b/sys/dev/bhnd/cores/chipc/chipc.h
@@ -0,0 +1,51 @@
+/*-
+ * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ * 
+ * $FreeBSD$
+ */
+
+#ifndef _BHND_CORES_CHIPC_CHIPC_H_
+#define _BHND_CORES_CHIPC_CHIPC_H_
+
+#include <dev/bhnd/bhnd.h>
+#include <dev/bhnd/nvram/bhnd_nvram.h>
+
+#include "bhnd_chipc_if.h"
+
+/**
+ * Query a ChipCommon device and return the preferred NVRAM data source.
+ *
+ * @param dev A bhnd(4) ChipCommon device.
+ */
+static inline bhnd_nvram_src_t
+bhnd_chipc_nvram_src(device_t dev)
+{
+	return (BHND_CHIPC_NVRAM_SRC(dev));
+}
+
+#endif /* _BHND_CORES_CHIPC_CHIPC_H_ */
\ No newline at end of file
diff --git a/sys/dev/bhnd/cores/chipc/chipcreg.h b/sys/dev/bhnd/cores/chipc/chipcreg.h
new file mode 100644
index 0000000000000..502468481bf62
--- /dev/null
+++ b/sys/dev/bhnd/cores/chipc/chipcreg.h
@@ -0,0 +1,1395 @@
+/*-
+ * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
+ * Copyright (c) 2010 Broadcom Corporation
+ * All rights reserved.
+ *
+ * This file is derived from the sbchipc.h header distributed with
+ * Broadcom's initial brcm80211 Linux driver release, as
+ * contributed to the Linux staging repository.
+ * 
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _BHND_CORES_CHIPC_CHIPCREG_H_
+#define	_BHND_CORES_CHIPC_CHIPCREG_H_
+
+#define	CHIPC_CHIPID_SIZE	0x100	/**< size of the register block
+					     containing the chip
+					     identification registers. */
+
+/** Evaluates to true if the given ChipCommon core revision provides
+ *  the core count via the chip identification register. */
+#define	CHIPC_NCORES_MIN_HWREV(hwrev)	((hwrev) == 4 || (hwrev) >= 6)
+
+#define	CHIPC_GET_ATTR(_entry, _attr) \
+	((_entry & CHIPC_ ## _attr ## _MASK) >> CHIPC_ ## _attr ## _SHIFT)
+
+#define	CHIPC_ID		0x0
+#define	CHIPC_CAPABILITIES	0x04
+#define	CHIPC_CHIPST		0x2c
+#define	CHIPC_EROMPTR		0xfc		/**< 32-bit EROM base address
+						  *  on BCMA devices */
+
+/** chipid */
+#define	CHIPC_ID		0x0		/**< identification register */
+#define	CHIPC_ID_CHIP_MASK	0x0000FFFF	/**< chip id */
+#define	CHIPC_ID_CHIP_SHIFT	0
+#define	CHIPC_ID_REV_MASK	0x000F0000	/**< chip revision */
+#define	CHIPC_ID_REV_SHIFT	16
+#define	CHIPC_ID_PKG_MASK	0x00F00000	/**< physical package ID */
+#define	CHIPC_ID_PKG_SHIFT	20
+#define	CHIPC_ID_NUMCORE_MASK	0x0F000000	/**< number of cores on chip (rev >= 4) */
+#define	CHIPC_ID_NUMCORE_SHIFT	24
+#define	CHIPC_ID_BUS_MASK	0xF0000000	/**< chip/interconnect type (BHND_CHIPTYPE_*) */
+#define	CHIPC_ID_BUS_SHIFT	28
+
+#define	CHIPC_OTPST			0x10
+#define	CHIPC_JTAGCMD			0x30
+#define	CHIPC_JTAGIR			0x34
+#define	CHIPC_JTAGDR			0x38
+#define	CHIPC_JTAGCTRL			0x3c
+#define	CHIPC_GPIOPU			0x58
+#define	CHIPC_GPIOPD			0x5c
+#define	CHIPC_GPIOIN			0x60
+#define	CHIPC_GPIOOUT			0x64
+#define	CHIPC_GPIOOUTEN			0x68
+#define	CHIPC_GPIOCTRL			0x6c
+#define	CHIPC_GPIOPOL			0x70
+#define	CHIPC_GPIOINTM			0x74
+#define	CHIPC_WATCHDOG			0x80
+#define	CHIPC_CLKC_N			0x90
+#define	CHIPC_CLKC_M0			0x94
+#define	CHIPC_CLKC_M1			0x98
+#define	CHIPC_CLKC_M2			0x9c
+#define	CHIPC_CLKC_M3			0xa0
+#define	CHIPC_CLKDIV			0xa4
+#define	CHIPC_SYS_CLK_CTL		0xc0
+#define	CHIPC_SPROM_CTRL		0x190	/**< SPROM interface (rev >= 32) */
+#define	CHIPC_SPROM_ADDR		0x194
+#define	CHIPC_SPROM_DATA		0x198
+#define	CHIPC_CLK_CTL_ST		SI_CLK_CTL_ST
+#define	CHIPC_PMU_CTL			0x600
+#define	CHIPC_PMU_CAP			0x604
+#define	CHIPC_PMU_ST			0x608
+#define	CHIPC_PMU_RES_STATE		0x60c
+#define	CHIPC_PMU_TIMER			0x614
+#define	CHIPC_PMU_MIN_RES_MASK		0x618
+#define	CHIPC_PMU_MAX_RES_MASK		0x61c
+#define	CHIPC_CHIPCTL_ADDR		0x650
+#define	CHIPC_CHIPCTL_DATA		0x654
+#define	CHIPC_PMU_REG_CONTROL_ADDR	0x658
+#define	CHIPC_PMU_REG_CONTROL_DATA	0x65C
+#define	CHIPC_PMU_PLL_CONTROL_ADDR 	0x660
+#define	CHIPC_PMU_PLL_CONTROL_DATA 	0x664
+#define	CHIPC_SPROM_OTP			0x800	/* SPROM/OTP address space */
+
+/* capabilities */
+#define	CHIPC_CAP_UARTS_MASK		0x00000003	/* Number of UARTs */
+#define	CHIPC_CAP_MIPSEB		0x00000004	/* MIPS is in big-endian mode */
+#define	CHIPC_CAP_UCLKSEL		0x00000018	/* UARTs clock select */
+#define	CHIPC_CAP_UINTCLK		0x00000008	/* UARTs are driven by internal divided clock */
+#define	CHIPC_CAP_UARTGPIO		0x00000020	/* UARTs own GPIOs 15:12 */
+#define	CHIPC_CAP_EXTBUS_MASK		0x000000c0	/* External bus mask */
+#define	CHIPC_CAP_EXTBUS_NONE		0x00000000	/* No ExtBus present */
+#define	CHIPC_CAP_EXTBUS_FULL		0x00000040	/* ExtBus: PCMCIA, IDE & Prog */
+#define	CHIPC_CAP_EXTBUS_PROG		0x00000080	/* ExtBus: ProgIf only */
+#define	CHIPC_CAP_FLASH_MASK		0x00000700	/* Type of flash */
+#define	CHIPC_CAP_PLL_MASK		0x00038000	/* Type of PLL */
+#define	CHIPC_CAP_PWR_CTL		0x00040000	/* Power control */
+#define	CHIPC_CAP_OTP_SIZE		0x00380000	/* OTP Size (0 = none) */
+#define	CHIPC_CAP_OTP_SIZE_SHIFT	19		/* OTP Size shift */
+#define	CHIPC_CAP_OTP_SIZE_BASE		5		/* OTP Size base */
+#define	CHIPC_CAP_JTAGP			0x00400000	/* JTAG Master Present */
+#define	CHIPC_CAP_ROM			0x00800000	/* Internal boot rom active */
+#define	CHIPC_CAP_BKPLN64		0x08000000	/* 64-bit backplane */
+#define	CHIPC_CAP_PMU			0x10000000	/* PMU Present, rev >= 20 */
+#define	CHIPC_CAP_SPROM			0x40000000	/* SPROM Present, rev >= 32 */
+#define	CHIPC_CAP_NFLASH		0x80000000	/* Nand flash present, rev >= 35 */
+
+#define	CHIPC_CAP2_SECI			0x00000001	/* SECI Present, rev >= 36 */
+#define	CHIPC_CAP2_GSIO			0x00000002	/* GSIO (spi/i2c) present, rev >= 37 */
+
+/*
+ * ChipStatus (Common)
+ */
+
+/** ChipStatus CIS/OTP/SPROM values used to advertise OTP/SPROM availability in
+ *  chipcommon revs 11-31. */
+enum {
+	CHIPC_CST_DEFCIS_SEL	= 0,	/**< OTP is powered up, use default CIS, no SPROM */
+	CHIPC_CST_SPROM_SEL	= 1,	/**< OTP is powered up, SPROM is present */
+	CHIPC_CST_OTP_SEL	= 2,	/**< OTP is powered up, no SPROM */
+	CHIPC_CST_OTP_PWRDN	= 3	/**< OTP is powered down, SPROM is present (rev <= 22 only) */
+};
+
+
+#define	CHIPC_CST_SPROM_OTP_SEL_R22_MASK	0x00000003	/**< chipstatus OTP/SPROM SEL value (rev 22) */
+#define	CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT	0
+#define	CHIPC_CST_SPROM_OTP_SEL_R23_MASK	0x000000c0	/**< chipstatus OTP/SPROM SEL value (revs 23-31)
+								  *  
+								  *  it is unknown whether this is supported on
+								  *  any CC revs >= 32 that also vend CHIPC_CAP_*
+								  *  constants for OTP/SPROM/NVRAM availability.
+								  */
+#define	CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT	6
+
+/* PLL type */
+#define	CHIPC_PLL_NONE		0x00000000
+#define	CHIPC_PLL_TYPE1		0x00010000	/* 48MHz base, 3 dividers */
+#define	CHIPC_PLL_TYPE2		0x00020000	/* 48MHz, 4 dividers */
+#define	CHIPC_PLL_TYPE3		0x00030000	/* 25MHz, 2 dividers */
+#define	CHIPC_PLL_TYPE4		0x00008000	/* 48MHz, 4 dividers */
+#define	CHIPC_PLL_TYPE5		0x00018000	/* 25MHz, 4 dividers */
+#define	CHIPC_PLL_TYPE6		0x00028000	/* 100/200 or 120/240 only */
+#define	CHIPC_PLL_TYPE7		0x00038000	/* 25MHz, 4 dividers */
+
+/* ILP clock */
+#define	CHIPC_ILP_CLOCK		32000
+
+/* ALP clock on pre-PMU chips */
+#define	CHIPC_ALP_CLOCK		20000000
+
+/* HT clock */
+#define	CHIPC_HT_CLOCK		80000000
+
+/* corecontrol */
+#define	CHIPC_UARTCLKO		0x00000001	/* Drive UART with internal clock */
+#define	CHIPC_SE		0x00000002	/* sync clk out enable (corerev >= 3) */
+#define	CHIPC_UARTCLKEN		0x00000008	/* enable UART Clock (corerev > = 21 */
+
+/* chipcontrol */
+#define	CHIPCTRL_4321A0_DEFAULT	0x3a4
+#define	CHIPCTRL_4321A1_DEFAULT	0x0a4
+#define	CHIPCTRL_4321_PLL_DOWN	0x800000	/* serdes PLL down override */
+
+/* Fields in the otpstatus register in rev >= 21 */
+#define	CHIPC_OTPS_OL_MASK		0x000000ff
+#define	CHIPC_OTPS_OL_MFG		0x00000001	/* manuf row is locked */
+#define	CHIPC_OTPS_OL_OR1		0x00000002	/* otp redundancy row 1 is locked */
+#define	CHIPC_OTPS_OL_OR2		0x00000004	/* otp redundancy row 2 is locked */
+#define	CHIPC_OTPS_OL_GU		0x00000008	/* general use region is locked */
+#define	CHIPC_OTPS_GUP_MASK		0x00000f00
+#define	CHIPC_OTPS_GUP_SHIFT		8
+#define	CHIPC_OTPS_GUP_HW		0x00000100	/* h/w subregion is programmed */
+#define	CHIPC_OTPS_GUP_SW		0x00000200	/* s/w subregion is programmed */
+#define	CHIPC_OTPS_GUP_CI		0x00000400	/* chipid/pkgopt subregion is programmed */
+#define	CHIPC_OTPS_GUP_FUSE		0x00000800	/* fuse subregion is programmed */
+#define	CHIPC_OTPS_READY		0x00001000
+#define	CHIPC_OTPS_RV(x)		(1 << (16 + (x)))	/* redundancy entry valid */
+#define	CHIPC_OTPS_RV_MASK		0x0fff0000
+
+/* Fields in the otpcontrol register in rev >= 21 */
+#define	CHIPC_OTPC_PROGSEL		0x00000001
+#define	CHIPC_OTPC_PCOUNT_MASK		0x0000000e
+#define	CHIPC_OTPC_PCOUNT_SHIFT	1
+#define	CHIPC_OTPC_VSEL_MASK		0x000000f0
+#define	CHIPC_OTPC_VSEL_SHIFT		4
+#define	CHIPC_OTPC_TMM_MASK		0x00000700
+#define	CHIPC_OTPC_TMM_SHIFT		8
+#define	CHIPC_OTPC_ODM			0x00000800
+#define	CHIPC_OTPC_PROGEN		0x80000000
+
+/* Fields in otpprog in rev >= 21 and HND OTP */
+#define	CHIPC_OTPP_COL_MASK		0x000000ff
+#define	CHIPC_OTPP_COL_SHIFT		0
+#define	CHIPC_OTPP_ROW_MASK		0x0000ff00
+#define	CHIPC_OTPP_ROW_SHIFT		8
+#define	CHIPC_OTPP_OC_MASK		0x0f000000
+#define	CHIPC_OTPP_OC_SHIFT		24
+#define	CHIPC_OTPP_READERR		0x10000000
+#define	CHIPC_OTPP_VALUE_MASK		0x20000000
+#define	CHIPC_OTPP_VALUE_SHIFT	29
+#define	CHIPC_OTPP_START_BUSY		0x80000000
+#define	CHIPC_OTPP_READ			0x40000000	/* HND OTP */
+
+/* otplayout reg corerev >= 36 */
+#define	CHIPC_OTP_CISFORMAT_NEW	0x80000000
+
+/* Opcodes for OTPP_OC field */
+#define	CHIPC_OTPPOC_READ		0
+#define	CHIPC_OTPPOC_BIT_PROG		1
+#define	CHIPC_OTPPOC_VERIFY		3
+#define	CHIPC_OTPPOC_INIT		4
+#define	CHIPC_OTPPOC_SET		5
+#define	CHIPC_OTPPOC_RESET		6
+#define	CHIPC_OTPPOC_OCST		7
+#define	CHIPC_OTPPOC_ROW_LOCK		8
+#define	CHIPC_OTPPOC_PRESCN_TEST	9
+
+/* Jtagm characteristics that appeared at a given corerev */
+#define	CHIPC_JTAGM_CREV_OLD		10	/* Old command set, 16bit max IR */
+#define	CHIPC_JTAGM_CREV_IRP		22	/* Able to do pause-ir */
+#define	CHIPC_JTAGM_CREV_RTI		28	/* Able to do return-to-idle */
+
+/* jtagcmd */
+#define	CHIPC_JCMD_START		0x80000000
+#define	CHIPC_JCMD_BUSY			0x80000000
+#define	CHIPC_JCMD_STATE_MASK		0x60000000
+#define	CHIPC_JCMD_STATE_TLR		0x00000000	/* Test-logic-reset */
+#define	CHIPC_JCMD_STATE_PIR		0x20000000	/* Pause IR */
+#define	CHIPC_JCMD_STATE_PDR		0x40000000	/* Pause DR */
+#define	CHIPC_JCMD_STATE_RTI		0x60000000	/* Run-test-idle */
+#define	CHIPC_JCMD0_ACC_MASK		0x0000f000
+#define	CHIPC_JCMD0_ACC_IRDR		0x00000000
+#define	CHIPC_JCMD0_ACC_DR		0x00001000
+#define	CHIPC_JCMD0_ACC_IR		0x00002000
+#define	CHIPC_JCMD0_ACC_RESET		0x00003000
+#define	CHIPC_JCMD0_ACC_IRPDR		0x00004000
+#define	CHIPC_JCMD0_ACC_PDR		0x00005000
+#define	CHIPC_JCMD0_IRW_MASK		0x00000f00
+#define	CHIPC_JCMD_ACC_MASK		0x000f0000	/* Changes for corerev 11 */
+#define	CHIPC_JCMD_ACC_IRDR		0x00000000
+#define	CHIPC_JCMD_ACC_DR		0x00010000
+#define	CHIPC_JCMD_ACC_IR		0x00020000
+#define	CHIPC_JCMD_ACC_RESET		0x00030000
+#define	CHIPC_JCMD_ACC_IRPDR		0x00040000
+#define	CHIPC_JCMD_ACC_PDR		0x00050000
+#define	CHIPC_JCMD_ACC_PIR		0x00060000
+#define	CHIPC_JCMD_ACC_IRDR_I		0x00070000	/* rev 28: return to run-test-idle */
+#define	CHIPC_JCMD_ACC_DR_I		0x00080000	/* rev 28: return to run-test-idle */
+#define	CHIPC_JCMD_IRW_MASK		0x00001f00
+#define	CHIPC_JCMD_IRW_SHIFT		8
+#define	CHIPC_JCMD_DRW_MASK		0x0000003f
+
+/* jtagctrl */
+#define	CHIPC_JCTRL_FORCE_CLK		4	/* Force clock */
+#define	CHIPC_JCTRL_EXT_EN		2	/* Enable external targets */
+#define	CHIPC_JCTRL_EN		1	/* Enable Jtag master */
+
+/* Fields in clkdiv */
+#define	CHIPC_CLKD_SFLASH		0x0f000000
+#define	CHIPC_CLKD_SFLASH_SHIFT		24
+#define	CHIPC_CLKD_OTP			0x000f0000
+#define	CHIPC_CLKD_OTP_SHIFT		16
+#define	CHIPC_CLKD_JTAG			0x00000f00
+#define	CHIPC_CLKD_JTAG_SHIFT		8
+#define	CHIPC_CLKD_UART			0x000000ff
+
+#define	CHIPC_CLKD2_SPROM		0x00000003
+
+/* intstatus/intmask */
+#define	CHIPC_CI_GPIO			0x00000001	/* gpio intr */
+#define	CHIPC_CI_EI			0x00000002	/* extif intr (corerev >= 3) */
+#define	CHIPC_CI_TEMP			0x00000004	/* temp. ctrl intr (corerev >= 15) */
+#define	CHIPC_CI_SIRQ			0x00000008	/* serial IRQ intr (corerev >= 15) */
+#define	CHIPC_CI_PMU			0x00000020	/* pmu intr (corerev >= 21) */
+#define	CHIPC_CI_UART			0x00000040	/* uart intr (corerev >= 21) */
+#define	CHIPC_CI_WDRESET		0x80000000	/* watchdog reset occurred */
+
+/* slow_clk_ctl */
+#define	CHIPC_SCC_SS_MASK		0x00000007	/* slow clock source mask */
+#define	CHIPC_SCC_SS_LPO		0x00000000	/* source of slow clock is LPO */
+#define	CHIPC_SCC_SS_XTAL		0x00000001	/* source of slow clock is crystal */
+#define	CHIPC_SCC_SS_PCI		0x00000002	/* source of slow clock is PCI */
+#define	CHIPC_SCC_LF			0x00000200	/* LPOFreqSel, 1: 160Khz, 0: 32KHz */
+#define	CHIPC_SCC_LP			0x00000400	/* LPOPowerDown, 1: LPO is disabled,
+						 * 0: LPO is enabled
+						 */
+#define	CHIPC_SCC_FS			0x00000800	/* ForceSlowClk, 1: sb/cores running on slow clock,
+						 * 0: power logic control
+						 */
+#define	CHIPC_SCC_IP			0x00001000	/* IgnorePllOffReq, 1/0: power logic ignores/honors
+						 * PLL clock disable requests from core
+						 */
+#define	CHIPC_SCC_XC			0x00002000	/* XtalControlEn, 1/0: power logic does/doesn't
+						 * disable crystal when appropriate
+						 */
+#define	CHIPC_SCC_XP			0x00004000	/* XtalPU (RO), 1/0: crystal running/disabled */
+#define	CHIPC_SCC_CD_MASK		0xffff0000	/* ClockDivider (SlowClk = 1/(4+divisor)) */
+#define	CHIPC_SCC_CD_SHIFT		16
+
+/* system_clk_ctl */
+#define	CHIPC_SYCC_IE			0x00000001	/* ILPen: Enable Idle Low Power */
+#define	CHIPC_SYCC_AE			0x00000002	/* ALPen: Enable Active Low Power */
+#define	CHIPC_SYCC_FP			0x00000004	/* ForcePLLOn */
+#define	CHIPC_SYCC_AR			0x00000008	/* Force ALP (or HT if ALPen is not set */
+#define	CHIPC_SYCC_HR			0x00000010	/* Force HT */
+#define	CHIPC_SYCC_CD_MASK		0xffff0000	/* ClkDiv  (ILP = 1/(4 * (divisor + 1)) */
+#define	CHIPC_SYCC_CD_SHIFT		16
+
+/* Indirect backplane access */
+#define	CHIPC_BPIA_BYTEEN		0x0000000f
+#define	CHIPC_BPIA_SZ1			0x00000001
+#define	CHIPC_BPIA_SZ2			0x00000003
+#define	CHIPC_BPIA_SZ4			0x00000007
+#define	CHIPC_BPIA_SZ8			0x0000000f
+#define	CHIPC_BPIA_WRITE		0x00000100
+#define	CHIPC_BPIA_START		0x00000200
+#define	CHIPC_BPIA_BUSY			0x00000200
+#define	CHIPC_BPIA_ERROR		0x00000400
+
+/* pcmcia/prog/flash_config */
+#define	CHIPC_CF_EN			0x00000001	/* enable */
+#define	CHIPC_CF_EM_MASK		0x0000000e	/* mode */
+#define	CHIPC_CF_EM_SHIFT		1
+#define	CHIPC_CF_EM_FLASH		0	/* flash/asynchronous mode */
+#define	CHIPC_CF_EM_SYNC		2	/* synchronous mode */
+#define	CHIPC_CF_EM_PCMCIA		4	/* pcmcia mode */
+#define	CHIPC_CF_DS			0x00000010	/* destsize:  0=8bit, 1=16bit */
+#define	CHIPC_CF_BS			0x00000020	/* byteswap */
+#define	CHIPC_CF_CD_MASK		0x000000c0	/* clock divider */
+#define	CHIPC_CF_CD_SHIFT		6
+#define	CHIPC_CF_CD_DIV2		0x00000000	/* backplane/2 */
+#define	CHIPC_CF_CD_DIV3		0x00000040	/* backplane/3 */
+#define	CHIPC_CF_CD_DIV4		0x00000080	/* backplane/4 */
+#define	CHIPC_CF_CE			0x00000100	/* clock enable */
+#define	CHIPC_CF_SB			0x00000200	/* size/bytestrobe (synch only) */
+
+/* pcmcia_memwait */
+#define	CHIPC_PM_W0_MASK		0x0000003f	/* waitcount0 */
+#define	CHIPC_PM_W1_MASK		0x00001f00	/* waitcount1 */
+#define	CHIPC_PM_W1_SHIFT		8
+#define	CHIPC_PM_W2_MASK		0x001f0000	/* waitcount2 */
+#define	CHIPC_PM_W2_SHIFT		16
+#define	CHIPC_PM_W3_MASK		0x1f000000	/* waitcount3 */
+#define	CHIPC_PM_W3_SHIFT		24
+
+/* pcmcia_attrwait */
+#define	CHIPC_PA_W0_MASK		0x0000003f	/* waitcount0 */
+#define	CHIPC_PA_W1_MASK		0x00001f00	/* waitcount1 */
+#define	CHIPC_PA_W1_SHIFT		8
+#define	CHIPC_PA_W2_MASK		0x001f0000	/* waitcount2 */
+#define	CHIPC_PA_W2_SHIFT		16
+#define	CHIPC_PA_W3_MASK		0x1f000000	/* waitcount3 */
+#define	CHIPC_PA_W3_SHIFT		24
+
+/* pcmcia_iowait */
+#define	CHIPC_PI_W0_MASK		0x0000003f	/* waitcount0 */
+#define	CHIPC_PI_W1_MASK		0x00001f00	/* waitcount1 */
+#define	CHIPC_PI_W1_SHIFT		8
+#define	CHIPC_PI_W2_MASK		0x001f0000	/* waitcount2 */
+#define	CHIPC_PI_W2_SHIFT		16
+#define	CHIPC_PI_W3_MASK		0x1f000000	/* waitcount3 */
+#define	CHIPC_PI_W3_SHIFT		24
+
+/* prog_waitcount */
+#define	CHIPC_PW_W0_MASK		0x0000001f	/* waitcount0 */
+#define	CHIPC_PW_W1_MASK		0x00001f00	/* waitcount1 */
+#define	CHIPC_PW_W1_SHIFT		8
+#define	CHIPC_PW_W2_MASK		0x001f0000	/* waitcount2 */
+#define	CHIPC_PW_W2_SHIFT		16
+#define	CHIPC_PW_W3_MASK		0x1f000000	/* waitcount3 */
+#define	CHIPC_PW_W3_SHIFT		24
+
+#define	CHIPC_PW_W0       		0x0000000c
+#define	CHIPC_PW_W1       		0x00000a00
+#define	CHIPC_PW_W2       		0x00020000
+#define	CHIPC_PW_W3       		0x01000000
+
+/* flash_waitcount */
+#define	CHIPC_FW_W0_MASK		0x0000003f	/* waitcount0 */
+#define	CHIPC_FW_W1_MASK		0x00001f00	/* waitcount1 */
+#define	CHIPC_FW_W1_SHIFT		8
+#define	CHIPC_FW_W2_MASK		0x001f0000	/* waitcount2 */
+#define	CHIPC_FW_W2_SHIFT		16
+#define	CHIPC_FW_W3_MASK		0x1f000000	/* waitcount3 */
+#define	CHIPC_FW_W3_SHIFT		24
+
+/* When SPROM support present, fields in spromcontrol */
+#define	CHIPC_SRC_START			0x80000000
+#define	CHIPC_SRC_BUSY			0x80000000
+#define	CHIPC_SRC_OPCODE		0x60000000
+#define	CHIPC_SRC_OP_READ		0x00000000
+#define	CHIPC_SRC_OP_WRITE		0x20000000
+#define	CHIPC_SRC_OP_WRDIS		0x40000000
+#define	CHIPC_SRC_OP_WREN		0x60000000
+#define	CHIPC_SRC_OTPSEL		0x00000010
+#define	CHIPC_SRC_LOCK			0x00000008
+#define	CHIPC_SRC_SIZE_MASK		0x00000006
+#define	CHIPC_SRC_SIZE_1K		0x00000000
+#define	CHIPC_SRC_SIZE_4K		0x00000002
+#define	CHIPC_SRC_SIZE_16K		0x00000004
+#define	CHIPC_SRC_SIZE_SHIFT		1
+#define	CHIPC_SRC_PRESENT		0x00000001
+
+/* Fields in pmucontrol */
+#define	CHIPC_PCTL_ILP_DIV_MASK		0xffff0000
+#define	CHIPC_PCTL_ILP_DIV_SHIFT	16
+#define	CHIPC_PCTL_PLL_PLLCTL_UPD	0x00000400	/* rev 2 */
+#define	CHIPC_PCTL_NOILP_ON_WAIT	0x00000200	/* rev 1 */
+#define	CHIPC_PCTL_HT_REQ_EN		0x00000100
+#define	CHIPC_PCTL_ALP_REQ_EN		0x00000080
+#define	CHIPC_PCTL_XTALFREQ_MASK	0x0000007c
+#define	CHIPC_PCTL_XTALFREQ_SHIFT	2
+#define	CHIPC_PCTL_ILP_DIV_EN		0x00000002
+#define	CHIPC_PCTL_LPO_SEL		0x00000001
+
+/* Fields in clkstretch */
+#define	CHIPC_CSTRETCH_HT		0xffff0000
+#define	CHIPC_CSTRETCH_ALP		0x0000ffff
+
+/* gpiotimerval */
+#define	CHIPC_GPIO_ONTIME_SHIFT	16
+
+/* clockcontrol_n */
+#define	CHIPC_CN_N1_MASK		0x3f	/* n1 control */
+#define	CHIPC_CN_N2_MASK		0x3f00	/* n2 control */
+#define	CHIPC_CN_N2_SHIFT		8
+#define	CHIPC_CN_PLLC_MASK		0xf0000	/* pll control */
+#define	CHIPC_CN_PLLC_SHIFT		16
+
+/* clockcontrol_sb/pci/uart */
+#define	CHIPC_M1_MASK		0x3f	/* m1 control */
+#define	CHIPC_M2_MASK		0x3f00	/* m2 control */
+#define	CHIPC_M2_SHIFT		8
+#define	CHIPC_M3_MASK		0x3f0000	/* m3 control */
+#define	CHIPC_M3_SHIFT		16
+#define	CHIPC_MC_MASK		0x1f000000	/* mux control */
+#define	CHIPC_MC_SHIFT		24
+
+/* N3M Clock control magic field values */
+#define	CHIPC_F6_2		0x02	/* A factor of 2 in */
+#define	CHIPC_F6_3		0x03	/* 6-bit fields like */
+#define	CHIPC_F6_4		0x05	/* N1, M1 or M3 */
+#define	CHIPC_F6_5		0x09
+#define	CHIPC_F6_6		0x11
+#define	CHIPC_F6_7		0x21
+
+#define	CHIPC_F5_BIAS		5	/* 5-bit fields get this added */
+
+#define	CHIPC_MC_BYPASS		0x08
+#define	CHIPC_MC_M1		0x04
+#define	CHIPC_MC_M1M2		0x02
+#define	CHIPC_MC_M1M2M3		0x01
+#define	CHIPC_MC_M1M3		0x11
+
+/* Type 2 Clock control magic field values */
+#define	CHIPC_T2_BIAS		2	/* n1, n2, m1 & m3 bias */
+#define	CHIPC_T2M2_BIAS		3	/* m2 bias */
+
+#define	CHIPC_T2MC_M1BYP	1
+#define	CHIPC_T2MC_M2BYP	2
+#define	CHIPC_T2MC_M3BYP	4
+
+/* Type 6 Clock control magic field values */
+#define	CHIPC_T6_MMASK		1	/* bits of interest in m */
+#define	CHIPC_T6_M0		120000000	/* sb clock for m = 0 */
+#define	CHIPC_T6_M1		100000000	/* sb clock for m = 1 */
+#define	CHIPC_SB2MIPS_T6(sb)	(2 * (sb))
+
+/* Common clock base */
+#define	CHIPC_CLOCK_BASE1	24000000	/* Half the clock freq */
+#define	CHIPC_CLOCK_BASE2	12500000	/* Alternate crystal on some PLLs */
+
+/* Clock control values for 200MHz in 5350 */
+#define	CHIPC_CLKC_5350_N	0x0311
+#define	CHIPC_CLKC_5350_M	0x04020009
+
+/* Flash types in the chipcommon capabilities register */
+#define	CHIPC_FLASH_NONE	0x000	/* No flash */
+#define	CHIPC_SFLASH_ST		0x100	/* ST serial flash */
+#define	CHIPC_SFLASH_AT		0x200	/* Atmel serial flash */
+#define	CHIPC_PFLASH		0x700	/* Parallel flash */
+
+/* Bits in the ExtBus config registers */
+#define	CHIPC_CFG_EN		0x0001	/* Enable */
+#define	CHIPC_CFG_EM_MASK	0x000e	/* Extif Mode */
+#define	CHIPC_CFG_EM_ASYNC	0x0000	/*   Async/Parallel flash */
+#define	CHIPC_CFG_EM_SYNC	0x0002	/*   Synchronous */
+#define	CHIPC_CFG_EM_PCMCIA	0x0004	/*   PCMCIA */
+#define	CHIPC_CFG_EM_IDE	0x0006	/*   IDE */
+#define	CHIPC_CFG_DS		0x0010	/* Data size, 0=8bit, 1=16bit */
+#define	CHIPC_CFG_CD_MASK	0x00e0	/* Sync: Clock divisor, rev >= 20 */
+#define	CHIPC_CFG_CE		0x0100	/* Sync: Clock enable, rev >= 20 */
+#define	CHIPC_CFG_SB		0x0200	/* Sync: Size/Bytestrobe, rev >= 20 */
+#define	CHIPC_CFG_IS		0x0400	/* Extif Sync Clk Select, rev >= 20 */
+
+/* ExtBus address space */
+#define	CHIPC_EB_BASE		0x1a000000	/* Chipc ExtBus base address */
+#define	CHIPC_EB_PCMCIA_MEM	0x1a000000	/* PCMCIA 0 memory base address */
+#define	CHIPC_EB_PCMCIA_IO	0x1a200000	/* PCMCIA 0 I/O base address */
+#define	CHIPC_EB_PCMCIA_CFG	0x1a400000	/* PCMCIA 0 config base address */
+#define	CHIPC_EB_IDE		0x1a800000	/* IDE memory base */
+#define	CHIPC_EB_PCMCIA1_MEM	0x1a800000	/* PCMCIA 1 memory base address */
+#define	CHIPC_EB_PCMCIA1_IO	0x1aa00000	/* PCMCIA 1 I/O base address */
+#define	CHIPC_EB_PCMCIA1_CFG	0x1ac00000	/* PCMCIA 1 config base address */
+#define	CHIPC_EB_PROGIF		0x1b000000	/* ProgIF Async/Sync base address */
+
+/* Start/busy bit in flashcontrol */
+#define	CHIPC_SFLASH_OPCODE	0x000000ff
+#define	CHIPC_SFLASH_ACTION	0x00000700
+#define	CHIPC_SFLASH_CS_ACTIVE	0x00001000	/* Chip Select Active, rev >= 20 */
+#define	CHIPC_SFLASH_START	0x80000000
+#define	CHIPC_SFLASH_BUSY	SFLASH_START
+
+/* flashcontrol action codes */
+#define	CHIPC_SFLASH_ACT_OPONLY		0x0000	/* Issue opcode only */
+#define	CHIPC_SFLASH_ACT_OP1D		0x0100	/* opcode + 1 data byte */
+#define	CHIPC_SFLASH_ACT_OP3A		0x0200	/* opcode + 3 addr bytes */
+#define	CHIPC_SFLASH_ACT_OP3A1D		0x0300	/* opcode + 3 addr & 1 data bytes */
+#define	CHIPC_SFLASH_ACT_OP3A4D		0x0400	/* opcode + 3 addr & 4 data bytes */
+#define	CHIPC_SFLASH_ACT_OP3A4X4D	0x0500	/* opcode + 3 addr, 4 don't care & 4 data bytes */
+#define	CHIPC_SFLASH_ACT_OP3A1X4D	0x0700	/* opcode + 3 addr, 1 don't care & 4 data bytes */
+
+/* flashcontrol action+opcodes for ST flashes */
+#define	CHIPC_SFLASH_ST_WREN		0x0006	/* Write Enable */
+#define	CHIPC_SFLASH_ST_WRDIS		0x0004	/* Write Disable */
+#define	CHIPC_SFLASH_ST_RDSR		0x0105	/* Read Status Register */
+#define	CHIPC_SFLASH_ST_WRSR		0x0101	/* Write Status Register */
+#define	CHIPC_SFLASH_ST_READ		0x0303	/* Read Data Bytes */
+#define	CHIPC_SFLASH_ST_PP		0x0302	/* Page Program */
+#define	CHIPC_SFLASH_ST_SE		0x02d8	/* Sector Erase */
+#define	CHIPC_SFLASH_ST_BE		0x00c7	/* Bulk Erase */
+#define	CHIPC_SFLASH_ST_DP		0x00b9	/* Deep Power-down */
+#define	CHIPC_SFLASH_ST_RES		0x03ab	/* Read Electronic Signature */
+#define	CHIPC_SFLASH_ST_CSA		0x1000	/* Keep chip select asserted */
+#define	CHIPC_SFLASH_ST_SSE		0x0220	/* Sub-sector Erase */
+
+/* Status register bits for ST flashes */
+#define	CHIPC_SFLASH_ST_WIP		0x01	/* Write In Progress */
+#define	CHIPC_SFLASH_ST_WEL		0x02	/* Write Enable Latch */
+#define	CHIPC_SFLASH_ST_BP_MASK		0x1c	/* Block Protect */
+#define	CHIPC_SFLASH_ST_BP_SHIFT	2
+#define	CHIPC_SFLASH_ST_SRWD		0x80	/* Status Register Write Disable */
+
+/* flashcontrol action+opcodes for Atmel flashes */
+#define	CHIPC_SFLASH_AT_READ				0x07e8
+#define	CHIPC_SFLASH_AT_PAGE_READ			0x07d2
+#define	CHIPC_SFLASH_AT_BUF1_READ
+#define	CHIPC_SFLASH_AT_BUF2_READ
+#define	CHIPC_SFLASH_AT_STATUS				0x01d7
+#define	CHIPC_SFLASH_AT_BUF1_WRITE			0x0384
+#define	CHIPC_SFLASH_AT_BUF2_WRITE			0x0387
+#define	CHIPC_SFLASH_AT_BUF1_ERASE_PROGRAM		0x0283
+#define	CHIPC_SFLASH_AT_BUF2_ERASE_PROGRAM		0x0286
+#define	CHIPC_SFLASH_AT_BUF1_PROGRAM			0x0288
+#define	CHIPC_SFLASH_AT_BUF2_PROGRAM			0x0289
+#define	CHIPC_SFLASH_AT_PAGE_ERASE			0x0281
+#define	CHIPC_SFLASH_AT_BLOCK_ERASE			0x0250
+#define	CHIPC_SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM	0x0382
+#define	CHIPC_SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM	0x0385
+#define	CHIPC_SFLASH_AT_BUF1_LOAD			0x0253
+#define	CHIPC_SFLASH_AT_BUF2_LOAD			0x0255
+#define	CHIPC_SFLASH_AT_BUF1_COMPARE			0x0260
+#define	CHIPC_SFLASH_AT_BUF2_COMPARE			0x0261
+#define	CHIPC_SFLASH_AT_BUF1_REPROGRAM			0x0258
+#define	CHIPC_SFLASH_AT_BUF2_REPROGRAM			0x0259
+
+/* Status register bits for Atmel flashes */
+#define	CHIPC_SFLASH_AT_READY				0x80
+#define	CHIPC_SFLASH_AT_MISMATCH			0x40
+#define	CHIPC_SFLASH_AT_ID_MASK				0x38
+#define	CHIPC_SFLASH_AT_ID_SHIFT			3
+
+/*
+ * These are the UART port assignments, expressed as offsets from the base
+ * register.  These assignments should hold for any serial port based on
+ * a 8250, 16450, or 16550(A).
+ */
+
+#define	CHIPC_UART_RX			0	/* In:  Receive buffer (DLAB=0) */
+#define	CHIPC_UART_TX			0	/* Out: Transmit buffer (DLAB=0) */
+#define	CHIPC_UART_DLL			0	/* Out: Divisor Latch Low (DLAB=1) */
+#define	CHIPC_UART_IER			1	/* In/Out: Interrupt Enable Register (DLAB=0) */
+#define	CHIPC_UART_DLM			1	/* Out: Divisor Latch High (DLAB=1) */
+#define	CHIPC_UART_IIR			2	/* In: Interrupt Identity Register  */
+#define	CHIPC_UART_FCR			2	/* Out: FIFO Control Register */
+#define	CHIPC_UART_LCR			3	/* Out: Line Control Register */
+#define	CHIPC_UART_MCR			4	/* Out: Modem Control Register */
+#define	CHIPC_UART_LSR			5	/* In:  Line Status Register */
+#define	CHIPC_UART_MSR			6	/* In:  Modem Status Register */
+#define	CHIPC_UART_SCR			7	/* I/O: Scratch Register */
+#define	CHIPC_UART_LCR_DLAB		0x80	/* Divisor latch access bit */
+#define	CHIPC_UART_LCR_WLEN8		0x03	/* Word length: 8 bits */
+#define	CHIPC_UART_MCR_OUT2		0x08	/* MCR GPIO out 2 */
+#define	CHIPC_UART_MCR_LOOP		0x10	/* Enable loopback test mode */
+#define	CHIPC_UART_LSR_RX_FIFO 		0x80	/* Receive FIFO error */
+#define	CHIPC_UART_LSR_TDHR		0x40	/* Data-hold-register empty */
+#define	CHIPC_UART_LSR_THRE		0x20	/* Transmit-hold-register empty */
+#define	CHIPC_UART_LSR_BREAK		0x10	/* Break interrupt */
+#define	CHIPC_UART_LSR_FRAMING		0x08	/* Framing error */
+#define	CHIPC_UART_LSR_PARITY		0x04	/* Parity error */
+#define	CHIPC_UART_LSR_OVERRUN		0x02	/* Overrun error */
+#define	CHIPC_UART_LSR_RXRDY		0x01	/* Receiver ready */
+#define	CHIPC_UART_FCR_FIFO_ENABLE	1	/* FIFO control register bit controlling FIFO enable/disable */
+
+/* Interrupt Identity Register (IIR) bits */
+#define	CHIPC_UART_IIR_FIFO_MASK	0xc0	/* IIR FIFO disable/enabled mask */
+#define	CHIPC_UART_IIR_INT_MASK		0xf	/* IIR interrupt ID source */
+#define	CHIPC_UART_IIR_MDM_CHG		0x0	/* Modem status changed */
+#define	CHIPC_UART_IIR_NOINT		0x1	/* No interrupt pending */
+#define	CHIPC_UART_IIR_THRE		0x2	/* THR empty */
+#define	CHIPC_UART_IIR_RCVD_DATA	0x4	/* Received data available */
+#define	CHIPC_UART_IIR_RCVR_STATUS 	0x6	/* Receiver status */
+#define	CHIPC_UART_IIR_CHAR_TIME 	0xc	/* Character time */
+
+/* Interrupt Enable Register (IER) bits */
+#define	CHIPC_UART_IER_EDSSI	8	/* enable modem status interrupt */
+#define	CHIPC_UART_IER_ELSI	4	/* enable receiver line status interrupt */
+#define	CHIPC_UART_IER_ETBEI	2	/* enable transmitter holding register empty interrupt */
+#define	CHIPC_UART_IER_ERBFI	1	/* enable data available interrupt */
+
+/* pmustatus */
+#define	CHIPC_PST_EXTLPOAVAIL	0x0100
+#define	CHIPC_PST_WDRESET	0x0080
+#define	CHIPC_PST_INTPEND	0x0040
+#define	CHIPC_PST_SBCLKST	0x0030
+#define	CHIPC_PST_SBCLKST_ILP	0x0010
+#define	CHIPC_PST_SBCLKST_ALP	0x0020
+#define	CHIPC_PST_SBCLKST_HT	0x0030
+#define	CHIPC_PST_ALPAVAIL	0x0008
+#define	CHIPC_PST_HTAVAIL	0x0004
+#define	CHIPC_PST_RESINIT	0x0003
+
+/* pmucapabilities */
+#define	CHIPC_PCAP_REV_MASK	0x000000ff
+#define	CHIPC_PCAP_RC_MASK	0x00001f00
+#define	CHIPC_PCAP_RC_SHIFT	8
+#define	CHIPC_PCAP_TC_MASK	0x0001e000
+#define	CHIPC_PCAP_TC_SHIFT	13
+#define	CHIPC_PCAP_PC_MASK	0x001e0000
+#define	CHIPC_PCAP_PC_SHIFT	17
+#define	CHIPC_PCAP_VC_MASK	0x01e00000
+#define	CHIPC_PCAP_VC_SHIFT	21
+#define	CHIPC_PCAP_CC_MASK	0x1e000000
+#define	CHIPC_PCAP_CC_SHIFT	25
+#define	CHIPC_PCAP5_PC_MASK	0x003e0000	/* PMU corerev >= 5 */
+#define	CHIPC_PCAP5_PC_SHIFT	17
+#define	CHIPC_PCAP5_VC_MASK	0x07c00000
+#define	CHIPC_PCAP5_VC_SHIFT	22
+#define	CHIPC_PCAP5_CC_MASK	0xf8000000
+#define	CHIPC_PCAP5_CC_SHIFT	27
+
+/* PMU Resource Request Timer registers */
+/* This is based on PmuRev0 */
+#define	CHIPC_PRRT_TIME_MASK	0x03ff
+#define	CHIPC_PRRT_INTEN	0x0400
+#define	CHIPC_PRRT_REQ_ACTIVE	0x0800
+#define	CHIPC_PRRT_ALP_REQ	0x1000
+#define	CHIPC_PRRT_HT_REQ	0x2000
+
+/* PMU resource bit position */
+#define	CHIPC_PMURES_BIT(bit)	(1 << (bit))
+
+/* PMU resource number limit */
+#define	CHIPC_PMURES_MAX_RESNUM	30
+
+/* PMU chip control0 register */
+#define	CHIPC_PMU_CHIPCTL0	0
+
+/* PMU chip control1 register */
+#define	CHIPC_PMU_CHIPCTL1		1
+#define	CHIPC_PMU_CC1_RXC_DLL_BYPASS	0x00010000
+
+#define	CHIPC_PMU_CC1_IF_TYPE_MASK	0x00000030
+#define	CHIPC_PMU_CC1_IF_TYPE_RMII	0x00000000
+#define	CHIPC_PMU_CC1_IF_TYPE_MII	0x00000010
+#define	CHIPC_PMU_CC1_IF_TYPE_RGMII	0x00000020
+
+#define	CHIPC_PMU_CC1_SW_TYPE_MASK	0x000000c0
+#define	CHIPC_PMU_CC1_SW_TYPE_EPHY	0x00000000
+#define	CHIPC_PMU_CC1_SW_TYPE_EPHYMII	0x00000040
+#define	CHIPC_PMU_CC1_SW_TYPE_EPHYRMII	0x00000080
+#define	CHIPC_PMU_CC1_SW_TYPE_RGMII	0x000000c0
+
+/* PMU corerev and chip specific PLL controls.
+ * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number
+ * to differentiate different PLLs controlled by the same PMU rev.
+ */
+/* pllcontrol registers */
+/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */
+#define	CHIPC_PMU0_PLL0_PLLCTL0			0
+#define	CHIPC_PMU0_PLL0_PC0_PDIV_MASK		1
+#define	CHIPC_PMU0_PLL0_PC0_PDIV_FREQ		25000
+#define	CHIPC_PMU0_PLL0_PC0_DIV_ARM_MASK	0x00000038
+#define	CHIPC_PMU0_PLL0_PC0_DIV_ARM_SHIFT	3
+#define	CHIPC_PMU0_PLL0_PC0_DIV_ARM_BASE	8
+
+/* PC0_DIV_ARM for PLLOUT_ARM */
+#define	CHIPC_PMU0_PLL0_PC0_DIV_ARM_110MHZ	0
+#define	CHIPC_PMU0_PLL0_PC0_DIV_ARM_97_7MHZ	1
+#define	CHIPC_PMU0_PLL0_PC0_DIV_ARM_88MHZ	2
+#define	CHIPC_PMU0_PLL0_PC0_DIV_ARM_80MHZ	3	/* Default */
+#define	CHIPC_PMU0_PLL0_PC0_DIV_ARM_73_3MHZ	4
+#define	CHIPC_PMU0_PLL0_PC0_DIV_ARM_67_7MHZ	5
+#define	CHIPC_PMU0_PLL0_PC0_DIV_ARM_62_9MHZ	6
+#define	CHIPC_PMU0_PLL0_PC0_DIV_ARM_58_6MHZ	7
+
+/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */
+#define	CHIPC_PMU0_PLL0_PLLCTL1			1
+#define	CHIPC_PMU0_PLL0_PC1_WILD_INT_MASK	0xf0000000
+#define	CHIPC_PMU0_PLL0_PC1_WILD_INT_SHIFT	28
+#define	CHIPC_PMU0_PLL0_PC1_WILD_FRAC_MASK	0x0fffff00
+#define	CHIPC_PMU0_PLL0_PC1_WILD_FRAC_SHIFT	8
+#define	CHIPC_PMU0_PLL0_PC1_STOP_MOD		0x00000040
+
+/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */
+#define	CHIPC_PMU0_PLL0_PLLCTL2			2
+#define	CHIPC_PMU0_PLL0_PC2_WILD_INT_MASK	0xf
+#define	CHIPC_PMU0_PLL0_PC2_WILD_INT_SHIFT	4
+
+/* pllcontrol registers */
+/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
+#define	CHIPC_PMU1_PLL0_PLLCTL0		0
+#define	CHIPC_PMU1_PLL0_PC0_P1DIV_MASK	0x00f00000
+#define	CHIPC_PMU1_PLL0_PC0_P1DIV_SHIFT	20
+#define	CHIPC_PMU1_PLL0_PC0_P2DIV_MASK	0x0f000000
+#define	CHIPC_PMU1_PLL0_PC0_P2DIV_SHIFT	24
+
+/* m<x>div */
+#define	CHIPC_PMU1_PLL0_PLLCTL1		1
+#define	CHIPC_PMU1_PLL0_PC1_M1DIV_MASK	0x000000ff
+#define	CHIPC_PMU1_PLL0_PC1_M1DIV_SHIFT	0
+#define	CHIPC_PMU1_PLL0_PC1_M2DIV_MASK	0x0000ff00
+#define	CHIPC_PMU1_PLL0_PC1_M2DIV_SHIFT	8
+#define	CHIPC_PMU1_PLL0_PC1_M3DIV_MASK	0x00ff0000
+#define	CHIPC_PMU1_PLL0_PC1_M3DIV_SHIFT	16
+#define	CHIPC_PMU1_PLL0_PC1_M4DIV_MASK	0xff000000
+#define	CHIPC_PMU1_PLL0_PC1_M4DIV_SHIFT	24
+
+#define	CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8
+#define	CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
+#define	CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_VAL  (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
+
+/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
+#define	CHIPC_PMU1_PLL0_PLLCTL2			2
+#define	CHIPC_PMU1_PLL0_PC2_M5DIV_MASK		0x000000ff
+#define	CHIPC_PMU1_PLL0_PC2_M5DIV_SHIFT		0
+#define	CHIPC_PMU1_PLL0_PC2_M6DIV_MASK		0x0000ff00
+#define	CHIPC_PMU1_PLL0_PC2_M6DIV_SHIFT		8
+#define	CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MASK	0x000e0000
+#define	CHIPC_PMU1_PLL0_PC2_NDIV_MODE_SHIFT	17
+#define	CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MASH	1
+#define	CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MFB	2	/* recommended for 4319 */
+#define	CHIPC_PMU1_PLL0_PC2_NDIV_INT_MASK	0x1ff00000
+#define	CHIPC_PMU1_PLL0_PC2_NDIV_INT_SHIFT	20
+
+/* ndiv_frac */
+#define	CHIPC_PMU1_PLL0_PLLCTL3			3
+#define	CHIPC_PMU1_PLL0_PC3_NDIV_FRAC_MASK	0x00ffffff
+#define	CHIPC_PMU1_PLL0_PC3_NDIV_FRAC_SHIFT	0
+
+/* pll_ctrl */
+#define	CHIPC_PMU1_PLL0_PLLCTL4		4
+
+/* pll_ctrl, vco_rng, clkdrive_ch<x> */
+#define	CHIPC_PMU1_PLL0_PLLCTL5			5
+#define	CHIPC_PMU1_PLL0_PC5_CLK_DRV_MASK	0xffffff00
+#define	CHIPC_PMU1_PLL0_PC5_CLK_DRV_SHIFT	8
+
+/* PMU rev 2 control words */
+#define	CHIPC_PMU2_PHY_PLL_PLLCTL		4
+#define	CHIPC_PMU2_SI_PLL_PLLCTL		10
+
+/* PMU rev 2 */
+/* pllcontrol registers */
+/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
+#define	CHIPC_PMU2_PLL_PLLCTL0		0
+#define	CHIPC_PMU2_PLL_PC0_P1DIV_MASK 	0x00f00000
+#define	CHIPC_PMU2_PLL_PC0_P1DIV_SHIFT	20
+#define	CHIPC_PMU2_PLL_PC0_P2DIV_MASK 	0x0f000000
+#define	CHIPC_PMU2_PLL_PC0_P2DIV_SHIFT	24
+
+/* m<x>div */
+#define	CHIPC_PMU2_PLL_PLLCTL1		1
+#define	CHIPC_PMU2_PLL_PC1_M1DIV_MASK 	0x000000ff
+#define	CHIPC_PMU2_PLL_PC1_M1DIV_SHIFT	0
+#define	CHIPC_PMU2_PLL_PC1_M2DIV_MASK 	0x0000ff00
+#define	CHIPC_PMU2_PLL_PC1_M2DIV_SHIFT	8
+#define	CHIPC_PMU2_PLL_PC1_M3DIV_MASK 	0x00ff0000
+#define	CHIPC_PMU2_PLL_PC1_M3DIV_SHIFT	16
+#define	CHIPC_PMU2_PLL_PC1_M4DIV_MASK 	0xff000000
+#define	CHIPC_PMU2_PLL_PC1_M4DIV_SHIFT	24
+
+/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
+#define	CHIPC_PMU2_PLL_PLLCTL2			2
+#define	CHIPC_PMU2_PLL_PC2_M5DIV_MASK 		0x000000ff
+#define	CHIPC_PMU2_PLL_PC2_M5DIV_SHIFT		0
+#define	CHIPC_PMU2_PLL_PC2_M6DIV_MASK 		0x0000ff00
+#define	CHIPC_PMU2_PLL_PC2_M6DIV_SHIFT		8
+#define	CHIPC_PMU2_PLL_PC2_NDIV_MODE_MASK	0x000e0000
+#define	CHIPC_PMU2_PLL_PC2_NDIV_MODE_SHIFT	17
+#define	CHIPC_PMU2_PLL_PC2_NDIV_INT_MASK	0x1ff00000
+#define	CHIPC_PMU2_PLL_PC2_NDIV_INT_SHIFT	20
+
+/* ndiv_frac */
+#define	CHIPC_PMU2_PLL_PLLCTL3			3
+#define	CHIPC_PMU2_PLL_PC3_NDIV_FRAC_MASK	0x00ffffff
+#define	CHIPC_PMU2_PLL_PC3_NDIV_FRAC_SHIFT	0
+
+/* pll_ctrl */
+#define	CHIPC_PMU2_PLL_PLLCTL4			4
+
+/* pll_ctrl, vco_rng, clkdrive_ch<x> */
+#define	CHIPC_PMU2_PLL_PLLCTL5			5
+#define	CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH1_MASK	0x00000f00
+#define	CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT	8
+#define	CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH2_MASK	0x0000f000
+#define	CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT	12
+#define	CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH3_MASK	0x000f0000
+#define	CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT	16
+#define	CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH4_MASK	0x00f00000
+#define	CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT	20
+#define	CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH5_MASK	0x0f000000
+#define	CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT	24
+#define	CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH6_MASK	0xf0000000
+#define	CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT	28
+
+/* PMU rev 5 (& 6) */
+#define	CHIPC_PMU5_PLL_P1P2_OFF		0
+#define	CHIPC_PMU5_PLL_P1_MASK		0x0f000000
+#define	CHIPC_PMU5_PLL_P1_SHIFT		24
+#define	CHIPC_PMU5_PLL_P2_MASK		0x00f00000
+#define	CHIPC_PMU5_PLL_P2_SHIFT		20
+#define	CHIPC_PMU5_PLL_M14_OFF		1
+#define	CHIPC_PMU5_PLL_MDIV_MASK	0x000000ff
+#define	CHIPC_PMU5_PLL_MDIV_WIDTH	8
+#define	CHIPC_PMU5_PLL_NM5_OFF		2
+#define	CHIPC_PMU5_PLL_NDIV_MASK	0xfff00000
+#define	CHIPC_PMU5_PLL_NDIV_SHIFT	20
+#define	CHIPC_PMU5_PLL_NDIV_MODE_MASK	0x000e0000
+#define	CHIPC_PMU5_PLL_NDIV_MODE_SHIFT	17
+#define	CHIPC_PMU5_PLL_FMAB_OFF		3
+#define	CHIPC_PMU5_PLL_MRAT_MASK	0xf0000000
+#define	CHIPC_PMU5_PLL_MRAT_SHIFT	28
+#define	CHIPC_PMU5_PLL_ABRAT_MASK	0x08000000
+#define	CHIPC_PMU5_PLL_ABRAT_SHIFT	27
+#define	CHIPC_PMU5_PLL_FDIV_MASK	0x07ffffff
+#define	CHIPC_PMU5_PLL_PLLCTL_OFF	4
+#define	CHIPC_PMU5_PLL_PCHI_OFF		5
+#define	CHIPC_PMU5_PLL_PCHI_MASK	0x0000003f
+
+/* pmu XtalFreqRatio */
+#define	CHIPC_PMU_XTALFREQ_REG_ILPCTR_MASK	0x00001FFF
+#define	CHIPC_PMU_XTALFREQ_REG_MEASURE_MASK	0x80000000
+#define	CHIPC_PMU_XTALFREQ_REG_MEASURE_SHIFT	31
+
+/* Divider allocation in 4716/47162/5356/5357 */
+#define	CHIPC_PMU5_MAINPLL_CPU		1
+#define	CHIPC_PMU5_MAINPLL_MEM		2
+#define	CHIPC_PMU5_MAINPLL_SI		3
+
+#define	CHIPC_PMU7_PLL_PLLCTL7		7
+#define	CHIPC_PMU7_PLL_PLLCTL8		8
+#define	CHIPC_PMU7_PLL_PLLCTL11		11
+
+/* PLL usage in 4716/47162 */
+#define	CHIPC_PMU4716_MAINPLL_PLL0	12
+
+/* PLL usage in 5356/5357 */
+#define	CHIPC_PMU5356_MAINPLL_PLL0	0
+#define	CHIPC_PMU5357_MAINPLL_PLL0	0
+
+/* 4716/47162 resources */
+#define	CHIPC_RES4716_PROC_PLL_ON	0x00000040
+#define	CHIPC_RES4716_PROC_HT_AVAIL	0x00000080
+
+/* 4716/4717/4718 Chip specific ChipControl register bits */
+#define	CHIPC_CCTRL471X_I2S_PINS_ENABLE	0x0080	/* I2S pins off by default, shared with pflash */
+
+/* 5354 resources */
+#define	CHIPC_RES5354_EXT_SWITCHER_PWM		0	/* 0x00001 */
+#define	CHIPC_RES5354_BB_SWITCHER_PWM		1	/* 0x00002 */
+#define	CHIPC_RES5354_BB_SWITCHER_BURST		2	/* 0x00004 */
+#define	CHIPC_RES5354_BB_EXT_SWITCHER_BURST	3	/* 0x00008 */
+#define	CHIPC_RES5354_ILP_REQUEST		4	/* 0x00010 */
+#define	CHIPC_RES5354_RADIO_SWITCHER_PWM	5	/* 0x00020 */
+#define	CHIPC_RES5354_RADIO_SWITCHER_BURST	6	/* 0x00040 */
+#define	CHIPC_RES5354_ROM_SWITCH		7	/* 0x00080 */
+#define	CHIPC_RES5354_PA_REF_LDO		8	/* 0x00100 */
+#define	CHIPC_RES5354_RADIO_LDO			9	/* 0x00200 */
+#define	CHIPC_RES5354_AFE_LDO			10	/* 0x00400 */
+#define	CHIPC_RES5354_PLL_LDO			11	/* 0x00800 */
+#define	CHIPC_RES5354_BG_FILTBYP		12	/* 0x01000 */
+#define	CHIPC_RES5354_TX_FILTBYP		13	/* 0x02000 */
+#define	CHIPC_RES5354_RX_FILTBYP		14	/* 0x04000 */
+#define	CHIPC_RES5354_XTAL_PU			15	/* 0x08000 */
+#define	CHIPC_RES5354_XTAL_EN			16	/* 0x10000 */
+#define	CHIPC_RES5354_BB_PLL_FILTBYP		17	/* 0x20000 */
+#define	CHIPC_RES5354_RF_PLL_FILTBYP		18	/* 0x40000 */
+#define	CHIPC_RES5354_BB_PLL_PU			19	/* 0x80000 */
+
+/* 5357 Chip specific ChipControl register bits */
+#define	CHIPC_CCTRL5357_EXTPA			(1<<14)	/* extPA in ChipControl 1, bit 14 */
+#define	CHIPC_CCTRL5357_ANT_MUX_2o3		(1<<15)	/* 2o3 in ChipControl 1, bit 15 */
+
+/* 4328 resources */
+#define	CHIPC_RES4328_EXT_SWITCHER_PWM		0	/* 0x00001 */
+#define	CHIPC_RES4328_BB_SWITCHER_PWM		1	/* 0x00002 */
+#define	CHIPC_RES4328_BB_SWITCHER_BURST		2	/* 0x00004 */
+#define	CHIPC_RES4328_BB_EXT_SWITCHER_BURST	3	/* 0x00008 */
+#define	CHIPC_RES4328_ILP_REQUEST		4	/* 0x00010 */
+#define	CHIPC_RES4328_RADIO_SWITCHER_PWM	5	/* 0x00020 */
+#define	CHIPC_RES4328_RADIO_SWITCHER_BURST	6	/* 0x00040 */
+#define	CHIPC_RES4328_ROM_SWITCH		7	/* 0x00080 */
+#define	CHIPC_RES4328_PA_REF_LDO		8	/* 0x00100 */
+#define	CHIPC_RES4328_RADIO_LDO			9	/* 0x00200 */
+#define	CHIPC_RES4328_AFE_LDO			10	/* 0x00400 */
+#define	CHIPC_RES4328_PLL_LDO			11	/* 0x00800 */
+#define	CHIPC_RES4328_BG_FILTBYP		12	/* 0x01000 */
+#define	CHIPC_RES4328_TX_FILTBYP		13	/* 0x02000 */
+#define	CHIPC_RES4328_RX_FILTBYP		14	/* 0x04000 */
+#define	CHIPC_RES4328_XTAL_PU			15	/* 0x08000 */
+#define	CHIPC_RES4328_XTAL_EN			16	/* 0x10000 */
+#define	CHIPC_RES4328_BB_PLL_FILTBYP		17	/* 0x20000 */
+#define	CHIPC_RES4328_RF_PLL_FILTBYP		18	/* 0x40000 */
+#define	CHIPC_RES4328_BB_PLL_PU			19	/* 0x80000 */
+
+/* 4325 A0/A1 resources */
+#define	CHIPC_RES4325_BUCK_BOOST_BURST		0	/* 0x00000001 */
+#define	CHIPC_RES4325_CBUCK_BURST		1	/* 0x00000002 */
+#define	CHIPC_RES4325_CBUCK_PWM			2	/* 0x00000004 */
+#define	CHIPC_RES4325_CLDO_CBUCK_BURST		3	/* 0x00000008 */
+#define	CHIPC_RES4325_CLDO_CBUCK_PWM		4	/* 0x00000010 */
+#define	CHIPC_RES4325_BUCK_BOOST_PWM		5	/* 0x00000020 */
+#define	CHIPC_RES4325_ILP_REQUEST		6	/* 0x00000040 */
+#define	CHIPC_RES4325_ABUCK_BURST		7	/* 0x00000080 */
+#define	CHIPC_RES4325_ABUCK_PWM			8	/* 0x00000100 */
+#define	CHIPC_RES4325_LNLDO1_PU			9	/* 0x00000200 */
+#define	CHIPC_RES4325_OTP_PU			10	/* 0x00000400 */
+#define	CHIPC_RES4325_LNLDO3_PU			11	/* 0x00000800 */
+#define	CHIPC_RES4325_LNLDO4_PU			12	/* 0x00001000 */
+#define	CHIPC_RES4325_XTAL_PU			13	/* 0x00002000 */
+#define	CHIPC_RES4325_ALP_AVAIL			14	/* 0x00004000 */
+#define	CHIPC_RES4325_RX_PWRSW_PU		15	/* 0x00008000 */
+#define	CHIPC_RES4325_TX_PWRSW_PU		16	/* 0x00010000 */
+#define	CHIPC_RES4325_RFPLL_PWRSW_PU		17	/* 0x00020000 */
+#define	CHIPC_RES4325_LOGEN_PWRSW_PU		18	/* 0x00040000 */
+#define	CHIPC_RES4325_AFE_PWRSW_PU		19	/* 0x00080000 */
+#define	CHIPC_RES4325_BBPLL_PWRSW_PU		20	/* 0x00100000 */
+#define	CHIPC_RES4325_HT_AVAIL			21	/* 0x00200000 */
+
+/* 4325 B0/C0 resources */
+#define	CHIPC_RES4325B0_CBUCK_LPOM		1	/* 0x00000002 */
+#define	CHIPC_RES4325B0_CBUCK_BURST		2	/* 0x00000004 */
+#define	CHIPC_RES4325B0_CBUCK_PWM		3	/* 0x00000008 */
+#define	CHIPC_RES4325B0_CLDO_PU			4	/* 0x00000010 */
+
+/* 4325 C1 resources */
+#define	CHIPC_RES4325C1_LNLDO2_PU		12	/* 0x00001000 */
+
+/* 4325 chip-specific ChipStatus register bits */
+#define	CHIPC_CST4325_SPROM_OTP_SEL_MASK	CHIPC_CST_SPROM_OTP_SEL_R22_MASK
+#define	CHIPC_CST4325_SPROM_OTP_SEL_SHIFT	CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT
+#define	CHIPC_CST4325_SDIO_USB_MODE_MASK	0x00000004
+#define	CHIPC_CST4325_SDIO_USB_MODE_SHIFT	2
+#define	CHIPC_CST4325_RCAL_VALID_MASK		0x00000008
+#define	CHIPC_CST4325_RCAL_VALID_SHIFT		3
+#define	CHIPC_CST4325_RCAL_VALUE_MASK		0x000001f0
+#define	CHIPC_CST4325_RCAL_VALUE_SHIFT		4
+#define	CHIPC_CST4325_PMUTOP_2B_MASK 		0x00000200	/* 1 for 2b, 0 for to 2a */
+#define	CHIPC_CST4325_PMUTOP_2B_SHIFT   	9
+
+#define	CHIPC_RES4329_RESERVED0			0	/* 0x00000001 */
+#define	CHIPC_RES4329_CBUCK_LPOM		1	/* 0x00000002 */
+#define	CHIPC_RES4329_CBUCK_BURST		2	/* 0x00000004 */
+#define	CHIPC_RES4329_CBUCK_PWM			3	/* 0x00000008 */
+#define	CHIPC_RES4329_CLDO_PU			4	/* 0x00000010 */
+#define	CHIPC_RES4329_PALDO_PU			5	/* 0x00000020 */
+#define	CHIPC_RES4329_ILP_REQUEST		6	/* 0x00000040 */
+#define	CHIPC_RES4329_RESERVED7			7	/* 0x00000080 */
+#define	CHIPC_RES4329_RESERVED8			8	/* 0x00000100 */
+#define	CHIPC_RES4329_LNLDO1_PU			9	/* 0x00000200 */
+#define	CHIPC_RES4329_OTP_PU			10	/* 0x00000400 */
+#define	CHIPC_RES4329_RESERVED11		11	/* 0x00000800 */
+#define	CHIPC_RES4329_LNLDO2_PU			12	/* 0x00001000 */
+#define	CHIPC_RES4329_XTAL_PU			13	/* 0x00002000 */
+#define	CHIPC_RES4329_ALP_AVAIL			14	/* 0x00004000 */
+#define	CHIPC_RES4329_RX_PWRSW_PU		15	/* 0x00008000 */
+#define	CHIPC_RES4329_TX_PWRSW_PU		16	/* 0x00010000 */
+#define	CHIPC_RES4329_RFPLL_PWRSW_PU		17	/* 0x00020000 */
+#define	CHIPC_RES4329_LOGEN_PWRSW_PU		18	/* 0x00040000 */
+#define	CHIPC_RES4329_AFE_PWRSW_PU		19	/* 0x00080000 */
+#define	CHIPC_RES4329_BBPLL_PWRSW_PU		20	/* 0x00100000 */
+#define	CHIPC_RES4329_HT_AVAIL			21	/* 0x00200000 */
+
+/* 4329 chip-specific ChipStatus register bits */
+#define	CHIPC_CST4329_SPROM_OTP_SEL_MASK	CHIPC_CST_SPROM_OTP_SEL_R22_MASK
+#define	CHIPC_CST4329_SPROM_OTP_SEL_SHIFT	CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT
+#define	CHIPC_CST4329_SPI_SDIO_MODE_MASK	0x00000004
+#define	CHIPC_CST4329_SPI_SDIO_MODE_SHIFT	2
+
+/* 4312 chip-specific ChipStatus register bits */
+#define	CHIPC_CST4312_SPROM_OTP_SEL_MASK	CHIPC_CST_SPROM_OTP_SEL_R22_MASK
+#define	CHIPC_CST4312_SPROM_OTP_SEL_SHIFT	CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT
+
+/* 4312 resources (all PMU chips with little memory constraint) */
+#define	CHIPC_RES4312_SWITCHER_BURST		0	/* 0x00000001 */
+#define	CHIPC_RES4312_SWITCHER_PWM    		1	/* 0x00000002 */
+#define	CHIPC_RES4312_PA_REF_LDO		2	/* 0x00000004 */
+#define	CHIPC_RES4312_CORE_LDO_BURST		3	/* 0x00000008 */
+#define	CHIPC_RES4312_CORE_LDO_PWM		4	/* 0x00000010 */
+#define	CHIPC_RES4312_RADIO_LDO			5	/* 0x00000020 */
+#define	CHIPC_RES4312_ILP_REQUEST		6	/* 0x00000040 */
+#define	CHIPC_RES4312_BG_FILTBYP		7	/* 0x00000080 */
+#define	CHIPC_RES4312_TX_FILTBYP		8	/* 0x00000100 */
+#define	CHIPC_RES4312_RX_FILTBYP		9	/* 0x00000200 */
+#define	CHIPC_RES4312_XTAL_PU			10	/* 0x00000400 */
+#define	CHIPC_RES4312_ALP_AVAIL			11	/* 0x00000800 */
+#define	CHIPC_RES4312_BB_PLL_FILTBYP		12	/* 0x00001000 */
+#define	CHIPC_RES4312_RF_PLL_FILTBYP		13	/* 0x00002000 */
+#define	CHIPC_RES4312_HT_AVAIL			14	/* 0x00004000 */
+
+/* 4322 resources */
+#define	CHIPC_RES4322_RF_LDO			0
+#define	CHIPC_RES4322_ILP_REQUEST		1
+#define	CHIPC_RES4322_XTAL_PU			2
+#define	CHIPC_RES4322_ALP_AVAIL			3
+#define	CHIPC_RES4322_SI_PLL_ON			4
+#define	CHIPC_RES4322_HT_SI_AVAIL		5
+#define	CHIPC_RES4322_PHY_PLL_ON		6
+#define	CHIPC_RES4322_HT_PHY_AVAIL		7
+#define	CHIPC_RES4322_OTP_PU			8
+
+/* 4322 chip-specific ChipStatus register bits */
+#define	CHIPC_CST4322_XTAL_FREQ_20_40MHZ	0x00000020
+#define	CHIPC_CST4322_SPROM_OTP_SEL_MASK	CHIPC_CST_SPROM_OTP_SEL_R23_MASK
+#define	CHIPC_CST4322_SPROM_OTP_SEL_SHIFT	CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT
+#define	CHIPC_CST4322_PCI_OR_USB		0x00000100
+#define	CHIPC_CST4322_BOOT_MASK			0x00000600
+#define	CHIPC_CST4322_BOOT_SHIFT		9
+#define	CHIPC_CST4322_BOOT_FROM_SRAM		0	/* boot from SRAM, ARM in reset */
+#define	CHIPC_CST4322_BOOT_FROM_ROM		1	/* boot from ROM */
+#define	CHIPC_CST4322_BOOT_FROM_FLASH		2	/* boot from FLASH */
+#define	CHIPC_CST4322_BOOT_FROM_INVALID		3
+#define	CHIPC_CST4322_ILP_DIV_EN		0x00000800
+#define	CHIPC_CST4322_FLASH_TYPE_MASK		0x00001000
+#define	CHIPC_CST4322_FLASH_TYPE_SHIFT		12
+#define	CHIPC_CST4322_FLASH_TYPE_SHIFT_ST	0	/* ST serial FLASH */
+#define	CHIPC_CST4322_FLASH_TYPE_SHIFT_ATMEL	1	/* ATMEL flash */
+#define	CHIPC_CST4322_ARM_TAP_SEL		0x00002000
+#define	CHIPC_CST4322_RES_INIT_MODE_MASK	0x0000c000
+#define	CHIPC_CST4322_RES_INIT_MODE_SHIFT	14
+#define	CHIPC_CST4322_RES_INIT_MODE_ILPAVAIL	0	/* resinitmode: ILP available */
+#define	CHIPC_CST4322_RES_INIT_MODE_ILPREQ	1	/* resinitmode: ILP request */
+#define	CHIPC_CST4322_RES_INIT_MODE_ALPAVAIL	2	/* resinitmode: ALP available */
+#define	CHIPC_CST4322_RES_INIT_MODE_HTAVAIL	3	/* resinitmode: HT available */
+#define	CHIPC_CST4322_PCIPLLCLK_GATING		0x00010000
+#define	CHIPC_CST4322_CLK_SWITCH_PCI_TO_ALP	0x00020000
+#define	CHIPC_CST4322_PCI_CARDBUS_MODE		0x00040000
+
+/* 43224 chip-specific ChipControl register bits */
+#define	CHIPC_CCTRL43224_GPIO_TOGGLE		0x8000
+#define	CHIPC_CCTRL_43224A0_12MA_LED_DRIVE	0x00F000F0	/* 12 mA drive strength */
+#define	CHIPC_CCTRL_43224B0_12MA_LED_DRIVE	0xF0	/* 12 mA drive strength for later 43224s */
+
+/* 43236 resources */
+#define	CHIPC_RES43236_REGULATOR		0
+#define	CHIPC_RES43236_ILP_REQUEST		1
+#define	CHIPC_RES43236_XTAL_PU			2
+#define	CHIPC_RES43236_ALP_AVAIL		3
+#define	CHIPC_RES43236_SI_PLL_ON		4
+#define	CHIPC_RES43236_HT_SI_AVAIL		5
+
+/* 43236 chip-specific ChipControl register bits */
+#define	CHIPC_CCTRL43236_BT_COEXIST		(1<<0)	/* 0 disable */
+#define	CHIPC_CCTRL43236_SECI			(1<<1)	/* 0 SECI is disabled (JATG functional) */
+#define	CHIPC_CCTRL43236_EXT_LNA		(1<<2)	/* 0 disable */
+#define	CHIPC_CCTRL43236_ANT_MUX_2o3		(1<<3)	/* 2o3 mux, chipcontrol bit 3 */
+#define	CHIPC_CCTRL43236_GSIO			(1<<4)	/* 0 disable */
+
+/* 43236 Chip specific ChipStatus register bits */
+#define	CHIPC_CST43236_SFLASH_MASK		0x00000040
+#define	CHIPC_CST43236_OTP_SEL_MASK		0x00000080
+#define	CHIPC_CST43236_OTP_SEL_SHIFT		7
+#define	CHIPC_CST43236_HSIC_MASK		0x00000100	/* USB/HSIC */
+#define	CHIPC_CST43236_BP_CLK			0x00000200	/* 120/96Mbps */
+#define	CHIPC_CST43236_BOOT_MASK		0x00001800
+#define	CHIPC_CST43236_BOOT_SHIFT		11
+#define	CHIPC_CST43236_BOOT_FROM_SRAM		0	/* boot from SRAM, ARM in reset */
+#define	CHIPC_CST43236_BOOT_FROM_ROM		1	/* boot from ROM */
+#define	CHIPC_CST43236_BOOT_FROM_FLASH		2	/* boot from FLASH */
+#define	CHIPC_CST43236_BOOT_FROM_INVALID	3
+
+/* 4331 resources */
+#define	CHIPC_RES4331_REGULATOR			0
+#define	CHIPC_RES4331_ILP_REQUEST		1
+#define	CHIPC_RES4331_XTAL_PU			2
+#define	CHIPC_RES4331_ALP_AVAIL			3
+#define	CHIPC_RES4331_SI_PLL_ON			4
+#define	CHIPC_RES4331_HT_SI_AVAIL		5
+
+/* 4331 chip-specific ChipControl register bits */
+#define	CHIPC_CCTRL4331_BT_COEXIST		(1<<0)	/* 0 disable */
+#define	CHIPC_CCTRL4331_SECI			(1<<1)	/* 0 SECI is disabled (JATG functional) */
+#define	CHIPC_CCTRL4331_EXT_LNA			(1<<2)	/* 0 disable */
+#define	CHIPC_CCTRL4331_SPROM_GPIO13_15		(1<<3)	/* sprom/gpio13-15 mux */
+#define	CHIPC_CCTRL4331_EXTPA_EN		(1<<4)	/* 0 ext pa disable, 1 ext pa enabled */
+#define	CHIPC_CCTRL4331_GPIOCLK_ON_SPROMCS	(1<<5)	/* set drive out GPIO_CLK on sprom_cs pin */
+#define	CHIPC_CCTRL4331_PCIE_MDIO_ON_SPROMCS	(1<<6)	/* use sprom_cs pin as PCIE mdio interface */
+#define	CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5	(1<<7)	/* aband extpa will be at gpio2/5 and sprom_dout */
+#define	CHIPC_CCTRL4331_OVR_PIPEAUXCLKEN	(1<<8)	/* override core control on pipe_AuxClkEnable */
+#define	CHIPC_CCTRL4331_OVR_PIPEAUXPWRDOWN	(1<<9)	/* override core control on pipe_AuxPowerDown */
+#define	CHIPC_CCTRL4331_PCIE_AUXCLKEN		(1<<10)	/* pcie_auxclkenable */
+#define	CHIPC_CCTRL4331_PCIE_PIPE_PLLDOWN	(1<<11)	/* pcie_pipe_pllpowerdown */
+#define	CHIPC_CCTRL4331_BT_SHD0_ON_GPIO4	(1<<16)	/* enable bt_shd0 at gpio4 */
+#define	CHIPC_CCTRL4331_BT_SHD1_ON_GPIO5	(1<<17)	/* enable bt_shd1 at gpio5 */
+
+/* 4331 Chip specific ChipStatus register bits */
+#define	CHIPC_CST4331_XTAL_FREQ			0x00000001	/* crystal frequency 20/40Mhz */
+#define	CHIPC_CST4331_SPROM_PRESENT		0x00000002
+#define	CHIPC_CST4331_OTP_PRESENT		0x00000004
+#define	CHIPC_CST4331_LDO_RF			0x00000008
+#define	CHIPC_CST4331_LDO_PAR			0x00000010
+
+/* 4315 resources */
+#define	CHIPC_RES4315_CBUCK_LPOM		1	/* 0x00000002 */
+#define	CHIPC_RES4315_CBUCK_BURST		2	/* 0x00000004 */
+#define	CHIPC_RES4315_CBUCK_PWM			3	/* 0x00000008 */
+#define	CHIPC_RES4315_CLDO_PU			4	/* 0x00000010 */
+#define	CHIPC_RES4315_PALDO_PU			5	/* 0x00000020 */
+#define	CHIPC_RES4315_ILP_REQUEST		6	/* 0x00000040 */
+#define	CHIPC_RES4315_LNLDO1_PU			9	/* 0x00000200 */
+#define	CHIPC_RES4315_OTP_PU			10	/* 0x00000400 */
+#define	CHIPC_RES4315_LNLDO2_PU			12	/* 0x00001000 */
+#define	CHIPC_RES4315_XTAL_PU			13	/* 0x00002000 */
+#define	CHIPC_RES4315_ALP_AVAIL			14	/* 0x00004000 */
+#define	CHIPC_RES4315_RX_PWRSW_PU		15	/* 0x00008000 */
+#define	CHIPC_RES4315_TX_PWRSW_PU		16	/* 0x00010000 */
+#define	CHIPC_RES4315_RFPLL_PWRSW_PU		17	/* 0x00020000 */
+#define	CHIPC_RES4315_LOGEN_PWRSW_PU		18	/* 0x00040000 */
+#define	CHIPC_RES4315_AFE_PWRSW_PU		19	/* 0x00080000 */
+#define	CHIPC_RES4315_BBPLL_PWRSW_PU		20	/* 0x00100000 */
+#define	CHIPC_RES4315_HT_AVAIL			21	/* 0x00200000 */
+
+/* 4315 chip-specific ChipStatus register bits */
+#define	CHIPC_CST4315_SPROM_OTP_SEL_MASK	CHIPC_CST_SPROM_OTP_SEL_R22_MASK
+#define	CHIPC_CST4315_SPROM_OTP_SEL_SHIFT	CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT
+#define	CHIPC_CST4315_SDIO_MODE			0x00000004	/* gpio [8], sdio/usb mode */
+#define	CHIPC_CST4315_RCAL_VALID		0x00000008
+#define	CHIPC_CST4315_RCAL_VALUE_MASK		0x000001f0
+#define	CHIPC_CST4315_RCAL_VALUE_SHIFT		4
+#define	CHIPC_CST4315_PALDO_EXTPNP		0x00000200	/* PALDO is configured with external PNP */
+#define	CHIPC_CST4315_CBUCK_MODE_MASK		0x00000c00
+#define	CHIPC_CST4315_CBUCK_MODE_BURST		0x00000400
+#define	CHIPC_CST4315_CBUCK_MODE_LPBURST	0x00000c00
+
+/* 4319 resources */
+#define	CHIPC_RES4319_CBUCK_LPOM		1	/* 0x00000002 */
+#define	CHIPC_RES4319_CBUCK_BURST		2	/* 0x00000004 */
+#define	CHIPC_RES4319_CBUCK_PWM			3	/* 0x00000008 */
+#define	CHIPC_RES4319_CLDO_PU			4	/* 0x00000010 */
+#define	CHIPC_RES4319_PALDO_PU			5	/* 0x00000020 */
+#define	CHIPC_RES4319_ILP_REQUEST		6	/* 0x00000040 */
+#define	CHIPC_RES4319_LNLDO1_PU			9	/* 0x00000200 */
+#define	CHIPC_RES4319_OTP_PU			10	/* 0x00000400 */
+#define	CHIPC_RES4319_LNLDO2_PU			12	/* 0x00001000 */
+#define	CHIPC_RES4319_XTAL_PU			13	/* 0x00002000 */
+#define	CHIPC_RES4319_ALP_AVAIL			14	/* 0x00004000 */
+#define	CHIPC_RES4319_RX_PWRSW_PU		15	/* 0x00008000 */
+#define	CHIPC_RES4319_TX_PWRSW_PU		16	/* 0x00010000 */
+#define	CHIPC_RES4319_RFPLL_PWRSW_PU		17	/* 0x00020000 */
+#define	CHIPC_RES4319_LOGEN_PWRSW_PU		18	/* 0x00040000 */
+#define	CHIPC_RES4319_AFE_PWRSW_PU		19	/* 0x00080000 */
+#define	CHIPC_RES4319_BBPLL_PWRSW_PU		20	/* 0x00100000 */
+#define	CHIPC_RES4319_HT_AVAIL			21	/* 0x00200000 */
+
+/* 4319 chip-specific ChipStatus register bits */
+#define	CHIPC_CST4319_SPI_CPULESSUSB		0x00000001
+#define	CHIPC_CST4319_SPI_CLK_POL		0x00000002
+#define	CHIPC_CST4319_SPI_CLK_PH		0x00000008
+#define	CHIPC_CST4319_SPROM_OTP_SEL_MASK	CHIPC_CST_SPROM_OTP_SEL_R23_MASK	/* gpio [7:6], SDIO CIS selection */
+#define	CHIPC_CST4319_SPROM_OTP_SEL_SHIFT	CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT
+#define	CHIPC_CST4319_SDIO_USB_MODE		0x00000100	/* gpio [8], sdio/usb mode */
+#define	CHIPC_CST4319_REMAP_SEL_MASK		0x00000600
+#define	CHIPC_CST4319_ILPDIV_EN			0x00000800
+#define	CHIPC_CST4319_XTAL_PD_POL		0x00001000
+#define	CHIPC_CST4319_LPO_SEL			0x00002000
+#define	CHIPC_CST4319_RES_INIT_MODE		0x0000c000
+#define	CHIPC_CST4319_PALDO_EXTPNP		0x00010000	/* PALDO is configured with external PNP */
+#define	CHIPC_CST4319_CBUCK_MODE_MASK		0x00060000
+#define	CHIPC_CST4319_CBUCK_MODE_BURST		0x00020000
+#define	CHIPC_CST4319_CBUCK_MODE_LPBURST	0x00060000
+#define	CHIPC_CST4319_RCAL_VALID		0x01000000
+#define	CHIPC_CST4319_RCAL_VALUE_MASK		0x3e000000
+#define	CHIPC_CST4319_RCAL_VALUE_SHIFT		25
+
+#define	CHIPC_PMU1_PLL0_CHIPCTL0		0
+#define	CHIPC_PMU1_PLL0_CHIPCTL1		1
+#define	CHIPC_PMU1_PLL0_CHIPCTL2		2
+#define	CHIPC_CCTL_4319USB_XTAL_SEL_MASK	0x00180000
+#define	CHIPC_CCTL_4319USB_XTAL_SEL_SHIFT	19
+#define	CHIPC_CCTL_4319USB_48MHZ_PLL_SEL	1
+#define	CHIPC_CCTL_4319USB_24MHZ_PLL_SEL	2
+
+/* PMU resources for 4336 */
+#define	CHIPC_RES4336_CBUCK_LPOM		0
+#define	CHIPC_RES4336_CBUCK_BURST		1
+#define	CHIPC_RES4336_CBUCK_LP_PWM		2
+#define	CHIPC_RES4336_CBUCK_PWM			3
+#define	CHIPC_RES4336_CLDO_PU			4
+#define	CHIPC_RES4336_DIS_INT_RESET_PD		5
+#define	CHIPC_RES4336_ILP_REQUEST		6
+#define	CHIPC_RES4336_LNLDO_PU			7
+#define	CHIPC_RES4336_LDO3P3_PU			8
+#define	CHIPC_RES4336_OTP_PU			9
+#define	CHIPC_RES4336_XTAL_PU			10
+#define	CHIPC_RES4336_ALP_AVAIL			11
+#define	CHIPC_RES4336_RADIO_PU			12
+#define	CHIPC_RES4336_BG_PU			13
+#define	CHIPC_RES4336_VREG1p4_PU_PU		14
+#define	CHIPC_RES4336_AFE_PWRSW_PU		15
+#define	CHIPC_RES4336_RX_PWRSW_PU		16
+#define	CHIPC_RES4336_TX_PWRSW_PU		17
+#define	CHIPC_RES4336_BB_PWRSW_PU		18
+#define	CHIPC_RES4336_SYNTH_PWRSW_PU		19
+#define	CHIPC_RES4336_MISC_PWRSW_PU		20
+#define	CHIPC_RES4336_LOGEN_PWRSW_PU		21
+#define	CHIPC_RES4336_BBPLL_PWRSW_PU		22
+#define	CHIPC_RES4336_MACPHY_CLKAVAIL		23
+#define	CHIPC_RES4336_HT_AVAIL			24
+#define	CHIPC_RES4336_RSVD			25
+
+/* 4336 chip-specific ChipStatus register bits */
+#define	CHIPC_CST4336_SPI_MODE_MASK		0x00000001
+#define	CHIPC_CST4336_SPROM_PRESENT		0x00000002
+#define	CHIPC_CST4336_OTP_PRESENT		0x00000004
+#define	CHIPC_CST4336_ARMREMAP_0		0x00000008
+#define	CHIPC_CST4336_ILPDIV_EN_MASK		0x00000010
+#define	CHIPC_CST4336_ILPDIV_EN_SHIFT		4
+#define	CHIPC_CST4336_XTAL_PD_POL_MASK		0x00000020
+#define	CHIPC_CST4336_XTAL_PD_POL_SHIFT		5
+#define	CHIPC_CST4336_LPO_SEL_MASK		0x00000040
+#define	CHIPC_CST4336_LPO_SEL_SHIFT		6
+#define	CHIPC_CST4336_RES_INIT_MODE_MASK	0x00000180
+#define	CHIPC_CST4336_RES_INIT_MODE_SHIFT	7
+#define	CHIPC_CST4336_CBUCK_MODE_MASK		0x00000600
+#define	CHIPC_CST4336_CBUCK_MODE_SHIFT		9
+
+/* 4330 resources */
+#define	CHIPC_RES4330_CBUCK_LPOM		0
+#define	CHIPC_RES4330_CBUCK_BURST		1
+#define	CHIPC_RES4330_CBUCK_LP_PWM		2
+#define	CHIPC_RES4330_CBUCK_PWM			3
+#define	CHIPC_RES4330_CLDO_PU			4
+#define	CHIPC_RES4330_DIS_INT_RESET_PD		5
+#define	CHIPC_RES4330_ILP_REQUEST		6
+#define	CHIPC_RES4330_LNLDO_PU			7
+#define	CHIPC_RES4330_LDO3P3_PU			8
+#define	CHIPC_RES4330_OTP_PU			9
+#define	CHIPC_RES4330_XTAL_PU			10
+#define	CHIPC_RES4330_ALP_AVAIL			11
+#define	CHIPC_RES4330_RADIO_PU			12
+#define	CHIPC_RES4330_BG_PU			13
+#define	CHIPC_RES4330_VREG1p4_PU_PU		14
+#define	CHIPC_RES4330_AFE_PWRSW_PU		15
+#define	CHIPC_RES4330_RX_PWRSW_PU		16
+#define	CHIPC_RES4330_TX_PWRSW_PU		17
+#define	CHIPC_RES4330_BB_PWRSW_PU		18
+#define	CHIPC_RES4330_SYNTH_PWRSW_PU		19
+#define	CHIPC_RES4330_MISC_PWRSW_PU		20
+#define	CHIPC_RES4330_LOGEN_PWRSW_PU		21
+#define	CHIPC_RES4330_BBPLL_PWRSW_PU		22
+#define	CHIPC_RES4330_MACPHY_CLKAVAIL		23
+#define	CHIPC_RES4330_HT_AVAIL			24
+#define	CHIPC_RES4330_5gRX_PWRSW_PU		25
+#define	CHIPC_RES4330_5gTX_PWRSW_PU		26
+#define	CHIPC_RES4330_5g_LOGEN_PWRSW_PU	27
+
+/* 4330 chip-specific ChipStatus register bits */
+#define	CHIPC_CST4330_CHIPMODE_SDIOD(cs)	(((cs) & 0x7) < 6)	/* SDIO || gSPI */
+#define	CHIPC_CST4330_CHIPMODE_USB20D(cs)	(((cs) & 0x7) >= 6)	/* USB || USBDA */
+#define	CHIPC_CST4330_CHIPMODE_SDIO(cs)		(((cs) & 0x4) == 0)	/* SDIO */
+#define	CHIPC_CST4330_CHIPMODE_GSPI(cs)		(((cs) & 0x6) == 4)	/* gSPI */
+#define	CHIPC_CST4330_CHIPMODE_USB(cs)		(((cs) & 0x7) == 6)	/* USB packet-oriented */
+#define	CHIPC_CST4330_CHIPMODE_USBDA(cs)	(((cs) & 0x7) == 7)	/* USB Direct Access */
+#define	CHIPC_CST4330_OTP_PRESENT		0x00000010
+#define	CHIPC_CST4330_LPO_AUTODET_EN		0x00000020
+#define	CHIPC_CST4330_ARMREMAP_0		0x00000040
+#define	CHIPC_CST4330_SPROM_PRESENT		0x00000080	/* takes priority over OTP if both set */
+#define	CHIPC_CST4330_ILPDIV_EN			0x00000100
+#define	CHIPC_CST4330_LPO_SEL			0x00000200
+#define	CHIPC_CST4330_RES_INIT_MODE_SHIFT	10
+#define	CHIPC_CST4330_RES_INIT_MODE_MASK	0x00000c00
+#define	CHIPC_CST4330_CBUCK_MODE_SHIFT		12
+#define	CHIPC_CST4330_CBUCK_MODE_MASK		0x00003000
+#define	CHIPC_CST4330_CBUCK_POWER_OK		0x00004000
+#define	CHIPC_CST4330_BB_PLL_LOCKED		0x00008000
+#define	CHIPC_SOCDEVRAM_4330_BP_ADDR		0x1E000000
+#define	CHIPC_SOCDEVRAM_4330_ARM_ADDR		0x00800000
+
+/* 4313 resources */
+#define	CHIPC_RES4313_BB_PU_RSRC		0
+#define	CHIPC_RES4313_ILP_REQ_RSRC		1
+#define	CHIPC_RES4313_XTAL_PU_RSRC		2
+#define	CHIPC_RES4313_ALP_AVAIL_RSRC		3
+#define	CHIPC_RES4313_RADIO_PU_RSRC		4
+#define	CHIPC_RES4313_BG_PU_RSRC		5
+#define	CHIPC_RES4313_VREG1P4_PU_RSRC		6
+#define	CHIPC_RES4313_AFE_PWRSW_RSRC		7
+#define	CHIPC_RES4313_RX_PWRSW_RSRC		8
+#define	CHIPC_RES4313_TX_PWRSW_RSRC		9
+#define	CHIPC_RES4313_BB_PWRSW_RSRC		10
+#define	CHIPC_RES4313_SYNTH_PWRSW_RSRC		11
+#define	CHIPC_RES4313_MISC_PWRSW_RSRC		12
+#define	CHIPC_RES4313_BB_PLL_PWRSW_RSRC		13
+#define	CHIPC_RES4313_HT_AVAIL_RSRC		14
+#define	CHIPC_RES4313_MACPHY_CLK_AVAIL_RSRC	15
+
+/* 4313 chip-specific ChipStatus register bits */
+#define	CHIPC_CST4313_SPROM_PRESENT		1
+#define	CHIPC_CST4313_OTP_PRESENT		2
+#define	CHIPC_CST4313_SPROM_OTP_SEL_MASK	0x00000002
+#define	CHIPC_CST4313_SPROM_OTP_SEL_SHIFT	0
+
+/* 4313 Chip specific ChipControl register bits */
+#define	CHIPC_CCTRL_4313_12MA_LED_DRIVE		0x00000007	/* 12 mA drive strengh for later 4313 */
+
+/* 43228 resources */
+#define	CHIPC_RES43228_NOT_USED			0
+#define	CHIPC_RES43228_ILP_REQUEST		1
+#define	CHIPC_RES43228_XTAL_PU			2
+#define	CHIPC_RES43228_ALP_AVAIL		3
+#define	CHIPC_RES43228_PLL_EN			4
+#define	CHIPC_RES43228_HT_PHY_AVAIL		5
+
+/* 43228 chipstatus  reg bits */
+#define	CHIPC_CST43228_ILP_DIV_EN		0x1
+#define	CHIPC_CST43228_OTP_PRESENT		0x2
+#define	CHIPC_CST43228_SERDES_REFCLK_PADSEL	0x4
+#define	CHIPC_CST43228_SDIO_MODE		0x8
+
+#define	CHIPC_CST43228_SDIO_OTP_PRESENT		0x10
+#define	CHIPC_CST43228_SDIO_RESET		0x20
+
+/*
+* Maximum delay for the PMU state transition in us.
+* This is an upper bound intended for spinwaits etc.
+*/
+#define	CHIPC_PMU_MAX_TRANSITION_DLY		15000
+
+/* PMU resource up transition time in ILP cycles */
+#define	CHIPC_PMURES_UP_TRANSITION		2
+
+/*
+* Register eci_inputlo bitfield values.
+* - BT packet type information bits [7:0]
+*/
+/*  [3:0] - Task (link) type */
+#define	CHIPC_BT_ACL				0x00
+#define	CHIPC_BT_SCO				0x01
+#define	CHIPC_BT_eSCO				0x02
+#define	CHIPC_BT_A2DP				0x03
+#define	CHIPC_BT_SNIFF				0x04
+#define	CHIPC_BT_PAGE_SCAN			0x05
+#define	CHIPC_BT_INQUIRY_SCAN			0x06
+#define	CHIPC_BT_PAGE				0x07
+#define	CHIPC_BT_INQUIRY			0x08
+#define	CHIPC_BT_MSS				0x09
+#define	CHIPC_BT_PARK				0x0a
+#define	CHIPC_BT_RSSISCAN			0x0b
+#define	CHIPC_BT_MD_ACL				0x0c
+#define	CHIPC_BT_MD_eSCO			0x0d
+#define	CHIPC_BT_SCAN_WITH_SCO_LINK		0x0e
+#define	CHIPC_BT_SCAN_WITHOUT_SCO_LINK		0x0f
+/* [7:4] = packet duration code */
+/* [8] - Master / Slave */
+#define	CHIPC_BT_MASTER				0
+#define	CHIPC_BT_SLAVE				1
+/* [11:9] - multi-level priority */
+#define	CHIPC_BT_LOWEST_PRIO			0x0
+#define	CHIPC_BT_HIGHEST_PRIO			0x3
+
+#endif /* _BHND_CORES_CHIPC_CHIPCREG_H_ */
diff --git a/sys/dev/bhnd/cores/chipc/chipcvar.h b/sys/dev/bhnd/cores/chipc/chipcvar.h
new file mode 100644
index 0000000000000..988224b110101
--- /dev/null
+++ b/sys/dev/bhnd/cores/chipc/chipcvar.h
@@ -0,0 +1,94 @@
+/*-
+ * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ * 
+ * $FreeBSD$
+ */
+
+#ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_
+#define _BHND_CORES_CHIPC_CHIPCVAR_H_
+
+#include "chipc.h"
+
+DECLARE_CLASS(bhnd_chipc);
+extern devclass_t bhnd_chipc_devclass;
+
+#define	CHIPC_MAX_RES	1
+#define	CHIPC_MAX_RSPEC	(CHIPC_MAX_RES+1)
+
+/* 
+ * ChipCommon device quirks / features
+ */
+enum {
+	/** No quirks */
+	CHIPC_QUIRK_NONE		= 0,
+	
+	/**
+	 * The device always provides an external SROM.
+	 */
+	CHIPC_QUIRK_ALWAYS_HAS_SPROM	= (1<<1),
+	
+	
+	/**
+	 * SROM availability must be determined through chip-specific
+	 * ChipStatus flags.
+	 */
+	CHIPC_QUIRK_SPROM_CHECK_CHIPST	= (1<<3),
+
+	/**
+	 * Use the rev22 chipstatus register format when determining SPROM
+	 * availability.
+	 */
+	CHIPC_QUIRK_SPROM_CHECK_CST_R22	= (1<<4)|CHIPC_QUIRK_SPROM_CHECK_CHIPST,
+	
+	/**
+	 * Use the rev23 chipstatus register format when determining SPROM
+	 * availability.
+	 */
+	CHIPC_QUIRK_SPROM_CHECK_CST_R23	= (1<<5)|CHIPC_QUIRK_SPROM_CHECK_CHIPST,
+
+	/**
+	 * External NAND NVRAM is supported, along with the CHIPC_CAP_NFLASH
+	 * capability flag.
+	 */
+	CHIPC_QUIRK_SUPPORTS_NFLASH	= (1<<6),
+};
+
+struct chipc_softc {
+	device_t		dev;
+
+	struct resource_spec	 rspec[CHIPC_MAX_RSPEC];
+	struct bhnd_resource	*res[CHIPC_MAX_RES];
+
+	struct bhnd_resource	*core;		/**< core registers. */
+	struct bhnd_chipid	 ccid;		/**< chip identification */
+	uint32_t		 quirks;	/**< CHIPC_QUIRK_* quirk flags */
+	uint32_t		 caps;		/**< CHIPC_CAP_* capability register flags */
+	uint32_t		 cst;		/**< CHIPC_CST* status register flags */
+};
+
+#endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */
\ No newline at end of file
diff --git a/sys/dev/bhnd/cores/pci/bhnd_pci.c b/sys/dev/bhnd/cores/pci/bhnd_pci.c
new file mode 100644
index 0000000000000..2feccd78c1335
--- /dev/null
+++ b/sys/dev/bhnd/cores/pci/bhnd_pci.c
@@ -0,0 +1,52 @@
+/*-
+ * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Broadcom Common PCI Support.
+ * 
+ * This module provides common implementation shared across the PCI/PCIe
+ * endpoint and root complex drivers.
+ */
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+
+#include "bhnd_pcivar.h"
+
+/**
+ * PCIe MDIO interface device class
+ */
+devclass_t bhnd_mdio_pci_devclass;
+
+MODULE_VERSION(bhnd_pci, 1);
+MODULE_DEPEND(bhnd_pci, pci, 1, 1, 1);
diff --git a/sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c b/sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c
new file mode 100644
index 0000000000000..c508f8cc1592b
--- /dev/null
+++ b/sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c
@@ -0,0 +1,117 @@
+/*-
+ * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Broadcom PCI-BHND Host Bridge.
+ * 
+ * This driver is used to "eat" PCI(e) cores operating in endpoint mode when
+ * they're attached to a bhndb_pci driver on the host side.
+ */
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+#include <sys/systm.h>
+
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/bhnd/bhnd.h>
+
+struct bhnd_pci_hostb_softc {
+};
+
+static int
+bhnd_pci_hostb_probe(device_t dev)
+{
+	/* Ignore non-PCI cores */
+	switch (bhnd_get_class(dev)){
+	case BHND_DEVCLASS_PCI:
+	case BHND_DEVCLASS_PCIE:
+		break;
+	default:
+		return (ENXIO);
+	}
+
+	/* Ignore PCI cores not in host bridge mode. */
+	if (!bhnd_is_hostb_device(dev))
+		return (ENXIO);
+
+	bhnd_set_generic_core_desc(dev);
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+bhnd_pci_hostb_attach(device_t dev)
+{
+	return (0);
+}
+
+static int
+bhnd_pci_hostb_detach(device_t dev)
+{
+	return (0);
+}
+
+static int
+bhnd_pci_hostb_suspend(device_t dev)
+{
+	return (0);
+}
+
+static int
+bhnd_pci_hostb_resume(device_t dev)
+{
+	return (0);
+}
+
+static device_method_t bhnd_pci_hostb_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		bhnd_pci_hostb_probe),
+	DEVMETHOD(device_attach,	bhnd_pci_hostb_attach),
+	DEVMETHOD(device_detach,	bhnd_pci_hostb_detach),
+	DEVMETHOD(device_suspend,	bhnd_pci_hostb_suspend),
+	DEVMETHOD(device_resume,	bhnd_pci_hostb_resume),
+
+	DEVMETHOD_END
+};
+
+DEFINE_CLASS_0(bhnd_pci_hostb, bhnd_pci_hostb_driver, bhnd_pci_hostb_methods, 
+    sizeof(struct bhnd_pci_hostb_softc));
+
+DRIVER_MODULE(bhnd_hostb, bhnd, bhnd_pci_hostb_driver, bhnd_hostb_devclass, 0, 0);
+
+MODULE_VERSION(bhnd_pci_hostb, 1);
+MODULE_DEPEND(bhnd_pci_hostb, pci, 1, 1, 1);
+MODULE_DEPEND(bhnd_pci_hostb, bhnd_pci, 1, 1, 1);
\ No newline at end of file
diff --git a/sys/dev/bhnd/cores/pci/bhnd_pcib.c b/sys/dev/bhnd/cores/pci/bhnd_pcib.c
new file mode 100644
index 0000000000000..8dbdcd0b653a3
--- /dev/null
+++ b/sys/dev/bhnd/cores/pci/bhnd_pcib.c
@@ -0,0 +1,127 @@
+/*-
+ * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Broadcom PCI-BHND Host Bridge.
+ * 
+ * This driver is used to "eat" PCI(e) cores operating in endpoint mode when
+ * they're attached to a bhndb_pci driver on the host side.
+ */
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/bhnd/bhnd.h>
+
+#include "bhnd_pcireg.h"
+
+#include "bhnd_pcibvar.h"
+
+static const struct bhnd_pcib_device {
+	uint16_t	 vendor;
+	uint16_t	 device;
+	const char	*desc;
+} bhnd_pcib_devs[] = {
+	{ BHND_MFGID_BCM,	BHND_COREID_PCI,	"BHND Host-PCI bridge" },
+	{ BHND_MFGID_BCM,	BHND_COREID_PCIE,	"BHND Host-PCI bridge (PCIe Gen1)" },
+	{ BHND_MFGID_INVALID,	BHND_COREID_INVALID,	NULL }
+};
+
+static int
+bhnd_pcib_probe(device_t dev)
+{
+	const struct bhnd_pcib_device *id;
+
+	/* Ignore PCI cores configured in host bridge mode */
+	if (bhnd_is_hostb_device(dev))
+		return (ENXIO);
+
+	for (id = bhnd_pcib_devs; id->device != BHND_COREID_INVALID; id++) {
+		if (bhnd_get_vendor(dev) != id->vendor)
+			continue;
+
+		if (bhnd_get_device(dev) != id->device)
+			continue;
+
+		device_set_desc(dev, id->desc);
+		return (BUS_PROBE_SPECIFIC);
+	}
+
+	return (ENXIO);
+}
+
+static int
+bhnd_pcib_attach(device_t dev)
+{
+	return (ENXIO);
+}
+
+static int
+bhnd_pcib_detach(device_t dev)
+{
+	return (ENXIO);
+}
+
+static int
+bhnd_pcib_suspend(device_t dev)
+{
+	return (ENXIO);
+}
+
+static int
+bhnd_pcib_resume(device_t dev)
+{
+	return (ENXIO);
+}
+
+static device_method_t bhnd_pcib_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		bhnd_pcib_probe),
+	DEVMETHOD(device_attach,	bhnd_pcib_attach),
+	DEVMETHOD(device_detach,	bhnd_pcib_detach),
+	DEVMETHOD(device_suspend,	bhnd_pcib_suspend),
+	DEVMETHOD(device_resume,	bhnd_pcib_resume),
+	DEVMETHOD_END
+};
+
+DEFINE_CLASS_0(bhnd_pcib, bhnd_pcib_driver, bhnd_pcib_methods, sizeof(struct bhnd_pcib_softc));
+DRIVER_MODULE(bhnd_pcib, bhnd, bhnd_pcib_driver, bhnd_hostb_devclass, 0, 0);
+
+MODULE_VERSION(bhnd_pcib, 1);
+MODULE_DEPEND(bhnd_pcib, pci, 1, 1, 1);
+MODULE_DEPEND(bhnd_pcib, bhnd_pci_mdio, 1, 1, 1);
diff --git a/sys/dev/bhnd/cores/pci/bhnd_pcibvar.h b/sys/dev/bhnd/cores/pci/bhnd_pcibvar.h
new file mode 100644
index 0000000000000..d30f74d1daf21
--- /dev/null
+++ b/sys/dev/bhnd/cores/pci/bhnd_pcibvar.h
@@ -0,0 +1,50 @@
+/*-
+ * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ * 
+ * $FreeBSD$
+ */
+
+#ifndef _BHND_CORES_PCI_BHND_PCIBVAR_H_
+#define _BHND_CORES_PCI_BHND_PCIBVAR_H_
+
+#include "bhnd_pcivar.h"
+
+/* PCI bridge driver-specific state */
+#define	BHND_PCIB_MAX_RES	2
+#define	BHND_PCIB_MAX_RSPEC	(BHND_PCIB_MAX_RES+1)
+struct bhnd_pcib_softc {
+	device_t		 dev;		/**< pci device */
+	struct bhnd_resource	*core;		/**< core registers. */
+	bhnd_pci_regfmt_t	 regfmt;	/**< device register format */
+
+	struct resource_spec	 rspec[BHND_PCIB_MAX_RSPEC];
+	struct bhnd_resource	*res[BHND_PCIB_MAX_RES];
+
+};
+
+#endif /* _BHND_CORES_PCI_BHND_PCIBVAR_H_ */
\ No newline at end of file
diff --git a/sys/dev/bhnd/cores/pci/bhnd_pcireg.h b/sys/dev/bhnd/cores/pci/bhnd_pcireg.h
new file mode 100644
index 0000000000000..e707b9c0348ae
--- /dev/null
+++ b/sys/dev/bhnd/cores/pci/bhnd_pcireg.h
@@ -0,0 +1,387 @@
+/*-
+ * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
+ * Copyright (c) 2010 Broadcom Corporation
+ * All rights reserved.
+ *
+ * This file is derived from the hndsoc.h, pci_core.h, and pcie_core.h headers
+ * distributed with Broadcom's initial brcm80211 Linux driver release, as
+ * contributed to the Linux staging repository.
+ * 
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _BHND_CORES_PCI_BHND_PCIREG_H_
+#define _BHND_CORES_PCI_BHND_PCIREG_H_
+
+/*
+ * PCI/PCIe-Gen1 DMA Constants
+ */
+
+#define	BHND_PCI_DMA32_TRANSLATION	0x40000000	/* Client Mode sb2pcitranslation2 (1 GB) */
+#define	BHND_PCI_DMA32_SZ		0x40000000	/* Client Mode sb2pcitranslation2 size in bytes */
+
+#define	BHND_PCIE_DMA32_TRANSLATION	BHND_PCI_DMA32_TRANSLATION
+#define	BHND_PCIE_DMA32_SZ		BHND_PCI_DMA32_SZ
+
+#define	BHND_PCIE_DMA64_L32		0x00000000	/**< 64-bit client mode sb2pcitranslation2 (2 ZettaBytes, low 32 bits) */
+#define	BHND_PCIE_DMA64_H32		0x80000000	/**< 64-bit client mode sb2pcitranslation2 (2 ZettaBytes, high 32 bits) */
+
+/*
+ * PCI Core Registers
+ */
+
+#define	BHND_PCI_CTL			0x000	/**< PCI core control*/
+#define	BHND_PCI_ARB_CTL		0x010	/**< PCI arbiter control */
+#define	BHND_PCI_CLKRUN_CTL		0x014	/**< PCI clckrun control (>= rev11) */
+#define	BHND_PCI_INTR_STATUS		0x020	/**< Interrupt status */
+#define	BHND_PCI_INTR_MASK		0x024	/**< Interrupt mask */
+#define	BHND_PCI_SBTOPCI_MBOX		0x028	/**< Sonics to PCI mailbox */
+#define	BHND_PCI_BCAST_ADDR		0x050	/**< Sonics broadcast address (pci) */
+#define	BHND_PCI_BCAST_DATA		0x054	/**< Sonics broadcast data (pci) */
+#define	BHND_PCI_GPIO_IN		0x060	/**< GPIO input (>= rev2) */
+#define	BHND_PCI_GPIO_OUT		0x064	/**< GPIO output (>= rev2) */
+#define	BHND_PCI_GPIO_EN		0x068	/**< GPIO output enable (>= rev2) */
+#define	BHND_PCI_GPIO_CTL		0x06C	/**< GPIO control (>= rev2) */
+#define	BHND_PCI_SBTOPCI0		0x100	/**< Sonics to PCI translation 0 */
+#define	BHND_PCI_SBTOPCI1		0x104	/**< Sonics to PCI translation 1 */
+#define	BHND_PCI_SBTOPCI2		0x108	/**< Sonics to PCI translation 2 */
+#define	BHND_PCI_FUNC0_CFG		0x400	/**< PCI function 0 cfg space (>= rev8) */
+#define	BHND_PCI_FUNC1_CFG		0x500	/**< PCI function 1 cfg space (>= rev8) */
+#define	BHND_PCI_FUNC2_CFG		0x600	/**< PCI function 2 cfg space (>= rev8) */
+#define	BHND_PCI_FUNC3_CFG		0x700	/**< PCI function 3 cfg space (>= rev8) */
+#define	BHND_PCI_SPROM_SHADOW		0x800	/**< PCI SPROM shadow */
+
+/* BHND_PCI_CTL */
+#define	BHND_PCI_CTL_RST_OE		0x01	/* When set, drives PCI_RESET out to pin */
+#define	BHND_PCI_CTL_RST		0x02	/* Value driven out to pin */
+#define	BHND_PCI_CTL_CLK_OE		0x04	/* When set, drives clock as gated by PCI_CLK out to pin */
+#define	BHND_PCI_CTL_CLK		0x08	/* Gate for clock driven out to pin */
+
+/* BHND_PCI_ARB_CTL */
+#define	BHND_PCI_ARB_INT		0x01	/* When set, use an internal arbiter */
+#define	BHND_PCI_ARB_EXT		0x02	/* When set, use an external arbiter */
+
+/* BHND_PCI_ARB_CTL - ParkID (>= rev8) */
+#define	BHND_PCI_ARB_PARKID_MASK	0x1c	/* Selects which agent is parked on an idle bus */
+#define	BHND_PCI_ARB_PARKID_SHIFT	2
+#define	BHND_PCI_ARB_PARKID_EXT0	0	/* External master 0 */
+#define	BHND_PCI_ARB_PARKID_EXT1	1	/* External master 1 */
+#define	BHND_PCI_ARB_PARKID_EXT2	2	/* External master 2 */
+#define	BHND_PCI_ARB_PARKID_EXT3	3	/* External master 3 (rev >= 11) */
+#define	BHND_PCI_ARB_PARKID_INT_r10	3	/* Internal master (rev < 11) */
+#define	BHND_PCI_ARB_PARKID_INT_r11	4	/* Internal master (rev >= 11) */
+#define	BHND_PCI_ARB_PARKID_LAST_r10	4	/* Last active master (rev < 11) */
+#define	BHND_PCI_ARB_PARKID_LAST_r11	5	/* Last active master (rev >= 11) */
+
+/* BHND_PCI_CLKRUN_CTL */
+#define	BHND_PCI_CLKRUN_DSBL		0x8000	/* Bit 15 forceClkrun */
+
+/* BHND_PCI_INTR_STATUS / BHND_PCI_INTR_MASK */
+#define	BHND_PCI_INTR_A			0x01	/* PCI INTA# is asserted */
+#define	BHND_PCI_INTR_B			0x02	/* PCI INTB# is asserted */
+#define	BHND_PCI_INTR_SERR		0x04	/* PCI SERR# has been asserted (write one to clear) */
+#define	BHND_PCI_INTR_PERR		0x08	/* PCI PERR# has been asserted (write one to clear) */
+
+/* BHND_PCI_SBTOPCI_MBOX
+ * (General) PCI/SB mailbox interrupts, two bits per pci function */
+#define	BHND_PCI_SBTOPCI_MBOX_F0_0	0x100	/* function 0, int 0 */
+#define	BHND_PCI_SBTOPCI_MBOX_F0_1	0x200	/* function 0, int 1 */
+#define	BHND_PCI_SBTOPCI_MBOX_F1_0	0x400	/* function 1, int 0 */
+#define	BHND_PCI_SBTOPCI_MBOX_F1_1	0x800	/* function 1, int 1 */
+#define	BHND_PCI_SBTOPCI_MBOX_F2_0	0x1000	/* function 2, int 0 */
+#define	BHND_PCI_SBTOPCI_MBOX_F2_1	0x2000	/* function 2, int 1 */
+#define	BHND_PCI_SBTOPCI_MBOX_F3_0	0x4000	/* function 3, int 0 */
+#define	BHND_PCI_SBTOPCI_MBOX_F3_1	0x8000	/* function 3, int 1 */
+
+/* BHND_PCI_BCAST_ADDR */
+#define	BHNC_PCI_BCAST_ADDR_MASK	0xFF	/* Broadcast register address */
+
+/* Sonics to PCI translation types */
+#define BHND_PCI_SBTOPCI0_MASK	0xfc000000
+#define BHND_PCI_SBTOPCI1_MASK	0xfc000000
+#define BHND_PCI_SBTOPCI2_MASK	0xc0000000
+
+/* Access type bits (0:1) */
+#define	BHND_PCI_SBTOPCI_MEM		0
+#define	BHND_PCI_SBTOPCI_IO		1
+#define	BHND_PCI_SBTOPCI_CFG0		2
+#define	BHND_PCI_SBTOPCI_CFG1		3
+
+#define	BHND_PCI_SBTOPCI_PREF		0x4	/* prefetch enable */
+#define	BHND_PCI_SBTOPCI_BURST		0x8	/* burst enable */
+
+#define	BHND_PCI_SBTOPCI_RC_MASK	0x30	/* read command (>= rev11) */
+#define	BHND_PCI_SBTOPCI_RC_READ	0x00	/* memory read */
+#define	BHND_PCI_SBTOPCI_RC_READLINE	0x10	/* memory read line */
+#define	BHND_PCI_SBTOPCI_RC_READMULTI	0x20	/* memory read multiple */
+
+/* PCI core index in SROM shadow area */
+#define	BHND_PCI_SRSH_PI_OFFSET		0	/* first word */
+#define	BHND_PCI_SRSH_PI_MASK		0xf000	/* bit 15:12 */
+#define	BHND_PCI_SRSH_PI_SHIFT		12	/* bit 15:12 */
+
+
+
+/*
+ * PCIe-Gen1 Core Registers
+ */
+
+#define	BHND_PCIE_CTL		BHND_PCI_CTL		/**< PCI core control*/
+#define	BHND_PCIE_BIST_STATUS	0x00C			/**< BIST status */
+#define	BHND_PCIE_GPIO_SEL	0x010			/**< GPIO select */
+#define	BHND_PCIE_GPIO_OUT_EN	0x014			/**< GPIO output enable */
+#define	BHND_PCIE_INTR_STATUS	BHND_PCI_INTR_STATUS	/**< Interrupt status */
+#define	BHND_PCIE_INTR_MASK	BHND_PCI_INTR_MASK	/**< Interrupt mask */
+#define	BHND_PCIE_SBTOPCI_MBOX	BHND_PCI_SBTOPCI_MBOX	/**< Sonics to PCI mailbox */
+#define	BHND_PCIE_SBTOPCI0	BHND_PCI_SBTOPCI0	/**< Sonics to PCI translation 0 */
+#define	BHND_PCIE_SBTOPCI1	BHND_PCI_SBTOPCI1	/**< Sonics to PCI translation 1 */
+#define	BHND_PCIE_SBTOPCI2	BHND_PCI_SBTOPCI2	/**< Sonics to PCI translation 2 */
+
+/* indirect pci config space access */
+#define	BHND_PCIE_CFG_ADDR	0x120			/**< pcie config space address */
+#define	BHND_PCIE_CFG_DATA	0x124			/**< pcie config space data */
+
+/* mdio register access */
+#define	BHND_PCIE_MDIO_CTL	0x128			/**< mdio control */
+#define	BHND_PCIE_MDIO_DATA	0x12C			/**< mdio data */
+
+/* indirect protocol phy/dllp/tlp register access */
+#define	BHND_PCIE_IND_ADDR	0x130			/**< internal protocol register address */
+#define	BHND_PCIE_IND_DATA	0x134			/**< internal protocol register data */
+
+#define	BHND_PCIE_CLKREQEN_CTL	0x138			/**< clkreq rdma control */
+#define	BHND_PCIE_FUNC0_CFG	BHND_PCI_FUNC0_CFG	/**< PCI function 0 cfg space */
+#define	BHND_PCIE_FUNC1_CFG	BHND_PCI_FUNC1_CFG	/**< PCI function 1 cfg space */
+#define	BHND_PCIE_FUNC2_CFG	BHND_PCI_FUNC2_CFG	/**< PCI function 2 cfg space */
+#define	BHND_PCIE_FUNC3_CFG	BHND_PCI_FUNC3_CFG	/**< PCI function 3 cfg space */
+#define	BHND_PCIE_SPROM_SHADOW	BHND_PCI_SPROM_SHADOW	/**< PCI SPROM shadow */
+
+/* BHND_PCIE_CTL */
+#define	BHND_PCIE_CTL_RST_OE	BHND_PCI_CTL_RST_OE	/* When set, drives PCI_RESET out to pin */
+#define	BHND_PCIE_CTL_RST	BHND_PCI_CTL_RST_OE	/* Value driven out to pin */
+
+/* BHND_PCI_INTR_STATUS / BHND_PCI_INTR_MASK */
+#define	BHND_PCIE_INTR_A	BHND_PCI_INTR_A		/* PCIE INTA message is received */
+#define	BHND_PCIE_INTR_B	BHND_PCI_INTR_B		/* PCIE INTB message is received */
+#define	BHND_PCIE_INTR_FATAL	0x04			/* PCIE INTFATAL message is received */
+#define	BHND_PCIE_INTR_NFATAL	0x08			/* PCIE INTNONFATAL message is received */
+#define	BHND_PCIE_INTR_CORR	0x10			/* PCIE INTCORR message is received */
+#define	BHND_PCIE_INTR_PME	0x20			/* PCIE INTPME message is received */
+
+/* SB to PCIE translation masks */
+#define	BHND_PCIE_SBTOPCI0_MASK	BHND_PCI_SBTOPCI0_MASK
+#define	BHND_PCIE_SBTOPCI1_MASK	BHND_PCI_SBTOPCI1_MASK
+#define	BHND_PCIE_SBTOPCI2_MASK	BHND_PCI_SBTOPCI2_MASK
+
+/* Access type bits (0:1) */
+#define	BHND_PCIE_SBTOPCI_MEM	BHND_PCI_SBTOPCI_MEM
+#define	BHND_PCIE_SBTOPCI_IO	BHND_PCI_SBTOPCI_IO
+#define	BHND_PCIE_SBTOPCI_CFG0	BHND_PCI_SBTOPCI_CFG0
+#define	BHND_PCIE_SBTOPCI_CFG1	BHND_PCI_SBTOPCI_CFG1
+
+#define	BHND_PCIE_SBTOPCI_PREF	BHND_PCI_SBTOPCI_PREF	/* prefetch enable */
+#define	BHND_PCIE_SBTOPCI_BURST	BHND_PCI_SBTOPCI_BURST	/* burst enable */
+
+/* BHND_PCIE_CFG_ADDR / BHND_PCIE_CFG_DATA */
+#define	BHND_PCIE_CFG_ADDR_FUNC_MASK	0x7000
+#define	BHND_PCIE_CFG_ADDR_FUNC_SHIFT	12
+#define	BHND_PCIE_CFG_ADDR_REG_MASK	0x0FFF
+#define	BHND_PCIE_CFG_ADDR_REG_SHIFT	0
+
+#define	BHND_PCIE_CFG_OFFSET(f, r)	\
+	((((f) & BHND_PCIE_CFG_ADDR_FUNC_MASK) << BHND_PCIE_CFG_ADDR_FUNC_SHIFT) | \
+	(((r) & BHND_PCIE_CFG_ADDR_FUNC_SHIFT) << BHND_PCIE_CFG_ADDR_REG_SHIFT))
+
+/* PCIE protocol PHY diagnostic registers */
+#define	BHND_PCIE_PLP_MODEREG			0x200	/* Mode */
+#define	BHND_PCIE_PLP_STATUSREG			0x204	/* Status */
+#define	BHND_PCIE_PLP_LTSSMCTRLREG		0x208	/* LTSSM control */
+#define	BHND_PCIE_PLP_LTLINKNUMREG		0x20c	/* Link Training Link number */
+#define	BHND_PCIE_PLP_LTLANENUMREG		0x210	/* Link Training Lane number */
+#define	BHND_PCIE_PLP_LTNFTSREG			0x214	/* Link Training N_FTS */
+#define	BHND_PCIE_PLP_ATTNREG			0x218	/* Attention */
+#define	BHND_PCIE_PLP_ATTNMASKREG		0x21C	/* Attention Mask */
+#define	BHND_PCIE_PLP_RXERRCTR			0x220	/* Rx Error */
+#define	BHND_PCIE_PLP_RXFRMERRCTR		0x224	/* Rx Framing Error */
+#define	BHND_PCIE_PLP_RXERRTHRESHREG		0x228	/* Rx Error threshold */
+#define	BHND_PCIE_PLP_TESTCTRLREG		0x22C	/* Test Control reg */
+#define	BHND_PCIE_PLP_SERDESCTRLOVRDREG		0x230	/* SERDES Control Override */
+#define	BHND_PCIE_PLP_TIMINGOVRDREG		0x234	/* Timing param override */
+#define	BHND_PCIE_PLP_RXTXSMDIAGREG		0x238	/* RXTX State Machine Diag */
+#define	BHND_PCIE_PLP_LTSSMDIAGREG		0x23C	/* LTSSM State Machine Diag */
+
+/* PCIE protocol DLLP diagnostic registers */
+#define	BHND_PCIE_DLLP_LCREG			0x100	/* Link Control */
+#define	  BHND_PCIE_DLLP_LCREG_PCIPM_EN		0x40	/* Enable PCI-PM power management */
+#define	BHND_PCIE_DLLP_LSREG			0x104	/* Link Status */
+#define	BHND_PCIE_DLLP_LAREG			0x108	/* Link Attention */
+#define	BHND_PCIE_DLLP_LAMASKREG		0x10C	/* Link Attention Mask */
+#define	BHND_PCIE_DLLP_NEXTTXSEQNUMREG		0x110	/* Next Tx Seq Num */
+#define	BHND_PCIE_DLLP_ACKEDTXSEQNUMREG		0x114	/* Acked Tx Seq Num */
+#define	BHND_PCIE_DLLP_PURGEDTXSEQNUMREG	0x118	/* Purged Tx Seq Num */
+#define	BHND_PCIE_DLLP_RXSEQNUMREG		0x11C	/* Rx Sequence Number */
+#define	BHND_PCIE_DLLP_LRREG			0x120	/* Link Replay */
+#define	BHND_PCIE_DLLP_LACKTOREG		0x124	/* Link Ack Timeout */
+#define	BHND_PCIE_DLLP_PMTHRESHREG		0x128	/* Power Management Threshold */
+#define	  BHND_PCIE_L0THRESHOLDTIME_MASK	0xFF00	/* bits 0 - 7 */
+#define	  BHND_PCIE_L1THRESHOLDTIME_MASK	0xFF00	/* bits 8 - 15 */
+#define	  BHND_PCIE_L1THRESHOLDTIME_SHIFT	8	/* PCIE_L1THRESHOLDTIME_SHIFT */
+#define	  BHND_PCIE_L1THRESHOLD_WARVAL		0x72	/* WAR value */
+#define	  BHND_PCIE_ASPMTIMER_EXTEND		0x1000000 /* > rev7: enable extend ASPM timer */
+#define	BHND_PCIE_DLLP_RTRYWPREG		0x12C	/* Retry buffer write ptr */
+#define	BHND_PCIE_DLLP_RTRYRPREG		0x130	/* Retry buffer Read ptr */
+#define	BHND_PCIE_DLLP_RTRYPPREG		0x134	/* Retry buffer Purged ptr */
+#define	BHND_PCIE_DLLP_RTRRWREG			0x138	/* Retry buffer Read/Write */
+#define	BHND_PCIE_DLLP_ECTHRESHREG		0x13C	/* Error Count Threshold */
+#define	BHND_PCIE_DLLP_TLPERRCTRREG		0x140	/* TLP Error Counter */
+#define	BHND_PCIE_DLLP_ERRCTRREG		0x144	/* Error Counter */
+#define	BHND_PCIE_DLLP_NAKRXCTRREG		0x148	/* NAK Received Counter */
+#define	BHND_PCIE_DLLP_TESTREG			0x14C	/* Test */
+#define	BHND_PCIE_DLLP_PKTBIST			0x150	/* Packet BIST */
+#define	BHND_PCIE_DLLP_PCIE11			0x154	/* DLLP PCIE 1.1 reg */
+
+#define	BHND_PCIE_DLLP_LSREG_LINKUP		(1 << 16)
+
+/* PCIE protocol TLP diagnostic registers */
+#define	BHND_PCIE_TLP_CONFIGREG			0x000	/* Configuration */
+#define	BHND_PCIE_TLP_WORKAROUNDSREG		0x004	/* TLP Workarounds */
+#define	  BHND_PCIE_TLP_WORKAROUND_URBIT	0x8	/* If enabled, UR status bit is set 
+							 * on memory access of an unmatched
+							 * address */
+
+#define	BHND_PCIE_TLP_WRDMAUPPER		0x010	/* Write DMA Upper Address */
+#define	BHND_PCIE_TLP_WRDMALOWER		0x014	/* Write DMA Lower Address */
+#define	BHND_PCIE_TLP_WRDMAREQ_LBEREG		0x018	/* Write DMA Len/ByteEn Req */
+#define	BHND_PCIE_TLP_RDDMAUPPER		0x01C	/* Read DMA Upper Address */
+#define	BHND_PCIE_TLP_RDDMALOWER		0x020	/* Read DMA Lower Address */
+#define	BHND_PCIE_TLP_RDDMALENREG		0x024	/* Read DMA Len Req */
+#define	BHND_PCIE_TLP_MSIDMAUPPER		0x028	/* MSI DMA Upper Address */
+#define	BHND_PCIE_TLP_MSIDMALOWER		0x02C	/* MSI DMA Lower Address */
+#define	BHND_PCIE_TLP_MSIDMALENREG		0x030	/* MSI DMA Len Req */
+#define	BHND_PCIE_TLP_SLVREQLENREG		0x034	/* Slave Request Len */
+#define	BHND_PCIE_TLP_FCINPUTSREQ		0x038	/* Flow Control Inputs */
+#define	BHND_PCIE_TLP_TXSMGRSREQ		0x03C	/* Tx StateMachine and Gated Req */
+#define	BHND_PCIE_TLP_ADRACKCNTARBLEN		0x040	/* Address Ack XferCnt and ARB Len */
+#define	BHND_PCIE_TLP_DMACPLHDR0		0x044	/* DMA Completion Hdr 0 */
+#define	BHND_PCIE_TLP_DMACPLHDR1		0x048	/* DMA Completion Hdr 1 */
+#define	BHND_PCIE_TLP_DMACPLHDR2		0x04C	/* DMA Completion Hdr 2 */
+#define	BHND_PCIE_TLP_DMACPLMISC0		0x050	/* DMA Completion Misc0 */
+#define	BHND_PCIE_TLP_DMACPLMISC1		0x054	/* DMA Completion Misc1 */
+#define	BHND_PCIE_TLP_DMACPLMISC2		0x058	/* DMA Completion Misc2 */
+#define	BHND_PCIE_TLP_SPTCTRLLEN		0x05C	/* Split Controller Req len */
+#define	BHND_PCIE_TLP_SPTCTRLMSIC0		0x060	/* Split Controller Misc 0 */
+#define	BHND_PCIE_TLP_SPTCTRLMSIC1		0x064	/* Split Controller Misc 1 */
+#define	BHND_PCIE_TLP_BUSDEVFUNC		0x068	/* Bus/Device/Func */
+#define	BHND_PCIE_TLP_RESETCTR			0x06C	/* Reset Counter */
+#define	BHND_PCIE_TLP_RTRYBUF			0x070	/* Retry Buffer value */
+#define	BHND_PCIE_TLP_TGTDEBUG1			0x074	/* Target Debug Reg1 */
+#define	BHND_PCIE_TLP_TGTDEBUG2			0x078	/* Target Debug Reg2 */
+#define	BHND_PCIE_TLP_TGTDEBUG3			0x07C	/* Target Debug Reg3 */
+#define	BHND_PCIE_TLP_TGTDEBUG4			0x080	/* Target Debug Reg4 */
+
+
+/*
+ * PCIe-G1 SerDes MDIO Registers (>= rev10)
+ */
+#define BHND_PCIE_PHYADDR_SD		0x0	/* serdes PHY address */
+#define	BHND_PCIE_DEVAD_SD		0x1	/* serdes pseudo-devad (PMA) recognized by
+						   the bhnd_mdio_pcie driver */
+
+#define	BHND_PCIE_SD_ADDREXT		0x1F	/* serdes address extension register */
+#define	BHND_PCIE_SD_ADDREXT_BLK_MASK	0xFFF0	/* register block mask */
+#define	BHND_PCIE_SD_ADDREXT_REG_MASK	0x000F	/* register address mask */
+
+#define	BHND_PCIE_SD_REGS_IEEE0		0x0000	/* IEEE0 AN CTRL block */
+#define	BHND_PCIE_SD_REGS_IEEE1		0x0010	/* IEEE1 AN ADV block */
+#define	BHND_PCIE_SD_REGS_BLK0		0x8000	/* ??? */
+#define	BHND_PCIE_SD_REGS_BLK1		0x8010	/* ??? */
+#define	BHND_PCIE_SD_REGS_BLK2		0x8020	/* ??? */
+#define	BHND_PCIE_SD_REGS_BLK3		0x8030	/* ??? */
+#define	BHND_PCIE_SD_REGS_BLK4		0x8040	/* ??? */
+#define	BHND_PCIE_SD_REGS_TXPLL		0x8080	/* TXPLL register block */
+#define	BHND_PCIE_SD_REGS_TXCTRL0		0x8200	/* ??? */
+#define	BHND_PCIE_SD_REGS_SERDESID		0x8310	/* ??? */
+#define	BHND_PCIE_SD_REGS_RXCTRL0		0x8400	/* ??? */
+
+/*
+ * PCIe-G1 SerDes-R9 MDIO Registers (<= rev9)
+ * 
+ * These register definitions appear to match those provided in the
+ * "PCI Express SerDes Registers" section of the BCM5761 Ethernet Controller 
+ * Programmer's Reference Guide.
+ */
+#define	BHND_PCIE_PHY_SDR9_PLL       		0x1C	/* SerDes PLL PHY Address*/
+#define	  BHND_PCIE_SDR9_PLL_CTRL		0x17	/* PLL control reg */
+#define	    BHND_PCIE_SDR9_PLL_CTRL_FREQDET_EN	0x4000	/* bit 14 is FREQDET on */
+#define	BHND_PCIE_PHY_SDR9_TXRX       	 	0x0F	/* SerDes RX/TX PHY Address */
+
+#define	BHND_PCIE_SDR9_RX_CTRL			0x11	/* RX ctrl register */
+#define	    BHND_PCIE_SDR9_RX_CTRL_FORCE	0x80	/* rxpolarity_force */
+#define	    BHND_PCIE_SDR9_RX_CTRL_POLARITY_INV	0x40	/* rxpolarity_value (if set, inverse polarity) */
+
+#define	BHND_PCIE_SDR9_RX_CDR			0x16	/* RX CDR ctrl register */
+#define	  BHND_PCIE_SDR9_RX_CDR_FREQ_OVR_EN	0x0100	/* freq_override_en flag */
+#define	  BHND_PCIE_SDR9_RX_CDR_FREQ_OVR_MASK	0x00FF	/* freq_override_val */
+#define	  BHND_PCIE_SDR9_RX_CDR_FREQ_OVR_SHIFT	0
+
+#define	BHND_PCIE_SDR9_RX_CDRBW			0x17	/* RX CDR bandwidth (PLL tuning) */
+#define	  BHND_PCIE_SDR9_RX_CDRBW_INTGTRK_MASK	0x7000	/* integral loop bandwidth (phase tracking mode) */
+#define	  BHND_PCIE_SDR9_RX_CDRBW_INTGTRK_SHIFT	11
+#define	  BHND_PCIE_SDR9_RX_CDRBW_INTGACQ_MASK	0x0700	/* integral loop bandwidth (phase acquisition mode) */
+#define	  BHND_PCIE_SDR9_RX_CDRBW_INTGACQ_SHIFT	8
+#define	  BHND_PCIE_SDR9_RX_CDRBW_PROPTRK_MASK	0x0070	/* proportional loop bandwidth (phase tracking mode) */
+#define	  BHND_PCIE_SDR9_RX_CDRBW_PROPTRK_SHIFT	4
+#define	  BHND_PCIE_SDR9_RX_CDRBW_PROPACQ_MASK	0x0007	/* proportional loop bandwidth (phase acquisition mode) */
+#define	  BHND_PCIE_SDR9_RX_CDRBW_PROPACQ_SHIFT	0
+
+#define	BHND_PCIE_SDR9_RX_TIMER1		0x12	/* timer1 register */
+#define	  BHND_PCIE_SDR9_RX_TIMER1_LKTRK_MASK	0xFF00	/* phase tracking delay before asserting RX seq completion (in 16ns units) */
+#define	  BHND_PCIE_SDR9_RX_TIMER1_LKTRK_SHIFT	8
+#define	  BHND_PCIE_SDR9_RX_TIMER1_LKACQ_MASK	0x00FF	/* phase acquisition mode time (in 1024ns units) */
+#define	  BHND_PCIE_SDR9_RX_TIMER1_LKACQ_SHIFT	0
+
+
+/* SPROM offsets */
+#define	BHND_PCIE_SRSH_PI_OFFSET		BHND_PCI_SRSH_PI_OFFSET	/**< PCI core index in SROM shadow area */
+#define	BHND_PCIE_SRSH_PI_MASK			BHND_PCI_SRSH_PI_MASK
+#define	BHND_PCIE_SRSH_PI_SHIFT			BHND_PCI_SRSH_PI_SHIFT
+
+#define	BHND_PCIE_SRSH_ASPM_OFFSET		8	/* word 4 */
+#define	BHND_PCIE_SRSH_ASPM_ENB			0x18	/* bit 3, 4 */
+#define	BHND_PCIE_SRSH_ASPM_L1_ENB		0x10	/* bit 4 */
+#define	BHND_PCIE_SRSH_ASPM_L0s_ENB		0x8	/* bit 3 */
+#define	BHND_PCIE_SRSH_PCIE_MISC_CONFIG		10	/* word 5 */
+#define	BHND_PCIE_SRSH_L23READY_EXIT_NOPRST	0x8000	/* bit 15 */
+#define	BHND_PCIE_SRSH_CLKREQ_OFFSET_REV5	40	/* word 20 for srom rev <= 5 */
+#define	BHND_PCIE_SRSH_CLKREQ_OFFSET_REV8	104	/* word 52 for srom rev 8 */
+#define	BHND_PCIE_SRSH_CLKREQ_ENB		0x0800	/* bit 11 */
+#define	BHND_PCIE_SRSH_BD_OFFSET		12	/* word 6 */
+#define	BHND_PCIE_SRSH_AUTOINIT_OFFSET		36	/* auto initialization enable */
+
+/* Linkcontrol reg offset in PCIE Cap */
+#define	BHND_PCIE_CAP_LINKCTRL_OFFSET		16	/* linkctrl offset in pcie cap */
+#define	BHND_PCIE_CAP_LCREG_ASPML0s		0x01	/* ASPM L0s in linkctrl */
+#define	BHND_PCIE_CAP_LCREG_ASPML1		0x02	/* ASPM L1 in linkctrl */
+#define	BHND_PCIE_CLKREQ_ENAB			0x100	/* CLKREQ Enab in linkctrl */
+
+#define	BHND_PCIE_ASPM_ENAB			3	/* ASPM L0s & L1 in linkctrl */
+#define	BHND_PCIE_ASPM_L1_ENAB			2	/* ASPM L0s & L1 in linkctrl */
+#define	BHND_PCIE_ASPM_L0s_ENAB			1	/* ASPM L0s & L1 in linkctrl */
+#define	BHND_PCIE_ASPM_DISAB			0	/* ASPM L0s & L1 in linkctrl */
+
+/* Status reg PCIE_PLP_STATUSREG */
+#define	BHND_PCIE_PLP_POLARITY_INV		0x10	/* lane polarity is inverted */
+
+#endif /* _BHND_CORES_PCI_BHND_PCIREG_H_ */
diff --git a/sys/dev/bhnd/cores/pci/bhnd_pcivar.h b/sys/dev/bhnd/cores/pci/bhnd_pcivar.h
new file mode 100644
index 0000000000000..070b5cbe6879e
--- /dev/null
+++ b/sys/dev/bhnd/cores/pci/bhnd_pcivar.h
@@ -0,0 +1,125 @@
+/*-
+ * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ * 
+ * $FreeBSD$
+ */
+
+#ifndef _BHND_CORES_PCI_BHND_PCIVAR_H_
+#define _BHND_CORES_PCI_BHND_PCIVAR_H_
+
+#include <sys/param.h>
+#include <sys/bus.h>
+
+/*
+ * Shared PCI Bridge/PCI Host Bridge definitions.
+ */
+
+extern devclass_t bhnd_mdio_pci_devclass;
+
+/* Device register families. */
+typedef enum {
+	BHND_PCI_REGFMT_PCI	= 0,	/* PCI register definitions */
+	BHND_PCI_REGFMT_PCIE	= 1,	/* PCIe-Gen1 register definitions */
+} bhnd_pci_regfmt_t;
+
+/* Common BHND_PCI_*_REG_(EXTRACT|INSERT) implementation */
+#define	_BHND_PCI_REG_EXTRACT(_regval, _mask, _shift)		\
+	((_regval & _mask) >> _shift)
+#define _BHND_PCI_REG_INSERT(_regval, _mask, _shift, _setval)	\
+	(((_regval) & ~ _mask) | (((_setval) << _shift) & _mask))
+
+/**
+ * Extract a register value by applying _MASK and _SHIFT defines.
+ * 
+ * @param _regv The register value containing the desired attribute
+ * @param _attr The register attribute name to which to append `_MASK`/`_SHIFT`
+ * suffixes.
+ */
+#define	BHND_PCI_REG_EXTRACT(_regv, _attr)	\
+	_BHND_PCI_REG_EXTRACT(_regv, _attr ## _MASK, _attr ## _SHIFT)
+
+/**
+ * Insert a value in @p _regv by applying _MASK and _SHIFT defines.
+ * 
+ * @param _regv The current register value.
+ * @param _attr The register attribute name to which to append `_MASK`/`_SHIFT`
+ * suffixes.
+ * @param _val The value to be set in @p _regv.
+ */
+#define	BHND_PCI_REG_INSERT(_regv, _attr, _val)		\
+	_BHND_PCI_REG_INSERT(_regv, _attr ## _MASK, _attr ## _SHIFT, _val)
+
+/**
+ * Extract a value by applying _MASK and _SHIFT defines to the common
+ * PCI/PCIe register definition @p _regv
+ * 
+ * @param _regf The PCI core register format (BHNDB_PCI_REGFMT_*).
+ * @param _regv The register value containing the desired attribute
+ * @param _attr The register attribute name to which to prepend the register
+ * definition prefix and append `_MASK`/`_SHIFT` suffixes.
+ */
+#define BHND_PCI_COMMON_REG_EXTRACT(_regf, _regv, _attr)		\
+	_BHND_PCI_REG_EXTRACT(_regv,				\
+	    BHND_PCI_COMMON_REG((_regf), _attr ## _MASK),	\
+	    BHND_PCI_COMMON_REG((_regf), _attr ## _SHIFT))
+
+/**
+ * Insert a register value by applying _MASK and _SHIFT defines to the common
+ * PCI/PCIe register definition @p _regv
+ * 
+ * @param _regf The PCI core register format (BHNDB_PCI_REGFMT_*).
+ * @param _regv The register value containing the desired attribute
+ * @param _attr The register attribute name to which to prepend the register
+ * definition prefix and append `_MASK`/`_SHIFT` suffixes.
+ * @param _val The value to bet set in @p _regv.
+ */
+#define BHND_PCI_COMMON_REG_INSERT(_regf, _regv, _attr, _val)	\
+	_BHND_PCI_REG_INSERT(_regv,				\
+	    BHND_PCI_COMMON_REG((_regf), _attr ## _MASK),	\
+	    BHND_PCI_COMMON_REG((_regf), _attr ## _SHIFT),	\
+	    _val)
+
+
+/**
+ * Evaluates to the offset of a common PCI/PCIe register definition. 
+ * 
+ * This will trigger a compile-time error if the register is not defined
+ * for all supported PCI/PCIe cores.
+ * 
+ * This should be optimized down to a constant value if the register constant
+ * is the same across the register definitions.
+ * 
+ * @param _regf The PCI core register format (BHNDB_PCI_REGFMT_*).
+ * @param _name The base name of the register.
+ */
+#define	BHND_PCI_COMMON_REG(_regf, _name)	(			\
+	(_regf) == BHND_PCI_REGFMT_PCI ? BHND_PCI_ ## _name :	\
+	BHND_PCIE_ ## _name						\
+)
+
+#endif /* _BHND_CORES_PCI_BHND_PCIVAR_H_ */
\ No newline at end of file
diff --git a/sys/dev/bhnd/cores/pci/mdio_pcie.c b/sys/dev/bhnd/cores/pci/mdio_pcie.c
new file mode 100644
index 0000000000000..1a29bcccf3178
--- /dev/null
+++ b/sys/dev/bhnd/cores/pci/mdio_pcie.c
@@ -0,0 +1,384 @@
+/*-
+ * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * MDIO Driver for PCIe-G1 Cores (All Revisions).
+ * 
+ * The MDIO interface provides access to the PCIe SerDes management registers.
+ */
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+#include <sys/systm.h>
+
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/bhnd/bhnd.h>
+
+#include "bhnd_pcireg.h"
+
+#include "mdio_pciereg.h"
+#include "mdio_pcievar.h"
+
+#define	BHND_MDIO_CTL_DELAY	10	/**< usec delay required between
+					  *  MDIO_CTL/MDIO_DATA accesses. */
+#define	BHND_MDIO_RETRY_DELAY	2000	/**< usec delay before retrying
+					  *  BHND_MDIOCTL_DONE. */
+#define	BHND_MDIO_RETRY_COUNT	200	/**< number of times to loop waiting
+					  *  for BHND_MDIOCTL_DONE. */
+
+#define	BHND_MDIO_READ_4(_sc, _reg)	\
+	bhnd_bus_read_4((_sc)->mem_res, (_sc)->mem_off + (_reg))
+
+#define	BHND_MDIO_WRITE_4(_sc, _reg, _val)		\
+	bhnd_bus_write_4((_sc)->mem_res, (_sc)->mem_off + (_reg), (_val))
+
+static int
+bhnd_mdio_pcie_probe(device_t dev)
+{
+	device_set_desc(dev, "Broadcom PCIe-G1 MDIO");
+	device_quiet(dev);
+
+	return (BUS_PROBE_DEFAULT);
+}
+
+/**
+ * Helper function that must be called by subclass BHND MDIO drivers
+ * when implementing DEVICE_ATTACH().
+ * 
+ * @param dev The bhnd_mdio device.
+ * @param mem_res A memory resource containing the device resources; this
+ * @param mem_rid The @p mem_res resource ID, or -1 if this is a borrowed
+ * reference that the device should not assume ownership of.
+ * @param offset The offset within @p mem_res at which the MMIO register
+ * block is defined.
+ * @param c22ext If true, the MDIO driver will automatically use the PCIe
+ * SerDes' non-standard extended address mechanism when handling C45 register
+ * accesses to the PCIe SerDes device (BHND_PCIE_PHYADDR_SD / 
+ * BHND_PCIE_DEVAD_SD).
+ */
+int bhnd_mdio_pcie_attach(device_t dev, struct bhnd_resource *mem_res,
+    int mem_rid, bus_size_t offset, bool c22ext)
+{
+	struct bhnd_mdio_pcie_softc *sc = device_get_softc(dev);
+
+	sc->dev = dev;
+	sc->mem_res = mem_res;
+	sc->mem_rid = mem_rid;
+	sc->mem_off = offset;
+	sc->c22ext = c22ext;
+
+	BHND_MDIO_PCIE_LOCK_INIT(sc);
+
+	return (bus_generic_attach(dev));
+}
+
+static int
+bhnd_mdio_pcie_detach(device_t dev)
+{
+	struct bhnd_mdio_pcie_softc *sc = device_get_softc(dev);
+	
+	BHND_MDIO_PCIE_LOCK_DESTROY(sc);
+
+	return (0);
+}
+
+/* Spin until the MDIO device reports itself as idle, or timeout is reached. */
+static int
+bhnd_mdio_pcie_wait_idle(struct bhnd_mdio_pcie_softc *sc)
+{
+	uint32_t ctl;
+
+	/* Spin waiting for the BUSY flag to clear */
+	for (int i = 0; i < BHND_MDIO_RETRY_COUNT; i++) {
+		ctl = BHND_MDIO_READ_4(sc, BHND_MDIO_CTL);
+		if ((ctl & BHND_MDIOCTL_DONE))
+			return (0);
+
+		DELAY(BHND_MDIO_RETRY_DELAY);
+	}
+
+	return (ETIMEDOUT);
+}
+
+
+/**
+ * Write an MDIO IOCTL and wait for completion.
+ */
+static int
+bhnd_mdio_pcie_ioctl(struct bhnd_mdio_pcie_softc *sc, uint32_t cmd)
+{
+	BHND_MDIO_PCIE_LOCK_ASSERT(sc, MA_OWNED);
+
+	BHND_MDIO_WRITE_4(sc, BHND_MDIO_CTL, cmd);
+	DELAY(BHND_MDIO_CTL_DELAY);
+	return (0);
+}
+
+/**
+ * Enable MDIO device
+ */
+static int
+bhnd_mdio_pcie_enable(struct bhnd_mdio_pcie_softc *sc)
+{
+	uint32_t ctl;
+
+	/* Enable MDIO clock and preamble mode */
+	ctl = BHND_MDIOCTL_PREAM_EN|BHND_MDIOCTL_DIVISOR_VAL;
+	return (bhnd_mdio_pcie_ioctl(sc, ctl));
+}
+
+/**
+ * Disable MDIO device.
+ */
+static void
+bhnd_mdio_pcie_disable(struct bhnd_mdio_pcie_softc *sc)
+{
+	if (bhnd_mdio_pcie_ioctl(sc, 0))
+		device_printf(sc->dev, "failed to disable MDIO clock\n");
+}
+
+
+/**
+ * Issue a write command and wait for completion
+ */
+static int
+bhnd_mdio_pcie_cmd_write(struct bhnd_mdio_pcie_softc *sc, uint32_t cmd)
+{
+	int error;
+
+	BHND_MDIO_PCIE_LOCK_ASSERT(sc, MA_OWNED);
+
+	cmd |= BHND_MDIODATA_START|BHND_MDIODATA_TA|BHND_MDIODATA_CMD_WRITE;
+
+	BHND_MDIO_WRITE_4(sc, BHND_MDIO_DATA, cmd);
+	DELAY(BHND_MDIO_CTL_DELAY);
+
+	if ((error = bhnd_mdio_pcie_wait_idle(sc)))
+		return (error);
+
+	return (0);
+}
+
+/**
+ * Issue an an MDIO read command, wait for completion, and return
+ * the result in @p data_read.
+ */
+static int
+bhnd_mdio_pcie_cmd_read(struct bhnd_mdio_pcie_softc *sc, uint32_t cmd,
+    uint16_t *data_read)
+{
+	int error;
+
+	BHND_MDIO_PCIE_LOCK_ASSERT(sc, MA_OWNED);
+
+	cmd |= BHND_MDIODATA_START|BHND_MDIODATA_TA|BHND_MDIODATA_CMD_READ;
+	BHND_MDIO_WRITE_4(sc, BHND_MDIO_DATA, cmd);
+	DELAY(BHND_MDIO_CTL_DELAY);
+
+	if ((error = bhnd_mdio_pcie_wait_idle(sc)))
+		return (error);
+
+	*data_read = (BHND_MDIO_READ_4(sc, BHND_MDIO_DATA) & 
+	    BHND_MDIODATA_DATA_MASK);
+	return (0);
+}
+
+
+static int
+bhnd_mdio_pcie_read(device_t dev, int phy, int reg)
+{
+	struct bhnd_mdio_pcie_softc	*sc;
+	uint32_t			 cmd;
+	uint16_t			 val;
+	int				 error;
+
+	sc = device_get_softc(dev);
+
+	/* Enable MDIO access */
+	BHND_MDIO_PCIE_LOCK(sc);
+	bhnd_mdio_pcie_enable(sc);
+
+	/* Issue the read */
+	cmd = BHND_MDIODATA_ADDR(phy, reg);
+	error = bhnd_mdio_pcie_cmd_read(sc, cmd, &val);
+
+	/* Disable MDIO access */
+	bhnd_mdio_pcie_disable(sc);
+	BHND_MDIO_PCIE_UNLOCK(sc);
+
+	if (error)
+		return (~0U);
+
+	return (val);
+}
+
+static int
+bhnd_mdio_pcie_write(device_t dev, int phy, int reg, int val)
+{
+	struct bhnd_mdio_pcie_softc	*sc;
+	uint32_t			 cmd;
+	int				 error;
+
+	sc = device_get_softc(dev);
+
+	/* Enable MDIO access */
+	BHND_MDIO_PCIE_LOCK(sc);
+	bhnd_mdio_pcie_enable(sc);
+
+	/* Issue the write */
+	cmd = BHND_MDIODATA_ADDR(phy, reg) | (val & BHND_MDIODATA_DATA_MASK);
+	error = bhnd_mdio_pcie_cmd_write(sc, cmd);
+
+	/* Disable MDIO access */
+	bhnd_mdio_pcie_disable(sc);
+	BHND_MDIO_PCIE_UNLOCK(sc);
+
+	return (error);
+}
+
+static int
+bhnd_mdio_pcie_read_ext(device_t dev, int phy, int devaddr, int reg)
+{
+	struct bhnd_mdio_pcie_softc	*sc;
+	uint32_t			 cmd;
+	uint16_t			 blk, val;
+	uint8_t				 blk_reg;
+	int				 error;
+
+	if (devaddr == MDIO_DEVADDR_NONE)
+		return (MDIO_READREG(dev, phy, reg));
+
+	sc = device_get_softc(dev);
+
+	/* Extended register access is only supported for the SerDes device,
+	 * using the non-standard C22 extended address mechanism */
+	if (!sc->c22ext)
+		return (~0U);	
+	if (phy != BHND_PCIE_PHYADDR_SD || devaddr != BHND_PCIE_DEVAD_SD)
+		return (~0U);
+
+	/* Enable MDIO access */
+	BHND_MDIO_PCIE_LOCK(sc);
+	bhnd_mdio_pcie_enable(sc);
+
+	/* Determine the block and register values */
+	blk = (reg & BHND_PCIE_SD_ADDREXT_BLK_MASK);
+	blk_reg = (reg & BHND_PCIE_SD_ADDREXT_REG_MASK);
+
+	/* Write the block address to the address extension register */
+	cmd = BHND_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) |
+	    (blk & BHND_MDIODATA_DATA_MASK);
+	if ((error = bhnd_mdio_pcie_cmd_write(sc, cmd)))
+		goto cleanup;
+
+	/* Issue the read */
+	cmd = BHND_MDIODATA_ADDR(phy, blk_reg);
+	error = bhnd_mdio_pcie_cmd_read(sc, cmd, &val);
+
+cleanup:
+	bhnd_mdio_pcie_disable(sc);
+	BHND_MDIO_PCIE_UNLOCK(sc);
+
+	if (error)
+		return (~0U);
+
+	return (val);
+}
+
+static int
+bhnd_mdio_pcie_write_ext(device_t dev, int phy, int devaddr, int reg,
+    int val)
+{	
+	struct bhnd_mdio_pcie_softc	*sc;
+	uint32_t			 cmd;
+	uint16_t			 blk;
+	uint8_t				 blk_reg;
+	int				 error;
+
+	if (devaddr == MDIO_DEVADDR_NONE)
+		return (MDIO_READREG(dev, phy, reg));
+
+	sc = device_get_softc(dev);
+
+	/* Extended register access is only supported for the SerDes device,
+	 * using the non-standard C22 extended address mechanism */
+	if (!sc->c22ext)
+		return (~0U);	
+	if (phy != BHND_PCIE_PHYADDR_SD || devaddr != BHND_PCIE_DEVAD_SD)
+		return (~0U);
+
+	/* Enable MDIO access */
+	BHND_MDIO_PCIE_LOCK(sc);
+	bhnd_mdio_pcie_enable(sc);
+
+	/* Determine the block and register values */
+	blk = (reg & BHND_PCIE_SD_ADDREXT_BLK_MASK);
+	blk_reg = (reg & BHND_PCIE_SD_ADDREXT_REG_MASK);
+
+	/* Write the block address to the address extension register */
+	cmd = BHND_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) |
+	    (blk & BHND_MDIODATA_DATA_MASK);
+	if ((error = bhnd_mdio_pcie_cmd_write(sc, cmd)))
+		goto cleanup;
+
+	/* Issue the write */
+	cmd = BHND_MDIODATA_ADDR(phy, blk_reg) |
+	    (val & BHND_MDIODATA_DATA_MASK);
+	error = bhnd_mdio_pcie_cmd_write(sc, cmd);
+
+cleanup:
+	bhnd_mdio_pcie_disable(sc);
+	BHND_MDIO_PCIE_UNLOCK(sc);
+
+	return (error);
+}
+
+static device_method_t bhnd_mdio_pcie_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		bhnd_mdio_pcie_probe),
+	DEVMETHOD(device_detach,	bhnd_mdio_pcie_detach),
+
+	/* MDIO interface */
+	DEVMETHOD(mdio_readreg,		bhnd_mdio_pcie_read),
+	DEVMETHOD(mdio_writereg,	bhnd_mdio_pcie_write),
+	DEVMETHOD(mdio_readextreg,	bhnd_mdio_pcie_read_ext),
+	DEVMETHOD(mdio_writeextreg,	bhnd_mdio_pcie_write_ext),
+
+	DEVMETHOD_END
+};
+
+DEFINE_CLASS_0(bhnd_mdio_pcie, bhnd_mdio_pcie_driver, bhnd_mdio_pcie_methods, sizeof(struct bhnd_mdio_pcie_softc));
diff --git a/sys/dev/bhnd/cores/pci/mdio_pciereg.h b/sys/dev/bhnd/cores/pci/mdio_pciereg.h
new file mode 100644
index 0000000000000..293b137071e9d
--- /dev/null
+++ b/sys/dev/bhnd/cores/pci/mdio_pciereg.h
@@ -0,0 +1,57 @@
+/*-
+ * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
+ * Copyright (c) 2010 Broadcom Corporation
+ * All rights reserved.
+ *
+ * This file is derived from the pcie_core.h header distributed with Broadcom's
+ * initial brcm80211 Linux driver release, as contributed to the Linux staging
+ * repository.
+ * 
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _BHND_CORES_PCI_MDIO_PCIEREG_H_
+#define _BHND_CORES_PCI_MDIO_PCIEREG_H_
+
+/* MDIO register offsets */
+#define	BHND_MDIO_CTL			0x0	/**< mdio control */
+#define	BHND_MDIO_DATA			0x4	/**< mdio data */
+
+/* MDIO control */
+#define	BHND_MDIOCTL_DIVISOR_MASK	0x7f	/* clock divisor mask */
+#define	BHND_MDIOCTL_DIVISOR_VAL	0x2	/* default clock divisor */
+#define	BHND_MDIOCTL_PREAM_EN		0x80	/* enable preamble mode */
+#define	BHND_MDIOCTL_DONE		0x100	/* tranaction completed */
+
+/* MDIO Data */
+#define	BHND_MDIODATA_PHYADDR_MASK	0x0f800000	/* phy addr */
+#define	BHND_MDIODATA_PHYADDR_SHIFT	23
+#define	BHND_MDIODATA_REGADDR_MASK	0x007c0000	/* reg/dev addr */
+#define	BHND_MDIODATA_REGADDR_SHIFT	18
+#define	BHND_MDIODATA_DATA_MASK		0x0000ffff	/* data  */
+
+#define	BHND_MDIODATA_TA		0x00020000	/* slave turnaround time */
+#define	BHND_MDIODATA_START		0x40000000	/* start of transaction */
+#define	BHND_MDIODATA_CMD_WRITE		0x10000000	/* write command */
+#define	BHND_MDIODATA_CMD_READ		0x20000000	/* read command */
+
+#define	BHND_MDIODATA_ADDR(_phyaddr, _regaddr)	(		\
+	(((_phyaddr) << BHND_MDIODATA_PHYADDR_SHIFT) &	\
+	    BHND_MDIODATA_PHYADDR_MASK) |		\
+	(((_regaddr) << BHND_MDIODATA_REGADDR_SHIFT) &	\
+	    BHND_MDIODATA_REGADDR_MASK)			\
+)
+
+#endif /* _BHND_CORES_PCI_MDIO_PCIEREG_H_ */
diff --git a/sys/dev/bhnd/cores/pci/mdio_pcievar.h b/sys/dev/bhnd/cores/pci/mdio_pcievar.h
new file mode 100644
index 0000000000000..40b3ff2bacd60
--- /dev/null
+++ b/sys/dev/bhnd/cores/pci/mdio_pcievar.h
@@ -0,0 +1,69 @@
+/*-
+ * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ * 
+ * $FreeBSD$
+ */
+
+#ifndef _BHND_CORES_PCI_MDIO_PCIEVAR_H_
+#define _BHND_CORES_PCI_MDIO_PCIEVAR_H_
+
+#include <dev/mdio/mdio.h>
+#include "mdio_if.h"
+
+DECLARE_CLASS(bhnd_mdio_pcie_driver);
+
+int bhnd_mdio_pcie_attach(device_t dev, struct bhnd_resource *mem_res,
+    int mem_rid, bus_size_t offset, bool c22ext);
+
+struct bhnd_mdio_pcie_softc {
+	device_t		 dev;		/**< mdio device */
+	struct mtx		 sc_mtx;	/**< mdio register lock */
+
+	struct bhnd_resource	*mem_res;	/**< parent pcie registers */
+	int			 mem_rid;	/**< MDIO register resID, or
+						     -1 if mem_res reference is
+						     borrowed. */
+	bus_size_t		 mem_off;	/**< mdio register offset */
+
+	bool			 c22ext;	/**< automatically rewrite C45
+						     register requests made
+						     to the PCIe SerDes slave
+						     to use its non-standard
+						     C22 address extension
+						     mechanism. */
+};
+
+#define	BHND_MDIO_PCIE_LOCK_INIT(sc) \
+	mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
+	    "bhnd_pci_mdio register lock", MTX_DEF)
+#define	BHND_MDIO_PCIE_LOCK(sc)			mtx_lock(&(sc)->sc_mtx)
+#define	BHND_MDIO_PCIE_UNLOCK(sc)		mtx_unlock(&(sc)->sc_mtx)
+#define	BHND_MDIO_PCIE_LOCK_ASSERT(sc, what)	mtx_assert(&(sc)->sc_mtx, what)
+#define	BHND_MDIO_PCIE_LOCK_DESTROY(sc)		mtx_destroy(&(sc)->sc_mtx)
+
+#endif /* _BHND_CORES_PCI_MDIO_PCIEVAR_H_ */