27 files changed, 46 insertions, 118 deletions

diff --git a/sys/dev/bhnd/cores/chipc/chipc.c b/sys/dev/bhnd/cores/chipc/chipc.c
index 29ed561a7cd04..1449c3b565dc6 100644
--- a/sys/dev/bhnd/cores/chipc/chipc.c
+++ b/sys/dev/bhnd/cores/chipc/chipc.c
@@ -79,7 +79,6 @@ static const struct bhnd_device chipc_devices[] = {
 	BHND_DEVICE_END
 };
 
-
 /* Device quirks table */
 static struct bhnd_device_quirk chipc_quirks[] = {
 	/* HND OTP controller revisions */
@@ -90,7 +89,7 @@ static struct bhnd_device_quirk chipc_quirks[] = {
 	/* IPX OTP controller revisions */
 	BHND_CORE_QUIRK	(HWREV_EQ (21),		CHIPC_QUIRK_OTP_IPX),
 	BHND_CORE_QUIRK	(HWREV_GTE(23),		CHIPC_QUIRK_OTP_IPX),
-	
+
 	BHND_CORE_QUIRK	(HWREV_GTE(32),		CHIPC_QUIRK_SUPPORTS_SPROM),
 	BHND_CORE_QUIRK	(HWREV_GTE(35),		CHIPC_QUIRK_SUPPORTS_CAP_EXT),
 	BHND_CORE_QUIRK	(HWREV_GTE(49),		CHIPC_QUIRK_IPX_OTPL_SIZE),
@@ -225,7 +224,7 @@ chipc_attach(device_t dev)
 		goto failed;
 
 	return (0);
-	
+
 failed:
 	device_delete_children(sc->dev);
 
@@ -521,7 +520,6 @@ chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps)
 		caps->flash_type = CHIPC_NFLASH_4706;
 	}
 
-
 	/* Determine NVRAM source. Must occur after the SPROM/OTP/flash
 	 * capability flags have been populated. */
 	caps->nvram_src = chipc_find_nvram_src(sc, caps);
@@ -674,7 +672,6 @@ chipc_get_resource_list(device_t dev, device_t child)
 	return (&dinfo->resources);
 }
 
-
 /* Allocate region records for the given port, and add the port's memory
  * range to the mem_rman */
 static int
@@ -971,7 +968,7 @@ chipc_adjust_resource(device_t dev, device_t child, int type,
 	struct chipc_softc		*sc;
 	struct chipc_region		*cr;
 	struct rman			*rm;
-	
+
 	sc = device_get_softc(dev);
 
 	/* Handled by parent bus? */
@@ -985,7 +982,7 @@ chipc_adjust_resource(device_t dev, device_t child, int type,
 	cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
 	if (cr == NULL)
 		return (EINVAL);
-	
+
 	if (end <= start)
 		return (EINVAL);
 
@@ -1031,7 +1028,7 @@ chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type,
 	cr = chipc_find_region(sc, r_start, r_end);
 	if (cr == NULL)
 		return (EINVAL);
-	
+
 	/* Calculate subregion offset within the chipc region */
 	cr_offset = r_start - cr->cr_addr;
 
@@ -1070,7 +1067,7 @@ chipc_activate_bhnd_resource(device_t dev, device_t child, int type,
 	int			 error;
 
 	sc = device_get_softc(dev);
-	
+
 	/* Delegate non-locally managed resources to parent */
 	rm = chipc_get_rman(sc, type);
 	if (rm == NULL || !rman_is_region_manager(r->res, rm)) {
@@ -1267,7 +1264,6 @@ chipc_disable_sprom(device_t dev)
 		break;
 	}
 
-
 	CHIPC_UNLOCK(sc);
 }
 
diff --git a/sys/dev/bhnd/cores/chipc/chipc_cfi.c b/sys/dev/bhnd/cores/chipc/chipc_cfi.c
index 20a5ae9d3e5b0..0602893d90277 100644
--- a/sys/dev/bhnd/cores/chipc/chipc_cfi.c
+++ b/sys/dev/bhnd/cores/chipc/chipc_cfi.c
@@ -78,7 +78,6 @@ static device_method_t chipc_cfi_methods[] = {
 	DEVMETHOD(device_probe,		chipc_cfi_probe),
 	DEVMETHOD(device_attach,	chipc_cfi_attach),
 	DEVMETHOD(device_detach,	cfi_detach),
-
 	{0, 0}
 };
 
diff --git a/sys/dev/bhnd/cores/chipc/chipc_gpio.c b/sys/dev/bhnd/cores/chipc/chipc_gpio.c
index 4d13d66379904..9123531d3ab6f 100644
--- a/sys/dev/bhnd/cores/chipc/chipc_gpio.c
+++ b/sys/dev/bhnd/cores/chipc/chipc_gpio.c
@@ -75,7 +75,6 @@ static chipc_gpio_pin_mode	chipc_gpio_pin_get_mode(
 				    struct chipc_gpio_softc *sc,
 				    uint32_t pin_num);
 
-
 /* Debugging flags */
 static u_long chipc_gpio_debug = 0;
 TUNABLE_ULONG("hw.bhnd_chipc.gpio_debug", &chipc_gpio_debug);
@@ -430,7 +429,7 @@ chipc_gpio_pin_getname(device_t dev, uint32_t pin_num, char *name)
 
 	if (ret >= GPIOMAXNAME)
 		return (ENOMEM);
-	
+
 	return (0);
 }
 
@@ -440,7 +439,7 @@ chipc_gpio_pin_setflags(device_t dev, uint32_t pin_num, uint32_t flags)
 	struct chipc_gpio_softc		*sc;
 	struct chipc_gpio_update	 upd;
 	int				 error;
-	
+
 	sc = device_get_softc(dev);
 
 	if (!CC_GPIO_VALID_PIN(pin_num))
@@ -548,7 +547,7 @@ chipc_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
 	struct chipc_gpio_softc		*sc;
 	struct chipc_gpio_update	 upd;
 	int				 error;
-	
+
 	sc = device_get_softc(dev);
 
 	if (!CC_GPIO_VALID_PINS(first_pin, num_pins))
@@ -580,7 +579,6 @@ chipc_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
 	return (error);
 }
 
-
 /**
  * Commit a single @p reg register update.
  */
@@ -742,7 +740,7 @@ chipc_gpio_check_flags(struct chipc_gpio_softc *sc, uint32_t pin_num,
 			/* Check for unhandled flags */
 			if ((flags & ~(mode_flag | output_flag)) != 0)
 				return (EINVAL);
-	
+
 			*mode = CC_GPIO_PIN_OUTPUT;
 			return (0);
 
diff --git a/sys/dev/bhnd/cores/chipc/chipc_subr.c b/sys/dev/bhnd/cores/chipc/chipc_subr.c
index ea182894f000c..03c9851d73e18 100644
--- a/sys/dev/bhnd/cores/chipc/chipc_subr.c
+++ b/sys/dev/bhnd/cores/chipc/chipc_subr.c
@@ -213,7 +213,6 @@ chipc_set_irq_resource(struct chipc_softc *sc, device_t child, int rid,
 	return (0);
 }
 
-
 /**
  * Add a SYS_RES_MEMORY resource with a given resource ID, relative to the
  * given port and region, to @p child's resource list.
@@ -275,7 +274,6 @@ chipc_set_mem_resource(struct chipc_softc *sc, device_t child, int rid,
 	    region_addr + start, count));
 }
 
-
 /*
  * Print a capability structure.
  */
@@ -486,7 +484,6 @@ chipc_retain_region(struct chipc_softc *sc, struct chipc_region *cr, int flags)
 		cr->cr_refs++;
 	}
 
-
 	/* Handle activation */
 	if (flags & RF_ACTIVE) {
 		KASSERT(cr->cr_refs > 0,
diff --git a/sys/dev/bhnd/cores/chipc/chipcreg.h b/sys/dev/bhnd/cores/chipc/chipcreg.h
index 4ad6fcf9d357d..6c48ac20089d3 100644
--- a/sys/dev/bhnd/cores/chipc/chipcreg.h
+++ b/sys/dev/bhnd/cores/chipc/chipcreg.h
@@ -49,7 +49,6 @@
 #define	CHIPC_GET_BITS(_value, _field)	\
 	((_value & _field ## _MASK) >> _field ## _SHIFT)
 
-
 #define	CHIPC_ID			0x00
 #define	CHIPC_CAPABILITIES		0x04
 #define	CHIPC_CORECTRL			0x08	/* rev >= 1 */
@@ -115,7 +114,7 @@
 #define	CHIPC_PLL_ON_DELAY		0xB0	/* rev >= 4 */
 #define	CHIPC_PLL_FREFSEL_DELAY		0xB4	/* rev >= 4 */
 #define	CHIPC_PLL_SLOWCLK_CTL		0xB8	/* "slowclock" (rev 6-9) */
- 
+
  /* "instaclock" clock control registers */
 #define	CHIPC_SYS_CLK_CTL		0xC0	/* "instaclock" (rev >= 10) */
 #define	CHIPC_SYS_CLK_ST_STRETCH	0xC4	/* state strech (?) rev >= 10 */
@@ -266,7 +265,6 @@ enum {
 	CHIPC_CST_OTP_PWRDN	= 3	/**< OTP is powered down, SPROM is present (rev <= 22 only) */
 };
 
-
 #define	CHIPC_CST_SPROM_OTP_SEL_R22_MASK	0x00000003	/**< chipstatus OTP/SPROM SEL value (rev 22) */
 #define	CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT	0
 #define	CHIPC_CST_SPROM_OTP_SEL_R23_MASK	0x000000c0	/**< chipstatus OTP/SPROM SEL value (revs 23-31)
@@ -782,7 +780,6 @@ enum {
 #define	CHIPC_CST4312_SPROM_OTP_SEL_MASK	CHIPC_CST_SPROM_OTP_SEL_R22_MASK
 #define	CHIPC_CST4312_SPROM_OTP_SEL_SHIFT	CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT
 
-
 /* 4322 chip-specific ChipStatus register bits */
 #define	CHIPC_CST4322_XTAL_FREQ_20_40MHZ	0x00000020
 #define	CHIPC_CST4322_SPROM_OTP_SEL_MASK	CHIPC_CST_SPROM_OTP_SEL_R23_MASK
diff --git a/sys/dev/bhnd/cores/chipc/chipcvar.h b/sys/dev/bhnd/cores/chipc/chipcvar.h
index 7da0d9bf9bcb4..a7ae1259aa4dd 100644
--- a/sys/dev/bhnd/cores/chipc/chipcvar.h
+++ b/sys/dev/bhnd/cores/chipc/chipcvar.h
@@ -60,7 +60,7 @@ const char	*chipc_sflash_device_name(chipc_flash type);
 enum {
 	/** No quirks */
 	CHIPC_QUIRK_NONE			= 0,
-	
+
 	/**
 	 * ChipCommon-controlled SPROM/OTP is supported, along with the
 	 * CHIPC_CAP_SPROM capability flag.
@@ -78,7 +78,7 @@ enum {
 	 * to allow reading/writing.
 	 */
 	CHIPC_QUIRK_MUX_SPROM			= (1<<3),
-	
+
 	/**
 	 * Access to the SPROM uses pins shared with the 802.11a external PA.
 	 * 
@@ -109,7 +109,6 @@ enum {
 	 */
 	CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM	= (1<<6) |
 	    CHIPC_QUIRK_4331_EXTPA_MUX_SPROM,
-	
 
 	/**
 	 * SPROM pins are muxed with the FEM control lines on this 4360-family
diff --git a/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl.c b/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl.c
index 1858357dab5ed..586e8a667ff37 100644
--- a/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl.c
+++ b/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl.c
@@ -68,7 +68,6 @@ static int	bhnd_pwrctl_updateclk(struct bhnd_pwrctl_softc *sc,
 
 static struct bhnd_device_quirk pwrctl_quirks[];
 
-
 /* Supported parent core device identifiers */
 static const struct bhnd_device pwrctl_devices[] = {
 	BHND_DEVICE(BCM, CC, "ChipCommon Power Control", pwrctl_quirks),
@@ -472,7 +471,6 @@ bhnd_pwrctl_request_clock(device_t dev, device_t child, bhnd_clock clock)
 	return (error);
 }
 
-
 static device_method_t bhnd_pwrctl_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,				bhnd_pwrctl_probe),
diff --git a/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c b/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
index 4a280632c52e3..3787dda1c8cc3 100644
--- a/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
+++ b/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c
@@ -539,7 +539,7 @@ bhnd_pwrctl_setclk(struct bhnd_pwrctl_softc *sc, bhnd_clock clock)
 			scc &= ~(CHIPC_SCC_FS | CHIPC_SCC_IP | CHIPC_SCC_XC);
 			if ((scc & CHIPC_SCC_SS_MASK) != CHIPC_SCC_SS_XTAL)
 				scc |= CHIPC_SCC_XC;
-	
+
 			bhnd_bus_write_4(sc->res, CHIPC_PLL_SLOWCLK_CTL, scc);
 
 			/* for dynamic control, we have to release our xtal_pu
diff --git a/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctlvar.h b/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctlvar.h
index 2952bbf7ee9ca..8d3c93ae22a1c 100644
--- a/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctlvar.h
+++ b/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctlvar.h
@@ -71,8 +71,7 @@ enum {
 	 * Dynamic clock control is not supported on these devices.
 	 */
 	PWRCTL_QUIRK_PCICLK_CTL		= (1 << 1) | PWRCTL_QUIRK_FIXED_CLK,
-	
-	
+
 	/**
 	 * On earliy BCM4311, BCM4321, and BCM4716 PCI(e) devices, no ALP
 	 * clock is available, and the HT clock must be enabled.
@@ -83,7 +82,7 @@ enum {
 	 * ChipCommon revisions 6-9 use the slowclk register layout.
 	 */
 	PWRCTL_QUIRK_SLOWCLK_CTL	= (1 << 3),
-	
+
 	/**
 	 * ChipCommon revisions 10-19 support the instaclk register layout.
 	 */
@@ -100,7 +99,6 @@ struct bhnd_pwrctl_clkres {
 	STAILQ_ENTRY(bhnd_pwrctl_clkres) cr_link;
 };
 
-
 /**
  * bhnd pwrctl driver instance state.
  */
diff --git a/sys/dev/bhnd/cores/pci/bhnd_pci.c b/sys/dev/bhnd/cores/pci/bhnd_pci.c
index a19c0c254b141..06aba31f40134 100644
--- a/sys/dev/bhnd/cores/pci/bhnd_pci.c
+++ b/sys/dev/bhnd/cores/pci/bhnd_pci.c
@@ -82,7 +82,6 @@ static const struct bhnd_pci_device {
 	BHND_PCI_DEV(PCI,	"PCI-BHND bridge",		BHND_DF_SOC),
 	BHND_PCI_DEV(PCIE,	"PCIe-G1 Host-PCI bridge",	BHND_DF_HOSTB),
 	BHND_PCI_DEV(PCIE,	"PCIe-G1 PCI-BHND bridge",	BHND_DF_SOC),
-
 	{ BHND_DEVICE_END, 0 }
 };
 
@@ -168,7 +167,7 @@ bhnd_pci_generic_detach(device_t dev)
 		return (error);
 
 	bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
-	
+
 	BHND_PCI_LOCK_DESTROY(sc);
 
 	return (0);
@@ -191,7 +190,7 @@ bhnd_pci_add_child(device_t dev, u_int order, const char *name, int unit)
 {
 	struct bhnd_pci_devinfo	*dinfo;
 	device_t		 child;
-	
+
 	child = device_add_child_ordered(dev, order, name, unit);
 	if (child == NULL)
 		return (NULL);
@@ -203,7 +202,7 @@ bhnd_pci_add_child(device_t dev, u_int order, const char *name, int unit)
 	}
 
 	resource_list_init(&dinfo->resources);
-	
+
 	device_set_ivars(child, dinfo);
 	return (child);
 }
@@ -295,7 +294,6 @@ bhnd_pcie_mdio_wait_idle(struct bhnd_pci_softc *sc)
 	return (ETIMEDOUT);
 }
 
-
 /**
  * Write an MDIO IOCTL and wait for completion.
  */
@@ -334,7 +332,6 @@ bhnd_pcie_mdio_disable(struct bhnd_pci_softc *sc)
 		device_printf(sc->dev, "failed to disable MDIO clock\n");
 }
 
-
 /**
  * Issue a write command and wait for completion
  */
@@ -380,7 +377,6 @@ bhnd_pcie_mdio_cmd_read(struct bhnd_pci_softc *sc, uint32_t cmd,
 	return (0);
 }
 
-
 int
 bhnd_pcie_mdio_read(struct bhnd_pci_softc *sc, int phy, int reg)
 {
@@ -530,7 +526,7 @@ static device_method_t bhnd_pci_methods[] = {
 	DEVMETHOD(bus_deactivate_resource,      bus_generic_deactivate_resource),
 	DEVMETHOD(bus_adjust_resource,          bus_generic_adjust_resource),
 	DEVMETHOD(bus_release_resource,		bus_generic_rl_release_resource),
-	
+
 	DEVMETHOD_END
 };
 
diff --git a/sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c b/sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c
index 66881b9965aae..0e2786f6af120 100644
--- a/sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c
+++ b/sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c
@@ -173,7 +173,6 @@ static const struct bhnd_device_quirk bhnd_pcie_quirks[] = {
 	BHND_DEVICE_QUIRK_END
 };
 
-
 #define	BHND_PCI_SOFTC(_sc)	(&((_sc)->common))
 
 #define	BHND_PCI_READ_2(_sc, _reg)		\
@@ -184,7 +183,7 @@ static const struct bhnd_device_quirk bhnd_pcie_quirks[] = {
 
 #define	BHND_PCI_WRITE_2(_sc, _reg, _val)	\
 	bhnd_bus_write_2(BHND_PCI_SOFTC(_sc)->mem_res, (_reg), (_val))
-	
+
 #define	BHND_PCI_WRITE_4(_sc, _reg, _val)	\
 	bhnd_bus_write_4(BHND_PCI_SOFTC(_sc)->mem_res, (_reg), (_val))
 
@@ -193,7 +192,7 @@ static const struct bhnd_device_quirk bhnd_pcie_quirks[] = {
 
 #define	BHND_PCI_PROTO_WRITE_4(_sc, _reg, _val)	\
 	bhnd_pcie_write_proto_reg(BHND_PCI_SOFTC(_sc), (_reg), (_val))
-	
+
 #define	BHND_PCI_MDIO_READ(_sc, _phy, _reg)	\
 	bhnd_pcie_mdio_read(BHND_PCI_SOFTC(_sc), (_phy), (_reg))
 
@@ -252,7 +251,7 @@ bhnd_pci_hostb_attach(device_t dev)
 		goto failed;
 
 	return (0);
-	
+
 failed:
 	bhnd_pci_generic_detach(dev);
 	return (error);
@@ -406,12 +405,12 @@ bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc, bhnd_pci_war_state state)
 	/* Disable PCI CLKRUN# */
 	if (sc->quirks & BHND_PCI_QUIRK_CLKRUN_DSBL) {
 		uint32_t ctl;
-	
+
 		ctl = BHND_PCI_READ_4(sc, BHND_PCI_CLKRUN_CTL);
 		ctl |= BHND_PCI_CLKRUN_DSBL;
 		BHND_PCI_WRITE_4(sc, BHND_PCI_CLKRUN_CTL, ctl);
 	}
-	
+
 	/* Enable TLP unmatched address handling work-around */
 	if (sc->quirks & BHND_PCIE_QUIRK_UR_STATUS_FIX) {
 		uint32_t wrs;
@@ -476,7 +475,7 @@ bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc, bhnd_pci_war_state state)
 		BHND_PCI_MDIO_WRITE(sc, BHND_PCIE_PHY_SDR9_PLL,
 		    BHND_PCIE_SDR9_PLL_CTRL, pctl);
 	}
-	
+
 	/* Explicitly enable PCI-PM */
 	if (sc->quirks & BHND_PCIE_QUIRK_PCIPM_REQEN) {
 		uint32_t lcreg;
@@ -520,7 +519,6 @@ bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc, bhnd_pci_war_state state)
 		
 		BHND_PCI_WRITE_2(sc, reg, cfg);
 
-
 		/* Set ASPM/ECPM (CLKREQ) flags in PCIe link control register */
 		cfg = pcie_read_config(sc->pci_dev, PCIER_LINK_CTL, 2);
 
diff --git a/sys/dev/bhnd/cores/pci/bhnd_pci_hostbvar.h b/sys/dev/bhnd/cores/pci/bhnd_pci_hostbvar.h
index 524d1f950e24b..679d1ef7f43d8 100644
--- a/sys/dev/bhnd/cores/pci/bhnd_pci_hostbvar.h
+++ b/sys/dev/bhnd/cores/pci/bhnd_pci_hostbvar.h
@@ -51,7 +51,7 @@ DECLARE_CLASS(bhnd_pci_hostb_driver);
 enum {
 	/** No quirks */
 	BHND_PCI_QUIRK_NONE			= 0,
-	
+
 	/**
 	 * SBTOPCI_PREF and SBTOPCI_BURST must be set on the
 	 * SSB_PCICORE_SBTOPCI2 register.
@@ -112,7 +112,7 @@ enum {
 	 * explicitly set (to 114ns) to fix slow L1->L0 transition issues.
 	 */
 	BHND_PCIE_QUIRK_L1_IDLE_THRESH		= (1<<8),
-	
+
 	/**
 	 * The ASPM L1 entry timer should be extended for better performance,
 	 * and restored for better power savings.
@@ -171,7 +171,7 @@ enum {
 	 * If L23READY_EXIT_NOPRST is not already set in the SPROM, set it
 	 */
 	BHND_PCIE_QUIRK_SPROM_L23_PCI_RESET	= (1<<14),
-	
+
 	/**
 	 * The PCIe SerDes PLL must be configured to not retry the startup
 	 * sequence upon frequency detection failure on SerDes <= rev9 devices
@@ -254,5 +254,4 @@ struct bhnd_pcihb_softc {
 	} sdr9_quirk_polarity;
 };
 
-
 #endif /* _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ */
diff --git a/sys/dev/bhnd/cores/pci/bhnd_pcireg.h b/sys/dev/bhnd/cores/pci/bhnd_pcireg.h
index 673f1d4af17fb..0f26ce4785596 100644
--- a/sys/dev/bhnd/cores/pci/bhnd_pcireg.h
+++ b/sys/dev/bhnd/cores/pci/bhnd_pcireg.h
@@ -205,7 +205,7 @@
 #define	BHND_PCIE_CFG_OFFSET(f, r)	\
 	((((f) & BHND_PCIE_CFG_ADDR_FUNC_MASK) << BHND_PCIE_CFG_ADDR_FUNC_SHIFT) | \
 	(((r) & BHND_PCIE_CFG_ADDR_FUNC_SHIFT) << BHND_PCIE_CFG_ADDR_REG_SHIFT))
-	
+
 /* BHND_PCIE_MDIO_CTL control */
 #define	BHND_PCIE_MDIOCTL_DIVISOR_MASK		0x7f	/* clock divisor mask */
 #define	BHND_PCIE_MDIOCTL_DIVISOR_VAL		0x2	/* default clock divisor */
@@ -318,7 +318,6 @@
 #define	BHND_PCIE_TLP_TGTDEBUG3			0x07C	/* Target Debug Reg3 */
 #define	BHND_PCIE_TLP_TGTDEBUG4			0x080	/* Target Debug Reg4 */
 
-
 /*
  * PCIe-G1 SerDes MDIO Registers (>= rev10)
  */
@@ -395,7 +394,6 @@
 #define	  BHND_PCIE_SDR9_RX_TIMER1_LKACQ_MASK	0x00FF	/* phase acquisition mode time (in 1024ns units) */
 #define	  BHND_PCIE_SDR9_RX_TIMER1_LKACQ_SHIFT	0
 
-
 /* SPROM offsets */
 #define	BHND_PCIE_SRSH_PI_OFFSET		BHND_PCI_SRSH_PI_OFFSET	/**< PCI base address bits in SPROM shadow area */
 #define	BHND_PCIE_SRSH_PI_MASK			BHND_PCI_SRSH_PI_MASK	/**< bits 15:12 of the PCI core address */
diff --git a/sys/dev/bhnd/cores/pci/bhnd_pcivar.h b/sys/dev/bhnd/cores/pci/bhnd_pcivar.h
index d1ef94c1b23e0..4125b3742718c 100644
--- a/sys/dev/bhnd/cores/pci/bhnd_pcivar.h
+++ b/sys/dev/bhnd/cores/pci/bhnd_pcivar.h
@@ -103,7 +103,6 @@ struct bhnd_pci_softc {
 	int			 mem_rid;	/**< register block RID */
 };
 
-
 #define	BHND_PCI_LOCK_INIT(sc) \
 	mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
 	    "BHND PCI driver lock", MTX_DEF)
@@ -169,7 +168,6 @@ struct bhnd_pci_softc {
 	    BHND_PCI_COMMON_REG((_regf), _attr ## _SHIFT),	\
 	    _val)
 
-
 /**
  * Evaluates to the offset of a common PCI/PCIe register definition. 
  * 
diff --git a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c
index 3a6712abff61d..b914a68c81c9f 100644
--- a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c
+++ b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c
@@ -131,7 +131,7 @@ bhnd_pcie2_generic_detach(device_t dev)
 		return (error);
 
 	bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
-	
+
 	BHND_PCIE2_LOCK_DESTROY(sc);
 
 	return (0);
@@ -154,7 +154,7 @@ bhnd_pcie2_add_child(device_t dev, u_int order, const char *name, int unit)
 {
 	struct bhnd_pcie2_devinfo	*dinfo;
 	device_t			 child;
-	
+
 	child = device_add_child_ordered(dev, order, name, unit);
 	if (child == NULL)
 		return (NULL);
@@ -166,7 +166,7 @@ bhnd_pcie2_add_child(device_t dev, u_int order, const char *name, int unit)
 	}
 
 	resource_list_init(&dinfo->resources);
-	
+
 	device_set_ivars(child, dinfo);
 	return (child);
 }
@@ -280,7 +280,7 @@ static device_method_t bhnd_pcie2_methods[] = {
 	DEVMETHOD(bus_deactivate_resource,      bus_generic_deactivate_resource),
 	DEVMETHOD(bus_adjust_resource,          bus_generic_adjust_resource),
 	DEVMETHOD(bus_release_resource,		bus_generic_rl_release_resource),
-	
+
 	DEVMETHOD_END
 };
 
diff --git a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostb.c b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostb.c
index 12734437136a8..0c8419d48fc6a 100644
--- a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostb.c
+++ b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostb.c
@@ -75,7 +75,6 @@ __FBSDID("$FreeBSD$");
 
 static const struct bhnd_device_quirk bhnd_pcie2_quirks[];
 
-
 static int	bhnd_pcie2_wars_early_once(struct bhnd_pcie2hb_softc *sc);
 static int	bhnd_pcie2_wars_hwup(struct bhnd_pcie2hb_softc *sc);
 static int	bhnd_pcie2_wars_hwdown(struct bhnd_pcie2hb_softc *sc);
@@ -125,19 +124,16 @@ bhnd_pcie2_hostb_attach(device_t dev)
 	if ((error = bhnd_pcie2_generic_attach(dev)))
 		return (error);
 
-
 	/* Apply early single-shot work-arounds */
 	if ((error = bhnd_pcie2_wars_early_once(sc)))
 		goto failed;
 
-
 	/* Apply attach/resume work-arounds */
 	if ((error = bhnd_pcie2_wars_hwup(sc)))
 		goto failed;
 
-
 	return (0);
-	
+
 failed:
 	bhnd_pcie2_generic_detach(dev);
 	return (error);
diff --git a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostbvar.h b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostbvar.h
index f1204ca36874a..ecd2ae4a5f5be 100644
--- a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostbvar.h
+++ b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostbvar.h
@@ -45,7 +45,6 @@
 
 DECLARE_CLASS(bhnd_pcie2_hostb_driver);
 
-
 /* 
  * PCIe-Gen2 endpoint-mode device quirks
  */
@@ -59,7 +58,6 @@ enum {
 	BHND_PCIE2_QUIRK_SERDES_TXDRV_DEEMPH	= (1<<0),
 };
 
-
 /**
  * bhnd_pci_hostb driver instance state.
  */
@@ -70,5 +68,4 @@ struct bhnd_pcie2hb_softc {
 	uint32_t		quirks;		/**< hostb device quirks */
 };
 
-
 #endif /* _BHND_CORES_PCIE2_BHND_PCI_HOSTBVAR_H_ */
diff --git a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_reg.h b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_reg.h
index e128c4bf723cf..d1890b372aa4e 100644
--- a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_reg.h
+++ b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_reg.h
@@ -99,7 +99,6 @@
 #define	BHND_PCIE2_MDIO_WRDATA		0x12C	/**< mdio data write */
 #define	BHND_PCIE2_MDIO_RDDATA		0x130	/**< mdio data read */
 
-
 /* DMA doorbell registers (>= rev5) */
 #define	BHND_PCIE2_DB0_HOST2DEV0	0x140
 #define	BHND_PCIE2_DB0_HOST2DEV1	0x144
@@ -237,5 +236,4 @@
 #define	BHND_PCIE2_DMA_STATUS0		0x10	/**< current descriptor, xmt state */
 #define	BHND_PCIE2_DMA_STATUS1		0x10	/**< active descriptor, xmt error */
 
-
 #endif /* _BHND_CORES_PCIE2_BHND_PCIE2_REG_H_ */
diff --git a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h
index 5017a7f4d88f0..b7622e38329d4 100644
--- a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h
+++ b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h
@@ -50,7 +50,6 @@ int		bhnd_pcie2_generic_detach(device_t dev);
 int		bhnd_pcie2_generic_suspend(device_t dev);
 int		bhnd_pcie2_generic_resume(device_t dev);
 
-
 uint32_t	bhnd_pcie2_read_proto_reg(struct bhnd_pcie2_softc *sc,
 		    uint32_t addr);
 void		bhnd_pcie2_write_proto_reg(struct bhnd_pcie2_softc *sc,
@@ -88,7 +87,6 @@ struct bhnd_pcie2_softc {
 	int			 mem_rid;	/**< register block RID */
 };
 
-
 #define	BHND_PCIE2_LOCK_INIT(sc) \
 	mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
 	    "BHND PCIe-G2 driver lock", MTX_DEF)
diff --git a/sys/dev/bhnd/cores/pmu/bhnd_pmu.c b/sys/dev/bhnd/cores/pmu/bhnd_pmu.c
index 8b58212745e32..c3676ae08115c 100644
--- a/sys/dev/bhnd/cores/pmu/bhnd_pmu.c
+++ b/sys/dev/bhnd/cores/pmu/bhnd_pmu.c
@@ -197,7 +197,7 @@ bhnd_pmu_attach(device_t dev, struct bhnd_resource *res)
 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 	    "cpu_freq", CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
 	    bhnd_pmu_sysctl_cpu_freq, "IU", "CPU clock frequency");
-	
+
 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
 	    "mem_freq", CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
 	    bhnd_pmu_sysctl_mem_freq, "IU", "Memory clock frequency");
@@ -237,7 +237,7 @@ bhnd_pmu_detach(device_t dev)
 	bhnd_pmu_query_fini(&sc->query);
 	bhnd_free_core_clkctl(sc->clkctl);
 	bhnd_release_provider(sc->dev, sc->chipc_dev, BHND_SERVICE_CHIPC);
-	
+
 	return (0);
 }
 
@@ -275,7 +275,7 @@ bhnd_pmu_sysctl_bus_freq(SYSCTL_HANDLER_ARGS)
 {
 	struct bhnd_pmu_softc	*sc;
 	uint32_t		 freq;
-	
+
 	sc = arg1;
 
 	BPMU_LOCK(sc);
@@ -290,7 +290,7 @@ bhnd_pmu_sysctl_cpu_freq(SYSCTL_HANDLER_ARGS)
 {
 	struct bhnd_pmu_softc	*sc;
 	uint32_t		 freq;
-	
+
 	sc = arg1;
 
 	BPMU_LOCK(sc);
@@ -305,7 +305,7 @@ bhnd_pmu_sysctl_mem_freq(SYSCTL_HANDLER_ARGS)
 {
 	struct bhnd_pmu_softc	*sc;
 	uint32_t		 freq;
-	
+
 	sc = arg1;
 
 	BPMU_LOCK(sc);
@@ -427,7 +427,7 @@ bhnd_pmu_set_voltage_raw_method(device_t dev, bhnd_pmu_regulator regulator,
 	case BHND_REGULATOR_PAREF_LDO:
 		if (value > UINT8_MAX)
 			return (EINVAL);
-	
+
 		BPMU_LOCK(sc);
 		error = bhnd_pmu_set_ldo_voltage(sc, SET_LDO_VOLTAGE_PAREF,
 		    value);
@@ -488,7 +488,6 @@ bhnd_pmu_disable_regulator_method(device_t dev, bhnd_pmu_regulator regulator)
 	}
 }
 
-
 /**
  * Default bhnd_pmu driver implementation of BHND_PMU_GET_CLOCK_LATENCY().
  */
@@ -625,7 +624,7 @@ static device_method_t bhnd_pmu_methods[] = {
 
 	DEVMETHOD(bhnd_pmu_get_max_transition_latency,	bhnd_pmu_get_max_transition_latency_method),
 	DEVMETHOD(bhnd_pmu_request_spuravoid,		bhnd_pmu_request_spuravoid_method),
-	
+
 	DEVMETHOD_END
 };
 
diff --git a/sys/dev/bhnd/cores/pmu/bhnd_pmu.h b/sys/dev/bhnd/cores/pmu/bhnd_pmu.h
index ee15381518821..971468c9398f6 100644
--- a/sys/dev/bhnd/cores/pmu/bhnd_pmu.h
+++ b/sys/dev/bhnd/cores/pmu/bhnd_pmu.h
@@ -45,7 +45,6 @@
 #include "bhnd_pmu_if.h"
 #include "bhnd_pmu_types.h"
 
-
 /**
  * Return the current value of a PMU chipctrl register.
  *
@@ -251,7 +250,6 @@ bhnd_pmu_request_spuravoid(device_t dev, bhnd_pmu_spuravoid spuravoid)
 	return (BHND_PMU_REQUEST_SPURAVOID(dev, spuravoid));
 }
 
-
 /**
  * Return the PMU's maximum state transition latency in microseconds.
  *
diff --git a/sys/dev/bhnd/cores/pmu/bhnd_pmu_core.c b/sys/dev/bhnd/cores/pmu/bhnd_pmu_core.c
index 1d04f07ea714a..5a991d0cd9428 100644
--- a/sys/dev/bhnd/cores/pmu/bhnd_pmu_core.c
+++ b/sys/dev/bhnd/cores/pmu/bhnd_pmu_core.c
@@ -121,7 +121,7 @@ bhnd_pmu_core_detach(device_t dev)
 	int			 error;
 
 	sc = device_get_softc(dev);
-	
+
 	/* Delegate to common driver implementation */
 	if ((error = bhnd_pmu_detach(dev)))
 		return (error);
diff --git a/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h b/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h
index 93242931ca628..ac4079c275830 100644
--- a/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h
+++ b/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h
@@ -70,7 +70,6 @@
 #define	BHND_PMU_PLL_WRITE(_sc, _reg, _val, _mask)	\
 	BHND_PMU_IND_WRITE((_sc), PLL_CONTROL, (_reg), (_val), (_mask))
 
-
 /** FVCO frequencies, in Hz */
 enum {
 	FVCO_880	= 880	* 1000,	/**< 880MHz */
@@ -93,7 +92,6 @@ enum {
 	SET_LDO_VOLTAGE_LNLDO2_SEL	= 10,
 };
 
-
 uint32_t	bhnd_pmu_ind_read(const struct bhnd_pmu_io *io, void *io_ctx,
 		    bus_size_t addr, bus_size_t data, uint32_t reg);
 void		bhnd_pmu_ind_write(const struct bhnd_pmu_io *io, void *io_ctx,
diff --git a/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c b/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c
index 36c0e295f8e42..b93110176d2f4 100644
--- a/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c
+++ b/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c
@@ -765,7 +765,7 @@ bhnd_pmu_res_masks(struct bhnd_pmu_softc *sc, uint32_t *pmin, uint32_t *pmax)
 	case BHND_CHIPID_BCM4342:
 		if (sc->cid.chip_rev >= 2)
 			break;
-	
+
 		/* request ALP(can skip for A1) */
 		min_mask = PMURES_BIT(RES4322_RF_LDO) |
 			   PMURES_BIT(RES4322_XTAL_PU) |
@@ -1012,7 +1012,7 @@ bhnd_pmu_res_init(struct bhnd_pmu_softc *sc)
 		KASSERT(pmu_res_updown_table != NULL, ("no updown tables"));
 
 		updt = &pmu_res_updown_table[pmu_res_updown_table_sz - i - 1];
-	
+
 		PMU_DEBUG(sc, "Changing rsrc %d res_updn_timer to %#x\n",
 		    updt->resnum, updt->updown);
 
@@ -1571,7 +1571,7 @@ bhnd_pmu0_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal)
 	} else {
 		pll_data &= ~BHND_PMU0_PLL0_PC1_STOP_MOD;
 	}
-	
+
 	pll_mask = 
 	    BHND_PMU0_PLL0_PC1_WILD_INT_MASK |
 	    BHND_PMU0_PLL0_PC1_WILD_FRAC_MASK;
@@ -1665,8 +1665,6 @@ bhnd_pmu0_cpuclk0(struct bhnd_pmu_query *sc)
 	return FVCO / (divarm + BHND_PMU0_PLL0_PC0_DIV_ARM_BASE) * 1000;
 }
 
-
-
 /* Set up PLL registers in the PMU as per the crystal speed. */
 static void
 bhnd_pmu1_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal)
@@ -1862,7 +1860,6 @@ bhnd_pmu1_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal)
 
 	BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL0, plldata, pllmask);
 
-
 	if (sc->cid.chip_id == BHND_CHIPID_BCM4330)
 		bhnd_pmu_set_4330_plldivs(sc);
 
@@ -1885,7 +1882,6 @@ bhnd_pmu1_pllinit0(struct bhnd_pmu_softc *sc, uint32_t xtal)
 	} else {
 		ndiv_mode = BHND_PMU1_PLL0_PC2_NDIV_MODE_MASH;
 	}
-	
 
 	BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2,
 	    BHND_PMU_SET_BITS(xt->ndiv_int, BHND_PMU1_PLL0_PC2_NDIV_INT) |
@@ -2250,7 +2246,6 @@ bhnd_pmu5_clock(struct bhnd_pmu_query *sc, u_int pll0, u_int m)
 			return (133 * 1000000);
 	}
 
-
 	/* Fetch p1 and p2 */
 	BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR,
 	    pll0 + BHND_PMU5_PLL_P1P2_OFF);
@@ -2690,7 +2685,6 @@ bhnd_pmu_init(struct bhnd_pmu_softc *sc)
 		BHND_PMU_REGCTRL_WRITE(sc, 2, 0x00000005, 0x00000007);
 	}
 
-
 	/* Fetch target xtalfreq, in KHz */
 	error = bhnd_nvram_getvar_uint32(sc->chipc_dev, BHND_NVAR_XTALFREQ,
 	    &xtalfreq);
@@ -2876,7 +2870,6 @@ bhnd_pmu_rcal(struct bhnd_pmu_softc *sc)
 	uint8_t		rcal_code;
 	bool		bluetooth_rcal;
 
-
 	bluetooth_rcal = false;
 
 	switch (sc->cid.chip_id) {
@@ -3204,7 +3197,6 @@ bhnd_pmu_spuravoid_pllupdate(struct bhnd_pmu_softc *sc,
 			return (ENODEV);
 		}
 
-
 		pmuctrl = BHND_PMU_CTRL_NOILP_ON_WAIT | 
 			  BHND_PMU_CTRL_PLL_PLLCTL_UPD;
 		break;
diff --git a/sys/dev/bhnd/cores/pmu/bhnd_pmureg.h b/sys/dev/bhnd/cores/pmu/bhnd_pmureg.h
index 0146a2539789b..6a9ab0de68f87 100644
--- a/sys/dev/bhnd/cores/pmu/bhnd_pmureg.h
+++ b/sys/dev/bhnd/cores/pmu/bhnd_pmureg.h
@@ -366,7 +366,6 @@
 #define	BHND_PMU_XTALFREQ_REG_MEASURE_MASK	0x80000000
 #define	BHND_PMU_XTALFREQ_REG_MEASURE_SHIFT	31
 
-
 /* Divider allocation in 4716/47162/5356/5357 */
 #define	BHND_PMU5_MAINPLL_CPU		1
 #define	BHND_PMU5_MAINPLL_MEM		2
@@ -394,16 +393,13 @@
 #define	BHND_PMU7_PLL_PLLCTL8		8
 #define	BHND_PMU7_PLL_PLLCTL11		11
 
-
 /* PLL usage in 4716/47162 */
 #define	BHND_PMU4716_MAINPLL_PLL0	12
 
-
 /* PLL usage in 5356/5357 */
 #define	BHND_PMU5356_MAINPLL_PLL0	0
 #define	BHND_PMU5357_MAINPLL_PLL0	0
 
-
 /* 4716/47162 PMU resources */
 #define	BHND_PMU_RES4716_PROC_PLL_ON		0x00000040
 #define	BHND_PMU_RES4716_PROC_HT_AVAIL		0x00000080
@@ -411,7 +407,6 @@
 /* 4716/4717/4718 chip-specific CHIPCTRL PMU register bits */
 #define	BHND_PMU_CCTRL471X_I2S_PINS_ENABLE	0x0080	/* I2S pins off by default, shared with pflash */
 
-
 /* 5354 PMU resources */
 #define	BHND_PMU_RES5354_EXT_SWITCHER_PWM	0	/* 0x00001 */
 #define	BHND_PMU_RES5354_BB_SWITCHER_PWM	1	/* 0x00002 */
@@ -434,12 +429,10 @@
 #define	BHND_PMU_RES5354_RF_PLL_FILTBYP		18	/* 0x40000 */
 #define	BHND_PMU_RES5354_BB_PLL_PU		19	/* 0x80000 */
 
-
 /* 5357 chip-specific CHIPCTRL register bits */
 #define	BHND_PMU_CCTRL5357_EXTPA		(1<<14)	/* extPA in CHIPCTRL1, bit 14 */
 #define	BHND_PMU_CCTRL5357_ANT_MUX_2o3		(1<<15)	/* 2o3 in CHIPCTRL1, bit 15 */
 
-
 /* 4328 PMU resources */
 #define	BHND_PMU_RES4328_EXT_SWITCHER_PWM	0	/* 0x00001 */
 #define	BHND_PMU_RES4328_BB_SWITCHER_PWM	1	/* 0x00002 */
@@ -462,7 +455,6 @@
 #define	BHND_PMU_RES4328_RF_PLL_FILTBYP		18	/* 0x40000 */
 #define	BHND_PMU_RES4328_BB_PLL_PU		19	/* 0x80000 */
 
-
 /* 4325 A0/A1 PMU resources */
 #define	BHND_PMU_RES4325_BUCK_BOOST_BURST	0	/* 0x00000001 */
 #define	BHND_PMU_RES4325_CBUCK_BURST		1	/* 0x00000002 */
@@ -487,18 +479,15 @@
 #define	BHND_PMU_RES4325_BBPLL_PWRSW_PU		20	/* 0x00100000 */
 #define	BHND_PMU_RES4325_HT_AVAIL		21	/* 0x00200000 */
 
-
 /* 4325 B0/C0 PMU resources */
 #define	BHND_PMU_RES4325B0_CBUCK_LPOM		1	/* 0x00000002 */
 #define	BHND_PMU_RES4325B0_CBUCK_BURST		2	/* 0x00000004 */
 #define	BHND_PMU_RES4325B0_CBUCK_PWM		3	/* 0x00000008 */
 #define	BHND_PMU_RES4325B0_CLDO_PU		4	/* 0x00000010 */
 
-
 /* 4325 C1 PMU resources */
 #define	BHND_PMU_RES4325C1_LNLDO2_PU		12	/* 0x00001000 */
 
-
 /* 4325 PMU resources */
 #define	BHND_PMU_RES4329_RESERVED0		0	/* 0x00000001 */
 #define	BHND_PMU_RES4329_CBUCK_LPOM		1	/* 0x00000002 */
@@ -523,7 +512,6 @@
 #define	BHND_PMU_RES4329_BBPLL_PWRSW_PU		20	/* 0x00100000 */
 #define	BHND_PMU_RES4329_HT_AVAIL		21	/* 0x00200000 */
 
-
 /* 4312 PMU resources (all PMU chips with little memory constraint) */
 #define	BHND_PMU_RES4312_SWITCHER_BURST		0	/* 0x00000001 */
 #define	BHND_PMU_RES4312_SWITCHER_PWM    	1	/* 0x00000002 */
@@ -541,7 +529,6 @@
 #define	BHND_PMU_RES4312_RF_PLL_FILTBYP		13	/* 0x00002000 */
 #define	BHND_PMU_RES4312_HT_AVAIL		14	/* 0x00004000 */
 
-
 /* 4322 PMU resources */
 #define	BHND_PMU_RES4322_RF_LDO			0
 #define	BHND_PMU_RES4322_ILP_REQUEST		1
@@ -553,13 +540,11 @@
 #define	BHND_PMU_RES4322_HT_PHY_AVAIL		7
 #define	BHND_PMU_RES4322_OTP_PU			8
 
-
 /* 43224 chip-specific CHIPCTRL register bits */
 #define	BHND_PMU_CCTRL43224_GPIO_TOGGLE	0x8000
 #define	BHND_PMU_CCTRL43224A0_12MA_LED_DRIVE	0x00F000F0	/* 12 mA drive strength */
 #define	BHND_PMU_CCTRL43224B0_12MA_LED_DRIVE	0xF0		/* 12 mA drive strength for later 43224s */
 
-
 /* 43236 PMU resources */
 #define	BHND_PMU_RES43236_REGULATOR		0
 #define	BHND_PMU_RES43236_ILP_REQUEST		1
@@ -575,7 +560,6 @@
 #define	BHND_PMU_CCTRL43236_ANT_MUX_2o3		(1<<3)	/* 2o3 mux, chipcontrol bit 3 */
 #define	BHND_PMU_CCTRL43236_GSIO		(1<<4)	/* 0 disable */
 
-
 /* 4331 PMU resources */
 #define	BHND_PMU_RES4331_REGULATOR		0
 #define	BHND_PMU_RES4331_ILP_REQUEST		1
diff --git a/sys/dev/bhnd/cores/usb/bhnd_ehci.c b/sys/dev/bhnd/cores/usb/bhnd_ehci.c
index 62bb121a3d58f..e2cffddf87930 100644
--- a/sys/dev/bhnd/cores/usb/bhnd_ehci.c
+++ b/sys/dev/bhnd/cores/usb/bhnd_ehci.c
@@ -247,7 +247,6 @@ static device_method_t ehci_methods[] = {
 
 	/* Bus interface */
 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-
 	{0, 0}
 };
 
diff --git a/sys/dev/bhnd/cores/usb/bhnd_usb.c b/sys/dev/bhnd/cores/usb/bhnd_usb.c
index 52b09c4998fbc..98f75d922460a 100644
--- a/sys/dev/bhnd/cores/usb/bhnd_usb.c
+++ b/sys/dev/bhnd/cores/usb/bhnd_usb.c
@@ -147,7 +147,6 @@ bhnd_usb_attach(device_t dev)
 	bus_write_4(sc->sc_mem, OHCI_CONTROL, 0);
 
 	if ( bhnd_get_device(dev) == BHND_COREID_USB20H) {
-
 		uint32_t rev = bhnd_get_hwrev(dev);
 		BHND_INFO_DEV(dev, "USB HOST 2.0 setup for rev %d", rev);
 		if (rev == 1/* ? == 2 */) {
@@ -275,7 +274,6 @@ bhnd_usb_alloc_resource(device_t bus, device_t child, int type, int *rid,
 	 * attempt to satisfy the allocation ourselves.
 	 */
 	if (type == SYS_RES_MEMORY) {
-
 		rv = rman_reserve_resource(&sc->mem_rman, start, end, count,
 		    flags, child);
 		if (rv == NULL) {