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authorEmmanuel Vadot <manu@FreeBSD.org>2020-11-20 11:26:46 +0000
committerEmmanuel Vadot <manu@FreeBSD.org>2020-11-20 11:26:46 +0000
commit158ce7ba0ed04fc65f6f09381ab924f10b7e96a0 (patch)
tree769e8b514364d064ca260dc387d749c44ecb001a /sys/dev/dwc
parent612a1b8d69faf5d284191c28d03d650e0a6b1e22 (diff)
Notes
Diffstat (limited to 'sys/dev/dwc')
-rw-r--r--sys/dev/dwc/if_dwc.c61
1 files changed, 40 insertions, 21 deletions
diff --git a/sys/dev/dwc/if_dwc.c b/sys/dev/dwc/if_dwc.c
index 0b38439b3e129..6c15bf9e71dff 100644
--- a/sys/dev/dwc/if_dwc.c
+++ b/sys/dev/dwc/if_dwc.c
@@ -211,6 +211,8 @@ static void dwc_txfinish_locked(struct dwc_softc *sc);
static void dwc_rxfinish_locked(struct dwc_softc *sc);
static void dwc_stop_locked(struct dwc_softc *sc);
static void dwc_setup_rxfilter(struct dwc_softc *sc);
+static void dwc_setup_core(struct dwc_softc *sc);
+static void dwc_init_dma(struct dwc_softc *sc);
static inline uint32_t
next_rxidx(struct dwc_softc *sc, uint32_t curidx)
@@ -473,7 +475,6 @@ static void
dwc_init_locked(struct dwc_softc *sc)
{
struct ifnet *ifp = sc->ifp;
- uint32_t reg;
DWC_ASSERT_LOCKED(sc);
@@ -483,26 +484,8 @@ dwc_init_locked(struct dwc_softc *sc)
ifp->if_drv_flags |= IFF_DRV_RUNNING;
dwc_setup_rxfilter(sc);
-
- /* Initializa DMA and enable transmitters */
- reg = READ4(sc, OPERATION_MODE);
- reg |= (MODE_TSF | MODE_OSF | MODE_FUF);
- reg &= ~(MODE_RSF);
- reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT);
- WRITE4(sc, OPERATION_MODE, reg);
-
- WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT);
-
- /* Start DMA */
- reg = READ4(sc, OPERATION_MODE);
- reg |= (MODE_ST | MODE_SR);
- WRITE4(sc, OPERATION_MODE, reg);
-
- /* Enable transmitters */
- reg = READ4(sc, MAC_CONFIGURATION);
- reg |= (CONF_JD | CONF_ACS | CONF_BE);
- reg |= (CONF_TE | CONF_RE);
- WRITE4(sc, MAC_CONFIGURATION, reg);
+ dwc_setup_core(sc);
+ dwc_init_dma(sc);
/*
* Call mii_mediachg() which will call back into dwc_miibus_statchg()
@@ -788,6 +771,42 @@ dwc_setup_rxfilter(struct dwc_softc *sc)
}
}
+static void
+dwc_setup_core(struct dwc_softc *sc)
+{
+ uint32_t reg;
+
+ DWC_ASSERT_LOCKED(sc);
+
+ /* Enable transmitters */
+ reg = READ4(sc, MAC_CONFIGURATION);
+ reg |= (CONF_JD | CONF_ACS | CONF_BE);
+ reg |= (CONF_TE | CONF_RE);
+ WRITE4(sc, MAC_CONFIGURATION, reg);
+}
+
+static void
+dwc_init_dma(struct dwc_softc *sc)
+{
+ uint32_t reg;
+
+ DWC_ASSERT_LOCKED(sc);
+
+ /* Initializa DMA and enable transmitters */
+ reg = READ4(sc, OPERATION_MODE);
+ reg |= (MODE_TSF | MODE_OSF | MODE_FUF);
+ reg &= ~(MODE_RSF);
+ reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT);
+ WRITE4(sc, OPERATION_MODE, reg);
+
+ WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT);
+
+ /* Start DMA */
+ reg = READ4(sc, OPERATION_MODE);
+ reg |= (MODE_ST | MODE_SR);
+ WRITE4(sc, OPERATION_MODE, reg);
+}
+
static int
dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
{