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authorPrafulla Deuskar <pdeuskar@FreeBSD.org>2004-09-01 23:22:41 +0000
committerPrafulla Deuskar <pdeuskar@FreeBSD.org>2004-09-01 23:22:41 +0000
commit9821d34f430ab57abf692a1ed8ca5984987cece6 (patch)
treea56b0eef358761b21773943572e581d42e91725e /sys/dev/em
parentc78752b94b6b3d5a144915cc068e4b1572718e5f (diff)
Notes
Diffstat (limited to 'sys/dev/em')
-rw-r--r--sys/dev/em/if_em.c78
-rw-r--r--sys/dev/em/if_em.h19
-rw-r--r--sys/dev/em/if_em_hw.c559
-rw-r--r--sys/dev/em/if_em_hw.h34
4 files changed, 448 insertions, 242 deletions
diff --git a/sys/dev/em/if_em.c b/sys/dev/em/if_em.c
index 28aafa4b5b27c..3a0659c13861a 100644
--- a/sys/dev/em/if_em.c
+++ b/sys/dev/em/if_em.c
@@ -51,7 +51,7 @@ struct adapter *em_adapter_list = NULL;
* Driver version
*********************************************************************/
-char em_driver_version[] = "1.7.25";
+char em_driver_version[] = "1.7.35";
/*********************************************************************
@@ -80,7 +80,6 @@ static em_vendor_info_t em_vendor_info_array[] =
{ 0x8086, 0x1011, PCI_ANY_ID, PCI_ANY_ID, 0},
{ 0x8086, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0},
{ 0x8086, 0x1013, PCI_ANY_ID, PCI_ANY_ID, 0},
- { 0x8086, 0x1014, PCI_ANY_ID, PCI_ANY_ID, 0},
{ 0x8086, 0x1015, PCI_ANY_ID, PCI_ANY_ID, 0},
{ 0x8086, 0x1016, PCI_ANY_ID, PCI_ANY_ID, 0},
{ 0x8086, 0x1017, PCI_ANY_ID, PCI_ANY_ID, 0},
@@ -99,6 +98,7 @@ static em_vendor_info_t em_vendor_info_array[] =
{ 0x8086, 0x1079, PCI_ANY_ID, PCI_ANY_ID, 0},
{ 0x8086, 0x107A, PCI_ANY_ID, PCI_ANY_ID, 0},
{ 0x8086, 0x107B, PCI_ANY_ID, PCI_ANY_ID, 0},
+ { 0x8086, 0x107C, PCI_ANY_ID, PCI_ANY_ID, 0},
/* required last entry */
{ 0, 0, 0, 0, 0}
};
@@ -742,7 +742,7 @@ em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
em_init(adapter);
break;
default:
- IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%x)\n", (int)command);
+ IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%x)", (int)command);
error = EINVAL;
}
@@ -797,6 +797,7 @@ em_init_locked(struct adapter * adapter)
{
struct ifnet *ifp;
+ uint32_t pba;
ifp = &adapter->interface_data.ac_if;
INIT_DEBUGOUT("em_init: begin");
@@ -805,6 +806,36 @@ em_init_locked(struct adapter * adapter)
em_stop(adapter);
+ /* Packet Buffer Allocation (PBA)
+ * Writing PBA sets the receive portion of the buffer
+ * the remainder is used for the transmit buffer.
+ *
+ * Devices before the 82547 had a Packet Buffer of 64K.
+ * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
+ * After the 82547 the buffer was reduced to 40K.
+ * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
+ * Note: default does not leave enough room for Jumbo Frame >10k.
+ */
+ if(adapter->hw.mac_type < em_82547) {
+ /* Total FIFO is 64K */
+ if(adapter->rx_buffer_len > EM_RXBUFFER_8192)
+ pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
+ else
+ pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
+ } else {
+ /* Total FIFO is 40K */
+ if(adapter->hw.max_frame_size > EM_RXBUFFER_8192) {
+ pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
+ } else {
+ pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
+ }
+ adapter->tx_fifo_head = 0;
+ adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
+ adapter->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
+ }
+ INIT_DEBUGOUT1("em_init: pba=%dK",pba);
+ E1000_WRITE_REG(&adapter->hw, PBA, pba);
+
/* Get the latest mac address, User can use a LAA */
bcopy(adapter->interface_data.ac_enaddr, adapter->hw.mac_addr,
ETHER_ADDR_LEN);
@@ -1138,10 +1169,6 @@ em_tx_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int e
bcopy(seg, q->segs, nsegs * sizeof(seg[0]));
}
-#define EM_FIFO_HDR 0x10
-#define EM_82547_PKT_THRESH 0x3e0
-#define EM_82547_TX_FIFO_SIZE 0x2800
-#define EM_82547_TX_FIFO_BEGIN 0xf00
/*********************************************************************
*
* This routine maps the mbufs to tx descriptors.
@@ -1356,7 +1383,7 @@ em_82547_move_tail_locked(struct adapter *adapter)
if(eop) {
if (em_82547_fifo_workaround(adapter, length)) {
- adapter->tx_fifo_wrk++;
+ adapter->tx_fifo_wrk_cnt++;
callout_reset(&adapter->tx_fifo_timer, 1,
em_82547_move_tail, adapter);
break;
@@ -1387,7 +1414,7 @@ em_82547_fifo_workaround(struct adapter *adapter, int len)
fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR);
if (adapter->link_duplex == HALF_DUPLEX) {
- fifo_space = EM_82547_TX_FIFO_SIZE - adapter->tx_fifo_head;
+ fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
if (em_82547_tx_fifo_reset(adapter)) {
@@ -1409,8 +1436,8 @@ em_82547_update_fifo_head(struct adapter *adapter, int len)
/* tx_fifo_head is always 16 byte aligned */
adapter->tx_fifo_head += fifo_pkt_len;
- if (adapter->tx_fifo_head >= EM_82547_TX_FIFO_SIZE) {
- adapter->tx_fifo_head -= EM_82547_TX_FIFO_SIZE;
+ if (adapter->tx_fifo_head >= adapter->tx_fifo_size) {
+ adapter->tx_fifo_head -= adapter->tx_fifo_size;
}
return;
@@ -1435,17 +1462,17 @@ em_82547_tx_fifo_reset(struct adapter *adapter)
E1000_WRITE_REG(&adapter->hw, TCTL, tctl & ~E1000_TCTL_EN);
/* Reset FIFO pointers */
- E1000_WRITE_REG(&adapter->hw, TDFT, EM_82547_TX_FIFO_BEGIN);
- E1000_WRITE_REG(&adapter->hw, TDFH, EM_82547_TX_FIFO_BEGIN);
- E1000_WRITE_REG(&adapter->hw, TDFTS, EM_82547_TX_FIFO_BEGIN);
- E1000_WRITE_REG(&adapter->hw, TDFHS, EM_82547_TX_FIFO_BEGIN);
+ E1000_WRITE_REG(&adapter->hw, TDFT, adapter->tx_head_addr);
+ E1000_WRITE_REG(&adapter->hw, TDFH, adapter->tx_head_addr);
+ E1000_WRITE_REG(&adapter->hw, TDFTS, adapter->tx_head_addr);
+ E1000_WRITE_REG(&adapter->hw, TDFHS, adapter->tx_head_addr);
/* Re-enable TX unit */
E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
E1000_WRITE_FLUSH(&adapter->hw);
adapter->tx_fifo_head = 0;
- adapter->tx_fifo_reset++;
+ adapter->tx_fifo_reset_cnt++;
return(TRUE);
}
@@ -1459,13 +1486,23 @@ em_set_promisc(struct adapter * adapter)
{
u_int32_t reg_rctl;
+ u_int32_t ctrl;
struct ifnet *ifp = &adapter->interface_data.ac_if;
reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
+ ctrl = E1000_READ_REG(&adapter->hw, CTRL);
if (ifp->if_flags & IFF_PROMISC) {
reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
+
+ /* Disable VLAN stripping in promiscous mode
+ * This enables bridging of vlan tagged frames to occur
+ * and also allows vlan tags to be seen in tcpdump
+ */
+ ctrl &= ~E1000_CTRL_VME;
+ E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
+
} else if (ifp->if_flags & IFF_ALLMULTI) {
reg_rctl |= E1000_RCTL_MPE;
reg_rctl &= ~E1000_RCTL_UPE;
@@ -1486,6 +1523,7 @@ em_disable_promisc(struct adapter * adapter)
reg_rctl &= (~E1000_RCTL_MPE);
E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
+ em_enable_vlans(adapter);
return;
}
@@ -3169,6 +3207,10 @@ em_print_debug_info(struct adapter *adapter)
uint8_t *hw_addr = adapter->hw.hw_addr;
printf("em%d: Adapter hardware address = %p \n", unit, hw_addr);
+ printf("em%d:CTRL = 0x%x\n", unit,
+ E1000_READ_REG(&adapter->hw, CTRL));
+ printf("em%d:RCTL = 0x%x PS=(0x8402)\n", unit,
+ E1000_READ_REG(&adapter->hw, RCTL));
printf("em%d:tx_int_delay = %d, tx_abs_int_delay = %d\n", unit,
E1000_READ_REG(&adapter->hw, TIDV),
E1000_READ_REG(&adapter->hw, TADV));
@@ -3183,8 +3225,8 @@ em_print_debug_info(struct adapter *adapter)
adapter->clean_tx_interrupts);
#endif
printf("em%d: fifo workaround = %lld, fifo_reset = %lld\n", unit,
- (long long)adapter->tx_fifo_wrk,
- (long long)adapter->tx_fifo_reset);
+ (long long)adapter->tx_fifo_wrk_cnt,
+ (long long)adapter->tx_fifo_reset_cnt);
printf("em%d: hw tdh = %d, hw tdt = %d\n", unit,
E1000_READ_REG(&adapter->hw, TDH),
E1000_READ_REG(&adapter->hw, TDT));
diff --git a/sys/dev/em/if_em.h b/sys/dev/em/if_em.h
index 34be8fd8c1835..662c1af8b1395 100644
--- a/sys/dev/em/if_em.h
+++ b/sys/dev/em/if_em.h
@@ -399,8 +399,6 @@ struct adapter {
struct mbuf *fmp;
struct mbuf *lmp;
- u_int16_t tx_fifo_head;
-
struct sysctl_ctx_list sysctl_ctx;
struct sysctl_oid *sysctl_tree;
@@ -412,8 +410,21 @@ struct adapter {
unsigned long no_tx_desc_avail2;
unsigned long no_tx_map_avail;
unsigned long no_tx_dma_setup;
- u_int64_t tx_fifo_reset;
- u_int64_t tx_fifo_wrk;
+
+ /* Used in for 82547 10Mb Half workaround */
+ #define EM_PBA_BYTES_SHIFT 0xA
+ #define EM_TX_HEAD_ADDR_SHIFT 7
+ #define EM_PBA_TX_MASK 0xFFFF0000
+ #define EM_FIFO_HDR 0x10
+
+ #define EM_82547_PKT_THRESH 0x3e0
+
+ u_int32_t tx_fifo_size;
+ u_int32_t tx_fifo_head;
+ u_int32_t tx_fifo_head_addr;
+ u_int64_t tx_fifo_reset_cnt;
+ u_int64_t tx_fifo_wrk_cnt;
+ u_int32_t tx_head_addr;
/* For 82544 PCIX Workaround */
boolean_t pcix_82544;
diff --git a/sys/dev/em/if_em_hw.c b/sys/dev/em/if_em_hw.c
index 2b45905ebddf9..83459dd188f6b 100644
--- a/sys/dev/em/if_em_hw.c
+++ b/sys/dev/em/if_em_hw.c
@@ -73,6 +73,7 @@ static void em_release_eeprom(struct em_hw *hw);
static void em_standby_eeprom(struct em_hw *hw);
static int32_t em_id_led_init(struct em_hw * hw);
static int32_t em_set_vco_speed(struct em_hw *hw);
+static int32_t em_set_phy_mode(struct em_hw *hw);
/* IGP cable length table */
static const
@@ -258,6 +259,7 @@ em_set_mac_type(struct em_hw *hw)
break;
case E1000_DEV_ID_82541ER:
case E1000_DEV_ID_82541GI:
+ case E1000_DEV_ID_82541GI_LF:
case E1000_DEV_ID_82541GI_MOBILE:
hw->mac_type = em_82541_rev_2;
break;
@@ -477,11 +479,11 @@ em_init_hw(struct em_hw *hw)
uint16_t pcix_stat_hi_word;
uint16_t cmd_mmrbc;
uint16_t stat_mmrbc;
-
DEBUGFUNC("em_init_hw");
/* Initialize Identification LED */
- if((ret_val = em_id_led_init(hw))) {
+ ret_val = em_id_led_init(hw);
+ if(ret_val) {
DEBUGOUT("Error Initializing Identification LED\n");
return ret_val;
}
@@ -602,16 +604,16 @@ em_adjust_serdes_amplitude(struct em_hw *hw)
return E1000_SUCCESS;
}
- if ((ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
- &eeprom_data))) {
+ ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
+ if (ret_val) {
return ret_val;
}
if(eeprom_data != EEPROM_RESERVED_WORD) {
/* Adjust SERDES output amplitude only. */
eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
- if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
- eeprom_data)))
+ ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
+ if(ret_val)
return ret_val;
}
@@ -760,14 +762,16 @@ em_setup_fiber_serdes_link(struct em_hw *hw)
if(hw->media_type == em_media_type_fiber)
signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
- if((ret_val = em_adjust_serdes_amplitude(hw)))
+ ret_val = em_adjust_serdes_amplitude(hw);
+ if(ret_val)
return ret_val;
/* Take the link out of reset */
ctrl &= ~(E1000_CTRL_LRST);
/* Adjust VCO speed to improve BER performance */
- if((ret_val = em_set_vco_speed(hw)))
+ ret_val = em_set_vco_speed(hw);
+ if(ret_val)
return ret_val;
em_config_collision_dist(hw);
@@ -854,7 +858,8 @@ em_setup_fiber_serdes_link(struct em_hw *hw)
* we detect a signal. This will allow us to communicate with
* non-autonegotiating link partners.
*/
- if((ret_val = em_check_for_link(hw))) {
+ ret_val = em_check_for_link(hw);
+ if(ret_val) {
DEBUGOUT("Error while checking for link\n");
return ret_val;
}
@@ -901,12 +906,25 @@ em_setup_copper_link(struct em_hw *hw)
}
/* Make sure we have a valid PHY */
- if((ret_val = em_detect_gig_phy(hw))) {
+ ret_val = em_detect_gig_phy(hw);
+ if(ret_val) {
DEBUGOUT("Error, did not detect valid phy.\n");
return ret_val;
}
DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
+ /* Set PHY to class A mode (if necessary) */
+ ret_val = em_set_phy_mode(hw);
+ if(ret_val)
+ return ret_val;
+
+ if((hw->mac_type == em_82545_rev_3) ||
+ (hw->mac_type == em_82546_rev_3)) {
+ ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+ phy_data |= 0x00000008;
+ ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+ }
+
if(hw->mac_type <= em_82543 ||
hw->mac_type == em_82541 || hw->mac_type == em_82547 ||
hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2)
@@ -915,7 +933,8 @@ em_setup_copper_link(struct em_hw *hw)
if(!hw->phy_reset_disable) {
if (hw->phy_type == em_phy_igp) {
- if((ret_val = em_phy_reset(hw))) {
+ ret_val = em_phy_reset(hw);
+ if(ret_val) {
DEBUGOUT("Error Resetting the PHY\n");
return ret_val;
}
@@ -930,14 +949,16 @@ em_setup_copper_link(struct em_hw *hw)
E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
/* disable lplu d3 during driver init */
- if((ret_val = em_set_d3_lplu_state(hw, FALSE))) {
+ ret_val = em_set_d3_lplu_state(hw, FALSE);
+ if(ret_val) {
DEBUGOUT("Error Disabling LPLU D3\n");
return ret_val;
}
/* Configure mdi-mdix settings */
- if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
+ &phy_data);
+ if(ret_val)
return ret_val;
if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
@@ -964,8 +985,9 @@ em_setup_copper_link(struct em_hw *hw)
break;
}
}
- if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
- phy_data)))
+ ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
+ phy_data);
+ if(ret_val)
return ret_val;
/* set auto-master slave resolution settings */
@@ -983,27 +1005,28 @@ em_setup_copper_link(struct em_hw *hw)
* resolution as hardware default. */
if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
/* Disable SmartSpeed */
- if((ret_val = em_read_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+ &phy_data);
+ if(ret_val)
return ret_val;
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- if((ret_val = em_write_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- phy_data)))
+ ret_val = em_write_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG,
+ phy_data);
+ if(ret_val)
return ret_val;
/* Set auto Master/Slave resolution process */
- if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data &= ~CR_1000T_MS_ENABLE;
- if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
- phy_data)))
+ ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
+ if(ret_val)
return ret_val;
}
- if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
/* load defaults for future use */
@@ -1026,14 +1049,15 @@ em_setup_copper_link(struct em_hw *hw)
default:
break;
}
- if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
- phy_data)))
+ ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
+ if(ret_val)
return ret_val;
}
} else {
/* Enable CRS on TX. This must be set for half-duplex operation. */
- if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
+ &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
@@ -1072,15 +1096,17 @@ em_setup_copper_link(struct em_hw *hw)
phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
if(hw->disable_polarity_correction == 1)
phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
- if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
- phy_data)))
+ ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
+ phy_data);
+ if(ret_val)
return ret_val;
/* Force TX_CLK in the Extended PHY Specific Control Register
* to 25MHz clock.
*/
- if((ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
+ &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= M88E1000_EPSCR_TX_CLK_25;
@@ -1091,14 +1117,15 @@ em_setup_copper_link(struct em_hw *hw)
M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
- if((ret_val = em_write_phy_reg(hw,
- M88E1000_EXT_PHY_SPEC_CTRL,
- phy_data)))
+ ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
+ phy_data);
+ if(ret_val)
return ret_val;
}
/* SW Reset the PHY so all changes take effect */
- if((ret_val = em_phy_reset(hw))) {
+ ret_val = em_phy_reset(hw);
+ if(ret_val) {
DEBUGOUT("Error Resetting the PHY\n");
return ret_val;
}
@@ -1132,7 +1159,8 @@ em_setup_copper_link(struct em_hw *hw)
hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
- if((ret_val = em_phy_setup_autoneg(hw))) {
+ ret_val = em_phy_setup_autoneg(hw);
+ if(ret_val) {
DEBUGOUT("Error Setting up Auto-Negotiation\n");
return ret_val;
}
@@ -1141,18 +1169,21 @@ em_setup_copper_link(struct em_hw *hw)
/* Restart auto-negotiation by setting the Auto Neg Enable bit and
* the Auto Neg Restart bit in the PHY control register.
*/
- if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
- if((ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data)))
+ ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
+ if(ret_val)
return ret_val;
/* Does the user want to wait for Auto-Neg to complete here, or
* check at a later time (for example, callback routine).
*/
if(hw->wait_autoneg_complete) {
- if((ret_val = em_wait_autoneg(hw))) {
+ ret_val = em_wait_autoneg(hw);
+ if(ret_val) {
DEBUGOUT("Error while waiting for autoneg to complete\n");
return ret_val;
}
@@ -1160,7 +1191,8 @@ em_setup_copper_link(struct em_hw *hw)
hw->get_link_status = TRUE;
} else {
DEBUGOUT("Forcing speed and duplex\n");
- if((ret_val = em_phy_force_speed_duplex(hw))) {
+ ret_val = em_phy_force_speed_duplex(hw);
+ if(ret_val) {
DEBUGOUT("Error Forcing Speed and Duplex\n");
return ret_val;
}
@@ -1171,9 +1203,11 @@ em_setup_copper_link(struct em_hw *hw)
* valid.
*/
for(i = 0; i < 10; i++) {
- if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
- if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
if(phy_data & MII_SR_LINK_STATUS) {
@@ -1188,19 +1222,22 @@ em_setup_copper_link(struct em_hw *hw)
if(hw->mac_type >= em_82544) {
em_config_collision_dist(hw);
} else {
- if((ret_val = em_config_mac_to_phy(hw))) {
+ ret_val = em_config_mac_to_phy(hw);
+ if(ret_val) {
DEBUGOUT("Error configuring MAC to PHY settings\n");
return ret_val;
}
}
- if((ret_val = em_config_fc_after_link_up(hw))) {
+ ret_val = em_config_fc_after_link_up(hw);
+ if(ret_val) {
DEBUGOUT("Error Configuring Flow Control\n");
return ret_val;
}
DEBUGOUT("Valid link established!!!\n");
if(hw->phy_type == em_phy_igp) {
- if((ret_val = em_config_dsp_after_link_change(hw, TRUE))) {
+ ret_val = em_config_dsp_after_link_change(hw, TRUE);
+ if(ret_val) {
DEBUGOUT("Error Configuring DSP after link up\n");
return ret_val;
}
@@ -1230,12 +1267,13 @@ em_phy_setup_autoneg(struct em_hw *hw)
DEBUGFUNC("em_phy_setup_autoneg");
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
- if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
- &mii_autoneg_adv_reg)))
+ ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
+ if(ret_val)
return ret_val;
/* Read the MII 1000Base-T Control Register (Address 9). */
- if((ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
+ ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
+ if(ret_val)
return ret_val;
/* Need to parse both autoneg_advertised and fc and set up
@@ -1342,13 +1380,14 @@ em_phy_setup_autoneg(struct em_hw *hw)
return -E1000_ERR_CONFIG;
}
- if((ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV,
- mii_autoneg_adv_reg)))
+ ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
+ if(ret_val)
return ret_val;
DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
- if((ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
+ ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
+ if(ret_val)
return ret_val;
return E1000_SUCCESS;
@@ -1387,7 +1426,8 @@ em_phy_force_speed_duplex(struct em_hw *hw)
ctrl &= ~E1000_CTRL_ASDE;
/* Read the MII Control Register. */
- if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg)))
+ ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
+ if(ret_val)
return ret_val;
/* We need to disable autoneg in order to force link and duplex. */
@@ -1489,10 +1529,12 @@ em_phy_force_speed_duplex(struct em_hw *hw)
/* Read the MII Status Register and wait for Auto-Neg Complete bit
* to be set.
*/
- if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+ if(ret_val)
return ret_val;
- if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+ if(ret_val)
return ret_val;
if(mii_status_reg & MII_SR_LINK_STATUS) break;
@@ -1500,7 +1542,8 @@ em_phy_force_speed_duplex(struct em_hw *hw)
}
if((i == 0) && (hw->phy_type == em_phy_m88)) {
/* We didn't get link. Reset the DSP and wait again for link. */
- if((ret_val = em_phy_reset_dsp(hw))) {
+ ret_val = em_phy_reset_dsp(hw);
+ if(ret_val) {
DEBUGOUT("Error Resetting PHY DSP\n");
return ret_val;
}
@@ -1512,10 +1555,12 @@ em_phy_force_speed_duplex(struct em_hw *hw)
/* Read the MII Status Register and wait for Auto-Neg Complete bit
* to be set.
*/
- if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+ if(ret_val)
return ret_val;
- if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+ if(ret_val)
return ret_val;
}
}
@@ -1525,46 +1570,26 @@ em_phy_force_speed_duplex(struct em_hw *hw)
* Extended PHY Specific Control Register to 25MHz clock. This value
* defaults back to a 2.5MHz clock when the PHY is reset.
*/
- if((ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= M88E1000_EPSCR_TX_CLK_25;
- if((ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
- phy_data)))
+ ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
+ if(ret_val)
return ret_val;
/* In addition, because of the s/w reset above, we need to enable CRS on
* TX. This must be set for both full and half duplex operation.
*/
- if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
- if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
- phy_data)))
+ ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+ if(ret_val)
return ret_val;
-
- /* Polarity reversal workaround for forced 10F/10H links. */
- if(hw->mac_type <= em_82544 &&
- (hw->forced_speed_duplex == em_10_full ||
- hw->forced_speed_duplex == em_10_half)) {
- if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
- 0x0019)))
- return ret_val;
- if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
- 0x8F0F)))
- return ret_val;
- /* IEEE requirement is 150ms */
- msec_delay(200);
- if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
- 0x0019)))
- return ret_val;
- if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
- 0x8F00)))
- return ret_val;
- }
}
return E1000_SUCCESS;
}
@@ -1622,8 +1647,9 @@ em_config_mac_to_phy(struct em_hw *hw)
* registers depending on negotiated values.
*/
if (hw->phy_type == em_phy_igp) {
- if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
@@ -1641,8 +1667,9 @@ em_config_mac_to_phy(struct em_hw *hw)
IGP01E1000_PSSR_SPEED_100MBPS)
ctrl |= E1000_CTRL_SPD_100;
} else {
- if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
@@ -1760,7 +1787,8 @@ em_config_fc_after_link_up(struct em_hw *hw)
if(((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) ||
((hw->media_type == em_media_type_internal_serdes) && (hw->autoneg_failed)) ||
((hw->media_type == em_media_type_copper) && (!hw->autoneg))) {
- if((ret_val = em_force_mac_fc(hw))) {
+ ret_val = em_force_mac_fc(hw);
+ if(ret_val) {
DEBUGOUT("Error forcing flow control settings\n");
return ret_val;
}
@@ -1776,9 +1804,11 @@ em_config_fc_after_link_up(struct em_hw *hw)
* has completed. We read this twice because this reg has
* some "sticky" (latched) bits.
*/
- if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+ if(ret_val)
return ret_val;
- if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
+ ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+ if(ret_val)
return ret_val;
if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
@@ -1788,11 +1818,13 @@ em_config_fc_after_link_up(struct em_hw *hw)
* Register (Address 5) to determine how flow control was
* negotiated.
*/
- if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
- &mii_nway_adv_reg)))
+ ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
+ &mii_nway_adv_reg);
+ if(ret_val)
return ret_val;
- if((ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
- &mii_nway_lp_ability_reg)))
+ ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
+ &mii_nway_lp_ability_reg);
+ if(ret_val)
return ret_val;
/* Two bits in the Auto Negotiation Advertisement Register
@@ -1909,7 +1941,8 @@ em_config_fc_after_link_up(struct em_hw *hw)
* negotiated to HALF DUPLEX, flow control should not be
* enabled per IEEE 802.3 spec.
*/
- if((ret_val = em_get_speed_and_duplex(hw, &speed, &duplex))) {
+ ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
+ if(ret_val) {
DEBUGOUT("Error getting link speed and duplex\n");
return ret_val;
}
@@ -1920,7 +1953,8 @@ em_config_fc_after_link_up(struct em_hw *hw)
/* Now we call a subroutine to actually force the MAC
* controller to use the correct flow control settings.
*/
- if((ret_val = em_force_mac_fc(hw))) {
+ ret_val = em_force_mac_fc(hw);
+ if(ret_val) {
DEBUGOUT("Error forcing flow control settings\n");
return ret_val;
}
@@ -1941,7 +1975,7 @@ em_config_fc_after_link_up(struct em_hw *hw)
int32_t
em_check_for_link(struct em_hw *hw)
{
- uint32_t rxcw;
+ uint32_t rxcw = 0;
uint32_t ctrl;
uint32_t status;
uint32_t rctl;
@@ -1951,16 +1985,23 @@ em_check_for_link(struct em_hw *hw)
DEBUGFUNC("em_check_for_link");
+ ctrl = E1000_READ_REG(hw, CTRL);
+ status = E1000_READ_REG(hw, STATUS);
+
/* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
* set when the optics detect a signal. On older adapters, it will be
* cleared when there is a signal. This applies to fiber media only.
*/
- if(hw->media_type == em_media_type_fiber)
- signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
+ if((hw->media_type == em_media_type_fiber) ||
+ (hw->media_type == em_media_type_internal_serdes)) {
+ rxcw = E1000_READ_REG(hw, RXCW);
- ctrl = E1000_READ_REG(hw, CTRL);
- status = E1000_READ_REG(hw, STATUS);
- rxcw = E1000_READ_REG(hw, RXCW);
+ if(hw->media_type == em_media_type_fiber) {
+ signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
+ if(status & E1000_STATUS_LU)
+ hw->get_link_status = FALSE;
+ }
+ }
/* If we have a copper PHY then we only want to go out to the PHY
* registers to see if Auto-Neg has completed and/or if our link
@@ -1974,9 +2015,11 @@ em_check_for_link(struct em_hw *hw)
* of the PHY.
* Read the register twice since the link bit is sticky.
*/
- if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
- if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
if(phy_data & MII_SR_LINK_STATUS) {
@@ -2010,7 +2053,8 @@ em_check_for_link(struct em_hw *hw)
if(hw->mac_type >= em_82544)
em_config_collision_dist(hw);
else {
- if((ret_val = em_config_mac_to_phy(hw))) {
+ ret_val = em_config_mac_to_phy(hw);
+ if(ret_val) {
DEBUGOUT("Error configuring MAC to PHY settings\n");
return ret_val;
}
@@ -2020,7 +2064,8 @@ em_check_for_link(struct em_hw *hw)
* need to restore the desired flow control settings because we may
* have had to re-autoneg with a different link partner.
*/
- if((ret_val = em_config_fc_after_link_up(hw))) {
+ ret_val = em_config_fc_after_link_up(hw);
+ if(ret_val) {
DEBUGOUT("Error configuring flow control\n");
return ret_val;
}
@@ -2069,8 +2114,8 @@ em_check_for_link(struct em_hw *hw)
* in. The autoneg_failed flag does this.
*/
else if((((hw->media_type == em_media_type_fiber) &&
- ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
- (hw->media_type == em_media_type_internal_serdes)) &&
+ ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
+ (hw->media_type == em_media_type_internal_serdes)) &&
(!(status & E1000_STATUS_LU)) &&
(!(rxcw & E1000_RXCW_C))) {
if(hw->autoneg_failed == 0) {
@@ -2088,7 +2133,8 @@ em_check_for_link(struct em_hw *hw)
E1000_WRITE_REG(hw, CTRL, ctrl);
/* Configure Flow Control after forcing link up. */
- if((ret_val = em_config_fc_after_link_up(hw))) {
+ ret_val = em_config_fc_after_link_up(hw);
+ if(ret_val) {
DEBUGOUT("Error configuring flow control\n");
return ret_val;
}
@@ -2100,8 +2146,7 @@ em_check_for_link(struct em_hw *hw)
*/
else if(((hw->media_type == em_media_type_fiber) ||
(hw->media_type == em_media_type_internal_serdes)) &&
- (ctrl & E1000_CTRL_SLU) &&
- (rxcw & E1000_RXCW_C)) {
+ (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
E1000_WRITE_REG(hw, TXCW, hw->txcw);
E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
@@ -2181,13 +2226,15 @@ em_get_speed_and_duplex(struct em_hw *hw,
* match the duplex in the link partner's capabilities.
*/
if(hw->phy_type == em_phy_igp && hw->speed_downgraded) {
- if((ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
+ if(ret_val)
return ret_val;
if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
*duplex = HALF_DUPLEX;
else {
- if((ret_val == em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
+ if(ret_val)
return ret_val;
if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
(*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
@@ -2218,9 +2265,11 @@ em_wait_autoneg(struct em_hw *hw)
/* Read the MII Status Register and wait for Auto-Neg
* Complete bit to be set.
*/
- if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
- if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
if(phy_data & MII_SR_AUTONEG_COMPLETE) {
return E1000_SUCCESS;
@@ -2385,8 +2434,9 @@ em_read_phy_reg(struct em_hw *hw,
if(hw->phy_type == em_phy_igp &&
(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
- if((ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
- (uint16_t)reg_addr)))
+ ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
+ (uint16_t)reg_addr);
+ if(ret_val)
return ret_val;
}
@@ -2488,8 +2538,9 @@ em_write_phy_reg(struct em_hw *hw,
if(hw->phy_type == em_phy_igp &&
(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
- if((ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
- (uint16_t)reg_addr)))
+ ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
+ (uint16_t)reg_addr);
+ if(ret_val)
return ret_val;
}
@@ -2628,11 +2679,13 @@ em_phy_reset(struct em_hw *hw)
DEBUGFUNC("em_phy_reset");
if(hw->mac_type != em_82541_rev_2) {
- if((ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= MII_CR_RESET;
- if((ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data)))
+ ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
+ if(ret_val)
return ret_val;
usec_delay(1);
@@ -2659,12 +2712,14 @@ em_detect_gig_phy(struct em_hw *hw)
DEBUGFUNC("em_detect_gig_phy");
/* Read the PHY ID Registers to identify which PHY is onboard. */
- if((ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
+ ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high);
+ if(ret_val)
return ret_val;
hw->phy_id = (uint32_t) (phy_id_high << 16);
usec_delay(20);
- if((ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
+ ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low);
+ if(ret_val)
return ret_val;
hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
@@ -2716,9 +2771,12 @@ em_phy_reset_dsp(struct em_hw *hw)
DEBUGFUNC("em_phy_reset_dsp");
do {
- if((ret_val = em_write_phy_reg(hw, 29, 0x001d))) break;
- if((ret_val = em_write_phy_reg(hw, 30, 0x00c1))) break;
- if((ret_val = em_write_phy_reg(hw, 30, 0x0000))) break;
+ ret_val = em_write_phy_reg(hw, 29, 0x001d);
+ if(ret_val) break;
+ ret_val = em_write_phy_reg(hw, 30, 0x00c1);
+ if(ret_val) break;
+ ret_val = em_write_phy_reg(hw, 30, 0x0000);
+ if(ret_val) break;
ret_val = E1000_SUCCESS;
} while(0);
@@ -2751,13 +2809,14 @@ em_phy_igp_get_info(struct em_hw *hw,
phy_info->polarity_correction = em_polarity_reversal_enabled;
/* Check polarity status */
- if((ret_val = em_check_polarity(hw, &polarity)))
+ ret_val = em_check_polarity(hw, &polarity);
+ if(ret_val)
return ret_val;
phy_info->cable_polarity = polarity;
- if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
@@ -2766,7 +2825,8 @@ em_phy_igp_get_info(struct em_hw *hw,
if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
IGP01E1000_PSSR_SPEED_1000MBPS) {
/* Local/Remote Receiver Information are only valid at 1000 Mbps */
- if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
@@ -2775,7 +2835,8 @@ em_phy_igp_get_info(struct em_hw *hw,
SR_1000T_REMOTE_RX_STATUS_SHIFT;
/* Get cable length */
- if((ret_val = em_get_cable_length(hw, &min_length, &max_length)))
+ ret_val = em_get_cable_length(hw, &min_length, &max_length);
+ if(ret_val)
return ret_val;
/* transalte to old method */
@@ -2815,7 +2876,8 @@ em_phy_m88_get_info(struct em_hw *hw,
* and it stored in the hw->speed_downgraded parameter. */
phy_info->downshift = hw->speed_downgraded;
- if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data)))
+ ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+ if(ret_val)
return ret_val;
phy_info->extended_10bt_distance =
@@ -2826,12 +2888,14 @@ em_phy_m88_get_info(struct em_hw *hw,
M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
/* Check polarity status */
- if((ret_val = em_check_polarity(hw, &polarity)))
+ ret_val = em_check_polarity(hw, &polarity);
+ if(ret_val)
return ret_val;
phy_info->cable_polarity = polarity;
- if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data)))
+ ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
@@ -2844,7 +2908,8 @@ em_phy_m88_get_info(struct em_hw *hw,
phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
M88E1000_PSSR_CABLE_LENGTH_SHIFT);
- if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
@@ -2886,10 +2951,12 @@ em_phy_get_info(struct em_hw *hw,
return -E1000_ERR_CONFIG;
}
- if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
- if((ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
+ if(ret_val)
return ret_val;
if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
@@ -3352,6 +3419,7 @@ em_spi_eeprom_ready(struct em_hw *hw)
usec_delay(5);
retry_count += 5;
+ em_standby_eeprom(hw);
} while(retry_count < EEPROM_MAX_RETRY_SPI);
/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
@@ -4120,12 +4188,14 @@ em_setup_led(struct em_hw *hw)
case em_82541_rev_2:
case em_82547_rev_2:
/* Turn off PHY Smart Power Down (if enabled) */
- if((ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
- &hw->phy_spd_default)))
+ ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
+ &hw->phy_spd_default);
+ if(ret_val)
return ret_val;
- if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
- (uint16_t)(hw->phy_spd_default &
- ~IGP01E1000_GMII_SPD))))
+ ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+ (uint16_t)(hw->phy_spd_default &
+ ~IGP01E1000_GMII_SPD));
+ if(ret_val)
return ret_val;
/* Fall Through */
default:
@@ -4172,8 +4242,9 @@ em_cleanup_led(struct em_hw *hw)
case em_82541_rev_2:
case em_82547_rev_2:
/* Turn on PHY Smart Power Down (if previously enabled) */
- if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
- hw->phy_spd_default)))
+ ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+ hw->phy_spd_default);
+ if(ret_val)
return ret_val;
/* Fall Through */
default:
@@ -4620,8 +4691,9 @@ em_get_cable_length(struct em_hw *hw,
/* Use old method for Phy older than IGP */
if(hw->phy_type == em_phy_m88) {
- if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
/* Convert the enum value to ranged values */
@@ -4660,7 +4732,8 @@ em_get_cable_length(struct em_hw *hw,
/* Read the AGC registers for all channels */
for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
- if((ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data)))
+ ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data);
+ if(ret_val)
return ret_val;
cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
@@ -4727,15 +4800,17 @@ em_check_polarity(struct em_hw *hw,
if(hw->phy_type == em_phy_m88) {
/* return the Polarity bit in the Status register. */
- if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
*polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
M88E1000_PSSR_REV_POLARITY_SHIFT;
} else if(hw->phy_type == em_phy_igp) {
/* Read the Status register to check the speed */
- if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
/* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
@@ -4744,8 +4819,9 @@ em_check_polarity(struct em_hw *hw,
IGP01E1000_PSSR_SPEED_1000MBPS) {
/* Read the GIG initialization PCS register (0x00B4) */
- if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
+ &phy_data);
+ if(ret_val)
return ret_val;
/* Check the polarity bits */
@@ -4783,15 +4859,17 @@ em_check_downshift(struct em_hw *hw)
DEBUGFUNC("em_check_downshift");
if(hw->phy_type == em_phy_igp) {
- if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
+ &phy_data);
+ if(ret_val)
return ret_val;
hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
}
else if(hw->phy_type == em_phy_m88) {
- if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
@@ -4831,7 +4909,8 @@ em_config_dsp_after_link_change(struct em_hw *hw,
return E1000_SUCCESS;
if(link_up) {
- if((ret_val = em_get_speed_and_duplex(hw, &speed, &duplex))) {
+ ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
+ if(ret_val) {
DEBUGOUT("Error getting link speed and duplex\n");
return ret_val;
}
@@ -4844,14 +4923,16 @@ em_config_dsp_after_link_change(struct em_hw *hw,
min_length >= em_igp_cable_length_50) {
for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
- if((ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
+ &phy_data);
+ if(ret_val)
return ret_val;
phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
- if((ret_val = em_write_phy_reg(hw, dsp_reg_array[i],
- phy_data)))
+ ret_val = em_write_phy_reg(hw, dsp_reg_array[i],
+ phy_data);
+ if(ret_val)
return ret_val;
}
hw->dsp_config_state = em_dsp_config_activated;
@@ -4864,23 +4945,26 @@ em_config_dsp_after_link_change(struct em_hw *hw,
uint32_t idle_errs = 0;
/* clear previous idle error counts */
- if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
for(i = 0; i < ffe_idle_err_timeout; i++) {
usec_delay(1000);
- if((ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
+ &phy_data);
+ if(ret_val)
return ret_val;
idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
hw->ffe_config_state = em_ffe_config_active;
- if((ret_val = em_write_phy_reg(hw,
+ ret_val = em_write_phy_reg(hw,
IGP01E1000_PHY_DSP_FFE,
- IGP01E1000_PHY_DSP_FFE_CM_CP)))
+ IGP01E1000_PHY_DSP_FFE_CM_CP);
+ if(ret_val)
return ret_val;
break;
}
@@ -4892,47 +4976,91 @@ em_config_dsp_after_link_change(struct em_hw *hw,
}
} else {
if(hw->dsp_config_state == em_dsp_config_activated) {
- if((ret_val = em_write_phy_reg(hw, 0x0000,
- IGP01E1000_IEEE_FORCE_GIGA)))
+ ret_val = em_write_phy_reg(hw, 0x0000,
+ IGP01E1000_IEEE_FORCE_GIGA);
+ if(ret_val)
return ret_val;
for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
- if((ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
+ if(ret_val)
return ret_val;
phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
- if((ret_val = em_write_phy_reg(hw,dsp_reg_array[i],
- phy_data)))
+ ret_val = em_write_phy_reg(hw,dsp_reg_array[i], phy_data);
+ if(ret_val)
return ret_val;
}
- if((ret_val = em_write_phy_reg(hw, 0x0000,
- IGP01E1000_IEEE_RESTART_AUTONEG)))
+ ret_val = em_write_phy_reg(hw, 0x0000,
+ IGP01E1000_IEEE_RESTART_AUTONEG);
+ if(ret_val)
return ret_val;
hw->dsp_config_state = em_dsp_config_enabled;
}
if(hw->ffe_config_state == em_ffe_config_active) {
- if((ret_val = em_write_phy_reg(hw, 0x0000,
- IGP01E1000_IEEE_FORCE_GIGA)))
+ ret_val = em_write_phy_reg(hw, 0x0000,
+ IGP01E1000_IEEE_FORCE_GIGA);
+ if(ret_val)
return ret_val;
- if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
- IGP01E1000_PHY_DSP_FFE_DEFAULT)))
+ ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
+ IGP01E1000_PHY_DSP_FFE_DEFAULT);
+ if(ret_val)
return ret_val;
- if((ret_val = em_write_phy_reg(hw, 0x0000,
- IGP01E1000_IEEE_RESTART_AUTONEG)))
+ ret_val = em_write_phy_reg(hw, 0x0000,
+ IGP01E1000_IEEE_RESTART_AUTONEG);
+ if(ret_val)
return ret_val;
- hw->ffe_config_state = em_ffe_config_enabled;
+ hw->ffe_config_state = em_ffe_config_enabled;
}
}
return E1000_SUCCESS;
}
/*****************************************************************************
+ * Set PHY to class A mode
+ * Assumes the following operations will follow to enable the new class mode.
+ * 1. Do a PHY soft reset
+ * 2. Restart auto-negotiation or force link.
+ *
+ * hw - Struct containing variables accessed by shared code
+ ****************************************************************************/
+static int32_t
+em_set_phy_mode(struct em_hw *hw)
+{
+ int32_t ret_val;
+ uint16_t eeprom_data;
+
+ DEBUGFUNC("em_set_phy_mode");
+
+ if((hw->mac_type == em_82545_rev_3) &&
+ (hw->media_type == em_media_type_copper)) {
+ ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
+ if(ret_val) {
+ return ret_val;
+ }
+
+ if((eeprom_data != EEPROM_RESERVED_WORD) &&
+ (eeprom_data & EEPROM_PHY_CLASS_A)) {
+ ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
+ if(ret_val)
+ return ret_val;
+ ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
+ if(ret_val)
+ return ret_val;
+
+ hw->phy_reset_disable = FALSE;
+ }
+ }
+
+ return E1000_SUCCESS;
+}
+
+/*****************************************************************************
*
* This function sets the lplu state according to the active flag. When
* activating lplu this function also disables smart speed and vise versa.
@@ -4961,25 +5089,27 @@ em_set_d3_lplu_state(struct em_hw *hw,
/* During driver activity LPLU should not be used or it will attain link
* from the lowest speeds starting from 10Mbps. The capability is used for
* Dx transitions and states */
- if((ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data)))
+ ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
+ if(ret_val)
return ret_val;
if(!active) {
phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
- if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data)))
+ ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
+ if(ret_val)
return ret_val;
/* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
* Dx states where the power conservation is most important. During
* driver activity we should enable SmartSpeed, so performance is
* maintained. */
- if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
- if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
- phy_data)))
+ ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
+ if(ret_val)
return ret_val;
} else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
@@ -4987,17 +5117,18 @@ em_set_d3_lplu_state(struct em_hw *hw,
(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
phy_data |= IGP01E1000_GMII_FLEX_SPD;
- if((ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data)))
+ ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
+ if(ret_val)
return ret_val;
/* When LPLU is enabled we should disable SmartSpeed */
- if((ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
- &phy_data)))
+ ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
+ if(ret_val)
return ret_val;
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- if((ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
- phy_data)))
+ ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
+ if(ret_val)
return ret_val;
}
@@ -5028,34 +5159,40 @@ em_set_vco_speed(struct em_hw *hw)
/* Set PHY register 30, page 5, bit 8 to 0 */
- if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
- &default_page)))
+ ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
+ if(ret_val)
return ret_val;
- if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005)))
+ ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
+ if(ret_val)
return ret_val;
- if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data)))
+ ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
- if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data)))
+ ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
+ if(ret_val)
return ret_val;
/* Set PHY register 30, page 4, bit 11 to 1 */
- if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004)))
+ ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
+ if(ret_val)
return ret_val;
- if((ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data)))
+ ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
+ if(ret_val)
return ret_val;
phy_data |= M88E1000_PHY_VCO_REG_BIT11;
- if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data)))
+ ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
+ if(ret_val)
return ret_val;
- if((ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
- default_page)))
+ ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
+ if(ret_val)
return ret_val;
return E1000_SUCCESS;
diff --git a/sys/dev/em/if_em_hw.h b/sys/dev/em/if_em_hw.h
index 5157bee5b6690..f3574bd4de5e3 100644
--- a/sys/dev/em/if_em_hw.h
+++ b/sys/dev/em/if_em_hw.h
@@ -42,7 +42,7 @@
#include <dev/em/if_em_osdep.h>
#ifndef NO_VERSION_CONTROL
-#ident "@(#)$RCSfile: if_em_hw.h,v $$Revision: 1.37 $$Date: 2003/12/20 00:14:51 $"
+#ident "@(#)$RCSfile: if_em_hw.h,v $$Revision: 1.41 $$Date: 2004/05/17 15:18:53 $"
#endif
/* Forward declarations of structures used by the shared code */
@@ -365,6 +365,7 @@ int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active);
#define E1000_DEV_ID_82547GI 0x1075
#define E1000_DEV_ID_82541GI 0x1076
#define E1000_DEV_ID_82541GI_MOBILE 0x1077
+#define E1000_DEV_ID_82541GI_LF 0x107C
#define E1000_DEV_ID_82546GB_COPPER 0x1079
#define E1000_DEV_ID_82546GB_FIBER 0x107A
#define E1000_DEV_ID_82546GB_SERDES 0x107B
@@ -378,6 +379,9 @@ int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active);
#define E1000_82542_2_0_REV_ID 2
#define E1000_82542_2_1_REV_ID 3
+#define E1000_REVISION_0 0
+#define E1000_REVISION_1 1
+#define E1000_REVISION_2 2
#define SPEED_10 10
#define SPEED_100 100
@@ -772,6 +776,7 @@ struct em_ffvt_entry {
#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
+#define E1000_HOST_IF 0x08800 /* Host Interface */
#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
@@ -908,6 +913,7 @@ struct em_ffvt_entry {
#define E1000_82542_TDFT 0x08018
#define E1000_82542_FFMT E1000_FFMT
#define E1000_82542_FFVT E1000_FFVT
+#define E1000_82542_HOST_IF E1000_HOST_IF
/* Statistics counters collected by the MAC */
struct em_hw_stats {
@@ -1443,6 +1449,10 @@ struct em_hw {
#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
+#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
+ * filtering */
+#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
+ * memory */
#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
@@ -1489,6 +1499,7 @@ struct em_hw {
#define EEPROM_COMPAT 0x0003
#define EEPROM_ID_LED_SETTINGS 0x0004
#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
+#define EEPROM_PHY_CLASS_WORD 0x0007
#define EEPROM_INIT_CONTROL1_REG 0x000A
#define EEPROM_INIT_CONTROL2_REG 0x000F
#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
@@ -1522,6 +1533,9 @@ struct em_hw {
/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
+/* Mask bit for PHY class in Word 7 of the EEPROM */
+#define EEPROM_PHY_CLASS_A 0x8000
+
/* Mask bits for fields in Word 0x0a of the EEPROM */
#define EEPROM_WORD0A_ILOS 0x0010
#define EEPROM_WORD0A_SWDPIO 0x01E0
@@ -1549,7 +1563,7 @@ struct em_hw {
#define PBA_SIZE 4
/* Collision related configuration parameters */
-#define E1000_COLLISION_THRESHOLD 16
+#define E1000_COLLISION_THRESHOLD 15
#define E1000_CT_SHIFT 4
#define E1000_COLLISION_DISTANCE 64
#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
@@ -2015,7 +2029,7 @@ struct em_hw {
#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
/* IGP01E1000 Specific Port Control Register - R/W */
-#define IGP01E1000_PSCR_TP_LOOPBACK 0x0001
+#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
@@ -2025,16 +2039,18 @@ struct em_hw {
/* IGP01E1000 Specific Port Link Health Register */
#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
+#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
+#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
-#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0010
-#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0008
-#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0004
-#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0002
-#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0001
-#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0000
+#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
+#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
+#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
+#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
+#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
+#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
/* IGP01E1000 Channel Quality Register */
#define IGP01E1000_MSE_CHANNEL_D 0x000F
generated by cgit v1.3 (git 2.53.0) at 2026-08-04 00:37:24 +0000