2 files changed, 241 insertions, 28 deletions

diff --git a/sys/pccard/pcic_pci.c b/sys/pccard/pcic_pci.c
index edb19e2f4bfe2..63ddd89705f98 100644
--- a/sys/pccard/pcic_pci.c
+++ b/sys/pccard/pcic_pci.c
@@ -32,6 +32,7 @@
 #include <sys/param.h>
 #include <sys/kernel.h>
 #include <sys/systm.h>
+#include <sys/malloc.h>
 #include <sys/bus.h>
 #include <pci/pcireg.h>
 #include <pci/pcivar.h>
@@ -40,12 +41,14 @@
 #include <vm/vm.h>
 #include <vm/pmap.h>
 
+#define PRVERB(x)	if (bootverbose) device_printf x
+
 /*
  * Set up the CL-PD6832 to look like a ISA based PCMCIA chip (a
  * PD672X).  This routine is called once per PCMCIA socket.
  */
 static void
-pd6832_legacy_init(device_t self)
+pd6832_legacy_init(device_t dev)
 {
 	u_long bcr; 		/* to set interrupts */
 	u_short io_port;	/* the io_port to map this slot on */
@@ -53,7 +56,8 @@ pd6832_legacy_init(device_t self)
 	int unit;
 
 	num6832 = 0;
-	unit = device_get_unit(self);
+	unit = device_get_unit(dev);
+
 	/*
 	 * Some BIOS leave the legacy address uninitialized.  This
 	 * insures that the PD6832 puts itself where the driver will
@@ -63,15 +67,15 @@ pd6832_legacy_init(device_t self)
 	 */
 	io_port = PCIC_INDEX_0 + num6832 * CLPD6832_NUM_REGS;
 	if (unit == 0)
-		pci_write_config(self, CLPD6832_LEGACY_16BIT_IOADDR,
-				 io_port & ~PCI_MAP_IO, 4);
+		pci_write_config(dev, CLPD6832_LEGACY_16BIT_IOADDR,
+		    io_port & ~PCI_MAP_IO, 4);
 
 	/*
 	 * I think this should be a call to pci_map_port, but that
 	 * routine won't map regiaters above 0x28, and the register we
 	 * need to map is 0x44.
 	 */
-	io_port = pci_read_config(self, CLPD6832_LEGACY_16BIT_IOADDR, 4) &
+	io_port = pci_read_config(dev, CLPD6832_LEGACY_16BIT_IOADDR, 4) &
 	    ~PCI_MAP_IO;
 
 	/*
@@ -79,49 +83,148 @@ pd6832_legacy_init(device_t self)
 	 * words and deactivate the second by setting the limit lower
 	 * than the base.
 	 */
-	pci_write_config(self, CLPD6832_IO_BASE0, io_port | 1, 4);
-	pci_write_config(self, CLPD6832_IO_LIMIT0,
-			 (io_port + CLPD6832_NUM_REGS) | 1, 4);
+	pci_write_config(dev, CLPD6832_IO_BASE0, io_port | 1, 4);
+	pci_write_config(dev, CLPD6832_IO_LIMIT0,
+	    (io_port + CLPD6832_NUM_REGS) | 1, 4);
 
-	pci_write_config(self, CLPD6832_IO_BASE1, (io_port + 0x20) | 1, 4);
-	pci_write_config(self, CLPD6832_IO_LIMIT1, io_port | 1, 4);
+	pci_write_config(dev, CLPD6832_IO_BASE1, (io_port + 0x20) | 1, 4);
+	pci_write_config(dev, CLPD6832_IO_LIMIT1, io_port | 1, 4);
 
 	/*
 	 * Set default operating mode (I/O port space) and allocate
 	 * this socket to the current unit.
 	 */
-	pci_write_config(self, PCI_COMMAND_STATUS_REG,
-			 CLPD6832_COMMAND_DEFAULTS, 4);
-	pci_write_config(self, CLPD6832_SOCKET, unit, 4);
+	pci_write_config(dev, PCI_COMMAND_STATUS_REG,
+	    CLPD6832_COMMAND_DEFAULTS, 4);
+	pci_write_config(dev, CLPD6832_SOCKET, unit, 4);
 
 	/*
 	 * Set up the card inserted/card removed interrupts to come
 	 * through the isa IRQ.
 	 */
-	bcr = pci_read_config(self, CLPD6832_BRIDGE_CONTROL, 4);
+	bcr = pci_read_config(dev, CLPD6832_BRIDGE_CONTROL, 4);
 	bcr |= (CLPD6832_BCR_ISA_IRQ|CLPD6832_BCR_MGMT_IRQ_ENA);
-	pci_write_config(self, CLPD6832_BRIDGE_CONTROL, bcr, 4);
+	pci_write_config(dev, CLPD6832_BRIDGE_CONTROL, bcr, 4);
 
 	/* After initializing 2 sockets, the chip is fully configured */
 	if (unit == 1)
 		num6832++;
 
-	if (bootverbose)
-		printf("CardBus: Legacy PC-card 16bit I/O address [0x%x]\n",
-		       io_port);
+	PRVERB((dev, "CardBus: Legacy PC-card 16bit I/O address [0x%x]\n", 
+	    io_port));
 }
 
 /*
+ * TI1XXX PCI-CardBus Host Adapter specific function code.
+ * This function is separated from pcic_pci_attach().
+ * Support Device: TI1130,TI1131,TI1250,TI1220.
+ * Test Device: TI1221.
+ * Takeshi Shibagaki(shiba@jp.freebsd.org).
+ */
+static void
+ti1xxx_pci_init(device_t dev)
+{
+	u_long	syscntl,devcntl,cardcntl;
+	u_int32_t device_id = pci_get_devid(dev);
+	char	buf[128];
+	int 	ti113x = (device_id == PCI_DEVICE_ID_PCIC_TI1130)
+	    || (device_id == PCI_DEVICE_ID_PCIC_TI1131);
+
+	syscntl  = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
+	devcntl  = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
+	cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL,   1);
+
+	switch(ti113x){
+	case 0 :
+		strcpy(buf, "TI12XX PCI Config Reg: ");
+		break;
+	case 1 :
+		strcpy(buf, "TI113X PCI Config Reg: ");
+		/* 
+		 * Defalut card control register setting is
+		 * PCI interrupt.  The method of this code
+		 * switches PCI INT and ISA IRQ by bit 7 of
+		 * Bridge Control Register(Offset:0x3e,0x13e).
+		 * Takeshi Shibagaki(shiba@jp.freebsd.org) 
+		 */
+		cardcntl |= TI113X_CARDCNTL_PCI_IREQ;
+		cardcntl |= TI113X_CARDCNTL_PCI_CSC;
+		if (syscntl & TI113X_SYSCNTL_CLKRUN_ENA){
+			if (syscntl & TI113X_SYSCNTL_CLKRUN_SEL)
+				strcat(buf, "[clkrun irq 12]");
+			else
+				strcat(buf, "[clkrun irq 10]");
+		}
+		break;
+	}
+	if (cardcntl & TI113X_CARDCNTL_RING_ENA)
+		strcat(buf, "[ring enable]");
+	if (cardcntl & TI113X_CARDCNTL_SPKR_ENA)
+		strcat(buf, "[speaker enable]");
+	if (syscntl & TI113X_SYSCNTL_PWRSAVINGS)
+		strcat(buf, "[pwr save]");
+	switch(devcntl & TI113X_DEVCNTL_INTR_MASK){
+		case TI113X_DEVCNTL_INTR_ISA :
+			strcat(buf, "[CSC parallel isa irq]");
+			break;
+		case TI113X_DEVCNTL_INTR_SERIAL :
+			strcat(buf, "[CSC serial isa irq]");
+			break;
+		case TI113X_DEVCNTL_INTR_NONE :
+			strcat(buf, "[pci only]");
+			break;
+		case TI12XX_DEVCNTL_INTR_ALLSERIAL :
+			strcat(buf, "[FUNC pci int + CSC serial isa irq]");
+			break;
+	}
+	pci_write_config(dev, TI113X_PCI_CARD_CONTROL,  cardcntl, 1);
+	if (ti113x)
+		cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
+	device_printf(dev, "%s\n",buf);
+}
+
+static void
+generic_cardbus_attach(device_t dev)
+{
+	u_int16_t	brgcntl;
+	u_int32_t	iobase;
+	int		unit;
+
+	unit = device_get_unit(dev);
+
+	/* Output ISA IRQ indicated in ExCA register(0x03). */
+	brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
+	brgcntl |= CB_BCR_INT_EXCA;
+	pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
+
+	/* 16bit Legacy Mode Base Address */
+	if (unit != 0)
+		return;
+	
+	iobase = pci_read_config(dev, CB_PCI_LEGACY16_IOADDR, 2) 
+	    & ~PCI_MAP_IO;
+	if (!iobase) {
+		iobase = 0x3e0 | PCI_MAP_IO;
+		pci_write_config(dev, CB_PCI_LEGACY16_IOADDR, iobase, 2);
+		iobase = pci_read_config(dev, CB_PCI_LEGACY16_IOADDR, 2)
+		    & ~PCI_MAP_IO;
+	}
+	PRVERB((dev, "Legacy address set to %#x\n", iobase));
+	return;
+}
+
+
+/*
  * Return the ID string for the controller if the vendor/product id
  * matches, NULL otherwise.
  */
 static int
-pcic_pci_probe(device_t self)
+pcic_pci_probe(device_t dev)
 {
 	u_int32_t device_id;
 	char *desc;
 
-	device_id = pci_get_devid(self);
+	device_id = pci_get_devid(dev);
 	desc = NULL;
 
 	switch (device_id) {
@@ -182,6 +285,7 @@ pcic_pci_probe(device_t self)
 	case PCI_DEVICE_ID_RICOH_RL5C478:
 		desc = "Ricoh RL5C478 PCI-CardBus Bridge";
 		break;
+
 	/* 16bit PC-card bridges */
 	case PCI_DEVICE_ID_PCIC_CLPD6729:
 		desc = "Cirrus Logic PD6729/6730 PC-Card Controller";
@@ -200,7 +304,7 @@ pcic_pci_probe(device_t self)
 	if (desc == NULL)
 		return (ENXIO);
 	
-	device_set_desc(self, desc);
+	device_set_desc(dev, desc);
 	return 0;	/* exact match */
 }
 
@@ -210,13 +314,44 @@ pcic_pci_probe(device_t self)
  * it only understands the CL-PD6832.
  */
 static int
-pcic_pci_attach(device_t self)
+pcic_pci_attach(device_t dev)
 {
-	u_int32_t device_id = pci_get_devid(self);
+	u_int32_t device_id = pci_get_devid(dev);
+	u_long command;
+
+	/* Init. CardBus/PC-card controllers as 16-bit PC-card controllers */
+
+	/* Place any per "slot" initialization here */
+
+	/*
+	 * In sys/pci/pcireg.h, PCI_COMMAND_STATUS_REG must be separated
+	 * PCI_COMMAND_REG(0x04) and PCI_STATUS_REG(0x06).
+	 * Takeshi Shibagaki(shiba@jp.freebsd.org).
+	 */
+        command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
+        command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
+        pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4);
 
 	switch (device_id) {
+	case PCI_DEVICE_ID_PCIC_TI1130:
+	case PCI_DEVICE_ID_PCIC_TI1131:
+	case PCI_DEVICE_ID_PCIC_TI1220:
+	case PCI_DEVICE_ID_PCIC_TI1221:
+	case PCI_DEVICE_ID_PCIC_TI1250:
+	case PCI_DEVICE_ID_PCIC_TI1251:
+	case PCI_DEVICE_ID_PCIC_TI1251B:
+	case PCI_DEVICE_ID_PCIC_TI1225:
+	case PCI_DEVICE_ID_PCIC_TI1410:
+	case PCI_DEVICE_ID_PCIC_TI1420:
+	case PCI_DEVICE_ID_PCIC_TI1450:
+	case PCI_DEVICE_ID_PCIC_TI1451:
+                ti1xxx_pci_init(dev);
+		/* FALLTHROUGH */
+	default:
+                generic_cardbus_attach(dev);
+                break;
 	case PCI_DEVICE_ID_PCIC_CLPD6832:
-		pd6832_legacy_init(self);
+		pd6832_legacy_init(dev);
 		break;
 	}
 
@@ -229,10 +364,10 @@ pcic_pci_attach(device_t self)
 		for (j = 0; j < 0x98; j += 16) {
 			printf("%02x: ", j);
 			for (i = 0; i < 16; i += 4)
-				printf(" %08x", pci_read_config(self, i+j, 4));
+				printf(" %08x", pci_read_config(dev, i+j, 4));
 			printf("\n");
 		}
-		p = (u_char *)pmap_mapdev(pci_read_config(self, 0x10, 4),
+		p = (u_char *)pmap_mapdev(pci_read_config(dev, 0x10, 4),
 					  0x1000);
 		pl = (u_long *)p;
 		printf("Cardbus Socket registers:\n");
@@ -247,10 +382,9 @@ pcic_pci_attach(device_t self)
 			printf("%02x: %16D\n", i, p + 0x800 + i, " ");
 	}
 
-	return 0;	/* no error */
+	return 0;
 }
 
-
 static device_method_t pcic_pci_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,		pcic_pci_probe),
diff --git a/sys/pccard/pcic_pci.h b/sys/pccard/pcic_pci.h
index 0193a11ab17c2..a6966a87c3fda 100644
--- a/sys/pccard/pcic_pci.h
+++ b/sys/pccard/pcic_pci.h
@@ -69,3 +69,82 @@
 #define	CLPD6832_NUM_REGS		2
 
 /* End of CL-PD6832 defines */
+/* Texas Instruments PCI-1130/1131 CardBus Controller */
+#define TI113X_PCI_SYSTEM_CONTROL	0x80	/* System Control */
+#define TI113X_PCI_RETRY_STATUS		0x90	/* Retry Status */
+#define TI113X_PCI_CARD_CONTROL		0x91	/* Card Control */
+#define TI113X_PCI_DEVICE_CONTROL	0x92	/* Device Control */
+#define TI113X_PCI_BUFFER_CONTROL	0x93	/* Buffer Control */
+#define TI113X_PCI_SOCKET_DMA0		0x94	/* Socket DMA Register 0 */
+#define TI113X_PCI_SOCKET_DMA1		0x98	/* Socket DMA Register 1 */
+
+/* Card control register (TI113X_SYSTEM_CONTROL == 0x80) */
+#define TI113X_SYSCNTL_VCC_PROTECT	0x00200000u
+#define TI113X_SYSCNTL_CLKRUN_SEL	0x00000080u
+#define	TI113X_SYSCNTL_PWRSAVINGS	0x00000040u
+#define TI113X_SYSCNTL_KEEP_CLK		0x00000002u
+#define TI113X_SYSCNTL_CLKRUN_ENA	0x00000001u
+
+/* Card control register (TI113X_CARD_CONTROL == 0x91) */
+#define TI113X_CARDCNTL_RING_ENA	0x80u
+#define TI113X_CARDCNTL_ZOOM_VIDEO	0x40u
+#define TI113X_CARDCNTL_PCI_IRQ_ENA	0x20u
+#define TI113X_CARDCNTL_PCI_IREQ	0x10u
+#define TI113X_CARDCNTL_PCI_CSC		0x08u
+#define	TI113X_CARDCNTL_MASK		(TI113X_CARDCNTL_PCI_IRQ_ENA | TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC)
+#define	TI113X_FUNC0_VALID		TI113X_CARDCNTL_MASK
+#define	TI113X_FUNC1_VALID		(TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC)
+/* Reserved bit				0x04u */
+#define TI113X_CARDCNTL_SPKR_ENA	0x02u
+#define TI113X_CARDCNTL_INT		0x01u
+
+/* Device control register (TI113X_DEVICE_CONTROL == 0x92) */
+#define	TI113X_DEVCNTL_5V_SOCKET	0x40u
+#define	TI113X_DEVCNTL_3V_SOCKET	0x20u
+#define	TI113X_DEVCNTL_INTR_MASK	0x06u
+#define	TI113X_DEVCNTL_INTR_NONE	0x00u
+#define	TI113X_DEVCNTL_INTR_ISA		0x02u
+#define	TI113X_DEVCNTL_INTR_SERIAL	0x04u
+/* TI112X specific code */
+#define	TI12XX_DEVCNTL_INTR_ALLSERIAL	0x06u
+/* Texas Instruments PCI-1130/1131 CardBus Controller */
+#define	TI113X_ExCA_IO_OFFSET0		0x36	/* Offset of I/O window */
+#define	TI113X_ExCA_IO_OFFSET1		0x38	/* Offset of I/O window */
+#define	TI113X_ExCA_MEM_WINDOW_PAGE	0x3C	/* Memory Window Page */
+
+/* sanpei */
+
+/* For Bridge Control register (CB_PCI_BRIDGE_CTRL) */
+#define CB_BCR_CB_RESET		0x0040
+#define CB_BCR_INT_EXCA		0x0080
+/* PCI Configuration Registers (common) */
+#define	CB_PCI_VENDOR_ID	0x00	/* vendor ID */
+#define	CB_PCI_DEVICE_ID	0x02	/* device ID */
+#define	CB_PCI_COMMAND		0x04	/* PCI command */
+#define	CB_PCI_STATUS		0x06	/* PCI status */
+#define	CB_PCI_REVISION_ID	0x08	/* PCI revision ID */
+#define	CB_PCI_CLASS		0x09	/* PCI class code */
+#define	CB_PCI_CACHE_LINE_SIZE	0x0c	/* Cache line size */
+#define	CB_PCI_LATENCY		0x0d	/* PCI latency timer */
+#define	CB_PCI_HEADER_TYPE	0x0e	/* PCI header type */
+#define	CB_PCI_BIST		0x0f	/* Built-in self test */
+#define	CB_PCI_SOCKET_BASE	0x10	/* Socket/ExCA base address reg. */
+#define	CB_PCI_CB_STATUS	0x16	/* CardBus Status */
+#define	CB_PCI_PCI_BUS_NUM	0x18	/* PCI bus number */
+#define	CB_PCI_CB_BUS_NUM	0x19	/* CardBus bus number */
+#define	CB_PCI_CB_SUB_BUS_NUM	0x1A	/* Subordinate CardBus bus number */
+#define	CB_PCI_CB_LATENCY	0x1A	/* CardBus latency timer */
+#define	CB_PCI_MEMBASE0		0x1C	/* Memory base register 0 */
+#define	CB_PCI_MEMLIMIT0	0x20	/* Memory limit register 0 */
+#define	CB_PCI_MEMBASE1		0x24	/* Memory base register 1 */
+#define	CB_PCI_MEMLIMIT1	0x28	/* Memory limit register 1 */
+#define	CB_PCI_IOBASE0		0x2C	/* I/O base register 0 */
+#define	CB_PCI_IOLIMIT0		0x30	/* I/O limit register 0 */
+#define	CB_PCI_IOBASE1		0x34	/* I/O base register 1 */
+#define	CB_PCI_IOLIMIT1		0x38	/* I/O limit register 1 */
+#define	CB_PCI_INT_LINE		0x3C	/* Interrupt Line */
+#define	CB_PCI_INT_PIN		0x3D	/* Interrupt Pin */
+#define	CB_PCI_BRIDGE_CTRL	0x3E	/* Bridge Control */
+#define	CB_PCI_SUBSYS_VENDOR_ID	0x40	/* Subsystem Vendor ID */
+#define	CB_PCI_SUBSYS_ID	0x42	/* Subsystem ID */
+#define	CB_PCI_LEGACY16_IOADDR	0x44	/* Legacy 16bit I/O address */