diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2013-04-08 18:41:23 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2013-04-08 18:41:23 +0000 |
| commit | 4a16efa3e43e35f0cc9efe3a67f620f0017c3d36 (patch) | |
| tree | 06099edc18d30894081a822b756f117cbe0b8207 /test/Analysis/CostModel | |
| parent | 482e7bddf617ae804dc47133cb07eb4aa81e45de (diff) | |
Notes
Diffstat (limited to 'test/Analysis/CostModel')
22 files changed, 2745 insertions, 32 deletions
diff --git a/test/Analysis/CostModel/ARM/cast.ll b/test/Analysis/CostModel/ARM/cast.ll new file mode 100644 index 0000000000000..ba9d84cf3e23e --- /dev/null +++ b/test/Analysis/CostModel/ARM/cast.ll @@ -0,0 +1,547 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=cortex-a8 | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios6.0.0" + +define i32 @casts() { + + ; -- scalars -- + ; CHECK: cost of 1 {{.*}} sext + %r0 = sext i1 undef to i8 + ; CHECK: cost of 1 {{.*}} zext + %r1 = zext i1 undef to i8 + ; CHECK: cost of 1 {{.*}} sext + %r2 = sext i1 undef to i16 + ; CHECK: cost of 1 {{.*}} zext + %r3 = zext i1 undef to i16 + ; CHECK: cost of 1 {{.*}} sext + %r4 = sext i1 undef to i32 + ; CHECK: cost of 1 {{.*}} zext + %r5 = zext i1 undef to i32 + ; CHECK: cost of 1 {{.*}} sext + %r6 = sext i1 undef to i64 + ; CHECK: cost of 1 {{.*}} zext + %r7 = zext i1 undef to i64 + ; CHECK: cost of 0 {{.*}} trunc + %r8 = trunc i8 undef to i1 + ; CHECK: cost of 1 {{.*}} sext + %r9 = sext i8 undef to i16 + ; CHECK: cost of 1 {{.*}} zext + %r10 = zext i8 undef to i16 + ; CHECK: cost of 1 {{.*}} sext + %r11 = sext i8 undef to i32 + ; CHECK: cost of 1 {{.*}} zext + %r12 = zext i8 undef to i32 + ; CHECK: cost of 1 {{.*}} sext + %r13 = sext i8 undef to i64 + ; CHECK: cost of 1 {{.*}} zext + %r14 = zext i8 undef to i64 + ; CHECK: cost of 0 {{.*}} trunc + %r15 = trunc i16 undef to i1 + ; CHECK: cost of 0 {{.*}} trunc + %r16 = trunc i16 undef to i8 + ; CHECK: cost of 1 {{.*}} sext + %r17 = sext i16 undef to i32 + ; CHECK: cost of 1 {{.*}} zext + %r18 = zext i16 undef to i32 + ; CHECK: cost of 2 {{.*}} sext + %r19 = sext i16 undef to i64 + ; CHECK: cost of 1 {{.*}} zext + %r20 = zext i16 undef to i64 + ; CHECK: cost of 0 {{.*}} trunc + %r21 = trunc i32 undef to i1 + ; CHECK: cost of 0 {{.*}} trunc + %r22 = trunc i32 undef to i8 + ; CHECK: cost of 0 {{.*}} trunc + %r23 = trunc i32 undef to i16 + ; CHECK: cost of 1 {{.*}} sext + %r24 = sext i32 undef to i64 + ; CHECK: cost of 1 {{.*}} zext + %r25 = zext i32 undef to i64 + ; CHECK: cost of 0 {{.*}} trunc + %r26 = trunc i64 undef to i1 + ; CHECK: cost of 0 {{.*}} trunc + %r27 = trunc i64 undef to i8 + ; CHECK: cost of 0 {{.*}} trunc + %r28 = trunc i64 undef to i16 + ; CHECK: cost of 0 {{.*}} trunc + %r29 = trunc i64 undef to i32 + + ; -- floating point conversions -- + ; Moves between scalar and NEON registers. + ; CHECK: cost of 2 {{.*}} fptoui + %r30 = fptoui float undef to i1 + ; CHECK: cost of 2 {{.*}} fptosi + %r31 = fptosi float undef to i1 + ; CHECK: cost of 2 {{.*}} fptoui + %r32 = fptoui float undef to i8 + ; CHECK: cost of 2 {{.*}} fptosi + %r33 = fptosi float undef to i8 + ; CHECK: cost of 2 {{.*}} fptoui + %r34 = fptoui float undef to i16 + ; CHECK: cost of 2 {{.*}} fptosi + %r35 = fptosi float undef to i16 + ; CHECK: cost of 2 {{.*}} fptoui + %r36 = fptoui float undef to i32 + ; CHECK: cost of 2 {{.*}} fptosi + %r37 = fptosi float undef to i32 + ; CHECK: cost of 10 {{.*}} fptoui + %r38 = fptoui float undef to i64 + ; CHECK: cost of 10 {{.*}} fptosi + %r39 = fptosi float undef to i64 + ; CHECK: cost of 2 {{.*}} fptoui + %r40 = fptoui double undef to i1 + ; CHECK: cost of 2 {{.*}} fptosi + %r41 = fptosi double undef to i1 + ; CHECK: cost of 2 {{.*}} fptoui + %r42 = fptoui double undef to i8 + ; CHECK: cost of 2 {{.*}} fptosi + %r43 = fptosi double undef to i8 + ; CHECK: cost of 2 {{.*}} fptoui + %r44 = fptoui double undef to i16 + ; CHECK: cost of 2 {{.*}} fptosi + %r45 = fptosi double undef to i16 + ; CHECK: cost of 2 {{.*}} fptoui + %r46 = fptoui double undef to i32 + ; CHECK: cost of 2 {{.*}} fptosi + %r47 = fptosi double undef to i32 + ; Function call + ; CHECK: cost of 10 {{.*}} fptoui + %r48 = fptoui double undef to i64 + ; CHECK: cost of 10 {{.*}} fptosi + %r49 = fptosi double undef to i64 + + ; CHECK: cost of 2 {{.*}} sitofp + %r50 = sitofp i1 undef to float + ; CHECK: cost of 2 {{.*}} uitofp + %r51 = uitofp i1 undef to float + ; CHECK: cost of 2 {{.*}} sitofp + %r52 = sitofp i1 undef to double + ; CHECK: cost of 2 {{.*}} uitofp + %r53 = uitofp i1 undef to double + ; CHECK: cost of 2 {{.*}} sitofp + %r54 = sitofp i8 undef to float + ; CHECK: cost of 2 {{.*}} uitofp + %r55 = uitofp i8 undef to float + ; CHECK: cost of 2 {{.*}} sitofp + %r56 = sitofp i8 undef to double + ; CHECK: cost of 2 {{.*}} uitofp + %r57 = uitofp i8 undef to double + ; CHECK: cost of 2 {{.*}} sitofp + %r58 = sitofp i16 undef to float + ; CHECK: cost of 2 {{.*}} uitofp + %r59 = uitofp i16 undef to float + ; CHECK: cost of 2 {{.*}} sitofp + %r60 = sitofp i16 undef to double + ; CHECK: cost of 2 {{.*}} uitofp + %r61 = uitofp i16 undef to double + ; CHECK: cost of 2 {{.*}} sitofp + %r62 = sitofp i32 undef to float + ; CHECK: cost of 2 {{.*}} uitofp + %r63 = uitofp i32 undef to float + ; CHECK: cost of 2 {{.*}} sitofp + %r64 = sitofp i32 undef to double + ; CHECK: cost of 2 {{.*}} uitofp + %r65 = uitofp i32 undef to double + ; Function call + ; CHECK: cost of 10 {{.*}} sitofp + %r66 = sitofp i64 undef to float + ; CHECK: cost of 10 {{.*}} uitofp + %r67 = uitofp i64 undef to float + ; CHECK: cost of 10 {{.*}} sitofp + %r68 = sitofp i64 undef to double + ; CHECK: cost of 10 {{.*}} uitofp + %r69 = uitofp i64 undef to double + + ; CHECK: cost of 3 {{.*}} sext + %r70 = sext <8 x i8> undef to <8 x i32> + ; CHECK: cost of 6 {{.*}} sext + %r71 = sext <16 x i8> undef to <16 x i32> + ; CHECK: cost of 3 {{.*}} zext + %r72 = zext <8 x i8> undef to <8 x i32> + ; CHECK: cost of 6 {{.*}} zext + %r73 = zext <16 x i8> undef to <16 x i32> + + ; CHECK: cost of 7 {{.*}} sext + %rext_0 = sext <8 x i8> undef to <8 x i64> + ; CHECK: cost of 7 {{.*}} zext + %rext_1 = zext <8 x i8> undef to <8 x i64> + ; CHECK: cost of 6 {{.*}} sext + %rext_2 = sext <8 x i16> undef to <8 x i64> + ; CHECK: cost of 6 {{.*}} zext + %rext_3 = zext <8 x i16> undef to <8 x i64> + ; CHECK: cost of 3 {{.*}} sext + %rext_4 = sext <4 x i16> undef to <4 x i64> + ; CHECK: cost of 3 {{.*}} zext + %rext_5 = zext <4 x i16> undef to <4 x i64> + + ; Vector cast cost of instructions lowering the cast to the stack. + ; CHECK: cost of 19 {{.*}} trunc + %r74 = trunc <8 x i32> undef to <8 x i8> + ; CHECK: cost of 38 {{.*}} trunc + %r75 = trunc <16 x i32> undef to <16 x i8> + + ; Floating point truncation costs. + ; CHECK: cost of 1 {{.*}} fptrunc double + %r80 = fptrunc double undef to float + ; CHECK: cost of 2 {{.*}} fptrunc <2 x double + %r81 = fptrunc <2 x double> undef to <2 x float> + ; CHECK: cost of 4 {{.*}} fptrunc <4 x double + %r82 = fptrunc <4 x double> undef to <4 x float> + ; CHECK: cost of 8 {{.*}} fptrunc <8 x double + %r83 = fptrunc <8 x double> undef to <8 x float> + ; CHECK: cost of 16 {{.*}} fptrunc <16 x double + %r84 = fptrunc <16 x double> undef to <16 x float> + + ; Floating point extension costs. + ; CHECK: cost of 1 {{.*}} fpext float + %r85 = fpext float undef to double + ; CHECK: cost of 2 {{.*}} fpext <2 x float + %r86 = fpext <2 x float> undef to <2 x double> + ; CHECK: cost of 4 {{.*}} fpext <4 x float + %r87 = fpext <4 x float> undef to <4 x double> + ; CHECK: cost of 8 {{.*}} fpext <8 x float + %r88 = fpext <8 x float> undef to <8 x double> + ; CHECK: cost of 16 {{.*}} fpext <16 x float + %r89 = fpext <16 x float> undef to <16 x double> + + ;; Floating point to integer vector casts. + ; CHECK: cost of 1 {{.*}} fptoui + %r90 = fptoui <2 x float> undef to <2 x i1> + ; CHECK: cost of 1 {{.*}} fptosi + %r91 = fptosi <2 x float> undef to <2 x i1> + ; CHECK: cost of 1 {{.*}} fptoui + %r92 = fptoui <2 x float> undef to <2 x i8> + ; CHECK: cost of 1 {{.*}} fptosi + %r93 = fptosi <2 x float> undef to <2 x i8> + ; CHECK: cost of 1 {{.*}} fptoui + %r94 = fptoui <2 x float> undef to <2 x i16> + ; CHECK: cost of 1 {{.*}} fptosi + %r95 = fptosi <2 x float> undef to <2 x i16> + ; CHECK: cost of 1 {{.*}} fptoui + %r96 = fptoui <2 x float> undef to <2 x i32> + ; CHECK: cost of 1 {{.*}} fptosi + %r97 = fptosi <2 x float> undef to <2 x i32> + ; CHECK: cost of 24 {{.*}} fptoui + %r98 = fptoui <2 x float> undef to <2 x i64> + ; CHECK: cost of 24 {{.*}} fptosi + %r99 = fptosi <2 x float> undef to <2 x i64> + + ; CHECK: cost of 8 {{.*}} fptoui + %r100 = fptoui <2 x double> undef to <2 x i1> + ; CHECK: cost of 8 {{.*}} fptosi + %r101 = fptosi <2 x double> undef to <2 x i1> + ; CHECK: cost of 8 {{.*}} fptoui + %r102 = fptoui <2 x double> undef to <2 x i8> + ; CHECK: cost of 8 {{.*}} fptosi + %r103 = fptosi <2 x double> undef to <2 x i8> + ; CHECK: cost of 8 {{.*}} fptoui + %r104 = fptoui <2 x double> undef to <2 x i16> + ; CHECK: cost of 8 {{.*}} fptosi + %r105 = fptosi <2 x double> undef to <2 x i16> + ; CHECK: cost of 2 {{.*}} fptoui + %r106 = fptoui <2 x double> undef to <2 x i32> + ; CHECK: cost of 2 {{.*}} fptosi + %r107 = fptosi <2 x double> undef to <2 x i32> + ; CHECK: cost of 24 {{.*}} fptoui + %r108 = fptoui <2 x double> undef to <2 x i64> + ; CHECK: cost of 24 {{.*}} fptosi + %r109 = fptosi <2 x double> undef to <2 x i64> + + ; CHECK: cost of 16 {{.*}} fptoui + %r110 = fptoui <4 x float> undef to <4 x i1> + ; CHECK: cost of 16 {{.*}} fptosi + %r111 = fptosi <4 x float> undef to <4 x i1> + ; CHECK: cost of 3 {{.*}} fptoui + %r112 = fptoui <4 x float> undef to <4 x i8> + ; CHECK: cost of 3 {{.*}} fptosi + %r113 = fptosi <4 x float> undef to <4 x i8> + ; CHECK: cost of 2 {{.*}} fptoui + %r114 = fptoui <4 x float> undef to <4 x i16> + ; CHECK: cost of 2 {{.*}} fptosi + %r115 = fptosi <4 x float> undef to <4 x i16> + ; CHECK: cost of 1 {{.*}} fptoui + %r116 = fptoui <4 x float> undef to <4 x i32> + ; CHECK: cost of 1 {{.*}} fptosi + %r117 = fptosi <4 x float> undef to <4 x i32> + ; CHECK: cost of 48 {{.*}} fptoui + %r118 = fptoui <4 x float> undef to <4 x i64> + ; CHECK: cost of 48 {{.*}} fptosi + %r119 = fptosi <4 x float> undef to <4 x i64> + + ; CHECK: cost of 16 {{.*}} fptoui + %r120 = fptoui <4 x double> undef to <4 x i1> + ; CHECK: cost of 16 {{.*}} fptosi + %r121 = fptosi <4 x double> undef to <4 x i1> + ; CHECK: cost of 16 {{.*}} fptoui + %r122 = fptoui <4 x double> undef to <4 x i8> + ; CHECK: cost of 16 {{.*}} fptosi + %r123 = fptosi <4 x double> undef to <4 x i8> + ; CHECK: cost of 16 {{.*}} fptoui + %r124 = fptoui <4 x double> undef to <4 x i16> + ; CHECK: cost of 16 {{.*}} fptosi + %r125 = fptosi <4 x double> undef to <4 x i16> + ; CHECK: cost of 16 {{.*}} fptoui + %r126 = fptoui <4 x double> undef to <4 x i32> + ; CHECK: cost of 16 {{.*}} fptosi + %r127 = fptosi <4 x double> undef to <4 x i32> + ; CHECK: cost of 48 {{.*}} fptoui + %r128 = fptoui <4 x double> undef to <4 x i64> + ; CHECK: cost of 48 {{.*}} fptosi + %r129 = fptosi <4 x double> undef to <4 x i64> + + ; CHECK: cost of 32 {{.*}} fptoui + %r130 = fptoui <8 x float> undef to <8 x i1> + ; CHECK: cost of 32 {{.*}} fptosi + %r131 = fptosi <8 x float> undef to <8 x i1> + ; CHECK: cost of 32 {{.*}} fptoui + %r132 = fptoui <8 x float> undef to <8 x i8> + ; CHECK: cost of 32 {{.*}} fptosi + %r133 = fptosi <8 x float> undef to <8 x i8> + ; CHECK: cost of 4 {{.*}} fptoui + %r134 = fptoui <8 x float> undef to <8 x i16> + ; CHECK: cost of 4 {{.*}} fptosi + %r135 = fptosi <8 x float> undef to <8 x i16> + ; CHECK: cost of 2 {{.*}} fptoui + %r136 = fptoui <8 x float> undef to <8 x i32> + ; CHECK: cost of 2 {{.*}} fptosi + %r137 = fptosi <8 x float> undef to <8 x i32> + ; CHECK: cost of 96 {{.*}} fptoui + %r138 = fptoui <8 x float> undef to <8 x i64> + ; CHECK: cost of 96 {{.*}} fptosi + %r139 = fptosi <8 x float> undef to <8 x i64> + + ; CHECK: cost of 32 {{.*}} fptoui + %r140 = fptoui <8 x double> undef to <8 x i1> + ; CHECK: cost of 32 {{.*}} fptosi + %r141 = fptosi <8 x double> undef to <8 x i1> + ; CHECK: cost of 32 {{.*}} fptoui + %r142 = fptoui <8 x double> undef to <8 x i8> + ; CHECK: cost of 32 {{.*}} fptosi + %r143 = fptosi <8 x double> undef to <8 x i8> + ; CHECK: cost of 32 {{.*}} fptoui + %r144 = fptoui <8 x double> undef to <8 x i16> + ; CHECK: cost of 32 {{.*}} fptosi + %r145 = fptosi <8 x double> undef to <8 x i16> + ; CHECK: cost of 32 {{.*}} fptoui + %r146 = fptoui <8 x double> undef to <8 x i32> + ; CHECK: cost of 32 {{.*}} fptosi + %r147 = fptosi <8 x double> undef to <8 x i32> + ; CHECK: cost of 96 {{.*}} fptoui + %r148 = fptoui <8 x double> undef to <8 x i64> + ; CHECK: cost of 96 {{.*}} fptosi + %r149 = fptosi <8 x double> undef to <8 x i64> + + ; CHECK: cost of 64 {{.*}} fptoui + %r150 = fptoui <16 x float> undef to <16 x i1> + ; CHECK: cost of 64 {{.*}} fptosi + %r151 = fptosi <16 x float> undef to <16 x i1> + ; CHECK: cost of 64 {{.*}} fptoui + %r152 = fptoui <16 x float> undef to <16 x i8> + ; CHECK: cost of 64 {{.*}} fptosi + %r153 = fptosi <16 x float> undef to <16 x i8> + ; CHECK: cost of 8 {{.*}} fptoui + %r154 = fptoui <16 x float> undef to <16 x i16> + ; CHECK: cost of 8 {{.*}} fptosi + %r155 = fptosi <16 x float> undef to <16 x i16> + ; CHECK: cost of 4 {{.*}} fptoui + %r156 = fptoui <16 x float> undef to <16 x i32> + ; CHECK: cost of 4 {{.*}} fptosi + %r157 = fptosi <16 x float> undef to <16 x i32> + ; CHECK: cost of 192 {{.*}} fptoui + %r158 = fptoui <16 x float> undef to <16 x i64> + ; CHECK: cost of 192 {{.*}} fptosi + %r159 = fptosi <16 x float> undef to <16 x i64> + + ; CHECK: cost of 64 {{.*}} fptoui + %r160 = fptoui <16 x double> undef to <16 x i1> + ; CHECK: cost of 64 {{.*}} fptosi + %r161 = fptosi <16 x double> undef to <16 x i1> + ; CHECK: cost of 64 {{.*}} fptoui + %r162 = fptoui <16 x double> undef to <16 x i8> + ; CHECK: cost of 64 {{.*}} fptosi + %r163 = fptosi <16 x double> undef to <16 x i8> + ; CHECK: cost of 64 {{.*}} fptoui + %r164 = fptoui <16 x double> undef to <16 x i16> + ; CHECK: cost of 64 {{.*}} fptosi + %r165 = fptosi <16 x double> undef to <16 x i16> + ; CHECK: cost of 64 {{.*}} fptoui + %r166 = fptoui <16 x double> undef to <16 x i32> + ; CHECK: cost of 64 {{.*}} fptosi + %r167 = fptosi <16 x double> undef to <16 x i32> + ; CHECK: cost of 192 {{.*}} fptoui + %r168 = fptoui <16 x double> undef to <16 x i64> + ; CHECK: cost of 192 {{.*}} fptosi + %r169 = fptosi <16 x double> undef to <16 x i64> + + ; CHECK: cost of 8 {{.*}} uitofp + %r170 = uitofp <2 x i1> undef to <2 x float> + ; CHECK: cost of 8 {{.*}} sitofp + %r171 = sitofp <2 x i1> undef to <2 x float> + ; CHECK: cost of 3 {{.*}} uitofp + %r172 = uitofp <2 x i8> undef to <2 x float> + ; CHECK: cost of 3 {{.*}} sitofp + %r173 = sitofp <2 x i8> undef to <2 x float> + ; CHECK: cost of 2 {{.*}} uitofp + %r174 = uitofp <2 x i16> undef to <2 x float> + ; CHECK: cost of 2 {{.*}} sitofp + %r175 = sitofp <2 x i16> undef to <2 x float> + ; CHECK: cost of 1 {{.*}} uitofp + %r176 = uitofp <2 x i32> undef to <2 x float> + ; CHECK: cost of 1 {{.*}} sitofp + %r177 = sitofp <2 x i32> undef to <2 x float> + ; CHECK: cost of 24 {{.*}} uitofp + %r178 = uitofp <2 x i64> undef to <2 x float> + ; CHECK: cost of 24 {{.*}} sitofp + %r179 = sitofp <2 x i64> undef to <2 x float> + + ; CHECK: cost of 8 {{.*}} uitofp + %r180 = uitofp <2 x i1> undef to <2 x double> + ; CHECK: cost of 8 {{.*}} sitofp + %r181 = sitofp <2 x i1> undef to <2 x double> + ; CHECK: cost of 4 {{.*}} uitofp + %r182 = uitofp <2 x i8> undef to <2 x double> + ; CHECK: cost of 4 {{.*}} sitofp + %r183 = sitofp <2 x i8> undef to <2 x double> + ; CHECK: cost of 3 {{.*}} uitofp + %r184 = uitofp <2 x i16> undef to <2 x double> + ; CHECK: cost of 3 {{.*}} sitofp + %r185 = sitofp <2 x i16> undef to <2 x double> + ; CHECK: cost of 2 {{.*}} uitofp + %r186 = uitofp <2 x i32> undef to <2 x double> + ; CHECK: cost of 2 {{.*}} sitofp + %r187 = sitofp <2 x i32> undef to <2 x double> + ; CHECK: cost of 24 {{.*}} uitofp + %r188 = uitofp <2 x i64> undef to <2 x double> + ; CHECK: cost of 24 {{.*}} sitofp + %r189 = sitofp <2 x i64> undef to <2 x double> + + ; CHECK: cost of 3 {{.*}} uitofp + %r190 = uitofp <4 x i1> undef to <4 x float> + ; CHECK: cost of 3 {{.*}} sitofp + %r191 = sitofp <4 x i1> undef to <4 x float> + ; CHECK: cost of 3 {{.*}} uitofp + %r192 = uitofp <4 x i8> undef to <4 x float> + ; CHECK: cost of 3 {{.*}} sitofp + %r193 = sitofp <4 x i8> undef to <4 x float> + ; CHECK: cost of 2 {{.*}} uitofp + %r194 = uitofp <4 x i16> undef to <4 x float> + ; CHECK: cost of 2 {{.*}} sitofp + %r195 = sitofp <4 x i16> undef to <4 x float> + ; CHECK: cost of 1 {{.*}} uitofp + %r196 = uitofp <4 x i32> undef to <4 x float> + ; CHECK: cost of 1 {{.*}} sitofp + %r197 = sitofp <4 x i32> undef to <4 x float> + ; CHECK: cost of 48 {{.*}} uitofp + %r198 = uitofp <4 x i64> undef to <4 x float> + ; CHECK: cost of 48 {{.*}} sitofp + %r199 = sitofp <4 x i64> undef to <4 x float> + + ; CHECK: cost of 16 {{.*}} uitofp + %r200 = uitofp <4 x i1> undef to <4 x double> + ; CHECK: cost of 16 {{.*}} sitofp + %r201 = sitofp <4 x i1> undef to <4 x double> + ; CHECK: cost of 16 {{.*}} uitofp + %r202 = uitofp <4 x i8> undef to <4 x double> + ; CHECK: cost of 16 {{.*}} sitofp + %r203 = sitofp <4 x i8> undef to <4 x double> + ; CHECK: cost of 16 {{.*}} uitofp + %r204 = uitofp <4 x i16> undef to <4 x double> + ; CHECK: cost of 16 {{.*}} sitofp + %r205 = sitofp <4 x i16> undef to <4 x double> + ; CHECK: cost of 16 {{.*}} uitofp + %r206 = uitofp <4 x i32> undef to <4 x double> + ; CHECK: cost of 16 {{.*}} sitofp + %r207 = sitofp <4 x i32> undef to <4 x double> + ; CHECK: cost of 48 {{.*}} uitofp + %r208 = uitofp <4 x i64> undef to <4 x double> + ; CHECK: cost of 48 {{.*}} sitofp + %r209 = sitofp <4 x i64> undef to <4 x double> + + ; CHECK: cost of 32 {{.*}} uitofp + %r210 = uitofp <8 x i1> undef to <8 x float> + ; CHECK: cost of 32 {{.*}} sitofp + %r211 = sitofp <8 x i1> undef to <8 x float> + ; CHECK: cost of 32 {{.*}} uitofp + %r212 = uitofp <8 x i8> undef to <8 x float> + ; CHECK: cost of 32 {{.*}} sitofp + %r213 = sitofp <8 x i8> undef to <8 x float> + ; CHECK: cost of 4 {{.*}} uitofp + %r214 = uitofp <8 x i16> undef to <8 x float> + ; CHECK: cost of 4 {{.*}} sitofp + %r215 = sitofp <8 x i16> undef to <8 x float> + ; CHECK: cost of 2 {{.*}} uitofp + %r216 = uitofp <8 x i32> undef to <8 x float> + ; CHECK: cost of 2 {{.*}} sitofp + %r217 = sitofp <8 x i32> undef to <8 x float> + ; CHECK: cost of 96 {{.*}} uitofp + %r218 = uitofp <8 x i64> undef to <8 x float> + ; CHECK: cost of 96 {{.*}} sitofp + %r219 = sitofp <8 x i64> undef to <8 x float> + + ; CHECK: cost of 32 {{.*}} uitofp + %r220 = uitofp <8 x i1> undef to <8 x double> + ; CHECK: cost of 32 {{.*}} sitofp + %r221 = sitofp <8 x i1> undef to <8 x double> + ; CHECK: cost of 32 {{.*}} uitofp + %r222 = uitofp <8 x i8> undef to <8 x double> + ; CHECK: cost of 32 {{.*}} sitofp + %r223 = sitofp <8 x i8> undef to <8 x double> + ; CHECK: cost of 32 {{.*}} uitofp + %r224 = uitofp <8 x i16> undef to <8 x double> + ; CHECK: cost of 32 {{.*}} sitofp + %r225 = sitofp <8 x i16> undef to <8 x double> + ; CHECK: cost of 32 {{.*}} uitofp + %r226 = uitofp <8 x i16> undef to <8 x double> + ; CHECK: cost of 32 {{.*}} sitofp + %r227 = sitofp <8 x i16> undef to <8 x double> + ; CHECK: cost of 96 {{.*}} uitofp + %r228 = uitofp <8 x i64> undef to <8 x double> + ; CHECK: cost of 96 {{.*}} sitofp + %r229 = sitofp <8 x i64> undef to <8 x double> + + ; CHECK: cost of 64 {{.*}} uitofp + %r230 = uitofp <16 x i1> undef to <16 x float> + ; CHECK: cost of 64 {{.*}} sitofp + %r231 = sitofp <16 x i1> undef to <16 x float> + ; CHECK: cost of 64 {{.*}} uitofp + %r232 = uitofp <16 x i8> undef to <16 x float> + ; CHECK: cost of 64 {{.*}} sitofp + %r233 = sitofp <16 x i8> undef to <16 x float> + ; CHECK: cost of 8 {{.*}} uitofp + %r234 = uitofp <16 x i16> undef to <16 x float> + ; CHECK: cost of 8 {{.*}} sitofp + %r235 = sitofp <16 x i16> undef to <16 x float> + ; CHECK: cost of 4 {{.*}} uitofp + %r236 = uitofp <16 x i32> undef to <16 x float> + ; CHECK: cost of 4 {{.*}} sitofp + %r237 = sitofp <16 x i32> undef to <16 x float> + ; CHECK: cost of 192 {{.*}} uitofp + %r238 = uitofp <16 x i64> undef to <16 x float> + ; CHECK: cost of 192 {{.*}} sitofp + %r239 = sitofp <16 x i64> undef to <16 x float> + + ; CHECK: cost of 64 {{.*}} uitofp + %r240 = uitofp <16 x i1> undef to <16 x double> + ; CHECK: cost of 64 {{.*}} sitofp + %r241 = sitofp <16 x i1> undef to <16 x double> + ; CHECK: cost of 64 {{.*}} uitofp + %r242 = uitofp <16 x i8> undef to <16 x double> + ; CHECK: cost of 64 {{.*}} sitofp + %r243 = sitofp <16 x i8> undef to <16 x double> + ; C4ECK: cost of 64 {{.*}} uitofp + %r244 = uitofp <16 x i16> undef to <16 x double> + ; CHECK: cost of 64 {{.*}} sitofp + %r245 = sitofp <16 x i16> undef to <16 x double> + ; CHECK: cost of 64 {{.*}} uitofp + %r246 = uitofp <16 x i16> undef to <16 x double> + ; CHECK: cost of 64 {{.*}} sitofp + %r247 = sitofp <16 x i16> undef to <16 x double> + ; CHECK: cost of 192 {{.*}} uitofp + %r248 = uitofp <16 x i64> undef to <16 x double> + ; CHECK: cost of 192 {{.*}} sitofp + %r249 = sitofp <16 x i64> undef to <16 x double> + + ;CHECK: cost of 0 {{.*}} ret + ret i32 undef +} + diff --git a/test/Analysis/CostModel/ARM/gep.ll b/test/Analysis/CostModel/ARM/gep.ll new file mode 100644 index 0000000000000..a63b87d2ad113 --- /dev/null +++ b/test/Analysis/CostModel/ARM/gep.ll @@ -0,0 +1,43 @@ +; RUN: opt -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift < %s | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios6.0.0" + +define void @test_geps() { + ; Cost of scalar integer geps should be one. We can't always expect it to be + ; folded into the instruction addressing mode. +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i8* + %a0 = getelementptr inbounds i8* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i16* + %a1 = getelementptr inbounds i16* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i32* + %a2 = getelementptr inbounds i32* undef, i32 0 + +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i64* + %a3 = getelementptr inbounds i64* undef, i32 0 + + ; Cost of scalar floating point geps should be one. We cannot fold the address + ; computation. +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds float* + %a4 = getelementptr inbounds float* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds double* + %a5 = getelementptr inbounds double* undef, i32 0 + + + ; Cost of vector geps should be one. We cannot fold the address computation. +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i8>* + %a7 = getelementptr inbounds <4 x i8>* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i16>* + %a8 = getelementptr inbounds <4 x i16>* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i32>* + %a9 = getelementptr inbounds <4 x i32>* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i64>* + %a10 = getelementptr inbounds <4 x i64>* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x float>* + %a11 = getelementptr inbounds <4 x float>* undef, i32 0 +;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x double>* + %a12 = getelementptr inbounds <4 x double>* undef, i32 0 + + + ret void +} diff --git a/test/Analysis/CostModel/ARM/insertelement.ll b/test/Analysis/CostModel/ARM/insertelement.ll new file mode 100644 index 0000000000000..f951b08f9baa8 --- /dev/null +++ b/test/Analysis/CostModel/ARM/insertelement.ll @@ -0,0 +1,46 @@ +; RUN: opt -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift < %s | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios6.0.0" + +; Multiple insert elements from loads into d subregisters are expensive on swift +; due to renaming constraints. +%T_i8v = type <8 x i8> +%T_i8 = type i8 +; CHECK: insertelement_i8 +define void @insertelement_i8(%T_i8* %saddr, + %T_i8v* %vaddr) { + %v0 = load %T_i8v* %vaddr + %v1 = load %T_i8* %saddr +;CHECK: estimated cost of 3 for {{.*}} insertelement <8 x i8> + %v2 = insertelement %T_i8v %v0, %T_i8 %v1, i32 1 + store %T_i8v %v2, %T_i8v* %vaddr + ret void +} + + +%T_i16v = type <4 x i16> +%T_i16 = type i16 +; CHECK: insertelement_i16 +define void @insertelement_i16(%T_i16* %saddr, + %T_i16v* %vaddr) { + %v0 = load %T_i16v* %vaddr + %v1 = load %T_i16* %saddr +;CHECK: estimated cost of 3 for {{.*}} insertelement <4 x i16> + %v2 = insertelement %T_i16v %v0, %T_i16 %v1, i32 1 + store %T_i16v %v2, %T_i16v* %vaddr + ret void +} + +%T_i32v = type <2 x i32> +%T_i32 = type i32 +; CHECK: insertelement_i32 +define void @insertelement_i32(%T_i32* %saddr, + %T_i32v* %vaddr) { + %v0 = load %T_i32v* %vaddr + %v1 = load %T_i32* %saddr +;CHECK: estimated cost of 3 for {{.*}} insertelement <2 x i32> + %v2 = insertelement %T_i32v %v0, %T_i32 %v1, i32 1 + store %T_i32v %v2, %T_i32v* %vaddr + ret void +} diff --git a/test/Analysis/CostModel/ARM/lit.local.cfg b/test/Analysis/CostModel/ARM/lit.local.cfg new file mode 100644 index 0000000000000..cb77b09ef4adb --- /dev/null +++ b/test/Analysis/CostModel/ARM/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.c', '.cpp'] + +targets = set(config.root.targets_to_build.split()) +if not 'ARM' in targets: + config.unsupported = True + diff --git a/test/Analysis/CostModel/ARM/select.ll b/test/Analysis/CostModel/ARM/select.ll new file mode 100644 index 0000000000000..34ed1eefdaf42 --- /dev/null +++ b/test/Analysis/CostModel/ARM/select.ll @@ -0,0 +1,67 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios6.0.0" + +; CHECK: casts +define void @casts() { + ; Scalar values + ; CHECK: cost of 1 {{.*}} select + %v1 = select i1 undef, i8 undef, i8 undef + ; CHECK: cost of 1 {{.*}} select + %v2 = select i1 undef, i16 undef, i16 undef + ; CHECK: cost of 1 {{.*}} select + %v3 = select i1 undef, i32 undef, i32 undef + ; CHECK: cost of 2 {{.*}} select + %v4 = select i1 undef, i64 undef, i64 undef + ; CHECK: cost of 1 {{.*}} select + %v5 = select i1 undef, float undef, float undef + ; CHECK: cost of 1 {{.*}} select + %v6 = select i1 undef, double undef, double undef + + ; Vector values + ; CHECK: cost of 1 {{.*}} select + %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef + ; CHECK: cost of 1 {{.*}} select + %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef + ; CHECK: cost of 1 {{.*}} select + %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef + ; CHECK: cost of 1 {{.*}} select + %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef + + ; CHECK: cost of 1 {{.*}} select + %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef + ; CHECK: cost of 1 {{.*}} select + %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef + ; CHECK: cost of 1 {{.*}} select + %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef + ; CHECK: cost of 40 {{.*}} select + %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef + + ; CHECK: cost of 1 {{.*}} select + %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef + ; CHECK: cost of 1 {{.*}} select + %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef + ; CHECK: cost of 41 {{.*}} select + %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef + ; CHECK: cost of 82 {{.*}} select + %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef + + ; CHECK: cost of 1 {{.*}} select + %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef + ; CHECK: cost of 19 {{.*}} select + %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef + ; CHECK: cost of 50 {{.*}} select + %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef + ; CHECK: cost of 100 {{.*}} select + %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef + + ; CHECK: cost of 1 {{.*}} select + %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef + ; CHECK: cost of 1 {{.*}} select + %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef + + ; CHECK: cost of 1 {{.*}} select + %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef + + ret void +} diff --git a/test/Analysis/CostModel/ARM/shuffle.ll b/test/Analysis/CostModel/ARM/shuffle.ll new file mode 100644 index 0000000000000..c92d668804648 --- /dev/null +++ b/test/Analysis/CostModel/ARM/shuffle.ll @@ -0,0 +1,40 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios6.0.0" + +; CHECK: shuffle +define void @shuffle() { + + + ;; Reverse shuffles should be lowered to vrev and possibly a vext (for + ;; quadwords) + + ; Vector values + ; CHECK: cost of 1 {{.*}} shuffle + %v7 = shufflevector <2 x i8> undef, <2 x i8>undef, <2 x i32> <i32 1, i32 0> + ; CHECK: cost of 1 {{.*}} shuffle + %v8 = shufflevector <4 x i8> undef, <4 x i8>undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> + ; CHECK: cost of 1 {{.*}} shuffle + %v9 = shufflevector <8 x i8> undef, <8 x i8>undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> + ; CHECK: cost of 2 {{.*}} shuffle + %v10 = shufflevector <16 x i8> undef, <16 x i8>undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> + + ; CHECK: cost of 1 {{.*}} shuffle + %v11 = shufflevector <2 x i16> undef, <2 x i16>undef, <2 x i32> <i32 1, i32 0> + ; CHECK: cost of 1 {{.*}} shuffle + %v12 = shufflevector <4 x i16> undef, <4 x i16>undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> + ; CHECK: cost of 2 {{.*}} shuffle + %v13 = shufflevector <8 x i16> undef, <8 x i16>undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> + + ; CHECK: cost of 1 {{.*}} shuffle + %v14 = shufflevector <2 x i32> undef, <2 x i32>undef, <2 x i32> <i32 1, i32 0> + ; CHECK: cost of 2 {{.*}} shuffle + %v15 = shufflevector <4 x i32> undef, <4 x i32>undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> + + ; CHECK: cost of 1 {{.*}} shuffle + %v16 = shufflevector <2 x float> undef, <2 x float>undef, <2 x i32> <i32 1, i32 0> + ; CHECK: cost of 2 {{.*}} shuffle + %v17 = shufflevector <4 x float> undef, <4 x float>undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> + + ret void +} diff --git a/test/Analysis/CostModel/PowerPC/insert_extract.ll b/test/Analysis/CostModel/PowerPC/insert_extract.ll new file mode 100644 index 0000000000000..f51963d56fde3 --- /dev/null +++ b/test/Analysis/CostModel/PowerPC/insert_extract.ll @@ -0,0 +1,16 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i32 @insert(i32 %arg) { + ; CHECK: cost of 13 {{.*}} insertelement + %x = insertelement <4 x i32> undef, i32 %arg, i32 0 + ret i32 undef +} + +define i32 @extract(<4 x i32> %arg) { + ; CHECK: cost of 13 {{.*}} extractelement + %x = extractelement <4 x i32> %arg, i32 0 + ret i32 %x +} + diff --git a/test/Analysis/CostModel/PowerPC/lit.local.cfg b/test/Analysis/CostModel/PowerPC/lit.local.cfg new file mode 100644 index 0000000000000..4019eca0bb88f --- /dev/null +++ b/test/Analysis/CostModel/PowerPC/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.c', '.cpp'] + +targets = set(config.root.targets_to_build.split()) +if not 'PowerPC' in targets: + config.unsupported = True + diff --git a/test/Analysis/CostModel/PowerPC/load_store.ll b/test/Analysis/CostModel/PowerPC/load_store.ll new file mode 100644 index 0000000000000..c77cce955abff --- /dev/null +++ b/test/Analysis/CostModel/PowerPC/load_store.ll @@ -0,0 +1,34 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i32 @stores(i32 %arg) { + + ; CHECK: cost of 1 {{.*}} store + store i8 undef, i8* undef, align 4 + ; CHECK: cost of 1 {{.*}} store + store i16 undef, i16* undef, align 4 + ; CHECK: cost of 1 {{.*}} store + store i32 undef, i32* undef, align 4 + ; CHECK: cost of 2 {{.*}} store + store i64 undef, i64* undef, align 4 + ; CHECK: cost of 4 {{.*}} store + store i128 undef, i128* undef, align 4 + + ret i32 undef +} +define i32 @loads(i32 %arg) { + ; CHECK: cost of 1 {{.*}} load + load i8* undef, align 4 + ; CHECK: cost of 1 {{.*}} load + load i16* undef, align 4 + ; CHECK: cost of 1 {{.*}} load + load i32* undef, align 4 + ; CHECK: cost of 2 {{.*}} load + load i64* undef, align 4 + ; CHECK: cost of 4 {{.*}} load + load i128* undef, align 4 + + ret i32 undef +} + diff --git a/test/Analysis/CostModel/X86/arith.ll b/test/Analysis/CostModel/X86/arith.ll index 37cca8d540670..85b442533f412 100644 --- a/test/Analysis/CostModel/X86/arith.ll +++ b/test/Analysis/CostModel/X86/arith.ll @@ -1,4 +1,6 @@ ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s +; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=core2 | FileCheck %s --check-prefix=SSE3 +; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=core-avx2 | FileCheck %s --check-prefix=AVX2 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" @@ -14,7 +16,7 @@ define i32 @add(i32 %arg) { %D = add <4 x i64> undef, undef ;CHECK: cost of 8 {{.*}} add %E = add <8 x i64> undef, undef - ;CHECK: cost of 1 {{.*}} ret + ;CHECK: cost of 0 {{.*}} ret ret i32 undef } @@ -28,11 +30,41 @@ define i32 @xor(i32 %arg) { %C = xor <2 x i64> undef, undef ;CHECK: cost of 1 {{.*}} xor %D = xor <4 x i64> undef, undef - ;CHECK: cost of 1 {{.*}} ret + ;CHECK: cost of 0 {{.*}} ret ret i32 undef } +; CHECK: mul +define void @mul() { + ; A <2 x i32> gets expanded to a <2 x i64> vector. + ; A <2 x i64> vector multiply is implemented using + ; 3 PMULUDQ and 2 PADDS and 4 shifts. + ;CHECK: cost of 9 {{.*}} mul + %A0 = mul <2 x i32> undef, undef + ;CHECK: cost of 9 {{.*}} mul + %A1 = mul <2 x i64> undef, undef + ;CHECK: cost of 18 {{.*}} mul + %A2 = mul <4 x i64> undef, undef + ret void +} + +; SSE3: sse3mull +define void @sse3mull() { + ; SSE3: cost of 6 {{.*}} mul + %A0 = mul <4 x i32> undef, undef + ret void + ; SSE3: avx2mull +} + +; AVX2: avx2mull +define void @avx2mull() { + ; AVX2: cost of 9 {{.*}} mul + %A0 = mul <4 x i64> undef, undef + ret void + ; AVX2: fmul +} +; CHECK: fmul define i32 @fmul(i32 %arg) { ;CHECK: cost of 1 {{.*}} fmul %A = fmul <4 x float> undef, undef @@ -40,3 +72,57 @@ define i32 @fmul(i32 %arg) { %B = fmul <8 x float> undef, undef ret i32 undef } + +; AVX: shift +; AVX2: shift +define void @shift() { + ; AVX: cost of 2 {{.*}} shl + ; AVX2: cost of 1 {{.*}} shl + %A0 = shl <4 x i32> undef, undef + ; AVX: cost of 2 {{.*}} shl + ; AVX2: cost of 1 {{.*}} shl + %A1 = shl <2 x i64> undef, undef + + ; AVX: cost of 2 {{.*}} lshr + ; AVX2: cost of 1 {{.*}} lshr + %B0 = lshr <4 x i32> undef, undef + ; AVX: cost of 2 {{.*}} lshr + ; AVX2: cost of 1 {{.*}} lshr + %B1 = lshr <2 x i64> undef, undef + + ; AVX: cost of 2 {{.*}} ashr + ; AVX2: cost of 1 {{.*}} ashr + %C0 = ashr <4 x i32> undef, undef + ; AVX: cost of 6 {{.*}} ashr + ; AVX2: cost of 20 {{.*}} ashr + %C1 = ashr <2 x i64> undef, undef + + ret void +} + +; AVX: avx2shift +; AVX2: avx2shift +define void @avx2shift() { + ; AVX: cost of 2 {{.*}} shl + ; AVX2: cost of 1 {{.*}} shl + %A0 = shl <8 x i32> undef, undef + ; AVX: cost of 2 {{.*}} shl + ; AVX2: cost of 1 {{.*}} shl + %A1 = shl <4 x i64> undef, undef + + ; AVX: cost of 2 {{.*}} lshr + ; AVX2: cost of 1 {{.*}} lshr + %B0 = lshr <8 x i32> undef, undef + ; AVX: cost of 2 {{.*}} lshr + ; AVX2: cost of 1 {{.*}} lshr + %B1 = lshr <4 x i64> undef, undef + + ; AVX: cost of 2 {{.*}} ashr + ; AVX2: cost of 1 {{.*}} ashr + %C0 = ashr <8 x i32> undef, undef + ; AVX: cost of 12 {{.*}} ashr + ; AVX2: cost of 40 {{.*}} ashr + %C1 = ashr <4 x i64> undef, undef + + ret void +} diff --git a/test/Analysis/CostModel/X86/cast.ll b/test/Analysis/CostModel/X86/cast.ll index 75c97a781e7fa..b69b3bf6304c2 100644 --- a/test/Analysis/CostModel/X86/cast.ll +++ b/test/Analysis/CostModel/X86/cast.ll @@ -28,7 +28,7 @@ define i32 @add(i32 %arg) { ;CHECK: cost of 0 {{.*}} trunc %H = trunc i32 undef to i1 - ;CHECK: cost of 1 {{.*}} ret + ;CHECK: cost of 0 {{.*}} ret ret i32 undef } @@ -44,6 +44,10 @@ define i32 @zext_sext(<8 x i1> %in) { %B = zext <8 x i16> undef to <8 x i32> ;CHECK: cost of 1 {{.*}} sext %C = sext <4 x i32> undef to <4 x i64> + ;CHECK: cost of 6 {{.*}} sext + %C1 = sext <4 x i8> undef to <4 x i64> + ;CHECK: cost of 6 {{.*}} sext + %C2 = sext <4 x i16> undef to <4 x i64> ;CHECK: cost of 1 {{.*}} zext %D = zext <4 x i32> undef to <4 x i64> @@ -59,7 +63,7 @@ define i32 @zext_sext(<8 x i1> %in) { ret i32 undef } -define i32 @masks(<8 x i1> %in) { +define i32 @masks8(<8 x i1> %in) { ;CHECK: cost of 6 {{.*}} zext %Z = zext <8 x i1> %in to <8 x i32> ;CHECK: cost of 9 {{.*}} sext @@ -67,3 +71,84 @@ define i32 @masks(<8 x i1> %in) { ret i32 undef } +define i32 @masks4(<4 x i1> %in) { + ;CHECK: cost of 8 {{.*}} sext + %S = sext <4 x i1> %in to <4 x i64> + ret i32 undef +} + +define void @sitofp4(<4 x i1> %a, <4 x i8> %b, <4 x i16> %c, <4 x i32> %d) { + ; CHECK: cost of 3 {{.*}} sitofp + %A1 = sitofp <4 x i1> %a to <4 x float> + ; CHECK: cost of 3 {{.*}} sitofp + %A2 = sitofp <4 x i1> %a to <4 x double> + + ; CHECK: cost of 3 {{.*}} sitofp + %B1 = sitofp <4 x i8> %b to <4 x float> + ; CHECK: cost of 3 {{.*}} sitofp + %B2 = sitofp <4 x i8> %b to <4 x double> + + ; CHECK: cost of 3 {{.*}} sitofp + %C1 = sitofp <4 x i16> %c to <4 x float> + ; CHECK: cost of 3 {{.*}} sitofp + %C2 = sitofp <4 x i16> %c to <4 x double> + + ; CHECK: cost of 1 {{.*}} sitofp + %D1 = sitofp <4 x i32> %d to <4 x float> + ; CHECK: cost of 1 {{.*}} sitofp + %D2 = sitofp <4 x i32> %d to <4 x double> + ret void +} + +define void @sitofp8(<8 x i1> %a, <8 x i8> %b, <8 x i16> %c, <8 x i32> %d) { + ; CHECK: cost of 8 {{.*}} sitofp + %A1 = sitofp <8 x i1> %a to <8 x float> + + ; CHECK: cost of 8 {{.*}} sitofp + %B1 = sitofp <8 x i8> %b to <8 x float> + + ; CHECK: cost of 5 {{.*}} sitofp + %C1 = sitofp <8 x i16> %c to <8 x float> + + ; CHECK: cost of 1 {{.*}} sitofp + %D1 = sitofp <8 x i32> %d to <8 x float> + ret void +} + +define void @uitofp4(<4 x i1> %a, <4 x i8> %b, <4 x i16> %c, <4 x i32> %d) { + ; CHECK: cost of 7 {{.*}} uitofp + %A1 = uitofp <4 x i1> %a to <4 x float> + ; CHECK: cost of 7 {{.*}} uitofp + %A2 = uitofp <4 x i1> %a to <4 x double> + + ; CHECK: cost of 2 {{.*}} uitofp + %B1 = uitofp <4 x i8> %b to <4 x float> + ; CHECK: cost of 2 {{.*}} uitofp + %B2 = uitofp <4 x i8> %b to <4 x double> + + ; CHECK: cost of 2 {{.*}} uitofp + %C1 = uitofp <4 x i16> %c to <4 x float> + ; CHECK: cost of 2 {{.*}} uitofp + %C2 = uitofp <4 x i16> %c to <4 x double> + + ; CHECK: cost of 6 {{.*}} uitofp + %D1 = uitofp <4 x i32> %d to <4 x float> + ; CHECK: cost of 6 {{.*}} uitofp + %D2 = uitofp <4 x i32> %d to <4 x double> + ret void +} + +define void @uitofp8(<8 x i1> %a, <8 x i8> %b, <8 x i16> %c, <8 x i32> %d) { + ; CHECK: cost of 6 {{.*}} uitofp + %A1 = uitofp <8 x i1> %a to <8 x float> + + ; CHECK: cost of 5 {{.*}} uitofp + %B1 = uitofp <8 x i8> %b to <8 x float> + + ; CHECK: cost of 5 {{.*}} uitofp + %C1 = uitofp <8 x i16> %c to <8 x float> + + ; CHECK: cost of 9 {{.*}} uitofp + %D1 = uitofp <8 x i32> %d to <8 x float> + ret void +} diff --git a/test/Analysis/CostModel/X86/cmp.ll b/test/Analysis/CostModel/X86/cmp.ll index f868bd18b54fc..713b3742e9209 100644 --- a/test/Analysis/CostModel/X86/cmp.ll +++ b/test/Analysis/CostModel/X86/cmp.ll @@ -1,41 +1,55 @@ -; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s +; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck --check-prefix=AVX1 %s +; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=core-avx2 | FileCheck --check-prefix=AVX2 %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" define i32 @cmp(i32 %arg) { ; -- floats -- - ;CHECK: cost of 1 {{.*}} fcmp + ;AVX1: cost of 1 {{.*}} fcmp + ;AVX2: cost of 1 {{.*}} fcmp %A = fcmp olt <2 x float> undef, undef - ;CHECK: cost of 1 {{.*}} fcmp + ;AVX1: cost of 1 {{.*}} fcmp + ;AVX2: cost of 1 {{.*}} fcmp %B = fcmp olt <4 x float> undef, undef - ;CHECK: cost of 1 {{.*}} fcmp + ;AVX1: cost of 1 {{.*}} fcmp + ;AVX2: cost of 1 {{.*}} fcmp %C = fcmp olt <8 x float> undef, undef - ;CHECK: cost of 1 {{.*}} fcmp + ;AVX1: cost of 1 {{.*}} fcmp + ;AVX2: cost of 1 {{.*}} fcmp %D = fcmp olt <2 x double> undef, undef - ;CHECK: cost of 1 {{.*}} fcmp + ;AVX1: cost of 1 {{.*}} fcmp + ;AVX2: cost of 1 {{.*}} fcmp %E = fcmp olt <4 x double> undef, undef ; -- integers -- - ;CHECK: cost of 1 {{.*}} icmp + ;AVX1: cost of 1 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %F = icmp eq <16 x i8> undef, undef - ;CHECK: cost of 1 {{.*}} icmp + ;AVX1: cost of 1 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %G = icmp eq <8 x i16> undef, undef - ;CHECK: cost of 1 {{.*}} icmp + ;AVX1: cost of 1 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %H = icmp eq <4 x i32> undef, undef - ;CHECK: cost of 1 {{.*}} icmp + ;AVX1: cost of 1 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %I = icmp eq <2 x i64> undef, undef - ;CHECK: cost of 4 {{.*}} icmp + ;AVX1: cost of 4 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %J = icmp eq <4 x i64> undef, undef - ;CHECK: cost of 4 {{.*}} icmp + ;AVX1: cost of 4 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %K = icmp eq <8 x i32> undef, undef - ;CHECK: cost of 4 {{.*}} icmp + ;AVX1: cost of 4 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %L = icmp eq <16 x i16> undef, undef - ;CHECK: cost of 4 {{.*}} icmp + ;AVX1: cost of 4 {{.*}} icmp + ;AVX2: cost of 1 {{.*}} icmp %M = icmp eq <32 x i8> undef, undef - ;CHECK: cost of 1 {{.*}} ret + ;CHECK: cost of 0 {{.*}} ret ret i32 undef } diff --git a/test/Analysis/CostModel/X86/gep.ll b/test/Analysis/CostModel/X86/gep.ll new file mode 100644 index 0000000000000..877184a3eaa80 --- /dev/null +++ b/test/Analysis/CostModel/X86/gep.ll @@ -0,0 +1,40 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + + +define void @test_geps() { + ; Cost of should be zero. We expect it to be folded into + ; the instruction addressing mode. +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i8* + %a0 = getelementptr inbounds i8* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i16* + %a1 = getelementptr inbounds i16* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i32* + %a2 = getelementptr inbounds i32* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i64* + %a3 = getelementptr inbounds i64* undef, i32 0 + +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds float* + %a4 = getelementptr inbounds float* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds double* + %a5 = getelementptr inbounds double* undef, i32 0 + + ; Vector geps should also have zero cost. +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i8>* + %a7 = getelementptr inbounds <4 x i8>* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i16>* + %a8 = getelementptr inbounds <4 x i16>* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i32>* + %a9 = getelementptr inbounds <4 x i32>* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i64>* + %a10 = getelementptr inbounds <4 x i64>* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x float>* + %a11 = getelementptr inbounds <4 x float>* undef, i32 0 +;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x double>* + %a12 = getelementptr inbounds <4 x double>* undef, i32 0 + + + ret void +} diff --git a/test/Analysis/CostModel/X86/i32.ll b/test/Analysis/CostModel/X86/i32.ll index 4015e0b1eef4b..c2dce762a0912 100644 --- a/test/Analysis/CostModel/X86/i32.ll +++ b/test/Analysis/CostModel/X86/i32.ll @@ -1,8 +1,6 @@ ; RUN: opt < %s -cost-model -analyze -mtriple=i386 -mcpu=corei7-avx | FileCheck %s - -;CHECK: cost of 2 {{.*}} add -;CHECK: cost of 1 {{.*}} ret +;CHECK: cost of 0 {{.*}} ret define i32 @no_info(i32 %arg) { %e = add i64 undef, undef ret i32 undef diff --git a/test/Analysis/CostModel/X86/intrinsic-cost.ll b/test/Analysis/CostModel/X86/intrinsic-cost.ll new file mode 100644 index 0000000000000..e235a36222a7e --- /dev/null +++ b/test/Analysis/CostModel/X86/intrinsic-cost.ll @@ -0,0 +1,32 @@ +; RUN: opt -S -mtriple=x86_64-apple-darwin -mcpu=core2 -cost-model -analyze < %s | FileCheck %s -check-prefix=CORE2 +; RUN: opt -S -mtriple=x86_64-apple-darwin -mcpu=corei7 -cost-model -analyze < %s | FileCheck %s -check-prefix=COREI7 + +; If SSE4.1 roundps instruction is available it is cheap to lower, otherwise +; it'll be scalarized into calls which are expensive. +define void @test1(float* nocapture %f) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds float* %f, i64 %index + %1 = bitcast float* %0 to <4 x float>* + %wide.load = load <4 x float>* %1, align 4 + %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load) + store <4 x float> %2, <4 x float>* %1, align 4 + %index.next = add i64 %index, 4 + %3 = icmp eq i64 %index.next, 1024 + br i1 %3, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; CORE2: Printing analysis 'Cost Model Analysis' for function 'test1': +; CORE2: Cost Model: Found an estimated cost of 400 for instruction: %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load) + +; COREI7: Printing analysis 'Cost Model Analysis' for function 'test1': +; COREI7: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load) + +} + +declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone diff --git a/test/Analysis/CostModel/X86/load_store.ll b/test/Analysis/CostModel/X86/load_store.ll new file mode 100644 index 0000000000000..4195b1d879a15 --- /dev/null +++ b/test/Analysis/CostModel/X86/load_store.ll @@ -0,0 +1,64 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +define i32 @stores(i32 %arg) { + + ;CHECK: cost of 1 {{.*}} store + store i8 undef, i8* undef, align 4 + ;CHECK: cost of 1 {{.*}} store + store i16 undef, i16* undef, align 4 + ;CHECK: cost of 1 {{.*}} store + store i32 undef, i32* undef, align 4 + ;CHECK: cost of 1 {{.*}} store + store i64 undef, i64* undef, align 4 + ;CHECK: cost of 2 {{.*}} store + store i128 undef, i128* undef, align 4 + + ;CHECK: cost of 1 {{.*}} store + store <4 x i16> undef, <4 x i16>* undef, align 4 + ;CHECK: cost of 1 {{.*}} store + store <4 x i32> undef, <4 x i32>* undef, align 4 + ;CHECK: cost of 2 {{.*}} store + store <4 x i64> undef, <4 x i64>* undef, align 4 + + ;CHECK: cost of 1 {{.*}} store + store <8 x i16> undef, <8 x i16>* undef, align 4 + ;CHECK: cost of 2 {{.*}} store + store <8 x i32> undef, <8 x i32>* undef, align 4 + ;CHECK: cost of 4 {{.*}} store + store <8 x i64> undef, <8 x i64>* undef, align 4 + + ret i32 undef +} +define i32 @loads(i32 %arg) { + ;CHECK: cost of 1 {{.*}} load + load i8* undef, align 4 + ;CHECK: cost of 1 {{.*}} load + load i16* undef, align 4 + ;CHECK: cost of 1 {{.*}} load + load i32* undef, align 4 + ;CHECK: cost of 1 {{.*}} load + load i64* undef, align 4 + ;CHECK: cost of 2 {{.*}} load + load i128* undef, align 4 + + ;CHECK: cost of 1 {{.*}} load + load <2 x i32>* undef, align 4 + ;CHECK: cost of 1 {{.*}} load + load <4 x i32>* undef, align 4 + ;CHECK: cost of 2 {{.*}} load + load <8 x i32>* undef, align 4 + + + ;CHECK: cost of 1 {{.*}} load + load <2 x i64>* undef, align 4 + ;CHECK: cost of 2 {{.*}} load + load <4 x i64>* undef, align 4 + ;CHECK: cost of 4 {{.*}} load + load <8 x i64>* undef, align 4 + + ret i32 undef +} + diff --git a/test/Analysis/CostModel/X86/testshiftashr.ll b/test/Analysis/CostModel/X86/testshiftashr.ll new file mode 100644 index 0000000000000..f35eea87164c8 --- /dev/null +++ b/test/Analysis/CostModel/X86/testshiftashr.ll @@ -0,0 +1,531 @@ +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=core2 < %s | FileCheck --check-prefix=SSE2-CODEGEN %s +; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s + +%shifttype = type <2 x i16> +define %shifttype @shift2i16(%shifttype %a, %shifttype %b) { +entry: + ; SSE2: shift2i16 + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i16 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype %a , %b + ret %shifttype %0 +} + +%shifttype4i16 = type <4 x i16> +define %shifttype4i16 @shift4i16(%shifttype4i16 %a, %shifttype4i16 %b) { +entry: + ; SSE2: shift4i16 + ; SSE2: cost of 40 {{.*}} ashr + ; SSE2-CODEGEN: shift4i16 + ; SSE2-CODEGEN: sarl %cl + + %0 = ashr %shifttype4i16 %a , %b + ret %shifttype4i16 %0 +} + +%shifttype8i16 = type <8 x i16> +define %shifttype8i16 @shift8i16(%shifttype8i16 %a, %shifttype8i16 %b) { +entry: + ; SSE2: shift8i16 + ; SSE2: cost of 80 {{.*}} ashr + ; SSE2-CODEGEN: shift8i16 + ; SSE2-CODEGEN: sarw %cl + + %0 = ashr %shifttype8i16 %a , %b + ret %shifttype8i16 %0 +} + +%shifttype16i16 = type <16 x i16> +define %shifttype16i16 @shift16i16(%shifttype16i16 %a, %shifttype16i16 %b) { +entry: + ; SSE2: shift16i16 + ; SSE2: cost of 160 {{.*}} ashr + ; SSE2-CODEGEN: shift16i16 + ; SSE2-CODEGEN: sarw %cl + + %0 = ashr %shifttype16i16 %a , %b + ret %shifttype16i16 %0 +} + +%shifttype32i16 = type <32 x i16> +define %shifttype32i16 @shift32i16(%shifttype32i16 %a, %shifttype32i16 %b) { +entry: + ; SSE2: shift32i16 + ; SSE2: cost of 320 {{.*}} ashr + ; SSE2-CODEGEN: shift32i16 + ; SSE2-CODEGEN: sarw %cl + + %0 = ashr %shifttype32i16 %a , %b + ret %shifttype32i16 %0 +} + +%shifttype2i32 = type <2 x i32> +define %shifttype2i32 @shift2i32(%shifttype2i32 %a, %shifttype2i32 %b) { +entry: + ; SSE2: shift2i32 + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i32 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype2i32 %a , %b + ret %shifttype2i32 %0 +} + +%shifttype4i32 = type <4 x i32> +define %shifttype4i32 @shift4i32(%shifttype4i32 %a, %shifttype4i32 %b) { +entry: + ; SSE2: shift4i32 + ; SSE2: cost of 40 {{.*}} ashr + ; SSE2-CODEGEN: shift4i32 + ; SSE2-CODEGEN: sarl %cl + + %0 = ashr %shifttype4i32 %a , %b + ret %shifttype4i32 %0 +} + +%shifttype8i32 = type <8 x i32> +define %shifttype8i32 @shift8i32(%shifttype8i32 %a, %shifttype8i32 %b) { +entry: + ; SSE2: shift8i32 + ; SSE2: cost of 80 {{.*}} ashr + ; SSE2-CODEGEN: shift8i32 + ; SSE2-CODEGEN: sarl %cl + + %0 = ashr %shifttype8i32 %a , %b + ret %shifttype8i32 %0 +} + +%shifttype16i32 = type <16 x i32> +define %shifttype16i32 @shift16i32(%shifttype16i32 %a, %shifttype16i32 %b) { +entry: + ; SSE2: shift16i32 + ; SSE2: cost of 160 {{.*}} ashr + ; SSE2-CODEGEN: shift16i32 + ; SSE2-CODEGEN: sarl %cl + + %0 = ashr %shifttype16i32 %a , %b + ret %shifttype16i32 %0 +} + +%shifttype32i32 = type <32 x i32> +define %shifttype32i32 @shift32i32(%shifttype32i32 %a, %shifttype32i32 %b) { +entry: + ; SSE2: shift32i32 + ; SSE2: cost of 256 {{.*}} ashr + ; SSE2-CODEGEN: shift32i32 + ; SSE2-CODEGEN: sarl %cl + + %0 = ashr %shifttype32i32 %a , %b + ret %shifttype32i32 %0 +} + +%shifttype2i64 = type <2 x i64> +define %shifttype2i64 @shift2i64(%shifttype2i64 %a, %shifttype2i64 %b) { +entry: + ; SSE2: shift2i64 + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i64 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype2i64 %a , %b + ret %shifttype2i64 %0 +} + +%shifttype4i64 = type <4 x i64> +define %shifttype4i64 @shift4i64(%shifttype4i64 %a, %shifttype4i64 %b) { +entry: + ; SSE2: shift4i64 + ; SSE2: cost of 40 {{.*}} ashr + ; SSE2-CODEGEN: shift4i64 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype4i64 %a , %b + ret %shifttype4i64 %0 +} + +%shifttype8i64 = type <8 x i64> +define %shifttype8i64 @shift8i64(%shifttype8i64 %a, %shifttype8i64 %b) { +entry: + ; SSE2: shift8i64 + ; SSE2: cost of 80 {{.*}} ashr + ; SSE2-CODEGEN: shift8i64 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype8i64 %a , %b + ret %shifttype8i64 %0 +} + +%shifttype16i64 = type <16 x i64> +define %shifttype16i64 @shift16i64(%shifttype16i64 %a, %shifttype16i64 %b) { +entry: + ; SSE2: shift16i64 + ; SSE2: cost of 160 {{.*}} ashr + ; SSE2-CODEGEN: shift16i64 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype16i64 %a , %b + ret %shifttype16i64 %0 +} + +%shifttype32i64 = type <32 x i64> +define %shifttype32i64 @shift32i64(%shifttype32i64 %a, %shifttype32i64 %b) { +entry: + ; SSE2: shift32i64 + ; SSE2: cost of 256 {{.*}} ashr + ; SSE2-CODEGEN: shift32i64 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype32i64 %a , %b + ret %shifttype32i64 %0 +} + +%shifttype2i8 = type <2 x i8> +define %shifttype2i8 @shift2i8(%shifttype2i8 %a, %shifttype2i8 %b) { +entry: + ; SSE2: shift2i8 + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i8 + ; SSE2-CODEGEN: sarq %cl + + %0 = ashr %shifttype2i8 %a , %b + ret %shifttype2i8 %0 +} + +%shifttype4i8 = type <4 x i8> +define %shifttype4i8 @shift4i8(%shifttype4i8 %a, %shifttype4i8 %b) { +entry: + ; SSE2: shift4i8 + ; SSE2: cost of 40 {{.*}} ashr + ; SSE2-CODEGEN: shift4i8 + ; SSE2-CODEGEN: sarl %cl + + %0 = ashr %shifttype4i8 %a , %b + ret %shifttype4i8 %0 +} + +%shifttype8i8 = type <8 x i8> +define %shifttype8i8 @shift8i8(%shifttype8i8 %a, %shifttype8i8 %b) { +entry: + ; SSE2: shift8i8 + ; SSE2: cost of 80 {{.*}} ashr + ; SSE2-CODEGEN: shift8i8 + ; SSE2-CODEGEN: sarw %cl + + %0 = ashr %shifttype8i8 %a , %b + ret %shifttype8i8 %0 +} + +%shifttype16i8 = type <16 x i8> +define %shifttype16i8 @shift16i8(%shifttype16i8 %a, %shifttype16i8 %b) { +entry: + ; SSE2: shift16i8 + ; SSE2: cost of 160 {{.*}} ashr + ; SSE2-CODEGEN: shift16i8 + ; SSE2-CODEGEN: sarb %cl + + %0 = ashr %shifttype16i8 %a , %b + ret %shifttype16i8 %0 +} + +%shifttype32i8 = type <32 x i8> +define %shifttype32i8 @shift32i8(%shifttype32i8 %a, %shifttype32i8 %b) { +entry: + ; SSE2: shift32i8 + ; SSE2: cost of 320 {{.*}} ashr + ; SSE2-CODEGEN: shift32i8 + ; SSE2-CODEGEN: sarb %cl + + %0 = ashr %shifttype32i8 %a , %b + ret %shifttype32i8 %0 +} + +; Test shift by a constant a value. + +%shifttypec = type <2 x i16> +define %shifttypec @shift2i16const(%shifttypec %a, %shifttypec %b) { +entry: + ; SSE2: shift2i16const + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i16const + ; SSE2-CODEGEN: sarq $ + + %0 = ashr %shifttypec %a , <i16 3, i16 3> + ret %shifttypec %0 +} + +%shifttypec4i16 = type <4 x i16> +define %shifttypec4i16 @shift4i16const(%shifttypec4i16 %a, %shifttypec4i16 %b) { +entry: + ; SSE2: shift4i16const + ; SSE2: cost of 1 {{.*}} ashr + ; SSE2-CODEGEN: shift4i16const + ; SSE2-CODEGEN: psrad $3 + + %0 = ashr %shifttypec4i16 %a , <i16 3, i16 3, i16 3, i16 3> + ret %shifttypec4i16 %0 +} + +%shifttypec8i16 = type <8 x i16> +define %shifttypec8i16 @shift8i16const(%shifttypec8i16 %a, %shifttypec8i16 %b) { +entry: + ; SSE2: shift8i16const + ; SSE2: cost of 1 {{.*}} ashr + ; SSE2-CODEGEN: shift8i16const + ; SSE2-CODEGEN: psraw $3 + + %0 = ashr %shifttypec8i16 %a , <i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3> + ret %shifttypec8i16 %0 +} + +%shifttypec16i16 = type <16 x i16> +define %shifttypec16i16 @shift16i16const(%shifttypec16i16 %a, + %shifttypec16i16 %b) { +entry: + ; SSE2: shift16i16const + ; SSE2: cost of 2 {{.*}} ashr + ; SSE2-CODEGEN: shift16i16const + ; SSE2-CODEGEN: psraw $3 + + %0 = ashr %shifttypec16i16 %a , <i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3> + ret %shifttypec16i16 %0 +} + +%shifttypec32i16 = type <32 x i16> +define %shifttypec32i16 @shift32i16const(%shifttypec32i16 %a, + %shifttypec32i16 %b) { +entry: + ; SSE2: shift32i16const + ; SSE2: cost of 4 {{.*}} ashr + ; SSE2-CODEGEN: shift32i16const + ; SSE2-CODEGEN: psraw $3 + + %0 = ashr %shifttypec32i16 %a , <i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3> + ret %shifttypec32i16 %0 +} + +%shifttypec2i32 = type <2 x i32> +define %shifttypec2i32 @shift2i32c(%shifttypec2i32 %a, %shifttypec2i32 %b) { +entry: + ; SSE2: shift2i32c + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i32c + ; SSE2-CODEGEN: sarq $3 + + %0 = ashr %shifttypec2i32 %a , <i32 3, i32 3> + ret %shifttypec2i32 %0 +} + +%shifttypec4i32 = type <4 x i32> +define %shifttypec4i32 @shift4i32c(%shifttypec4i32 %a, %shifttypec4i32 %b) { +entry: + ; SSE2: shift4i32c + ; SSE2: cost of 1 {{.*}} ashr + ; SSE2-CODEGEN: shift4i32c + ; SSE2-CODEGEN: psrad $3 + + %0 = ashr %shifttypec4i32 %a , <i32 3, i32 3, i32 3, i32 3> + ret %shifttypec4i32 %0 +} + +%shifttypec8i32 = type <8 x i32> +define %shifttypec8i32 @shift8i32c(%shifttypec8i32 %a, %shifttypec8i32 %b) { +entry: + ; SSE2: shift8i32c + ; SSE2: cost of 2 {{.*}} ashr + ; SSE2-CODEGEN: shift8i32c + ; SSE2-CODEGEN: psrad $3 + + %0 = ashr %shifttypec8i32 %a , <i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3> + ret %shifttypec8i32 %0 +} + +%shifttypec16i32 = type <16 x i32> +define %shifttypec16i32 @shift16i32c(%shifttypec16i32 %a, %shifttypec16i32 %b) { +entry: + ; SSE2: shift16i32c + ; SSE2: cost of 4 {{.*}} ashr + ; SSE2-CODEGEN: shift16i32c + ; SSE2-CODEGEN: psrad $3 + + %0 = ashr %shifttypec16i32 %a , <i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3> + ret %shifttypec16i32 %0 +} + +%shifttypec32i32 = type <32 x i32> +define %shifttypec32i32 @shift32i32c(%shifttypec32i32 %a, %shifttypec32i32 %b) { +entry: + ; SSE2: shift32i32c + ; getTypeConversion fails here and promotes this to a i64. + ; SSE2: cost of 256 {{.*}} ashr + ; SSE2-CODEGEN: shift32i32c + ; SSE2-CODEGEN: psrad $3 + %0 = ashr %shifttypec32i32 %a , <i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3> + ret %shifttypec32i32 %0 +} + +%shifttypec2i64 = type <2 x i64> +define %shifttypec2i64 @shift2i64c(%shifttypec2i64 %a, %shifttypec2i64 %b) { +entry: + ; SSE2: shift2i64c + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i64c + ; SSE2-CODEGEN: sarq $3 + + %0 = ashr %shifttypec2i64 %a , <i64 3, i64 3> + ret %shifttypec2i64 %0 +} + +%shifttypec4i64 = type <4 x i64> +define %shifttypec4i64 @shift4i64c(%shifttypec4i64 %a, %shifttypec4i64 %b) { +entry: + ; SSE2: shift4i64c + ; SSE2: cost of 40 {{.*}} ashr + ; SSE2-CODEGEN: shift4i64c + ; SSE2-CODEGEN: sarq $3 + + %0 = ashr %shifttypec4i64 %a , <i64 3, i64 3, i64 3, i64 3> + ret %shifttypec4i64 %0 +} + +%shifttypec8i64 = type <8 x i64> +define %shifttypec8i64 @shift8i64c(%shifttypec8i64 %a, %shifttypec8i64 %b) { +entry: + ; SSE2: shift8i64c + ; SSE2: cost of 80 {{.*}} ashr + ; SSE2-CODEGEN: shift8i64c + ; SSE2-CODEGEN: sarq $3 + + %0 = ashr %shifttypec8i64 %a , <i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3> + ret %shifttypec8i64 %0 +} + +%shifttypec16i64 = type <16 x i64> +define %shifttypec16i64 @shift16i64c(%shifttypec16i64 %a, %shifttypec16i64 %b) { +entry: + ; SSE2: shift16i64c + ; SSE2: cost of 160 {{.*}} ashr + ; SSE2-CODEGEN: shift16i64c + ; SSE2-CODEGEN: sarq $3 + + %0 = ashr %shifttypec16i64 %a , <i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3> + ret %shifttypec16i64 %0 +} + +%shifttypec32i64 = type <32 x i64> +define %shifttypec32i64 @shift32i64c(%shifttypec32i64 %a, %shifttypec32i64 %b) { +entry: + ; SSE2: shift32i64c + ; SSE2: cost of 256 {{.*}} ashr + ; SSE2-CODEGEN: shift32i64c + ; SSE2-CODEGEN: sarq $3 + + %0 = ashr %shifttypec32i64 %a ,<i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3> + ret %shifttypec32i64 %0 +} + +%shifttypec2i8 = type <2 x i8> +define %shifttypec2i8 @shift2i8c(%shifttypec2i8 %a, %shifttypec2i8 %b) { +entry: + ; SSE2: shift2i8c + ; SSE2: cost of 20 {{.*}} ashr + ; SSE2-CODEGEN: shift2i8c + ; SSE2-CODEGEN: sarq $3 + + %0 = ashr %shifttypec2i8 %a , <i8 3, i8 3> + ret %shifttypec2i8 %0 +} + +%shifttypec4i8 = type <4 x i8> +define %shifttypec4i8 @shift4i8c(%shifttypec4i8 %a, %shifttypec4i8 %b) { +entry: + ; SSE2: shift4i8c + ; SSE2: cost of 1 {{.*}} ashr + ; SSE2-CODEGEN: shift4i8c + ; SSE2-CODEGEN: psrad $3 + + %0 = ashr %shifttypec4i8 %a , <i8 3, i8 3, i8 3, i8 3> + ret %shifttypec4i8 %0 +} + +%shifttypec8i8 = type <8 x i8> +define %shifttypec8i8 @shift8i8c(%shifttypec8i8 %a, %shifttypec8i8 %b) { +entry: + ; SSE2: shift8i8c + ; SSE2: cost of 1 {{.*}} ashr + ; SSE2-CODEGEN: shift8i8c + ; SSE2-CODEGEN: psraw $3 + + %0 = ashr %shifttypec8i8 %a , <i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3> + ret %shifttypec8i8 %0 +} + +%shifttypec16i8 = type <16 x i8> +define %shifttypec16i8 @shift16i8c(%shifttypec16i8 %a, %shifttypec16i8 %b) { +entry: + ; SSE2: shift16i8c + ; SSE2: cost of 4 {{.*}} ashr + ; SSE2-CODEGEN: shift16i8c + ; SSE2-CODEGEN: psrlw $3 + + %0 = ashr %shifttypec16i8 %a , <i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3> + ret %shifttypec16i8 %0 +} + +%shifttypec32i8 = type <32 x i8> +define %shifttypec32i8 @shift32i8c(%shifttypec32i8 %a, %shifttypec32i8 %b) { +entry: + ; SSE2: shift32i8c + ; SSE2: cost of 8 {{.*}} ashr + ; SSE2-CODEGEN: shift32i8c + ; SSE2-CODEGEN: psrlw $3 + + %0 = ashr %shifttypec32i8 %a , <i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3> + ret %shifttypec32i8 %0 +} + diff --git a/test/Analysis/CostModel/X86/testshiftlshr.ll b/test/Analysis/CostModel/X86/testshiftlshr.ll new file mode 100644 index 0000000000000..8d6ef38742080 --- /dev/null +++ b/test/Analysis/CostModel/X86/testshiftlshr.ll @@ -0,0 +1,530 @@ +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=core2 < %s | FileCheck --check-prefix=SSE2-CODEGEN %s +; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s + +%shifttype = type <2 x i16> +define %shifttype @shift2i16(%shifttype %a, %shifttype %b) { +entry: + ; SSE2: shift2i16 + ; SSE2: cost of 20 {{.*}} lshr + ; SSE2-CODEGEN: shift2i16 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype %a , %b + ret %shifttype %0 +} + +%shifttype4i16 = type <4 x i16> +define %shifttype4i16 @shift4i16(%shifttype4i16 %a, %shifttype4i16 %b) { +entry: + ; SSE2: shift4i16 + ; SSE2: cost of 40 {{.*}} lshr + ; SSE2-CODEGEN: shift4i16 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype4i16 %a , %b + ret %shifttype4i16 %0 +} + +%shifttype8i16 = type <8 x i16> +define %shifttype8i16 @shift8i16(%shifttype8i16 %a, %shifttype8i16 %b) { +entry: + ; SSE2: shift8i16 + ; SSE2: cost of 80 {{.*}} lshr + ; SSE2-CODEGEN: shift8i16 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype8i16 %a , %b + ret %shifttype8i16 %0 +} + +%shifttype16i16 = type <16 x i16> +define %shifttype16i16 @shift16i16(%shifttype16i16 %a, %shifttype16i16 %b) { +entry: + ; SSE2: shift16i16 + ; SSE2: cost of 160 {{.*}} lshr + ; SSE2-CODEGEN: shift16i16 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype16i16 %a , %b + ret %shifttype16i16 %0 +} + +%shifttype32i16 = type <32 x i16> +define %shifttype32i16 @shift32i16(%shifttype32i16 %a, %shifttype32i16 %b) { +entry: + ; SSE2: shift32i16 + ; SSE2: cost of 320 {{.*}} lshr + ; SSE2-CODEGEN: shift32i16 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype32i16 %a , %b + ret %shifttype32i16 %0 +} + +%shifttype2i32 = type <2 x i32> +define %shifttype2i32 @shift2i32(%shifttype2i32 %a, %shifttype2i32 %b) { +entry: + ; SSE2: shift2i32 + ; SSE2: cost of 20 {{.*}} lshr + ; SSE2-CODEGEN: shift2i32 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype2i32 %a , %b + ret %shifttype2i32 %0 +} + +%shifttype4i32 = type <4 x i32> +define %shifttype4i32 @shift4i32(%shifttype4i32 %a, %shifttype4i32 %b) { +entry: + ; SSE2: shift4i32 + ; SSE2: cost of 40 {{.*}} lshr + ; SSE2-CODEGEN: shift4i32 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype4i32 %a , %b + ret %shifttype4i32 %0 +} + +%shifttype8i32 = type <8 x i32> +define %shifttype8i32 @shift8i32(%shifttype8i32 %a, %shifttype8i32 %b) { +entry: + ; SSE2: shift8i32 + ; SSE2: cost of 80 {{.*}} lshr + ; SSE2-CODEGEN: shift8i32 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype8i32 %a , %b + ret %shifttype8i32 %0 +} + +%shifttype16i32 = type <16 x i32> +define %shifttype16i32 @shift16i32(%shifttype16i32 %a, %shifttype16i32 %b) { +entry: + ; SSE2: shift16i32 + ; SSE2: cost of 160 {{.*}} lshr + ; SSE2-CODEGEN: shift16i32 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype16i32 %a , %b + ret %shifttype16i32 %0 +} + +%shifttype32i32 = type <32 x i32> +define %shifttype32i32 @shift32i32(%shifttype32i32 %a, %shifttype32i32 %b) { +entry: + ; SSE2: shift32i32 + ; SSE2: cost of 256 {{.*}} lshr + ; SSE2-CODEGEN: shift32i32 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype32i32 %a , %b + ret %shifttype32i32 %0 +} + +%shifttype2i64 = type <2 x i64> +define %shifttype2i64 @shift2i64(%shifttype2i64 %a, %shifttype2i64 %b) { +entry: + ; SSE2: shift2i64 + ; SSE2: cost of 20 {{.*}} lshr + ; SSE2-CODEGEN: shift2i64 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype2i64 %a , %b + ret %shifttype2i64 %0 +} + +%shifttype4i64 = type <4 x i64> +define %shifttype4i64 @shift4i64(%shifttype4i64 %a, %shifttype4i64 %b) { +entry: + ; SSE2: shift4i64 + ; SSE2: cost of 40 {{.*}} lshr + ; SSE2-CODEGEN: shift4i64 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype4i64 %a , %b + ret %shifttype4i64 %0 +} + +%shifttype8i64 = type <8 x i64> +define %shifttype8i64 @shift8i64(%shifttype8i64 %a, %shifttype8i64 %b) { +entry: + ; SSE2: shift8i64 + ; SSE2: cost of 80 {{.*}} lshr + ; SSE2-CODEGEN: shift8i64 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype8i64 %a , %b + ret %shifttype8i64 %0 +} + +%shifttype16i64 = type <16 x i64> +define %shifttype16i64 @shift16i64(%shifttype16i64 %a, %shifttype16i64 %b) { +entry: + ; SSE2: shift16i64 + ; SSE2: cost of 160 {{.*}} lshr + ; SSE2-CODEGEN: shift16i64 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype16i64 %a , %b + ret %shifttype16i64 %0 +} + +%shifttype32i64 = type <32 x i64> +define %shifttype32i64 @shift32i64(%shifttype32i64 %a, %shifttype32i64 %b) { +entry: + ; SSE2: shift32i64 + ; SSE2: cost of 256 {{.*}} lshr + ; SSE2-CODEGEN: shift32i64 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype32i64 %a , %b + ret %shifttype32i64 %0 +} + +%shifttype2i8 = type <2 x i8> +define %shifttype2i8 @shift2i8(%shifttype2i8 %a, %shifttype2i8 %b) { +entry: + ; SSE2: shift2i8 + ; SSE2: cost of 20 {{.*}} lshr + ; SSE2-CODEGEN: shift2i8 + ; SSE2-CODEGEN: shrq %cl + + %0 = lshr %shifttype2i8 %a , %b + ret %shifttype2i8 %0 +} + +%shifttype4i8 = type <4 x i8> +define %shifttype4i8 @shift4i8(%shifttype4i8 %a, %shifttype4i8 %b) { +entry: + ; SSE2: shift4i8 + ; SSE2: cost of 40 {{.*}} lshr + ; SSE2-CODEGEN: shift4i8 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype4i8 %a , %b + ret %shifttype4i8 %0 +} + +%shifttype8i8 = type <8 x i8> +define %shifttype8i8 @shift8i8(%shifttype8i8 %a, %shifttype8i8 %b) { +entry: + ; SSE2: shift8i8 + ; SSE2: cost of 80 {{.*}} lshr + ; SSE2-CODEGEN: shift8i8 + ; SSE2-CODEGEN: shrl %cl + + %0 = lshr %shifttype8i8 %a , %b + ret %shifttype8i8 %0 +} + +%shifttype16i8 = type <16 x i8> +define %shifttype16i8 @shift16i8(%shifttype16i8 %a, %shifttype16i8 %b) { +entry: + ; SSE2: shift16i8 + ; SSE2: cost of 160 {{.*}} lshr + ; SSE2-CODEGEN: shift16i8 + ; SSE2-CODEGEN: shrb %cl + + %0 = lshr %shifttype16i8 %a , %b + ret %shifttype16i8 %0 +} + +%shifttype32i8 = type <32 x i8> +define %shifttype32i8 @shift32i8(%shifttype32i8 %a, %shifttype32i8 %b) { +entry: + ; SSE2: shift32i8 + ; SSE2: cost of 320 {{.*}} lshr + ; SSE2-CODEGEN: shift32i8 + ; SSE2-CODEGEN: shrb %cl + + %0 = lshr %shifttype32i8 %a , %b + ret %shifttype32i8 %0 +} + +; Test shift by a constant vector. + +%shifttypec = type <2 x i16> +define %shifttypec @shift2i16const(%shifttypec %a, %shifttypec %b) { +entry: + ; SSE2: shift2i16const + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift2i16const + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec %a , <i16 3, i16 3> + ret %shifttypec %0 +} + +%shifttypec4i16 = type <4 x i16> +define %shifttypec4i16 @shift4i16const(%shifttypec4i16 %a, %shifttypec4i16 %b) { +entry: + ; SSE2: shift4i16const + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift4i16const + ; SSE2-CODEGEN: psrld $3 + + %0 = lshr %shifttypec4i16 %a , <i16 3, i16 3, i16 3, i16 3> + ret %shifttypec4i16 %0 +} + +%shifttypec8i16 = type <8 x i16> +define %shifttypec8i16 @shift8i16const(%shifttypec8i16 %a, %shifttypec8i16 %b) { +entry: + ; SSE2: shift8i16const + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift8i16const + ; SSE2-CODEGEN: psrlw $3 + + %0 = lshr %shifttypec8i16 %a , <i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3> + ret %shifttypec8i16 %0 +} + +%shifttypec16i16 = type <16 x i16> +define %shifttypec16i16 @shift16i16const(%shifttypec16i16 %a, + %shifttypec16i16 %b) { +entry: + ; SSE2: shift16i16const + ; SSE2: cost of 2 {{.*}} lshr + ; SSE2-CODEGEN: shift16i16const + ; SSE2-CODEGEN: psrlw $3 + + %0 = lshr %shifttypec16i16 %a , <i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3> + ret %shifttypec16i16 %0 +} + +%shifttypec32i16 = type <32 x i16> +define %shifttypec32i16 @shift32i16const(%shifttypec32i16 %a, + %shifttypec32i16 %b) { +entry: + ; SSE2: shift32i16const + ; SSE2: cost of 4 {{.*}} lshr + ; SSE2-CODEGEN: shift32i16const + ; SSE2-CODEGEN: psrlw $3 + + %0 = lshr %shifttypec32i16 %a , <i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3> + ret %shifttypec32i16 %0 +} + +%shifttypec2i32 = type <2 x i32> +define %shifttypec2i32 @shift2i32c(%shifttypec2i32 %a, %shifttypec2i32 %b) { +entry: + ; SSE2: shift2i32c + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift2i32c + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec2i32 %a , <i32 3, i32 3> + ret %shifttypec2i32 %0 +} + +%shifttypec4i32 = type <4 x i32> +define %shifttypec4i32 @shift4i32c(%shifttypec4i32 %a, %shifttypec4i32 %b) { +entry: + ; SSE2: shift4i32c + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift4i32c + ; SSE2-CODEGEN: psrld $3 + + %0 = lshr %shifttypec4i32 %a , <i32 3, i32 3, i32 3, i32 3> + ret %shifttypec4i32 %0 +} + +%shifttypec8i32 = type <8 x i32> +define %shifttypec8i32 @shift8i32c(%shifttypec8i32 %a, %shifttypec8i32 %b) { +entry: + ; SSE2: shift8i32c + ; SSE2: cost of 2 {{.*}} lshr + ; SSE2-CODEGEN: shift8i32c + ; SSE2-CODEGEN: psrld $3 + + %0 = lshr %shifttypec8i32 %a , <i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3> + ret %shifttypec8i32 %0 +} + +%shifttypec16i32 = type <16 x i32> +define %shifttypec16i32 @shift16i32c(%shifttypec16i32 %a, %shifttypec16i32 %b) { +entry: + ; SSE2: shift16i32c + ; SSE2: cost of 4 {{.*}} lshr + ; SSE2-CODEGEN: shift16i32c + ; SSE2-CODEGEN: psrld $3 + + %0 = lshr %shifttypec16i32 %a , <i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3> + ret %shifttypec16i32 %0 +} + +%shifttypec32i32 = type <32 x i32> +define %shifttypec32i32 @shift32i32c(%shifttypec32i32 %a, %shifttypec32i32 %b) { +entry: + ; SSE2: shift32i32c + ; getTypeConversion fails here and promotes this to a i64. + ; SSE2: cost of 256 {{.*}} lshr + ; SSE2-CODEGEN: shift32i32c + ; SSE2-CODEGEN: psrld $3 + %0 = lshr %shifttypec32i32 %a , <i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3> + ret %shifttypec32i32 %0 +} + +%shifttypec2i64 = type <2 x i64> +define %shifttypec2i64 @shift2i64c(%shifttypec2i64 %a, %shifttypec2i64 %b) { +entry: + ; SSE2: shift2i64c + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift2i64c + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec2i64 %a , <i64 3, i64 3> + ret %shifttypec2i64 %0 +} + +%shifttypec4i64 = type <4 x i64> +define %shifttypec4i64 @shift4i64c(%shifttypec4i64 %a, %shifttypec4i64 %b) { +entry: + ; SSE2: shift4i64c + ; SSE2: cost of 2 {{.*}} lshr + ; SSE2-CODEGEN: shift4i64c + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec4i64 %a , <i64 3, i64 3, i64 3, i64 3> + ret %shifttypec4i64 %0 +} + +%shifttypec8i64 = type <8 x i64> +define %shifttypec8i64 @shift8i64c(%shifttypec8i64 %a, %shifttypec8i64 %b) { +entry: + ; SSE2: shift8i64c + ; SSE2: cost of 4 {{.*}} lshr + ; SSE2-CODEGEN: shift8i64c + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec8i64 %a , <i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3> + ret %shifttypec8i64 %0 +} + +%shifttypec16i64 = type <16 x i64> +define %shifttypec16i64 @shift16i64c(%shifttypec16i64 %a, %shifttypec16i64 %b) { +entry: + ; SSE2: shift16i64c + ; SSE2: cost of 8 {{.*}} lshr + ; SSE2-CODEGEN: shift16i64c + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec16i64 %a , <i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3> + ret %shifttypec16i64 %0 +} + +%shifttypec32i64 = type <32 x i64> +define %shifttypec32i64 @shift32i64c(%shifttypec32i64 %a, %shifttypec32i64 %b) { +entry: + ; SSE2: shift32i64c + ; SSE2: cost of 256 {{.*}} lshr + ; SSE2-CODEGEN: shift32i64c + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec32i64 %a ,<i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3> + ret %shifttypec32i64 %0 +} + +%shifttypec2i8 = type <2 x i8> +define %shifttypec2i8 @shift2i8c(%shifttypec2i8 %a, %shifttypec2i8 %b) { +entry: + ; SSE2: shift2i8c + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift2i8c + ; SSE2-CODEGEN: psrlq $3 + + %0 = lshr %shifttypec2i8 %a , <i8 3, i8 3> + ret %shifttypec2i8 %0 +} + +%shifttypec4i8 = type <4 x i8> +define %shifttypec4i8 @shift4i8c(%shifttypec4i8 %a, %shifttypec4i8 %b) { +entry: + ; SSE2: shift4i8c + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift4i8c + ; SSE2-CODEGEN: psrld $3 + + %0 = lshr %shifttypec4i8 %a , <i8 3, i8 3, i8 3, i8 3> + ret %shifttypec4i8 %0 +} + +%shifttypec8i8 = type <8 x i8> +define %shifttypec8i8 @shift8i8c(%shifttypec8i8 %a, %shifttypec8i8 %b) { +entry: + ; SSE2: shift8i8c + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift8i8c + ; SSE2-CODEGEN: psrlw $3 + + %0 = lshr %shifttypec8i8 %a , <i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3> + ret %shifttypec8i8 %0 +} + +%shifttypec16i8 = type <16 x i8> +define %shifttypec16i8 @shift16i8c(%shifttypec16i8 %a, %shifttypec16i8 %b) { +entry: + ; SSE2: shift16i8c + ; SSE2: cost of 1 {{.*}} lshr + ; SSE2-CODEGEN: shift16i8c + ; SSE2-CODEGEN: psrlw $3 + + %0 = lshr %shifttypec16i8 %a , <i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3> + ret %shifttypec16i8 %0 +} + +%shifttypec32i8 = type <32 x i8> +define %shifttypec32i8 @shift32i8c(%shifttypec32i8 %a, %shifttypec32i8 %b) { +entry: + ; SSE2: shift32i8c + ; SSE2: cost of 2 {{.*}} lshr + ; SSE2-CODEGEN: shift32i8c + ; SSE2-CODEGEN: psrlw $3 + + %0 = lshr %shifttypec32i8 %a , <i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3> + ret %shifttypec32i8 %0 +} diff --git a/test/Analysis/CostModel/X86/testshiftshl.ll b/test/Analysis/CostModel/X86/testshiftshl.ll new file mode 100644 index 0000000000000..f45a69879210d --- /dev/null +++ b/test/Analysis/CostModel/X86/testshiftshl.ll @@ -0,0 +1,530 @@ +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=core2 < %s | FileCheck --check-prefix=SSE2-CODEGEN %s +; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s + +%shifttype = type <2 x i16> +define %shifttype @shift2i16(%shifttype %a, %shifttype %b) { +entry: + ; SSE2: shift2i16 + ; SSE2: cost of 20 {{.*}} shl + ; SSE2-CODEGEN: shift2i16 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype %a , %b + ret %shifttype %0 +} + +%shifttype4i16 = type <4 x i16> +define %shifttype4i16 @shift4i16(%shifttype4i16 %a, %shifttype4i16 %b) { +entry: + ; SSE2: shift4i16 + ; SSE2: cost of 10 {{.*}} shl + ; SSE2-CODEGEN: shift4i16 + ; SSE2-CODEGEN: pmuludq + + %0 = shl %shifttype4i16 %a , %b + ret %shifttype4i16 %0 +} + +%shifttype8i16 = type <8 x i16> +define %shifttype8i16 @shift8i16(%shifttype8i16 %a, %shifttype8i16 %b) { +entry: + ; SSE2: shift8i16 + ; SSE2: cost of 80 {{.*}} shl + ; SSE2-CODEGEN: shift8i16 + ; SSE2-CODEGEN: shll %cl + + %0 = shl %shifttype8i16 %a , %b + ret %shifttype8i16 %0 +} + +%shifttype16i16 = type <16 x i16> +define %shifttype16i16 @shift16i16(%shifttype16i16 %a, %shifttype16i16 %b) { +entry: + ; SSE2: shift16i16 + ; SSE2: cost of 160 {{.*}} shl + ; SSE2-CODEGEN: shift16i16 + ; SSE2-CODEGEN: shll %cl + + %0 = shl %shifttype16i16 %a , %b + ret %shifttype16i16 %0 +} + +%shifttype32i16 = type <32 x i16> +define %shifttype32i16 @shift32i16(%shifttype32i16 %a, %shifttype32i16 %b) { +entry: + ; SSE2: shift32i16 + ; SSE2: cost of 320 {{.*}} shl + ; SSE2-CODEGEN: shift32i16 + ; SSE2-CODEGEN: shll %cl + + %0 = shl %shifttype32i16 %a , %b + ret %shifttype32i16 %0 +} + +%shifttype2i32 = type <2 x i32> +define %shifttype2i32 @shift2i32(%shifttype2i32 %a, %shifttype2i32 %b) { +entry: + ; SSE2: shift2i32 + ; SSE2: cost of 20 {{.*}} shl + ; SSE2-CODEGEN: shift2i32 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype2i32 %a , %b + ret %shifttype2i32 %0 +} + +%shifttype4i32 = type <4 x i32> +define %shifttype4i32 @shift4i32(%shifttype4i32 %a, %shifttype4i32 %b) { +entry: + ; SSE2: shift4i32 + ; SSE2: cost of 10 {{.*}} shl + ; SSE2-CODEGEN: shift4i32 + ; SSE2-CODEGEN: pmuludq + + %0 = shl %shifttype4i32 %a , %b + ret %shifttype4i32 %0 +} + +%shifttype8i32 = type <8 x i32> +define %shifttype8i32 @shift8i32(%shifttype8i32 %a, %shifttype8i32 %b) { +entry: + ; SSE2: shift8i32 + ; SSE2: cost of 20 {{.*}} shl + ; SSE2-CODEGEN: shift8i32 + ; SSE2-CODEGEN: pmuludq + + %0 = shl %shifttype8i32 %a , %b + ret %shifttype8i32 %0 +} + +%shifttype16i32 = type <16 x i32> +define %shifttype16i32 @shift16i32(%shifttype16i32 %a, %shifttype16i32 %b) { +entry: + ; SSE2: shift16i32 + ; SSE2: cost of 40 {{.*}} shl + ; SSE2-CODEGEN: shift16i32 + ; SSE2-CODEGEN: pmuludq + + %0 = shl %shifttype16i32 %a , %b + ret %shifttype16i32 %0 +} + +%shifttype32i32 = type <32 x i32> +define %shifttype32i32 @shift32i32(%shifttype32i32 %a, %shifttype32i32 %b) { +entry: + ; SSE2: shift32i32 + ; SSE2: cost of 256 {{.*}} shl + ; SSE2-CODEGEN: shift32i32 + ; SSE2-CODEGEN: pmuludq + + %0 = shl %shifttype32i32 %a , %b + ret %shifttype32i32 %0 +} + +%shifttype2i64 = type <2 x i64> +define %shifttype2i64 @shift2i64(%shifttype2i64 %a, %shifttype2i64 %b) { +entry: + ; SSE2: shift2i64 + ; SSE2: cost of 20 {{.*}} shl + ; SSE2-CODEGEN: shift2i64 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype2i64 %a , %b + ret %shifttype2i64 %0 +} + +%shifttype4i64 = type <4 x i64> +define %shifttype4i64 @shift4i64(%shifttype4i64 %a, %shifttype4i64 %b) { +entry: + ; SSE2: shift4i64 + ; SSE2: cost of 40 {{.*}} shl + ; SSE2-CODEGEN: shift4i64 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype4i64 %a , %b + ret %shifttype4i64 %0 +} + +%shifttype8i64 = type <8 x i64> +define %shifttype8i64 @shift8i64(%shifttype8i64 %a, %shifttype8i64 %b) { +entry: + ; SSE2: shift8i64 + ; SSE2: cost of 80 {{.*}} shl + ; SSE2-CODEGEN: shift8i64 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype8i64 %a , %b + ret %shifttype8i64 %0 +} + +%shifttype16i64 = type <16 x i64> +define %shifttype16i64 @shift16i64(%shifttype16i64 %a, %shifttype16i64 %b) { +entry: + ; SSE2: shift16i64 + ; SSE2: cost of 160 {{.*}} shl + ; SSE2-CODEGEN: shift16i64 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype16i64 %a , %b + ret %shifttype16i64 %0 +} + +%shifttype32i64 = type <32 x i64> +define %shifttype32i64 @shift32i64(%shifttype32i64 %a, %shifttype32i64 %b) { +entry: + ; SSE2: shift32i64 + ; SSE2: cost of 256 {{.*}} shl + ; SSE2-CODEGEN: shift32i64 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype32i64 %a , %b + ret %shifttype32i64 %0 +} + +%shifttype2i8 = type <2 x i8> +define %shifttype2i8 @shift2i8(%shifttype2i8 %a, %shifttype2i8 %b) { +entry: + ; SSE2: shift2i8 + ; SSE2: cost of 20 {{.*}} shl + ; SSE2-CODEGEN: shift2i8 + ; SSE2-CODEGEN: shlq %cl + + %0 = shl %shifttype2i8 %a , %b + ret %shifttype2i8 %0 +} + +%shifttype4i8 = type <4 x i8> +define %shifttype4i8 @shift4i8(%shifttype4i8 %a, %shifttype4i8 %b) { +entry: + ; SSE2: shift4i8 + ; SSE2: cost of 10 {{.*}} shl + ; SSE2-CODEGEN: shift4i8 + ; SSE2-CODEGEN: pmuludq + + %0 = shl %shifttype4i8 %a , %b + ret %shifttype4i8 %0 +} + +%shifttype8i8 = type <8 x i8> +define %shifttype8i8 @shift8i8(%shifttype8i8 %a, %shifttype8i8 %b) { +entry: + ; SSE2: shift8i8 + ; SSE2: cost of 80 {{.*}} shl + ; SSE2-CODEGEN: shift8i8 + ; SSE2-CODEGEN: shll + + %0 = shl %shifttype8i8 %a , %b + ret %shifttype8i8 %0 +} + +%shifttype16i8 = type <16 x i8> +define %shifttype16i8 @shift16i8(%shifttype16i8 %a, %shifttype16i8 %b) { +entry: + ; SSE2: shift16i8 + ; SSE2: cost of 30 {{.*}} shl + ; SSE2-CODEGEN: shift16i8 + ; SSE2-CODEGEN: cmpeqb + + %0 = shl %shifttype16i8 %a , %b + ret %shifttype16i8 %0 +} + +%shifttype32i8 = type <32 x i8> +define %shifttype32i8 @shift32i8(%shifttype32i8 %a, %shifttype32i8 %b) { +entry: + ; SSE2: shift32i8 + ; SSE2: cost of 60 {{.*}} shl + ; SSE2-CODEGEN: shift32i8 + ; SSE2-CODEGEN: cmpeqb + + %0 = shl %shifttype32i8 %a , %b + ret %shifttype32i8 %0 +} + +; Test shift by a constant vector. + +%shifttypec = type <2 x i16> +define %shifttypec @shift2i16const(%shifttypec %a, %shifttypec %b) { +entry: + ; SSE2: shift2i16const + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift2i16const + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec %a , <i16 3, i16 3> + ret %shifttypec %0 +} + +%shifttypec4i16 = type <4 x i16> +define %shifttypec4i16 @shift4i16const(%shifttypec4i16 %a, %shifttypec4i16 %b) { +entry: + ; SSE2: shift4i16const + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift4i16const + ; SSE2-CODEGEN: pslld $3 + + %0 = shl %shifttypec4i16 %a , <i16 3, i16 3, i16 3, i16 3> + ret %shifttypec4i16 %0 +} + +%shifttypec8i16 = type <8 x i16> +define %shifttypec8i16 @shift8i16const(%shifttypec8i16 %a, %shifttypec8i16 %b) { +entry: + ; SSE2: shift8i16const + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift8i16const + ; SSE2-CODEGEN: psllw $3 + + %0 = shl %shifttypec8i16 %a , <i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3> + ret %shifttypec8i16 %0 +} + +%shifttypec16i16 = type <16 x i16> +define %shifttypec16i16 @shift16i16const(%shifttypec16i16 %a, + %shifttypec16i16 %b) { +entry: + ; SSE2: shift16i16const + ; SSE2: cost of 2 {{.*}} shl + ; SSE2-CODEGEN: shift16i16const + ; SSE2-CODEGEN: psllw $3 + + %0 = shl %shifttypec16i16 %a , <i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3> + ret %shifttypec16i16 %0 +} + +%shifttypec32i16 = type <32 x i16> +define %shifttypec32i16 @shift32i16const(%shifttypec32i16 %a, + %shifttypec32i16 %b) { +entry: + ; SSE2: shift32i16const + ; SSE2: cost of 4 {{.*}} shl + ; SSE2-CODEGEN: shift32i16const + ; SSE2-CODEGEN: psllw $3 + + %0 = shl %shifttypec32i16 %a , <i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3, + i16 3, i16 3, i16 3, i16 3> + ret %shifttypec32i16 %0 +} + +%shifttypec2i32 = type <2 x i32> +define %shifttypec2i32 @shift2i32c(%shifttypec2i32 %a, %shifttypec2i32 %b) { +entry: + ; SSE2: shift2i32c + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift2i32c + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec2i32 %a , <i32 3, i32 3> + ret %shifttypec2i32 %0 +} + +%shifttypec4i32 = type <4 x i32> +define %shifttypec4i32 @shift4i32c(%shifttypec4i32 %a, %shifttypec4i32 %b) { +entry: + ; SSE2: shift4i32c + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift4i32c + ; SSE2-CODEGEN: pslld $3 + + %0 = shl %shifttypec4i32 %a , <i32 3, i32 3, i32 3, i32 3> + ret %shifttypec4i32 %0 +} + +%shifttypec8i32 = type <8 x i32> +define %shifttypec8i32 @shift8i32c(%shifttypec8i32 %a, %shifttypec8i32 %b) { +entry: + ; SSE2: shift8i32c + ; SSE2: cost of 2 {{.*}} shl + ; SSE2-CODEGEN: shift8i32c + ; SSE2-CODEGEN: pslld $3 + + %0 = shl %shifttypec8i32 %a , <i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3> + ret %shifttypec8i32 %0 +} + +%shifttypec16i32 = type <16 x i32> +define %shifttypec16i32 @shift16i32c(%shifttypec16i32 %a, %shifttypec16i32 %b) { +entry: + ; SSE2: shift16i32c + ; SSE2: cost of 4 {{.*}} shl + ; SSE2-CODEGEN: shift16i32c + ; SSE2-CODEGEN: pslld $3 + + %0 = shl %shifttypec16i32 %a , <i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3> + ret %shifttypec16i32 %0 +} + +%shifttypec32i32 = type <32 x i32> +define %shifttypec32i32 @shift32i32c(%shifttypec32i32 %a, %shifttypec32i32 %b) { +entry: + ; SSE2: shift32i32c + ; getTypeConversion fails here and promotes this to a i64. + ; SSE2: cost of 256 {{.*}} shl + ; SSE2-CODEGEN: shift32i32c + ; SSE2-CODEGEN: pslld $3 + %0 = shl %shifttypec32i32 %a , <i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3, + i32 3, i32 3, i32 3, i32 3> + ret %shifttypec32i32 %0 +} + +%shifttypec2i64 = type <2 x i64> +define %shifttypec2i64 @shift2i64c(%shifttypec2i64 %a, %shifttypec2i64 %b) { +entry: + ; SSE2: shift2i64c + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift2i64c + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec2i64 %a , <i64 3, i64 3> + ret %shifttypec2i64 %0 +} + +%shifttypec4i64 = type <4 x i64> +define %shifttypec4i64 @shift4i64c(%shifttypec4i64 %a, %shifttypec4i64 %b) { +entry: + ; SSE2: shift4i64c + ; SSE2: cost of 2 {{.*}} shl + ; SSE2-CODEGEN: shift4i64c + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec4i64 %a , <i64 3, i64 3, i64 3, i64 3> + ret %shifttypec4i64 %0 +} + +%shifttypec8i64 = type <8 x i64> +define %shifttypec8i64 @shift8i64c(%shifttypec8i64 %a, %shifttypec8i64 %b) { +entry: + ; SSE2: shift8i64c + ; SSE2: cost of 4 {{.*}} shl + ; SSE2-CODEGEN: shift8i64c + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec8i64 %a , <i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3> + ret %shifttypec8i64 %0 +} + +%shifttypec16i64 = type <16 x i64> +define %shifttypec16i64 @shift16i64c(%shifttypec16i64 %a, %shifttypec16i64 %b) { +entry: + ; SSE2: shift16i64c + ; SSE2: cost of 8 {{.*}} shl + ; SSE2-CODEGEN: shift16i64c + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec16i64 %a , <i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3> + ret %shifttypec16i64 %0 +} + +%shifttypec32i64 = type <32 x i64> +define %shifttypec32i64 @shift32i64c(%shifttypec32i64 %a, %shifttypec32i64 %b) { +entry: + ; SSE2: shift32i64c + ; SSE2: cost of 256 {{.*}} shl + ; SSE2-CODEGEN: shift32i64c + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec32i64 %a ,<i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3, + i64 3, i64 3, i64 3, i64 3> + ret %shifttypec32i64 %0 +} + +%shifttypec2i8 = type <2 x i8> +define %shifttypec2i8 @shift2i8c(%shifttypec2i8 %a, %shifttypec2i8 %b) { +entry: + ; SSE2: shift2i8c + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift2i8c + ; SSE2-CODEGEN: psllq $3 + + %0 = shl %shifttypec2i8 %a , <i8 3, i8 3> + ret %shifttypec2i8 %0 +} + +%shifttypec4i8 = type <4 x i8> +define %shifttypec4i8 @shift4i8c(%shifttypec4i8 %a, %shifttypec4i8 %b) { +entry: + ; SSE2: shift4i8c + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift4i8c + ; SSE2-CODEGEN: pslld $3 + + %0 = shl %shifttypec4i8 %a , <i8 3, i8 3, i8 3, i8 3> + ret %shifttypec4i8 %0 +} + +%shifttypec8i8 = type <8 x i8> +define %shifttypec8i8 @shift8i8c(%shifttypec8i8 %a, %shifttypec8i8 %b) { +entry: + ; SSE2: shift8i8c + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift8i8c + ; SSE2-CODEGEN: psllw $3 + + %0 = shl %shifttypec8i8 %a , <i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3> + ret %shifttypec8i8 %0 +} + +%shifttypec16i8 = type <16 x i8> +define %shifttypec16i8 @shift16i8c(%shifttypec16i8 %a, %shifttypec16i8 %b) { +entry: + ; SSE2: shift16i8c + ; SSE2: cost of 1 {{.*}} shl + ; SSE2-CODEGEN: shift16i8c + ; SSE2-CODEGEN: psllw $3 + + %0 = shl %shifttypec16i8 %a , <i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3> + ret %shifttypec16i8 %0 +} + +%shifttypec32i8 = type <32 x i8> +define %shifttypec32i8 @shift32i8c(%shifttypec32i8 %a, %shifttypec32i8 %b) { +entry: + ; SSE2: shift32i8c + ; SSE2: cost of 2 {{.*}} shl + ; SSE2-CODEGEN: shift32i8c + ; SSE2-CODEGEN: psllw $3 + + %0 = shl %shifttypec32i8 %a , <i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3, + i8 3, i8 3, i8 3, i8 3> + ret %shifttypec32i8 %0 +} diff --git a/test/Analysis/CostModel/X86/tiny.ll b/test/Analysis/CostModel/X86/tiny.ll index cc7b443a7dfc8..0dafdadb5b159 100644 --- a/test/Analysis/CostModel/X86/tiny.ll +++ b/test/Analysis/CostModel/X86/tiny.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-macosx10.8.0" ;CHECK: cost of 1 {{.*}} add -;CHECK: cost of 1 {{.*}} ret +;CHECK: cost of 0 {{.*}} ret define i32 @no_info(i32 %arg) { %e = add i32 %arg, %arg ret i32 %e diff --git a/test/Analysis/CostModel/X86/vectorized-loop.ll b/test/Analysis/CostModel/X86/vectorized-loop.ll index 7919a9ca9a64f..25b11145c661e 100644 --- a/test/Analysis/CostModel/X86/vectorized-loop.ll +++ b/test/Analysis/CostModel/X86/vectorized-loop.ll @@ -28,20 +28,21 @@ vector.body: ; preds = %for.body.lr.ph, %ve %4 = getelementptr inbounds i32* %B, i64 %3 ;CHECK: cost of 0 {{.*}} bitcast %5 = bitcast i32* %4 to <8 x i32>* - ;CHECK: cost of 1 {{.*}} load + ;CHECK: cost of 2 {{.*}} load %6 = load <8 x i32>* %5, align 4 ;CHECK: cost of 4 {{.*}} mul %7 = mul nsw <8 x i32> %6, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5> %8 = getelementptr inbounds i32* %A, i64 %index %9 = bitcast i32* %8 to <8 x i32>* + ;CHECK: cost of 2 {{.*}} load %10 = load <8 x i32>* %9, align 4 ;CHECK: cost of 4 {{.*}} add %11 = add nsw <8 x i32> %10, %7 - ;CHECK: cost of 1 {{.*}} store + ;CHECK: cost of 2 {{.*}} store store <8 x i32> %11, <8 x i32>* %9, align 4 %index.next = add i64 %index, 8 %12 = icmp eq i64 %index.next, %end.idx.rnd.down - ;CHECK: cost of 1 {{.*}} br + ;CHECK: cost of 0 {{.*}} br br i1 %12, label %middle.block, label %vector.body middle.block: ; preds = %vector.body, %for.body.lr.ph @@ -65,11 +66,11 @@ for.body: ; preds = %middle.block, %for. ;CHECK: cost of 0 {{.*}} trunc %16 = trunc i64 %indvars.iv.next to i32 %cmp = icmp slt i32 %16, %end - ;CHECK: cost of 1 {{.*}} br + ;CHECK: cost of 0 {{.*}} br br i1 %cmp, label %for.body, label %for.end for.end: ; preds = %middle.block, %for.body, %entry - ;CHECK: cost of 1 {{.*}} ret + ;CHECK: cost of 0 {{.*}} ret ret i32 undef } diff --git a/test/Analysis/CostModel/no_info.ll b/test/Analysis/CostModel/no_info.ll index d20d56b79a7f0..f3f165b1b52ae 100644 --- a/test/Analysis/CostModel/no_info.ll +++ b/test/Analysis/CostModel/no_info.ll @@ -1,11 +1,8 @@ ; RUN: opt < %s -cost-model -analyze | FileCheck %s ; The cost model does not have any target information so it can't make a decision. -; Notice that OPT does not read the triple information from the module itself, only through the command line. -; This info ignored: -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -target triple = "x86_64-apple-macosx10.8.0" +; -- No triple in this module -- ;CHECK: Unknown cost {{.*}} add ;CHECK: Unknown cost {{.*}} ret |