diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-12-18 20:10:56 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-12-18 20:10:56 +0000 |
| commit | 044eb2f6afba375a914ac9d8024f8f5142bb912e (patch) | |
| tree | 1475247dc9f9fe5be155ebd4c9069c75aadf8c20 /test/CodeGen/PowerPC | |
| parent | eb70dddbd77e120e5d490bd8fbe7ff3f8fa81c6b (diff) | |
Notes
Diffstat (limited to 'test/CodeGen/PowerPC')
438 files changed, 20815 insertions, 3086 deletions
diff --git a/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll b/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll index 7e21b511a9408..6699b74d58aef 100644 --- a/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll +++ b/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- define void @test() { %tr1 = lshr i32 1, 0 ; <i32> [#uses=0] ret void diff --git a/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll b/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll index ca096ca691776..4294ad33d469e 100644 --- a/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll +++ b/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- define void @main() { %tr4 = shl i64 1, 0 ; <i64> [#uses=0] diff --git a/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll b/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll index d2674f8f8c31c..1077283470aca 100644 --- a/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll +++ b/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- define void @main() { %shamt = add i8 0, 1 ; <i8> [#uses=1] diff --git a/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll b/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll index 687f426f12b83..a524fffccf9eb 100644 --- a/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll +++ b/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep .comm.*X,0 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep .comm.*X,0 @X = linkonce global { } zeroinitializer ; <{ }*> [#uses=0] diff --git a/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll b/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll index 63f1f147c8b91..49491cd30b09b 100644 --- a/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll +++ b/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- define i32 @main() { %setle = icmp sle i64 1, 0 ; <i1> [#uses=1] diff --git a/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll b/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll index b7037a3558504..39824caaa12f2 100644 --- a/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll +++ b/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- define i64 @test() { ret i64 undef diff --git a/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll b/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll index 2de58b30a1a62..3407af3ff6653 100644 --- a/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll +++ b/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll @@ -1,6 +1,6 @@ ; this should not crash the ppc backend -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- define i32 @test(i32 %j.0.0.i) { diff --git a/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll b/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll index 4f36d57a24762..c0396c979117d 100644 --- a/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll +++ b/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll @@ -1,6 +1,6 @@ ; This function should have exactly one call to fixdfdi, no more! -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mattr=-64bit | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mattr=-64bit | \ ; RUN: grep "bl .*fixdfdi" | count 1 define double @test2(double %tmp.7705) { diff --git a/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll b/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll index b5c1f5cb91e97..43279e54d513d 100644 --- a/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll +++ b/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll @@ -1,7 +1,7 @@ ; This was erroneously being turned into an rlwinm instruction. ; The sign bit does matter in this case. -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep srawi +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep srawi define i32 @test(i32 %X) { %Y = and i32 %X, -2 ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll b/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll index 4d7d36698c59f..8f1a7610f10ea 100644 --- a/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll +++ b/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- define double @CalcSpeed(float %tmp127) { diff --git a/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll b/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll index 71acb7bc980a7..dfd6fab707750 100644 --- a/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll +++ b/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \ ; RUN: grep "vspltish v.*, 10" define void @test(<8 x i16>* %P) { diff --git a/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll b/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll index 4fac0864c8d26..7de5e9ddaede9 100644 --- a/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll +++ b/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 ; END. define void @test(i8* %stack) { diff --git a/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll b/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll index bce581a124f5d..98f9ee86684a7 100644 --- a/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll +++ b/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- ; END. %struct.attr_desc = type { i8*, %struct.attr_desc*, %struct.attr_value*, %struct.attr_value*, i32 } diff --git a/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll index 56f4a4173ef59..5b8b8147cce2a 100644 --- a/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll +++ b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll @@ -6,7 +6,7 @@ define i32 @test(i32 %i) { ; CHECK-LABEL: test: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: addis 4, 2, .LC0@toc@ha ; CHECK-NEXT: extsw 3, 3 ; CHECK-NEXT: addis 5, 2, .LC1@toc@ha diff --git a/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll b/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll index 3f07df2b4323d..2b0d639b168fd 100644 --- a/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll +++ b/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- define void @img2buf(i32 %symbol_size_in_bytes, i16* %ui16) nounwind { %tmp93 = load i16, i16* null ; <i16> [#uses=1] diff --git a/test/CodeGen/PowerPC/2006-08-11-RetVector.ll b/test/CodeGen/PowerPC/2006-08-11-RetVector.ll index d2f12d766e187..4f592109e706b 100644 --- a/test/CodeGen/PowerPC/2006-08-11-RetVector.ll +++ b/test/CodeGen/PowerPC/2006-08-11-RetVector.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | grep vsldoi -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | not grep vor +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | grep vsldoi +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | not grep vor define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) { %tmp76 = shufflevector <4 x float> %fp0, <4 x float> %fp1, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/PowerPC/2006-09-28-shift_64.ll b/test/CodeGen/PowerPC/2006-09-28-shift_64.ll index 2ef5f8397ea86..d519f023c6a9d 100644 --- a/test/CodeGen/PowerPC/2006-09-28-shift_64.ll +++ b/test/CodeGen/PowerPC/2006-09-28-shift_64.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 +; RUN: llc -verify-machineinstrs < %s target datalayout = "E-p:64:64" target triple = "powerpc64-apple-darwin8" diff --git a/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll b/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll index 4109f0bc6fe5a..2a3e00f6b9d0e 100644 --- a/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll +++ b/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep IMPLICIT_DEF +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep IMPLICIT_DEF define void @foo(i64 %X) { entry: diff --git a/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll b/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll index e29f5e30cd653..59cd9625a0f50 100644 --- a/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll +++ b/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep xor +; RUN: llc -verify-machineinstrs < %s | grep xor target datalayout = "E-p:32:32" target triple = "powerpc-apple-darwin8.7.0" diff --git a/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll b/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll index 3284f0a624f67..3024e70c2f46e 100644 --- a/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll +++ b/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc64 +; RUN: llc < %s -mtriple=ppc64-- define i32* @foo(i32 %n) { %A = alloca i32, i32 %n ; <i32*> [#uses=1] diff --git a/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll b/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll index cf381643df99a..aa58a49b77b86 100644 --- a/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll +++ b/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep rlwimi +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rlwimi define void @test(i16 %div.0.i.i.i.i, i32 %L_num.0.i.i.i.i, i32 %tmp1.i.i206.i.i, i16* %P) { %X = shl i16 %div.0.i.i.i.i, 1 ; <i16> [#uses=1] diff --git a/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll b/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll index 8aa950680903b..624ce11f4bd1a 100644 --- a/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll +++ b/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 define void @glgRunProcessor15() { %tmp26355.i = shufflevector <4 x float> zeroinitializer, <4 x float> < float 0x379FFFE000000000, float 0x379FFFE000000000, float 0x379FFFE000000000, float 0x379FFFE000000000 >, <4 x i32> < i32 0, i32 1, i32 2, i32 7 >; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll index 147680744c2f2..cb90b3ebabdf5 100644 --- a/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll +++ b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -; RUN: llc -verify-machineinstrs < %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- +; RUN: llc -verify-machineinstrs < %s ; REQUIRES: default_triple define void @bitap() { diff --git a/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll b/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll index ac633dafd480a..4d18d9bb6b069 100644 --- a/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll +++ b/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- ; RUN: llc -verify-machineinstrs < %s ; REQUIRES: default_triple diff --git a/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll b/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll index 9e979bcd5dbd6..7b9aae58f555d 100644 --- a/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll +++ b/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep extsb -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep extsh +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep extsb +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep extsh define i32 @p1(i8 %c, i16 %s) { entry: diff --git a/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll b/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll index c6547c72ff030..2f0f7c2888e28 100644 --- a/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll +++ b/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 | \ ; RUN: grep cntlz define i32 @foo() nounwind { diff --git a/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll b/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll index faf05e98acb95..934b04b7de7a1 100644 --- a/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll +++ b/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -; RUN: llc -verify-machineinstrs < %s -march=ppc64 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- define i16 @test(i8* %d1, i16* %d2) { %tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 ) ; <i16> [#uses=1] diff --git a/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll b/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll index d0e6f5dfd1551..e063e25f61142 100644 --- a/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll +++ b/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -; RUN: llc -verify-machineinstrs < %s -march=ppc64 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- ; Test two things: 1) that a frameidx can be rewritten in an inline asm ; 2) that inline asms can handle reg+imm addr modes. diff --git a/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll b/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll index d04aef8e5ff87..6805cc59dfebd 100644 --- a/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll +++ b/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8.8.0 | \ ; RUN: grep align.*3 @X = global <{i32, i32}> <{ i32 1, i32 123 }> diff --git a/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll b/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll index 717e9c7a59184..7ed13631db729 100644 --- a/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll +++ b/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 define void @test(<4 x float>*, { { i16, i16, i32 } }*) { xOperationInitMasks.exit: diff --git a/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll b/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll index 14da52136c935..ad34477384a19 100644 --- a/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll +++ b/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 -no-integrated-as | grep "foo r3, r4" -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 -no-integrated-as | grep "bari r3, 47" +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8.8.0 -no-integrated-as | grep "foo r3, r4" +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8.8.0 -no-integrated-as | grep "bari r3, 47" ; PR1351 diff --git a/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll b/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll index 3e39bf0b6aa4a..db024772eb4d6 100644 --- a/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll +++ b/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" target triple = "powerpc-apple-darwin8.8.0" %struct..0anon = type { i32 } diff --git a/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll b/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll index 02ace31fdd430..a3ee0247f5211 100644 --- a/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll +++ b/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -enable-tail-merge=0 | grep bl.*baz | count 2 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -enable-tail-merge=0 | grep bl.*quux | count 2 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep bl.*baz | count 1 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep bl.*quux | count 1 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -enable-tail-merge=0 | grep bl.*baz | count 2 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -enable-tail-merge=0 | grep bl.*quux | count 2 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep bl.*baz | count 1 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep bl.*quux | count 1 ; Check that tail merging is the default on ppc, and that -enable-tail-merge works. ; ModuleID = 'tail.c' diff --git a/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll b/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll index a5e17c62e084b..1f8f5eb894681 100644 --- a/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll +++ b/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll @@ -1,9 +1,8 @@ +; RUN: llc -verify-machineinstrs < %s | grep "rlwinm r3, r3, 23, 30, 30" +; PR1473 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" target triple = "powerpc-apple-darwin8.8.0" -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep "rlwinm r3, r3, 23, 30, 30" -; PR1473 - define zeroext i8 @foo(i16 zeroext %a) { %tmp2 = lshr i16 %a, 10 ; <i16> [#uses=1] %tmp23 = trunc i16 %tmp2 to i8 ; <i8> [#uses=1] diff --git a/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll b/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll index 743cddf584e12..b039cf05a9da6 100644 --- a/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll +++ b/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mattr=+altivec +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mattr=+altivec %struct.XATest = type { float, i16, i8, i8 } %struct.XArrayRange = type { i8, i8, i8, i8 } diff --git a/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll b/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll index d92337bfd283a..0db79f23ddd3f 100644 --- a/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll +++ b/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- ; PR1596 %struct._obstack_chunk = type { i8* } diff --git a/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll b/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll index 0dcb45dff47ac..25f069957f420 100644 --- a/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll +++ b/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mattr=+altivec | grep dst | count 4 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mattr=+altivec | grep dst | count 4 define hidden void @_Z4borkPc(i8* %image) { entry: diff --git a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll index 3769ab4487171..89b7b6f188120 100644 --- a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll +++ b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -O1 | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | FileCheck --check-prefix=CHECK-OPT %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -O1 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- | FileCheck --check-prefix=CHECK-OPT %s %struct.__db_region = type { %struct.__mutex_t, [4 x i8], %struct.anon, i32, [1 x i32] } %struct.__mutex_t = type { i32 } diff --git a/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll b/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll index 4f38e7f3c7ca4..53552323b72ca 100644 --- a/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll +++ b/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- %struct.TCMalloc_SpinLock = type { i32 } diff --git a/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll b/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll index b7a3c3090c2c4..a69e145f3adf0 100644 --- a/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll +++ b/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- ; rdar://5538377 %struct.disk_unsigned = type { i32 } diff --git a/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll b/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll index d8d1d8b112a85..d54f1a39f89f0 100644 --- a/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll +++ b/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mattr=+altivec +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mattr=+altivec %struct.inoutprops = type <{ i8, [3 x i8] }> define void @bork(float* %argA, float* %argB, float* %res, i8 %inoutspec.0) { diff --git a/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll index 68d94eb503e51..d2e303be03cdd 100644 --- a/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll +++ b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs < %s -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g3 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 +; RUN: llc -verify-machineinstrs < %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g3 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 ; PR1811 ; REQUIRES: default_triple diff --git a/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll b/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll index 3d771fc494773..81aae48de18f8 100644 --- a/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll +++ b/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- %struct._cpp_strbuf = type { i8*, i32, i32 } %struct.cpp_string = type { i32, i8* } diff --git a/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll b/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll index af848ee22353a..186c8db367367 100644 --- a/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll +++ b/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- define i16 @test(i8* %d1, i16* %d2) { %tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 ) diff --git a/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll b/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll index aa550984033ab..7f9d172512500 100644 --- a/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll +++ b/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- define fastcc i8* @page_rec_get_next(i8* %rec) nounwind { entry: diff --git a/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll index 8e30f1f5dfabd..8d75093437cb2 100644 --- a/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll +++ b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- %struct..0objc_object = type { %struct.objc_class* } %struct.NSArray = type { %struct..0objc_object } diff --git a/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll b/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll index 960d07df03467..f6185ca6e7956 100644 --- a/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll +++ b/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s target triple = "powerpc-apple-darwin9.2.2" define i256 @func(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind readnone { diff --git a/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll b/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll index ea54895f238c3..9f2a9ee63b331 100644 --- a/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll +++ b/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- define void @t() nounwind { call void null( ppc_fp128 undef ) diff --git a/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll b/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll index fb3af168f0b58..1114b8942f28c 100644 --- a/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll +++ b/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- @g = external global ppc_fp128 @h = external global ppc_fp128 diff --git a/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll b/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll index d57c6498c3958..3a5cb89928d0a 100644 --- a/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll +++ b/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- ; <rdar://problem/6020042> define i32 @bork() nounwind { diff --git a/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll b/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll index 45a5ccda8753c..13bccc0dfbc83 100644 --- a/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll +++ b/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | grep vadduhm -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | grep vsubuhm +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | grep vadduhm +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | grep vsubuhm define <4 x i32> @test() nounwind { ret <4 x i32> < i32 4293066722, i32 4293066722, i32 4293066722, i32 4293066722> diff --git a/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll b/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll index 15a806a470722..3174a7130f002 100644 --- a/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll +++ b/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- define void @__divtc3({ ppc_fp128, ppc_fp128 }* noalias sret %agg.result, ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind { entry: diff --git a/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll b/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll index 55272c9de4e6d..3fa9d81c8dc50 100644 --- a/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll +++ b/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -o - | not grep fixunstfsi +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o - | not grep fixunstfsi define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone { entry: diff --git a/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll b/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll index f64e3dcf73282..76468f63ee741 100644 --- a/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll +++ b/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 -verify-machineinstrs +; RUN: llc < %s -mtriple=ppc32-- -verify-machineinstrs ; Machine code verifier will call isRegTiedToDefOperand() on /all/ register use ; operands. We must make sure that the operand flag is found correctly. @@ -8,7 +8,7 @@ define void @memory_asm_operand(i32 %a) { ; "m" operand will be represented as: - ; INLINEASM <es:fake $0>, 10, %R2, 20, -4, %R1 + ; INLINEASM fake $0, 10, %R2, 20, -4, %R1 ; It is difficult to find the flag operand (20) when starting from %R1 call i32 asm "lbzx $0, $1", "=r,m" (i32 %a) ret void diff --git a/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll b/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll index f55dfa948dccc..b0da553e0c428 100644 --- a/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll +++ b/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin10 -mcpu=g5 -disable-ppc-ilp-pref | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mcpu=g5 -disable-ppc-ilp-pref | FileCheck %s ; ModuleID = '<stdin>' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin10.0" diff --git a/test/CodeGen/PowerPC/2009-09-18-carrybit.ll b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll index b1b18950249e1..4d77ccd2cc807 100644 --- a/test/CodeGen/PowerPC/2009-09-18-carrybit.ll +++ b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -march=ppc32 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; ModuleID = '<stdin>' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin9.6" diff --git a/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll b/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll index d6a14e0348a8c..51bf3fee73359 100644 --- a/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll +++ b/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 -mtriple=powerpc-apple-darwin10.0 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mcpu=g5 -mtriple=powerpc-apple-darwin10.0 | FileCheck %s ; ModuleID = 'nn.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin11.0" diff --git a/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll b/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll index 0d3ec04e6621a..ab194196c6bab 100644 --- a/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll +++ b/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 -regalloc=basic | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin -mcpu=g5 -regalloc=basic | FileCheck %s declare i8* @llvm.frameaddress(i32) nounwind readnone diff --git a/test/CodeGen/PowerPC/2016-04-28-setjmp.ll b/test/CodeGen/PowerPC/2016-04-28-setjmp.ll index 09c0fa7ba972a..7f368f1fb6a8e 100644 --- a/test/CodeGen/PowerPC/2016-04-28-setjmp.ll +++ b/test/CodeGen/PowerPC/2016-04-28-setjmp.ll @@ -8,7 +8,7 @@ target triple = "powerpc64le-unknown-linux-gnu" ; EH_SjLj_Setup. ; CHECK: li 3, 1 -; CHECK-NEXT: b .+4 +; CHECK-NEXT: cmplwi 3, 0 define void @h() nounwind { %1 = load i8**, i8*** bitcast (i8** @ptr to i8***), align 8 diff --git a/test/CodeGen/PowerPC/Atomics-64.ll b/test/CodeGen/PowerPC/Atomics-64.ll index 77066de25e785..0422e4975d84e 100644 --- a/test/CodeGen/PowerPC/Atomics-64.ll +++ b/test/CodeGen/PowerPC/Atomics-64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc64 -verify-machineinstrs +; RUN: llc < %s -verify-machineinstrs ; ; This test is disabled until PPCISelLowering learns to insert proper 64-bit ; code for ATOMIC_CMP_SWAP. Currently, it is inserting 32-bit instructions with diff --git a/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll b/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll new file mode 100644 index 0000000000000..75cac9030ef89 --- /dev/null +++ b/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll @@ -0,0 +1,56 @@ +; The purpose of the test case is to ensure that a spill that happens during +; intermediate calculations for a comparison performed in a GPR spills the +; full register. Some i32 comparisons performed in GPRs use code that uses +; the full 64-bits of the register in intermediate stages. Spilling such a value +; as a 32-bit value is incorrect. +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +@glob = common local_unnamed_addr global i64 0, align 8 +@.str = private unnamed_addr constant [12 x i8] c"Value = %d\0A\00", align 1 + +; Function Attrs: noinline nounwind +define void @call(i64 %a) local_unnamed_addr #0 { +entry: + store i64 %a, i64* @glob, align 8 + tail call void asm sideeffect "#Do Nothing", "~{memory}"() + ret void +} + +; Function Attrs: noinline nounwind +define signext i32 @test(i32 signext %a, i32 signext %b, i32 signext %c) local_unnamed_addr #0 { +entry: + %add = add nsw i32 %b, %a + %sub = sub nsw i32 %add, %c + %conv = sext i32 %sub to i64 + tail call void @call(i64 %conv) + tail call void asm sideeffect "#Do Nothing", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() + %cmp = icmp sle i32 %add, %c + %conv1 = zext i1 %cmp to i32 + ret i32 %conv1 +; CHECK-LABEL: test +; CHECK: subf r3, +; CHECK: extsw r3, +; CHECK: bl call +; CHECK: sub r3, +; CHECK: rldicl r3, r3, 1, 63 +; CHECK: std r3, [[OFF:[0-9]+]](r1) +; CHECK: #APP +; CHECK: ld r3, [[OFF]](r1) +; CHECK: xori r3, r3, 1 +; CHECK: blr +} + +; Function Attrs: nounwind +define signext i32 @main() local_unnamed_addr #1 { +entry: + %call = tail call signext i32 @test(i32 signext 10, i32 signext -15, i32 signext 0) + %call1 = tail call signext i32 (i8*, ...) @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i64 0, i64 0), i32 signext %call) + ret i32 0 +} + +; Function Attrs: nounwind +declare signext i32 @printf(i8* nocapture readonly, ...) local_unnamed_addr #2 diff --git a/test/CodeGen/PowerPC/DbgValueOtherTargets.test b/test/CodeGen/PowerPC/DbgValueOtherTargets.test index 9702934f7e685..be0c1d076ef94 100644 --- a/test/CodeGen/PowerPC/DbgValueOtherTargets.test +++ b/test/CodeGen/PowerPC/DbgValueOtherTargets.test @@ -1 +1 @@ -RUN: llc -O0 -march=ppc32 -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll +RUN: llc -O0 -mtriple=ppc32-- -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/test/CodeGen/PowerPC/Frames-alloca.ll b/test/CodeGen/PowerPC/Frames-alloca.ll index c701fef8e629b..ffafa9dc2c6ff 100644 --- a/test/CodeGen/PowerPC/Frames-alloca.ll +++ b/test/CodeGen/PowerPC/Frames-alloca.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=CHECK-PPC32 -; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=CHECK-PPC64 -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=CHECK-PPC32-NOFP -; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=CHECK-PPC64-NOFP -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=CHECK-PPC32 -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=CHECK-PPC32-RS -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=CHECK-PPC32-RS-NOFP +; RUN: llc < %s -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=CHECK-PPC32 +; RUN: llc < %s -mtriple=powerpc64-apple-darwin8 | FileCheck %s -check-prefix=CHECK-PPC64 +; RUN: llc < %s -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=CHECK-PPC32-NOFP +; RUN: llc < %s -mtriple=powerpc64-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=CHECK-PPC64-NOFP +; RUN: llc < %s -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=CHECK-PPC32 +; RUN: llc < %s -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=CHECK-PPC32-RS +; RUN: llc < %s -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=CHECK-PPC32-RS-NOFP ; CHECK-PPC32: stw r31, -4(r1) ; CHECK-PPC32: lwz r1, 0(r1) diff --git a/test/CodeGen/PowerPC/Frames-large.ll b/test/CodeGen/PowerPC/Frames-large.ll index 5efbe5c2a3fb3..7ffc7afb149bf 100644 --- a/test/CodeGen/PowerPC/Frames-large.ll +++ b/test/CodeGen/PowerPC/Frames-large.ll @@ -1,11 +1,8 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | FileCheck %s -check-prefix=PPC32-NOFP -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-FP +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32-NOFP +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-FP -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | FileCheck %s -check-prefix=PPC64-NOFP -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-FP - - -target triple = "powerpc-apple-darwin8" +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin8 | FileCheck %s -check-prefix=PPC64-NOFP +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-FP define i32* @f1() nounwind { %tmp = alloca i32, i32 8191 ; <i32*> [#uses=1] diff --git a/test/CodeGen/PowerPC/Frames-leaf.ll b/test/CodeGen/PowerPC/Frames-leaf.ll index b6ee2fe96864e..6dce8e20bebe6 100644 --- a/test/CodeGen/PowerPC/Frames-leaf.ll +++ b/test/CodeGen/PowerPC/Frames-leaf.ll @@ -1,34 +1,34 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: not grep "stw r31, 20(r1)" -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: not grep "stwu r1, -.*(r1)" -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: not grep "addi r1, r1, " -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: not grep "lwz r31, 20(r1)" -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -disable-fp-elim | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -disable-fp-elim | \ ; RUN: not grep "stw r31, 20(r1)" -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -disable-fp-elim | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -disable-fp-elim | \ ; RUN: not grep "stwu r1, -.*(r1)" -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -disable-fp-elim | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -disable-fp-elim | \ ; RUN: not grep "addi r1, r1, " -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -disable-fp-elim | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -disable-fp-elim | \ ; RUN: not grep "lwz r31, 20(r1)" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- | \ ; RUN: not grep "std r31, 40(r1)" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- | \ ; RUN: not grep "stdu r1, -.*(r1)" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- | \ ; RUN: not grep "addi r1, r1, " -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- | \ ; RUN: not grep "ld r31, 40(r1)" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -disable-fp-elim | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -disable-fp-elim | \ ; RUN: not grep "stw r31, 40(r1)" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -disable-fp-elim | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -disable-fp-elim | \ ; RUN: not grep "stdu r1, -.*(r1)" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -disable-fp-elim | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -disable-fp-elim | \ ; RUN: not grep "addi r1, r1, " -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -disable-fp-elim | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -disable-fp-elim | \ ; RUN: not grep "ld r31, 40(r1)" define i32* @f1() { diff --git a/test/CodeGen/PowerPC/Frames-small.ll b/test/CodeGen/PowerPC/Frames-small.ll index accf4256edc97..e17e982673d35 100644 --- a/test/CodeGen/PowerPC/Frames-small.ll +++ b/test/CodeGen/PowerPC/Frames-small.ll @@ -1,21 +1,21 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -o %t1 +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 -o %t1 ; RUN: not grep "stw r31, -4(r1)" %t1 ; RUN: grep "stwu r1, -16416(r1)" %t1 ; RUN: grep "addi r1, r1, 16416" %t1 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: not grep "lwz r31, -4(r1)" -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ ; RUN: -o %t2 ; RUN: grep "stw r31, -4(r1)" %t2 ; RUN: grep "stwu r1, -16416(r1)" %t2 ; RUN: grep "addi r1, r1, 16416" %t2 ; RUN: grep "lwz r31, -4(r1)" %t2 -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -o %t3 +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin8 -o %t3 ; RUN: not grep "std r31, -8(r1)" %t3 ; RUN: grep "stdu r1, -16432(r1)" %t3 ; RUN: grep "addi r1, r1, 16432" %t3 ; RUN: not grep "ld r31, -8(r1)" %t3 -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin8 -disable-fp-elim \ ; RUN: -o %t4 ; RUN: grep "std r31, -8(r1)" %t4 ; RUN: grep "stdu r1, -16448(r1)" %t4 diff --git a/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll b/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll index b26b4f420b329..3db09b2cae1fc 100644 --- a/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll +++ b/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll @@ -1,8 +1,8 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin | \ ; RUN: grep "stw r3, 32751" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-apple-darwin | \ ; RUN: grep "stw r3, 32751" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-apple-darwin | \ ; RUN: grep "std r3, 9024" define void @test() nounwind { diff --git a/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll b/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll new file mode 100644 index 0000000000000..c72523f35937b --- /dev/null +++ b/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll @@ -0,0 +1,63 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; The instructions addis,addi, bl are used to calculate the address of TLS +; thread local variables. These TLS access code sequences are generated +; repeatedly every time the thread local variable is accessed. By communicating +; to Machine CSE that X2 is guaranteed to have the same value within the same +; function call (so called Caller Preserved Physical Register), the redudant +; TLS access code sequences are cleaned up. + +%"struct.CC::TT" = type { i64, i32 } +%class.CC = type { %struct.SS } +%struct.SS = type { void ()* } + +@_ZN2CC2ccE = external thread_local global %"struct.CC::TT", align 8 + +define noalias i8* @_ZN2CC3funEv(%class.CC* %this) { +; CHECK-LABEL: _ZN2CC3funEv: +; CHECK: mflr 0 +; CHECK-NEXT: std 0, 16(1) +; CHECK-NEXT: stdu 1, -48(1) +; CHECK-NEXT: .cfi_def_cfa_offset 48 +; CHECK-NEXT: .cfi_offset lr, 16 +; CHECK-NEXT: .cfi_offset r30, -16 +; CHECK-NEXT: std 30, 32(1) +; CHECK-NEXT: mr 30, 3 +; CHECK-NEXT: ld 12, 0(30) +; CHECK-NEXT: std 2, 24(1) +; CHECK-NEXT: mtctr 12 +; CHECK-NEXT: bctrl +; CHECK-NEXT: ld 2, 24(1) +; CHECK-NEXT: addis 3, 2, _ZN2CC2ccE@got@tlsgd@ha +; CHECK-NEXT: addi 3, 3, _ZN2CC2ccE@got@tlsgd@l +; CHECK-NEXT: bl __tls_get_addr(_ZN2CC2ccE@tlsgd) +; CHECK-NEXT: nop +; CHECK-NEXT: ld 4, 0(3) +; CHECK-NEXT: cmpldi 4, 0 +; CHECK-NEXT: beq 0, .LBB0_2 +; CHECK: addi 4, 3, 8 +; CHECK-NEXT: mr 3, 30 +; CHECK-NEXT: bl _ZN2CC3barEPi +; CHECK-NEXT: nop +; CHECK: ld 30, 32(1) +; CHECK-NEXT: li 3, 0 +; CHECK-NEXT: addi 1, 1, 48 +; CHECK-NEXT: ld 0, 16(1) +; CHECK-NEXT: mtlr 0 +; CHECK-NEXT: blr +entry: + %foo = getelementptr inbounds %class.CC, %class.CC* %this, i64 0, i32 0, i32 0 + %0 = load void ()*, void ()** %foo, align 8 + tail call void %0() + %1 = load i64, i64* getelementptr inbounds (%"struct.CC::TT", %"struct.CC::TT"* @_ZN2CC2ccE, i64 0, i32 0) + %tobool = icmp eq i64 %1, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: + tail call void @_ZN2CC3barEPi(%class.CC* nonnull %this, i32* getelementptr inbounds (%"struct.CC::TT", %"struct.CC::TT"* @_ZN2CC2ccE, i64 0, i32 1)) + br label %if.end + +if.end: + ret i8* null +} + +declare void @_ZN2CC3barEPi(%class.CC*, i32*) diff --git a/test/CodeGen/PowerPC/MMO-flags-assertion.ll b/test/CodeGen/PowerPC/MMO-flags-assertion.ll new file mode 100644 index 0000000000000..ab9f76f460900 --- /dev/null +++ b/test/CodeGen/PowerPC/MMO-flags-assertion.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -mtriple powerpc64le-unknown-linux-gnu + +; void llvm::MachineMemOperand::refineAlignment(const llvm::MachineMemOperand*): +; Assertion `MMO->getFlags() == getFlags() && "Flags mismatch !"' failed. + +declare void @_Z3fn11F(%class.F* byval align 8) local_unnamed_addr +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) +declare signext i32 @_ZN1F11isGlobalRegEv(%class.F*) local_unnamed_addr +declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) +declare void @_Z10EmitLValuev(%class.F* sret) local_unnamed_addr +declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) + +%class.F = type { i32, i64, i8, [64 x i8], i8, i32* } + +define signext i32 @_Z29EmitOMPAtomicSimpleUpdateExpr1F(%class.F* byval align 8 %p1) local_unnamed_addr { +entry: + call void @_Z3fn11F(%class.F* byval nonnull align 8 %p1) + %call = call signext i32 @_ZN1F11isGlobalRegEv(%class.F* nonnull %p1) + ret i32 %call +} + +define void @_Z3fn2v() local_unnamed_addr { +entry: + %agg.tmp1 = alloca %class.F, align 8 + %XLValue = alloca %class.F, align 8 + %0 = bitcast %class.F* %XLValue to i8* + call void @llvm.lifetime.start.p0i8(i64 96, i8* nonnull %0) + call void @_Z10EmitLValuev(%class.F* nonnull sret %XLValue) + %1 = bitcast %class.F* %agg.tmp1 to i8* + call void @llvm.lifetime.start.p0i8(i64 96, i8* nonnull %1) + call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull %1, i8* nonnull %0, i64 96, i32 8, i1 false) + call void @_Z3fn11F(%class.F* byval nonnull align 8 %XLValue) + %call.i = call signext i32 @_ZN1F11isGlobalRegEv(%class.F* nonnull %agg.tmp1) + call void @llvm.lifetime.end.p0i8(i64 96, i8* nonnull %1) + call void @llvm.lifetime.end.p0i8(i64 96, i8* nonnull %0) + ret void +} diff --git a/test/CodeGen/PowerPC/MergeConsecutiveStores.ll b/test/CodeGen/PowerPC/MergeConsecutiveStores.ll index 79f88c16ccb1f..712eb971ca805 100644 --- a/test/CodeGen/PowerPC/MergeConsecutiveStores.ll +++ b/test/CodeGen/PowerPC/MergeConsecutiveStores.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -march=ppc32 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec < %s | FileCheck %s ;; This test ensures that MergeConsecutiveStores does not attempt to ;; merge stores or loads when doing so would result in unaligned diff --git a/test/CodeGen/PowerPC/PR3488.ll b/test/CodeGen/PowerPC/PR3488.ll new file mode 100644 index 0000000000000..69c375a149f36 --- /dev/null +++ b/test/CodeGen/PowerPC/PR3488.ll @@ -0,0 +1,121 @@ +; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \ +; RUN: -mcpu=pwr8 | FileCheck %s +module asm "\09.section \22___kcrctab+numa_node\22, \22a\22\09" +module asm "\09.weak\09__crc_numa_node\09" +module asm "\09.long\09__crc_numa_node\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+_numa_mem_\22, \22a\22\09" +module asm "\09.weak\09__crc__numa_mem_\09" +module asm "\09.long\09__crc__numa_mem_\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+node_states\22, \22a\22\09" +module asm "\09.weak\09__crc_node_states\09" +module asm "\09.long\09__crc_node_states\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+totalram_pages\22, \22a\22\09" +module asm "\09.weak\09__crc_totalram_pages\09" +module asm "\09.long\09__crc_totalram_pages\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+movable_zone\22, \22a\22\09" +module asm "\09.weak\09__crc_movable_zone\09" +module asm "\09.long\09__crc_movable_zone\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+nr_node_ids\22, \22a\22\09" +module asm "\09.weak\09__crc_nr_node_ids\09" +module asm "\09.long\09__crc_nr_node_ids\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+nr_online_nodes\22, \22a\22\09" +module asm "\09.weak\09__crc_nr_online_nodes\09" +module asm "\09.long\09__crc_nr_online_nodes\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab_gpl+split_page\22, \22a\22\09" +module asm "\09.weak\09__crc_split_page\09" +module asm "\09.long\09__crc_split_page\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+__alloc_pages_nodemask\22, \22a\22\09" +module asm "\09.weak\09__crc___alloc_pages_nodemask\09" +module asm "\09.long\09__crc___alloc_pages_nodemask\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+__get_free_pages\22, \22a\22\09" +module asm "\09.weak\09__crc___get_free_pages\09" +module asm "\09.long\09__crc___get_free_pages\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+get_zeroed_page\22, \22a\22\09" +module asm "\09.weak\09__crc_get_zeroed_page\09" +module asm "\09.long\09__crc_get_zeroed_page\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+__free_pages\22, \22a\22\09" +module asm "\09.weak\09__crc___free_pages\09" +module asm "\09.long\09__crc___free_pages\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+free_pages\22, \22a\22\09" +module asm "\09.weak\09__crc_free_pages\09" +module asm "\09.long\09__crc_free_pages\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+__page_frag_cache_drain\22, \22a\22\09" +module asm "\09.weak\09__crc___page_frag_cache_drain\09" +module asm "\09.long\09__crc___page_frag_cache_drain\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+page_frag_alloc\22, \22a\22\09" +module asm "\09.weak\09__crc_page_frag_alloc\09" +module asm "\09.long\09__crc_page_frag_alloc\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+page_frag_free\22, \22a\22\09" +module asm "\09.weak\09__crc_page_frag_free\09" +module asm "\09.long\09__crc_page_frag_free\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+alloc_pages_exact\22, \22a\22\09" +module asm "\09.weak\09__crc_alloc_pages_exact\09" +module asm "\09.long\09__crc_alloc_pages_exact\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+free_pages_exact\22, \22a\22\09" +module asm "\09.weak\09__crc_free_pages_exact\09" +module asm "\09.long\09__crc_free_pages_exact\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab_gpl+nr_free_buffer_pages\22, \22a\22\09" +module asm "\09.weak\09__crc_nr_free_buffer_pages\09" +module asm "\09.long\09__crc_nr_free_buffer_pages\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab_gpl+si_mem_available\22, \22a\22\09" +module asm "\09.weak\09__crc_si_mem_available\09" +module asm "\09.long\09__crc_si_mem_available\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+si_meminfo\22, \22a\22\09" +module asm "\09.weak\09__crc_si_meminfo\09" +module asm "\09.long\09__crc_si_meminfo\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+adjust_managed_page_count\22, \22a\22\09" +module asm "\09.weak\09__crc_adjust_managed_page_count\09" +module asm "\09.long\09__crc_adjust_managed_page_count\09" +module asm "\09.previous\09\09\09\09\09" +module asm "\09.section \22___kcrctab+free_reserved_area\22, \22a\22\09" +module asm "\09.weak\09__crc_free_reserved_area\09" +module asm "\09.long\09__crc_free_reserved_area\09" +module asm "\09.previous\09\09\09\09\09" + +@nr_cpu_ids = external local_unnamed_addr global i32, align 4 + +; Function Attrs: nounwind +define void @__alloc_pages_nodemask() #0 { +entry: + %0 = call i64 asm sideeffect "ld${1:U}${1:X} $0,$1", "=r,*m"(i64* undef) + br i1 undef, label %do.body.lr.ph.i.i.i, label %zone_page_state_snapshot.exit.i.i +; CHECK: ld 3, 0(3) + +do.body.lr.ph.i.i.i: ; preds = %entry + br label %do.body.i.i.i + +do.body.i.i.i: ; preds = %do.body.i.i.i, %do.body.lr.ph.i.i.i + %x.022.i.i.i = phi i64 [ %0, %do.body.lr.ph.i.i.i ], [ %add7.i.i.i, %do.body.i.i.i ] + %1 = load i8, i8* undef, align 1 + %conv.i.i458.i = sext i8 %1 to i64 + %add7.i.i.i = add i64 %x.022.i.i.i, %conv.i.i458.i + %2 = load i32, i32* @nr_cpu_ids, align 4 + %cmp.i1.i.i = icmp ult i32 0, %2 + br i1 %cmp.i1.i.i, label %do.body.i.i.i, label %zone_page_state_snapshot.exit.i.i + +zone_page_state_snapshot.exit.i.i: ; preds = %do.body.i.i.i, %entry + %x.0.lcssa.i.i.i = phi i64 [ %0, %entry ], [ %add7.i.i.i, %do.body.i.i.i ] + %3 = icmp sgt i64 %x.0.lcssa.i.i.i, 0 + unreachable +} diff --git a/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll b/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll new file mode 100644 index 0000000000000..e38c5beb80ebb --- /dev/null +++ b/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-P8 +; RUN: llc < %s -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-P9 + +@a = external local_unnamed_addr global <4 x i32>, align 16 +@pb = external local_unnamed_addr global float*, align 8 + +define void @testExpandPostRAPseudo(i32* nocapture readonly %ptr) { +; CHECK-P8-LABEL: testExpandPostRAPseudo: +; CHECK-P8: lxsiwax 34, 0, 3 +; CHECK-P8-NEXT: xxspltw 34, 34, 1 +; CHECK-P8-NEXT: stvx 2, 0, 4 +; CHECK-P8: #APP +; CHECK-P8-NEXT: #Clobber Rigisters +; CHECK-P8-NEXT: #NO_APP +; CHECK-P8-NEXT: lis 4, 1024 +; CHECK-P8-NEXT: lfiwax 0, 0, 3 +; CHECK-P8: stfsx 0, 3, 4 +; CHECK-P8-NEXT: blr + +; CHECK-P9-LABEL: testExpandPostRAPseudo: +; CHECK-P9: lxvwsx 0, 0, 3 +; CHECK-P9: stxvx 0, 0, 4 +; CHECK-P9: #APP +; CHECK-P9-NEXT: #Clobber Rigisters +; CHECK-P9-NEXT: #NO_APP +; CHECK-P9-NEXT: lis 4, 1024 +; CHECK-P9-NEXT: lfiwax 0, 0, 3 +; CHECK-P9: stfsx 0, 3, 4 +; CHECK-P9-NEXT: blr + +entry: + %0 = load i32, i32* %ptr, align 4 + %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 + %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + store <4 x i32> %splat.splat, <4 x i32>* @a, align 16 + tail call void asm sideeffect "#Clobber Rigisters", "~{f0},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() + %1 = load i32, i32* %ptr, align 4 + %conv = sitofp i32 %1 to float + %2 = load float*, float** @pb, align 8 + %add.ptr = getelementptr inbounds float, float* %2, i64 16777216 + store float %conv, float* %add.ptr, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/a2-fp-basic.ll b/test/CodeGen/PowerPC/a2-fp-basic.ll index 33929387747d7..e4a7c537d7440 100644 --- a/test/CodeGen/PowerPC/a2-fp-basic.ll +++ b/test/CodeGen/PowerPC/a2-fp-basic.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2 -fp-contract=fast | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=a2 -fp-contract=fast | FileCheck %s %0 = type { double, double } diff --git a/test/CodeGen/PowerPC/a2q-stackalign.ll b/test/CodeGen/PowerPC/a2q-stackalign.ll index f7517e0dc023c..17e3df6d58ccc 100644 --- a/test/CodeGen/PowerPC/a2q-stackalign.ll +++ b/test/CodeGen/PowerPC/a2q-stackalign.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2q | FileCheck -check-prefix=CHECK-A2Q %s -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mtriple=powerpc64-bgq-linux -mcpu=a2 | FileCheck -check-prefix=CHECK-BGQ %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=a2q | FileCheck -check-prefix=CHECK-A2Q %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-bgq-linux -mcpu=a2 | FileCheck -check-prefix=CHECK-BGQ %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/a2q.ll b/test/CodeGen/PowerPC/a2q.ll index b1a6ebe6efba5..84e2dfa991d78 100644 --- a/test/CodeGen/PowerPC/a2q.ll +++ b/test/CodeGen/PowerPC/a2q.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2q | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2 -mattr=+qpx | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=a2q | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=a2 -mattr=+qpx | FileCheck %s define void @foo() { entry: diff --git a/test/CodeGen/PowerPC/addegluecrash.ll b/test/CodeGen/PowerPC/addegluecrash.ll index 7605340d305f5..642960f84900c 100644 --- a/test/CodeGen/PowerPC/addegluecrash.ll +++ b/test/CodeGen/PowerPC/addegluecrash.ll @@ -5,7 +5,7 @@ target triple = "powerpc64le-unknown-linux-gnu" define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* nocapture readonly %b) { ; CHECK-LABEL: bn_mul_comba8: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: ld 6, 0(4) ; CHECK-NEXT: ld 7, 0(5) ; CHECK-NEXT: mulhdu 8, 7, 6 @@ -23,7 +23,7 @@ define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* n ; CHECK-NEXT: cmpld 7, 4, 5 ; CHECK-NEXT: mfocrf 10, 1 ; CHECK-NEXT: rlwinm 10, 10, 29, 31, 31 -; CHECK-NEXT: # implicit-def: %X4 +; CHECK-NEXT: # implicit-def: %x4 ; CHECK-NEXT: mr 4, 10 ; CHECK-NEXT: clrldi 4, 4, 32 ; CHECK-NEXT: std 4, 0(3) diff --git a/test/CodeGen/PowerPC/addi-reassoc.ll b/test/CodeGen/PowerPC/addi-reassoc.ll index 637c59e223e05..cb3cf7ca151e0 100644 --- a/test/CodeGen/PowerPC/addi-reassoc.ll +++ b/test/CodeGen/PowerPC/addi-reassoc.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep addi +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep addi %struct.X = type { [5 x i8] } diff --git a/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll b/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll index deacbd6a00fad..c5651562f8537 100644 --- a/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll +++ b/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll @@ -10,7 +10,7 @@ entry: lnext: %elementArray = load i32*, i32** %elementArrayPtr, align 8 ; CHECK: lwz [[LDREG:[0-9]+]], 124(1) # 4-byte Folded Reload -; CHECK: # implicit-def: %X[[TEMPREG:[0-9]+]] +; CHECK: # implicit-def: %x[[TEMPREG:[0-9]+]] %element = load i32, i32* %elementArray, align 4 ; CHECK: mr [[TEMPREG]], [[LDREG]] ; CHECK: clrldi 4, [[TEMPREG]], 32 diff --git a/test/CodeGen/PowerPC/and-branch.ll b/test/CodeGen/PowerPC/and-branch.ll index 7c36deed03d10..f69150abf670b 100644 --- a/test/CodeGen/PowerPC/and-branch.ll +++ b/test/CodeGen/PowerPC/and-branch.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep mfcr +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep mfcr define void @foo(i32 %X, i32 %Y, i32 %Z) { entry: diff --git a/test/CodeGen/PowerPC/and-elim.ll b/test/CodeGen/PowerPC/and-elim.ll index 1706b3ca92c38..577034153832c 100644 --- a/test/CodeGen/PowerPC/and-elim.ll +++ b/test/CodeGen/PowerPC/and-elim.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep rlwin +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep rlwin define void @test(i8* %P) { %W = load i8, i8* %P diff --git a/test/CodeGen/PowerPC/and-imm.ll b/test/CodeGen/PowerPC/and-imm.ll index 43f8c27c4342b..b4838d7221fdc 100644 --- a/test/CodeGen/PowerPC/and-imm.ll +++ b/test/CodeGen/PowerPC/and-imm.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep "ori\|lis" +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep "ori\|lis" ; andi. r3, r3, 32769 define i32 @test(i32 %X) { diff --git a/test/CodeGen/PowerPC/and_add.ll b/test/CodeGen/PowerPC/and_add.ll index 82dd957654e87..1b5b726953ff9 100644 --- a/test/CodeGen/PowerPC/and_add.ll +++ b/test/CodeGen/PowerPC/and_add.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -o %t +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t ; RUN: grep slwi %t ; RUN: not grep addi %t ; RUN: not grep rlwinm %t diff --git a/test/CodeGen/PowerPC/and_sext.ll b/test/CodeGen/PowerPC/and_sext.ll index 4179082b56fd3..3b576ca18ee74 100644 --- a/test/CodeGen/PowerPC/and_sext.ll +++ b/test/CodeGen/PowerPC/and_sext.ll @@ -1,6 +1,6 @@ ; These tests should not contain a sign extend. -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep extsh -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep extsb +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep extsh +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep extsb define i32 @test1(i32 %mode.0.i.0) { %tmp.79 = trunc i32 %mode.0.i.0 to i16 diff --git a/test/CodeGen/PowerPC/and_sra.ll b/test/CodeGen/PowerPC/and_sra.ll index 62349a9453a6d..e366c303a26da 100644 --- a/test/CodeGen/PowerPC/and_sra.ll +++ b/test/CodeGen/PowerPC/and_sra.ll @@ -1,5 +1,5 @@ ; Neither of these functions should contain algebraic right shifts -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep srawi +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep srawi define i32 @test1(i32 %mode.0.i.0) { %tmp.79 = bitcast i32 %mode.0.i.0 to i32 ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/andc.ll b/test/CodeGen/PowerPC/andc.ll index df47bfc1e38ef..9bfbda2bbd715 100644 --- a/test/CodeGen/PowerPC/andc.ll +++ b/test/CodeGen/PowerPC/andc.ll @@ -3,7 +3,7 @@ define i1 @and_cmp1(i32 %x, i32 %y) { ; CHECK-LABEL: and_cmp1: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: andc 3, 4, 3 ; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31 @@ -15,7 +15,7 @@ define i1 @and_cmp1(i32 %x, i32 %y) { define i1 @and_cmp_const(i32 %x) { ; CHECK-LABEL: and_cmp_const: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: li 4, 43 ; CHECK-NEXT: andc 3, 4, 3 ; CHECK-NEXT: cntlzw 3, 3 @@ -28,7 +28,7 @@ define i1 @and_cmp_const(i32 %x) { define i1 @foo(i32 %i) { ; CHECK-LABEL: foo: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: lis 4, 4660 ; CHECK-NEXT: ori 4, 4, 22136 ; CHECK-NEXT: andc 3, 4, 3 @@ -42,7 +42,7 @@ define i1 @foo(i32 %i) { define <4 x i32> @hidden_not_v4i32(<4 x i32> %x) { ; CHECK-LABEL: hidden_not_v4i32: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, 6 ; CHECK-NEXT: xxlandc 34, 35, 34 ; CHECK-NEXT: blr diff --git a/test/CodeGen/PowerPC/asm-Zy.ll b/test/CodeGen/PowerPC/asm-Zy.ll index 91bb2418c9794..78bb0f4c73eca 100644 --- a/test/CodeGen/PowerPC/asm-Zy.ll +++ b/test/CodeGen/PowerPC/asm-Zy.ll @@ -1,6 +1,6 @@ +; RUN: llc -verify-machineinstrs < %s -mcpu=a2 | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-bgq-linux" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2 | FileCheck %s define i32 @zytest(i32 %a) nounwind { entry: diff --git a/test/CodeGen/PowerPC/atomic-1.ll b/test/CodeGen/PowerPC/atomic-1.ll index 7b6069c9db2cb..c3c04d3a6ed79 100644 --- a/test/CodeGen/PowerPC/atomic-1.ll +++ b/test/CodeGen/PowerPC/atomic-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin -march=ppc32 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin | FileCheck %s define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind { ; CHECK-LABEL: exchange_and_add: diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll index f402cb78bd189..c1fbb43502075 100644 --- a/test/CodeGen/PowerPC/atomic-2.ll +++ b/test/CodeGen/PowerPC/atomic-2.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -ppc-asm-full-reg-names -march=ppc64 | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE -; RUN: llc < %s -ppc-asm-full-reg-names -march=ppc64le -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE -; RUN: llc < %s -ppc-asm-full-reg-names -march=ppc64 -mcpu=pwr7 | FileCheck %s -; RUN: llc < %s -ppc-asm-full-reg-names -march=ppc64 -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-P8U +; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=ppc64-- | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE +; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE +; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=ppc64-- -mcpu=pwr7 | FileCheck %s +; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=ppc64-- -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-P8U define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind { ; CHECK-LABEL: exchange_and_add: diff --git a/test/CodeGen/PowerPC/atomics-constant.ll b/test/CodeGen/PowerPC/atomics-constant.ll index 77825c608a3bb..559cd9eb656ac 100644 --- a/test/CodeGen/PowerPC/atomics-constant.ll +++ b/test/CodeGen/PowerPC/atomics-constant.ll @@ -7,7 +7,7 @@ target triple = "powerpc64le-unknown-linux-gnu" define i64 @foo() { ; CHECK-LABEL: foo: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: li 4, 0 ; CHECK-NEXT: ld 3, .LC0@toc@l(3) diff --git a/test/CodeGen/PowerPC/atomics-fences.ll b/test/CodeGen/PowerPC/atomics-fences.ll index 7682f8a7ef46c..778d645abf816 100644 --- a/test/CodeGen/PowerPC/atomics-fences.ll +++ b/test/CodeGen/PowerPC/atomics-fences.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc64 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=powerpc-apple-darwin -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-apple-darwin -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=440 | FileCheck %s --check-prefix=PPC440 ; Fences diff --git a/test/CodeGen/PowerPC/atomics-indexed.ll b/test/CodeGen/PowerPC/atomics-indexed.ll index cfe15f0061c43..48781471f1def 100644 --- a/test/CodeGen/PowerPC/atomics-indexed.ll +++ b/test/CodeGen/PowerPC/atomics-indexed.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32 +; RUN: llc < %s -mtriple=powerpc-apple-darwin -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32 ; FIXME: -verify-machineinstrs currently fail on ppc64 (mismatched register/instruction). ; This is already checked for in Atomics-64.ll -; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc64 | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64 +; RUN: llc < %s -mtriple=powerpc64-apple-darwin | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64 ; In this file, we check that atomic load/store can make use of the indexed ; versions of the instructions. diff --git a/test/CodeGen/PowerPC/atomics-regression.ll b/test/CodeGen/PowerPC/atomics-regression.ll index 0c7a31d16b199..7079f6dd52e90 100644 --- a/test/CodeGen/PowerPC/atomics-regression.ll +++ b/test/CodeGen/PowerPC/atomics-regression.ll @@ -3,7 +3,7 @@ define i8 @test0(i8* %ptr) { ; PPC64LE-LABEL: test0: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lbz 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i8, i8* %ptr unordered, align 1 @@ -12,7 +12,7 @@ define i8 @test0(i8* %ptr) { define i8 @test1(i8* %ptr) { ; PPC64LE-LABEL: test1: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lbz 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i8, i8* %ptr monotonic, align 1 @@ -21,7 +21,7 @@ define i8 @test1(i8* %ptr) { define i8 @test2(i8* %ptr) { ; PPC64LE-LABEL: test2: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lbz 3, 0(3) ; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 @@ -33,7 +33,7 @@ define i8 @test2(i8* %ptr) { define i8 @test3(i8* %ptr) { ; PPC64LE-LABEL: test3: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: lbz 3, 0(3) @@ -47,7 +47,7 @@ define i8 @test3(i8* %ptr) { define i16 @test4(i16* %ptr) { ; PPC64LE-LABEL: test4: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lhz 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i16, i16* %ptr unordered, align 2 @@ -56,7 +56,7 @@ define i16 @test4(i16* %ptr) { define i16 @test5(i16* %ptr) { ; PPC64LE-LABEL: test5: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lhz 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i16, i16* %ptr monotonic, align 2 @@ -65,7 +65,7 @@ define i16 @test5(i16* %ptr) { define i16 @test6(i16* %ptr) { ; PPC64LE-LABEL: test6: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lhz 3, 0(3) ; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 @@ -77,7 +77,7 @@ define i16 @test6(i16* %ptr) { define i16 @test7(i16* %ptr) { ; PPC64LE-LABEL: test7: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: lhz 3, 0(3) @@ -91,7 +91,7 @@ define i16 @test7(i16* %ptr) { define i32 @test8(i32* %ptr) { ; PPC64LE-LABEL: test8: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwz 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i32, i32* %ptr unordered, align 4 @@ -100,7 +100,7 @@ define i32 @test8(i32* %ptr) { define i32 @test9(i32* %ptr) { ; PPC64LE-LABEL: test9: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwz 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i32, i32* %ptr monotonic, align 4 @@ -109,7 +109,7 @@ define i32 @test9(i32* %ptr) { define i32 @test10(i32* %ptr) { ; PPC64LE-LABEL: test10: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwz 3, 0(3) ; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 @@ -121,7 +121,7 @@ define i32 @test10(i32* %ptr) { define i32 @test11(i32* %ptr) { ; PPC64LE-LABEL: test11: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: lwz 3, 0(3) @@ -135,7 +135,7 @@ define i32 @test11(i32* %ptr) { define i64 @test12(i64* %ptr) { ; PPC64LE-LABEL: test12: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: ld 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i64, i64* %ptr unordered, align 8 @@ -144,7 +144,7 @@ define i64 @test12(i64* %ptr) { define i64 @test13(i64* %ptr) { ; PPC64LE-LABEL: test13: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: ld 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i64, i64* %ptr monotonic, align 8 @@ -153,7 +153,7 @@ define i64 @test13(i64* %ptr) { define i64 @test14(i64* %ptr) { ; PPC64LE-LABEL: test14: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: ld 3, 0(3) ; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 @@ -165,7 +165,7 @@ define i64 @test14(i64* %ptr) { define i64 @test15(i64* %ptr) { ; PPC64LE-LABEL: test15: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: ld 3, 0(3) @@ -179,7 +179,7 @@ define i64 @test15(i64* %ptr) { define void @test16(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test16: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: stb 4, 0(3) ; PPC64LE-NEXT: blr store atomic i8 %val, i8* %ptr unordered, align 1 @@ -188,7 +188,7 @@ define void @test16(i8* %ptr, i8 %val) { define void @test17(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test17: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: stb 4, 0(3) ; PPC64LE-NEXT: blr store atomic i8 %val, i8* %ptr monotonic, align 1 @@ -197,7 +197,7 @@ define void @test17(i8* %ptr, i8 %val) { define void @test18(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test18: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: stb 4, 0(3) ; PPC64LE-NEXT: blr @@ -207,7 +207,7 @@ define void @test18(i8* %ptr, i8 %val) { define void @test19(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test19: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: stb 4, 0(3) ; PPC64LE-NEXT: blr @@ -217,7 +217,7 @@ define void @test19(i8* %ptr, i8 %val) { define void @test20(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test20: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sth 4, 0(3) ; PPC64LE-NEXT: blr store atomic i16 %val, i16* %ptr unordered, align 2 @@ -226,7 +226,7 @@ define void @test20(i16* %ptr, i16 %val) { define void @test21(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test21: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sth 4, 0(3) ; PPC64LE-NEXT: blr store atomic i16 %val, i16* %ptr monotonic, align 2 @@ -235,7 +235,7 @@ define void @test21(i16* %ptr, i16 %val) { define void @test22(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test22: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: sth 4, 0(3) ; PPC64LE-NEXT: blr @@ -245,7 +245,7 @@ define void @test22(i16* %ptr, i16 %val) { define void @test23(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test23: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sth 4, 0(3) ; PPC64LE-NEXT: blr @@ -255,7 +255,7 @@ define void @test23(i16* %ptr, i16 %val) { define void @test24(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test24: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: stw 4, 0(3) ; PPC64LE-NEXT: blr store atomic i32 %val, i32* %ptr unordered, align 4 @@ -264,7 +264,7 @@ define void @test24(i32* %ptr, i32 %val) { define void @test25(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test25: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: stw 4, 0(3) ; PPC64LE-NEXT: blr store atomic i32 %val, i32* %ptr monotonic, align 4 @@ -273,7 +273,7 @@ define void @test25(i32* %ptr, i32 %val) { define void @test26(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test26: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: stw 4, 0(3) ; PPC64LE-NEXT: blr @@ -283,7 +283,7 @@ define void @test26(i32* %ptr, i32 %val) { define void @test27(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test27: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: stw 4, 0(3) ; PPC64LE-NEXT: blr @@ -293,7 +293,7 @@ define void @test27(i32* %ptr, i32 %val) { define void @test28(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test28: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: std 4, 0(3) ; PPC64LE-NEXT: blr store atomic i64 %val, i64* %ptr unordered, align 8 @@ -302,7 +302,7 @@ define void @test28(i64* %ptr, i64 %val) { define void @test29(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test29: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: std 4, 0(3) ; PPC64LE-NEXT: blr store atomic i64 %val, i64* %ptr monotonic, align 8 @@ -311,7 +311,7 @@ define void @test29(i64* %ptr, i64 %val) { define void @test30(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test30: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: std 4, 0(3) ; PPC64LE-NEXT: blr @@ -321,7 +321,7 @@ define void @test30(i64* %ptr, i64 %val) { define void @test31(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test31: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: std 4, 0(3) ; PPC64LE-NEXT: blr @@ -331,7 +331,7 @@ define void @test31(i64* %ptr, i64 %val) { define void @test32() { ; PPC64LE-LABEL: test32: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr fence acquire @@ -340,7 +340,7 @@ define void @test32() { define void @test33() { ; PPC64LE-LABEL: test33: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr fence release @@ -349,7 +349,7 @@ define void @test33() { define void @test34() { ; PPC64LE-LABEL: test34: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr fence acq_rel @@ -358,7 +358,7 @@ define void @test34() { define void @test35() { ; PPC64LE-LABEL: test35: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: blr fence seq_cst @@ -367,7 +367,7 @@ define void @test35() { define void @test36() { ; PPC64LE-LABEL: test36: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr fence syncscope("singlethread") acquire @@ -376,7 +376,7 @@ define void @test36() { define void @test37() { ; PPC64LE-LABEL: test37: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr fence syncscope("singlethread") release @@ -385,7 +385,7 @@ define void @test37() { define void @test38() { ; PPC64LE-LABEL: test38: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr fence syncscope("singlethread") acq_rel @@ -394,7 +394,7 @@ define void @test38() { define void @test39() { ; PPC64LE-LABEL: test39: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: blr fence syncscope("singlethread") seq_cst @@ -403,18 +403,17 @@ define void @test39() { define void @test40(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test40: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB40_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB40_1: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB40_2 ; PPC64LE-NEXT: .LBB40_2: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB40_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic @@ -423,15 +422,15 @@ define void @test40(i8* %ptr, i8 %cmp, i8 %val) { define void @test41(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test41: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB41_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB41_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB41_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB41_4: @@ -444,15 +443,15 @@ define void @test41(i8* %ptr, i8 %cmp, i8 %val) { define void @test42(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test42: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB42_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB42_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB42_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB42_4: @@ -465,19 +464,18 @@ define void @test42(i8* %ptr, i8 %cmp, i8 %val) { define void @test43(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test43: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB43_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB43_1: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB43_2 ; PPC64LE-NEXT: .LBB43_2: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB43_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic @@ -486,19 +484,18 @@ define void @test43(i8* %ptr, i8 %cmp, i8 %val) { define void @test44(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test44: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB44_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB44_1: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB44_2 ; PPC64LE-NEXT: .LBB44_2: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB44_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire @@ -507,16 +504,16 @@ define void @test44(i8* %ptr, i8 %cmp, i8 %val) { define void @test45(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test45: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB45_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB45_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB45_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB45_4: @@ -529,16 +526,16 @@ define void @test45(i8* %ptr, i8 %cmp, i8 %val) { define void @test46(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test46: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB46_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB46_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB46_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB46_4: @@ -551,16 +548,16 @@ define void @test46(i8* %ptr, i8 %cmp, i8 %val) { define void @test47(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test47: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB47_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB47_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB47_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB47_4: @@ -573,16 +570,16 @@ define void @test47(i8* %ptr, i8 %cmp, i8 %val) { define void @test48(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test48: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB48_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB48_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB48_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB48_4: @@ -595,16 +592,16 @@ define void @test48(i8* %ptr, i8 %cmp, i8 %val) { define void @test49(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test49: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB49_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB49_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB49_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB49_4: @@ -617,18 +614,17 @@ define void @test49(i8* %ptr, i8 %cmp, i8 %val) { define void @test50(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test50: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB50_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB50_1: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB50_2 ; PPC64LE-NEXT: .LBB50_2: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB50_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic @@ -637,15 +633,15 @@ define void @test50(i16* %ptr, i16 %cmp, i16 %val) { define void @test51(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test51: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB51_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB51_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB51_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB51_4: @@ -658,15 +654,15 @@ define void @test51(i16* %ptr, i16 %cmp, i16 %val) { define void @test52(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test52: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB52_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB52_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB52_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB52_4: @@ -679,19 +675,18 @@ define void @test52(i16* %ptr, i16 %cmp, i16 %val) { define void @test53(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test53: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB53_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB53_1: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB53_2 ; PPC64LE-NEXT: .LBB53_2: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB53_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic @@ -700,19 +695,18 @@ define void @test53(i16* %ptr, i16 %cmp, i16 %val) { define void @test54(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test54: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB54_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB54_1: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB54_2 ; PPC64LE-NEXT: .LBB54_2: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB54_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire @@ -721,16 +715,16 @@ define void @test54(i16* %ptr, i16 %cmp, i16 %val) { define void @test55(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test55: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB55_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB55_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB55_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB55_4: @@ -743,16 +737,16 @@ define void @test55(i16* %ptr, i16 %cmp, i16 %val) { define void @test56(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test56: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB56_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB56_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB56_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB56_4: @@ -765,16 +759,16 @@ define void @test56(i16* %ptr, i16 %cmp, i16 %val) { define void @test57(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test57: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB57_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB57_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB57_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB57_4: @@ -787,16 +781,16 @@ define void @test57(i16* %ptr, i16 %cmp, i16 %val) { define void @test58(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test58: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB58_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB58_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB58_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB58_4: @@ -809,16 +803,16 @@ define void @test58(i16* %ptr, i16 %cmp, i16 %val) { define void @test59(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test59: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB59_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB59_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB59_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB59_4: @@ -831,18 +825,17 @@ define void @test59(i16* %ptr, i16 %cmp, i16 %val) { define void @test60(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test60: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB60_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB60_1: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB60_2 ; PPC64LE-NEXT: .LBB60_2: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB60_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic @@ -851,15 +844,15 @@ define void @test60(i32* %ptr, i32 %cmp, i32 %val) { define void @test61(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test61: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB61_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB61_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB61_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB61_4: @@ -872,15 +865,15 @@ define void @test61(i32* %ptr, i32 %cmp, i32 %val) { define void @test62(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test62: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB62_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB62_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB62_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB62_4: @@ -893,19 +886,18 @@ define void @test62(i32* %ptr, i32 %cmp, i32 %val) { define void @test63(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test63: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB63_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB63_1: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB63_2 ; PPC64LE-NEXT: .LBB63_2: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB63_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic @@ -914,19 +906,18 @@ define void @test63(i32* %ptr, i32 %cmp, i32 %val) { define void @test64(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test64: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB64_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB64_1: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB64_2 ; PPC64LE-NEXT: .LBB64_2: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB64_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire @@ -935,16 +926,16 @@ define void @test64(i32* %ptr, i32 %cmp, i32 %val) { define void @test65(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test65: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB65_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB65_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB65_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB65_4: @@ -957,16 +948,16 @@ define void @test65(i32* %ptr, i32 %cmp, i32 %val) { define void @test66(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test66: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB66_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB66_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB66_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB66_4: @@ -979,16 +970,16 @@ define void @test66(i32* %ptr, i32 %cmp, i32 %val) { define void @test67(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test67: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB67_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB67_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB67_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB67_4: @@ -1001,16 +992,16 @@ define void @test67(i32* %ptr, i32 %cmp, i32 %val) { define void @test68(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test68: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB68_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB68_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB68_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB68_4: @@ -1023,16 +1014,16 @@ define void @test68(i32* %ptr, i32 %cmp, i32 %val) { define void @test69(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test69: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB69_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB69_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB69_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB69_4: @@ -1045,18 +1036,17 @@ define void @test69(i32* %ptr, i32 %cmp, i32 %val) { define void @test70(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test70: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB70_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB70_1: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB70_2 ; PPC64LE-NEXT: .LBB70_2: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: beq 0, .LBB70_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic @@ -1065,15 +1055,15 @@ define void @test70(i64* %ptr, i64 %cmp, i64 %val) { define void @test71(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test71: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB71_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB71_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB71_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB71_4: @@ -1086,15 +1076,15 @@ define void @test71(i64* %ptr, i64 %cmp, i64 %val) { define void @test72(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test72: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB72_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB72_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB72_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB72_4: @@ -1107,19 +1097,18 @@ define void @test72(i64* %ptr, i64 %cmp, i64 %val) { define void @test73(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test73: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB73_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB73_1: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB73_2 ; PPC64LE-NEXT: .LBB73_2: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: beq 0, .LBB73_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic @@ -1128,19 +1117,18 @@ define void @test73(i64* %ptr, i64 %cmp, i64 %val) { define void @test74(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test74: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB74_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB74_1: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB74_2 ; PPC64LE-NEXT: .LBB74_2: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: beq 0, .LBB74_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire @@ -1149,16 +1137,16 @@ define void @test74(i64* %ptr, i64 %cmp, i64 %val) { define void @test75(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test75: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB75_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB75_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB75_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB75_4: @@ -1171,16 +1159,16 @@ define void @test75(i64* %ptr, i64 %cmp, i64 %val) { define void @test76(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test76: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB76_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB76_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB76_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB76_4: @@ -1193,16 +1181,16 @@ define void @test76(i64* %ptr, i64 %cmp, i64 %val) { define void @test77(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test77: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB77_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB77_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB77_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB77_4: @@ -1215,16 +1203,16 @@ define void @test77(i64* %ptr, i64 %cmp, i64 %val) { define void @test78(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test78: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB78_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB78_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB78_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB78_4: @@ -1237,16 +1225,16 @@ define void @test78(i64* %ptr, i64 %cmp, i64 %val) { define void @test79(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test79: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB79_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB79_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB79_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB79_4: @@ -1259,18 +1247,17 @@ define void @test79(i64* %ptr, i64 %cmp, i64 %val) { define void @test80(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test80: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB80_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB80_1: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB80_2 ; PPC64LE-NEXT: .LBB80_2: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB80_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") monotonic monotonic @@ -1279,15 +1266,15 @@ define void @test80(i8* %ptr, i8 %cmp, i8 %val) { define void @test81(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test81: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB81_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB81_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB81_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB81_4: @@ -1300,15 +1287,15 @@ define void @test81(i8* %ptr, i8 %cmp, i8 %val) { define void @test82(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test82: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB82_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB82_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB82_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB82_4: @@ -1321,19 +1308,18 @@ define void @test82(i8* %ptr, i8 %cmp, i8 %val) { define void @test83(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test83: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB83_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB83_1: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB83_2 ; PPC64LE-NEXT: .LBB83_2: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB83_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic @@ -1342,19 +1328,18 @@ define void @test83(i8* %ptr, i8 %cmp, i8 %val) { define void @test84(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test84: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB84_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB84_1: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB84_2 ; PPC64LE-NEXT: .LBB84_2: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB84_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release acquire @@ -1363,16 +1348,16 @@ define void @test84(i8* %ptr, i8 %cmp, i8 %val) { define void @test85(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test85: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB85_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB85_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB85_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB85_4: @@ -1385,16 +1370,16 @@ define void @test85(i8* %ptr, i8 %cmp, i8 %val) { define void @test86(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test86: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB86_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB86_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB86_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB86_4: @@ -1407,16 +1392,16 @@ define void @test86(i8* %ptr, i8 %cmp, i8 %val) { define void @test87(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test87: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB87_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB87_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB87_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB87_4: @@ -1429,16 +1414,16 @@ define void @test87(i8* %ptr, i8 %cmp, i8 %val) { define void @test88(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test88: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB88_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB88_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB88_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB88_4: @@ -1451,16 +1436,16 @@ define void @test88(i8* %ptr, i8 %cmp, i8 %val) { define void @test89(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test89: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB89_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB89_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB89_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB89_4: @@ -1473,18 +1458,17 @@ define void @test89(i8* %ptr, i8 %cmp, i8 %val) { define void @test90(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test90: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB90_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB90_1: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB90_2 ; PPC64LE-NEXT: .LBB90_2: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB90_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") monotonic monotonic @@ -1493,15 +1477,15 @@ define void @test90(i16* %ptr, i16 %cmp, i16 %val) { define void @test91(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test91: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB91_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB91_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB91_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB91_4: @@ -1514,15 +1498,15 @@ define void @test91(i16* %ptr, i16 %cmp, i16 %val) { define void @test92(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test92: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB92_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB92_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB92_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB92_4: @@ -1535,19 +1519,18 @@ define void @test92(i16* %ptr, i16 %cmp, i16 %val) { define void @test93(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test93: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB93_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB93_1: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB93_2 ; PPC64LE-NEXT: .LBB93_2: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB93_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic @@ -1556,19 +1539,18 @@ define void @test93(i16* %ptr, i16 %cmp, i16 %val) { define void @test94(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test94: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB94_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB94_1: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB94_2 ; PPC64LE-NEXT: .LBB94_2: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB94_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release acquire @@ -1577,16 +1559,16 @@ define void @test94(i16* %ptr, i16 %cmp, i16 %val) { define void @test95(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test95: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB95_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB95_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB95_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB95_4: @@ -1599,16 +1581,16 @@ define void @test95(i16* %ptr, i16 %cmp, i16 %val) { define void @test96(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test96: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB96_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB96_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB96_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB96_4: @@ -1621,16 +1603,16 @@ define void @test96(i16* %ptr, i16 %cmp, i16 %val) { define void @test97(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test97: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB97_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB97_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB97_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB97_4: @@ -1643,16 +1625,16 @@ define void @test97(i16* %ptr, i16 %cmp, i16 %val) { define void @test98(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test98: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB98_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB98_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB98_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB98_4: @@ -1665,16 +1647,16 @@ define void @test98(i16* %ptr, i16 %cmp, i16 %val) { define void @test99(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test99: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB99_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB99_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB99_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB99_4: @@ -1687,18 +1669,17 @@ define void @test99(i16* %ptr, i16 %cmp, i16 %val) { define void @test100(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test100: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB100_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB100_1: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB100_2 ; PPC64LE-NEXT: .LBB100_2: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB100_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") monotonic monotonic @@ -1707,15 +1688,15 @@ define void @test100(i32* %ptr, i32 %cmp, i32 %val) { define void @test101(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test101: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB101_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB101_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB101_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB101_4: @@ -1728,15 +1709,15 @@ define void @test101(i32* %ptr, i32 %cmp, i32 %val) { define void @test102(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test102: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB102_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB102_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB102_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB102_4: @@ -1749,19 +1730,18 @@ define void @test102(i32* %ptr, i32 %cmp, i32 %val) { define void @test103(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test103: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB103_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB103_1: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB103_2 ; PPC64LE-NEXT: .LBB103_2: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB103_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release monotonic @@ -1770,19 +1750,18 @@ define void @test103(i32* %ptr, i32 %cmp, i32 %val) { define void @test104(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test104: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB104_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB104_1: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB104_2 ; PPC64LE-NEXT: .LBB104_2: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB104_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release acquire @@ -1791,16 +1770,16 @@ define void @test104(i32* %ptr, i32 %cmp, i32 %val) { define void @test105(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test105: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB105_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB105_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB105_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB105_4: @@ -1813,16 +1792,16 @@ define void @test105(i32* %ptr, i32 %cmp, i32 %val) { define void @test106(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test106: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB106_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB106_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB106_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB106_4: @@ -1835,16 +1814,16 @@ define void @test106(i32* %ptr, i32 %cmp, i32 %val) { define void @test107(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test107: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB107_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB107_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB107_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB107_4: @@ -1857,16 +1836,16 @@ define void @test107(i32* %ptr, i32 %cmp, i32 %val) { define void @test108(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test108: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB108_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB108_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB108_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB108_4: @@ -1879,16 +1858,16 @@ define void @test108(i32* %ptr, i32 %cmp, i32 %val) { define void @test109(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test109: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB109_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB109_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB109_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB109_4: @@ -1901,18 +1880,17 @@ define void @test109(i32* %ptr, i32 %cmp, i32 %val) { define void @test110(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test110: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB110_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB110_1: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB110_2 ; PPC64LE-NEXT: .LBB110_2: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: beq 0, .LBB110_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") monotonic monotonic @@ -1921,15 +1899,15 @@ define void @test110(i64* %ptr, i64 %cmp, i64 %val) { define void @test111(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test111: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB111_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB111_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB111_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB111_4: @@ -1942,15 +1920,15 @@ define void @test111(i64* %ptr, i64 %cmp, i64 %val) { define void @test112(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test112: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB112_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB112_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB112_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB112_4: @@ -1963,19 +1941,18 @@ define void @test112(i64* %ptr, i64 %cmp, i64 %val) { define void @test113(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test113: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB113_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB113_1: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB113_2 ; PPC64LE-NEXT: .LBB113_2: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: beq 0, .LBB113_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release monotonic @@ -1984,19 +1961,18 @@ define void @test113(i64* %ptr, i64 %cmp, i64 %val) { define void @test114(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test114: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB114_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB114_1: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: beqlr 0 -; PPC64LE-NEXT: b .LBB114_2 ; PPC64LE-NEXT: .LBB114_2: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: beq 0, .LBB114_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release acquire @@ -2005,16 +1981,16 @@ define void @test114(i64* %ptr, i64 %cmp, i64 %val) { define void @test115(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test115: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB115_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB115_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB115_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB115_4: @@ -2027,16 +2003,16 @@ define void @test115(i64* %ptr, i64 %cmp, i64 %val) { define void @test116(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test116: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB116_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB116_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB116_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB116_4: @@ -2049,16 +2025,16 @@ define void @test116(i64* %ptr, i64 %cmp, i64 %val) { define void @test117(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test117: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB117_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB117_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB117_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB117_4: @@ -2071,16 +2047,16 @@ define void @test117(i64* %ptr, i64 %cmp, i64 %val) { define void @test118(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test118: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB118_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB118_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB118_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB118_4: @@ -2093,16 +2069,16 @@ define void @test118(i64* %ptr, i64 %cmp, i64 %val) { define void @test119(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test119: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB119_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB119_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB119_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB119_4: @@ -2115,12 +2091,12 @@ define void @test119(i64* %ptr, i64 %cmp, i64 %val) { define i8 @test120(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test120: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB120_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB120_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i8* %ptr, i8 %val monotonic @@ -2129,13 +2105,13 @@ define i8 @test120(i8* %ptr, i8 %val) { define i8 @test121(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test121: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB121_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB121_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i8* %ptr, i8 %val acquire @@ -2144,13 +2120,13 @@ define i8 @test121(i8* %ptr, i8 %val) { define i8 @test122(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test122: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB122_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB122_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i8* %ptr, i8 %val release @@ -2159,13 +2135,13 @@ define i8 @test122(i8* %ptr, i8 %val) { define i8 @test123(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test123: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB123_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB123_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2175,13 +2151,13 @@ define i8 @test123(i8* %ptr, i8 %val) { define i8 @test124(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test124: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB124_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB124_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2191,12 +2167,12 @@ define i8 @test124(i8* %ptr, i8 %val) { define i16 @test125(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test125: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB125_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB125_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i16* %ptr, i16 %val monotonic @@ -2205,13 +2181,13 @@ define i16 @test125(i16* %ptr, i16 %val) { define i16 @test126(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test126: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB126_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB126_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i16* %ptr, i16 %val acquire @@ -2220,13 +2196,13 @@ define i16 @test126(i16* %ptr, i16 %val) { define i16 @test127(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test127: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB127_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB127_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i16* %ptr, i16 %val release @@ -2235,13 +2211,13 @@ define i16 @test127(i16* %ptr, i16 %val) { define i16 @test128(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test128: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB128_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB128_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2251,13 +2227,13 @@ define i16 @test128(i16* %ptr, i16 %val) { define i16 @test129(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test129: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB129_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB129_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2267,12 +2243,12 @@ define i16 @test129(i16* %ptr, i16 %val) { define i32 @test130(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test130: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB130_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB130_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i32* %ptr, i32 %val monotonic @@ -2281,13 +2257,13 @@ define i32 @test130(i32* %ptr, i32 %val) { define i32 @test131(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test131: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB131_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB131_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i32* %ptr, i32 %val acquire @@ -2296,13 +2272,13 @@ define i32 @test131(i32* %ptr, i32 %val) { define i32 @test132(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test132: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB132_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB132_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i32* %ptr, i32 %val release @@ -2311,13 +2287,13 @@ define i32 @test132(i32* %ptr, i32 %val) { define i32 @test133(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test133: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB133_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB133_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2327,13 +2303,13 @@ define i32 @test133(i32* %ptr, i32 %val) { define i32 @test134(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test134: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB134_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB134_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2343,12 +2319,12 @@ define i32 @test134(i32* %ptr, i32 %val) { define i64 @test135(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test135: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB135_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB135_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i64* %ptr, i64 %val monotonic @@ -2357,13 +2333,13 @@ define i64 @test135(i64* %ptr, i64 %val) { define i64 @test136(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test136: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB136_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB136_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i64* %ptr, i64 %val acquire @@ -2372,13 +2348,13 @@ define i64 @test136(i64* %ptr, i64 %val) { define i64 @test137(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test137: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB137_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB137_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i64* %ptr, i64 %val release @@ -2387,13 +2363,13 @@ define i64 @test137(i64* %ptr, i64 %val) { define i64 @test138(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test138: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB138_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB138_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2403,13 +2379,13 @@ define i64 @test138(i64* %ptr, i64 %val) { define i64 @test139(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test139: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB139_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB139_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2419,13 +2395,13 @@ define i64 @test139(i64* %ptr, i64 %val) { define i8 @test140(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test140: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB140_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB140_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i8* %ptr, i8 %val monotonic @@ -2434,14 +2410,14 @@ define i8 @test140(i8* %ptr, i8 %val) { define i8 @test141(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test141: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB141_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB141_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i8* %ptr, i8 %val acquire @@ -2450,14 +2426,14 @@ define i8 @test141(i8* %ptr, i8 %val) { define i8 @test142(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test142: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB142_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB142_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i8* %ptr, i8 %val release @@ -2466,14 +2442,14 @@ define i8 @test142(i8* %ptr, i8 %val) { define i8 @test143(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test143: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB143_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB143_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2483,14 +2459,14 @@ define i8 @test143(i8* %ptr, i8 %val) { define i8 @test144(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test144: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB144_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB144_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2500,13 +2476,13 @@ define i8 @test144(i8* %ptr, i8 %val) { define i16 @test145(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test145: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB145_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB145_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i16* %ptr, i16 %val monotonic @@ -2515,14 +2491,14 @@ define i16 @test145(i16* %ptr, i16 %val) { define i16 @test146(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test146: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB146_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB146_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i16* %ptr, i16 %val acquire @@ -2531,14 +2507,14 @@ define i16 @test146(i16* %ptr, i16 %val) { define i16 @test147(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test147: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB147_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB147_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i16* %ptr, i16 %val release @@ -2547,14 +2523,14 @@ define i16 @test147(i16* %ptr, i16 %val) { define i16 @test148(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test148: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB148_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB148_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2564,14 +2540,14 @@ define i16 @test148(i16* %ptr, i16 %val) { define i16 @test149(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test149: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB149_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB149_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2581,13 +2557,13 @@ define i16 @test149(i16* %ptr, i16 %val) { define i32 @test150(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test150: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB150_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB150_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i32* %ptr, i32 %val monotonic @@ -2596,14 +2572,14 @@ define i32 @test150(i32* %ptr, i32 %val) { define i32 @test151(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test151: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB151_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB151_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i32* %ptr, i32 %val acquire @@ -2612,14 +2588,14 @@ define i32 @test151(i32* %ptr, i32 %val) { define i32 @test152(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test152: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB152_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB152_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i32* %ptr, i32 %val release @@ -2628,14 +2604,14 @@ define i32 @test152(i32* %ptr, i32 %val) { define i32 @test153(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test153: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB153_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB153_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2645,14 +2621,14 @@ define i32 @test153(i32* %ptr, i32 %val) { define i32 @test154(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test154: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB154_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB154_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2662,13 +2638,13 @@ define i32 @test154(i32* %ptr, i32 %val) { define i64 @test155(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test155: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB155_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB155_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i64* %ptr, i64 %val monotonic @@ -2677,14 +2653,14 @@ define i64 @test155(i64* %ptr, i64 %val) { define i64 @test156(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test156: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB156_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB156_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i64* %ptr, i64 %val acquire @@ -2693,14 +2669,14 @@ define i64 @test156(i64* %ptr, i64 %val) { define i64 @test157(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test157: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB157_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB157_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i64* %ptr, i64 %val release @@ -2709,14 +2685,14 @@ define i64 @test157(i64* %ptr, i64 %val) { define i64 @test158(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test158: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB158_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB158_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2726,14 +2702,14 @@ define i64 @test158(i64* %ptr, i64 %val) { define i64 @test159(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test159: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB159_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB159_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2743,13 +2719,13 @@ define i64 @test159(i64* %ptr, i64 %val) { define i8 @test160(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test160: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB160_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB160_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i8* %ptr, i8 %val monotonic @@ -2758,14 +2734,14 @@ define i8 @test160(i8* %ptr, i8 %val) { define i8 @test161(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test161: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB161_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: subf 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB161_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i8* %ptr, i8 %val acquire @@ -2774,14 +2750,14 @@ define i8 @test161(i8* %ptr, i8 %val) { define i8 @test162(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test162: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB162_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB162_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i8* %ptr, i8 %val release @@ -2790,14 +2766,14 @@ define i8 @test162(i8* %ptr, i8 %val) { define i8 @test163(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test163: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB163_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB163_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2807,14 +2783,14 @@ define i8 @test163(i8* %ptr, i8 %val) { define i8 @test164(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test164: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB164_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB164_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2824,13 +2800,13 @@ define i8 @test164(i8* %ptr, i8 %val) { define i16 @test165(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test165: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB165_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB165_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i16* %ptr, i16 %val monotonic @@ -2839,14 +2815,14 @@ define i16 @test165(i16* %ptr, i16 %val) { define i16 @test166(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test166: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB166_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: subf 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB166_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i16* %ptr, i16 %val acquire @@ -2855,14 +2831,14 @@ define i16 @test166(i16* %ptr, i16 %val) { define i16 @test167(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test167: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB167_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB167_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i16* %ptr, i16 %val release @@ -2871,14 +2847,14 @@ define i16 @test167(i16* %ptr, i16 %val) { define i16 @test168(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test168: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB168_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB168_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2888,14 +2864,14 @@ define i16 @test168(i16* %ptr, i16 %val) { define i16 @test169(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test169: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB169_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB169_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2905,13 +2881,13 @@ define i16 @test169(i16* %ptr, i16 %val) { define i32 @test170(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test170: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB170_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB170_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i32* %ptr, i32 %val monotonic @@ -2920,14 +2896,14 @@ define i32 @test170(i32* %ptr, i32 %val) { define i32 @test171(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test171: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB171_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: subf 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB171_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i32* %ptr, i32 %val acquire @@ -2936,14 +2912,14 @@ define i32 @test171(i32* %ptr, i32 %val) { define i32 @test172(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test172: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB172_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB172_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i32* %ptr, i32 %val release @@ -2952,14 +2928,14 @@ define i32 @test172(i32* %ptr, i32 %val) { define i32 @test173(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test173: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB173_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB173_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2969,14 +2945,14 @@ define i32 @test173(i32* %ptr, i32 %val) { define i32 @test174(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test174: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB174_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB174_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2986,13 +2962,13 @@ define i32 @test174(i32* %ptr, i32 %val) { define i64 @test175(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test175: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB175_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB175_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i64* %ptr, i64 %val monotonic @@ -3001,14 +2977,14 @@ define i64 @test175(i64* %ptr, i64 %val) { define i64 @test176(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test176: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB176_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: sub 6, 3, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB176_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i64* %ptr, i64 %val acquire @@ -3017,14 +2993,14 @@ define i64 @test176(i64* %ptr, i64 %val) { define i64 @test177(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test177: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB177_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB177_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i64* %ptr, i64 %val release @@ -3033,14 +3009,14 @@ define i64 @test177(i64* %ptr, i64 %val) { define i64 @test178(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test178: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB178_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB178_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3050,14 +3026,14 @@ define i64 @test178(i64* %ptr, i64 %val) { define i64 @test179(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test179: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB179_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB179_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3067,13 +3043,13 @@ define i64 @test179(i64* %ptr, i64 %val) { define i8 @test180(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test180: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB180_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB180_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i8* %ptr, i8 %val monotonic @@ -3082,14 +3058,14 @@ define i8 @test180(i8* %ptr, i8 %val) { define i8 @test181(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test181: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB181_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB181_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i8* %ptr, i8 %val acquire @@ -3098,14 +3074,14 @@ define i8 @test181(i8* %ptr, i8 %val) { define i8 @test182(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test182: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB182_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB182_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i8* %ptr, i8 %val release @@ -3114,14 +3090,14 @@ define i8 @test182(i8* %ptr, i8 %val) { define i8 @test183(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test183: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB183_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB183_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3131,14 +3107,14 @@ define i8 @test183(i8* %ptr, i8 %val) { define i8 @test184(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test184: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB184_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB184_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3148,13 +3124,13 @@ define i8 @test184(i8* %ptr, i8 %val) { define i16 @test185(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test185: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB185_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB185_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i16* %ptr, i16 %val monotonic @@ -3163,14 +3139,14 @@ define i16 @test185(i16* %ptr, i16 %val) { define i16 @test186(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test186: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB186_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB186_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i16* %ptr, i16 %val acquire @@ -3179,14 +3155,14 @@ define i16 @test186(i16* %ptr, i16 %val) { define i16 @test187(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test187: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB187_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB187_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i16* %ptr, i16 %val release @@ -3195,14 +3171,14 @@ define i16 @test187(i16* %ptr, i16 %val) { define i16 @test188(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test188: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB188_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB188_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3212,14 +3188,14 @@ define i16 @test188(i16* %ptr, i16 %val) { define i16 @test189(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test189: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB189_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB189_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3229,13 +3205,13 @@ define i16 @test189(i16* %ptr, i16 %val) { define i32 @test190(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test190: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB190_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB190_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i32* %ptr, i32 %val monotonic @@ -3244,14 +3220,14 @@ define i32 @test190(i32* %ptr, i32 %val) { define i32 @test191(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test191: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB191_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB191_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i32* %ptr, i32 %val acquire @@ -3260,14 +3236,14 @@ define i32 @test191(i32* %ptr, i32 %val) { define i32 @test192(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test192: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB192_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB192_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i32* %ptr, i32 %val release @@ -3276,14 +3252,14 @@ define i32 @test192(i32* %ptr, i32 %val) { define i32 @test193(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test193: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB193_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB193_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3293,14 +3269,14 @@ define i32 @test193(i32* %ptr, i32 %val) { define i32 @test194(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test194: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB194_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB194_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3310,13 +3286,13 @@ define i32 @test194(i32* %ptr, i32 %val) { define i64 @test195(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test195: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB195_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB195_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i64* %ptr, i64 %val monotonic @@ -3325,14 +3301,14 @@ define i64 @test195(i64* %ptr, i64 %val) { define i64 @test196(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test196: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB196_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB196_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i64* %ptr, i64 %val acquire @@ -3341,14 +3317,14 @@ define i64 @test196(i64* %ptr, i64 %val) { define i64 @test197(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test197: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB197_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB197_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i64* %ptr, i64 %val release @@ -3357,14 +3333,14 @@ define i64 @test197(i64* %ptr, i64 %val) { define i64 @test198(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test198: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB198_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB198_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3374,14 +3350,14 @@ define i64 @test198(i64* %ptr, i64 %val) { define i64 @test199(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test199: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB199_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB199_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3391,13 +3367,13 @@ define i64 @test199(i64* %ptr, i64 %val) { define i8 @test200(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test200: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB200_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB200_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i8* %ptr, i8 %val monotonic @@ -3406,14 +3382,14 @@ define i8 @test200(i8* %ptr, i8 %val) { define i8 @test201(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test201: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB201_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB201_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i8* %ptr, i8 %val acquire @@ -3422,14 +3398,14 @@ define i8 @test201(i8* %ptr, i8 %val) { define i8 @test202(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test202: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB202_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB202_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i8* %ptr, i8 %val release @@ -3438,14 +3414,14 @@ define i8 @test202(i8* %ptr, i8 %val) { define i8 @test203(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test203: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB203_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB203_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3455,14 +3431,14 @@ define i8 @test203(i8* %ptr, i8 %val) { define i8 @test204(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test204: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB204_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB204_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3472,13 +3448,13 @@ define i8 @test204(i8* %ptr, i8 %val) { define i16 @test205(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test205: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB205_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB205_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i16* %ptr, i16 %val monotonic @@ -3487,14 +3463,14 @@ define i16 @test205(i16* %ptr, i16 %val) { define i16 @test206(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test206: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB206_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB206_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i16* %ptr, i16 %val acquire @@ -3503,14 +3479,14 @@ define i16 @test206(i16* %ptr, i16 %val) { define i16 @test207(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test207: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB207_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB207_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i16* %ptr, i16 %val release @@ -3519,14 +3495,14 @@ define i16 @test207(i16* %ptr, i16 %val) { define i16 @test208(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test208: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB208_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB208_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3536,14 +3512,14 @@ define i16 @test208(i16* %ptr, i16 %val) { define i16 @test209(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test209: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB209_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB209_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3553,13 +3529,13 @@ define i16 @test209(i16* %ptr, i16 %val) { define i32 @test210(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test210: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB210_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB210_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i32* %ptr, i32 %val monotonic @@ -3568,14 +3544,14 @@ define i32 @test210(i32* %ptr, i32 %val) { define i32 @test211(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test211: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB211_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB211_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i32* %ptr, i32 %val acquire @@ -3584,14 +3560,14 @@ define i32 @test211(i32* %ptr, i32 %val) { define i32 @test212(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test212: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB212_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB212_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i32* %ptr, i32 %val release @@ -3600,14 +3576,14 @@ define i32 @test212(i32* %ptr, i32 %val) { define i32 @test213(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test213: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB213_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB213_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3617,14 +3593,14 @@ define i32 @test213(i32* %ptr, i32 %val) { define i32 @test214(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test214: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB214_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB214_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3634,13 +3610,13 @@ define i32 @test214(i32* %ptr, i32 %val) { define i64 @test215(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test215: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB215_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB215_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i64* %ptr, i64 %val monotonic @@ -3649,14 +3625,14 @@ define i64 @test215(i64* %ptr, i64 %val) { define i64 @test216(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test216: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB216_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB216_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i64* %ptr, i64 %val acquire @@ -3665,14 +3641,14 @@ define i64 @test216(i64* %ptr, i64 %val) { define i64 @test217(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test217: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB217_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB217_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i64* %ptr, i64 %val release @@ -3681,14 +3657,14 @@ define i64 @test217(i64* %ptr, i64 %val) { define i64 @test218(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test218: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB218_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB218_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3698,14 +3674,14 @@ define i64 @test218(i64* %ptr, i64 %val) { define i64 @test219(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test219: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB219_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB219_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3715,13 +3691,13 @@ define i64 @test219(i64* %ptr, i64 %val) { define i8 @test220(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test220: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB220_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB220_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i8* %ptr, i8 %val monotonic @@ -3730,14 +3706,14 @@ define i8 @test220(i8* %ptr, i8 %val) { define i8 @test221(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test221: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB221_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB221_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i8* %ptr, i8 %val acquire @@ -3746,14 +3722,14 @@ define i8 @test221(i8* %ptr, i8 %val) { define i8 @test222(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test222: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB222_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB222_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i8* %ptr, i8 %val release @@ -3762,14 +3738,14 @@ define i8 @test222(i8* %ptr, i8 %val) { define i8 @test223(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test223: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB223_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB223_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3779,14 +3755,14 @@ define i8 @test223(i8* %ptr, i8 %val) { define i8 @test224(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test224: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB224_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB224_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3796,13 +3772,13 @@ define i8 @test224(i8* %ptr, i8 %val) { define i16 @test225(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test225: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB225_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB225_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i16* %ptr, i16 %val monotonic @@ -3811,14 +3787,14 @@ define i16 @test225(i16* %ptr, i16 %val) { define i16 @test226(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test226: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB226_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB226_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i16* %ptr, i16 %val acquire @@ -3827,14 +3803,14 @@ define i16 @test226(i16* %ptr, i16 %val) { define i16 @test227(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test227: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB227_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB227_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i16* %ptr, i16 %val release @@ -3843,14 +3819,14 @@ define i16 @test227(i16* %ptr, i16 %val) { define i16 @test228(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test228: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB228_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB228_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3860,14 +3836,14 @@ define i16 @test228(i16* %ptr, i16 %val) { define i16 @test229(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test229: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB229_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB229_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3877,13 +3853,13 @@ define i16 @test229(i16* %ptr, i16 %val) { define i32 @test230(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test230: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB230_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB230_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i32* %ptr, i32 %val monotonic @@ -3892,14 +3868,14 @@ define i32 @test230(i32* %ptr, i32 %val) { define i32 @test231(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test231: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB231_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB231_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i32* %ptr, i32 %val acquire @@ -3908,14 +3884,14 @@ define i32 @test231(i32* %ptr, i32 %val) { define i32 @test232(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test232: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB232_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB232_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i32* %ptr, i32 %val release @@ -3924,14 +3900,14 @@ define i32 @test232(i32* %ptr, i32 %val) { define i32 @test233(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test233: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB233_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB233_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3941,14 +3917,14 @@ define i32 @test233(i32* %ptr, i32 %val) { define i32 @test234(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test234: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB234_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB234_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3958,13 +3934,13 @@ define i32 @test234(i32* %ptr, i32 %val) { define i64 @test235(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test235: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB235_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB235_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i64* %ptr, i64 %val monotonic @@ -3973,14 +3949,14 @@ define i64 @test235(i64* %ptr, i64 %val) { define i64 @test236(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test236: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB236_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB236_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i64* %ptr, i64 %val acquire @@ -3989,14 +3965,14 @@ define i64 @test236(i64* %ptr, i64 %val) { define i64 @test237(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test237: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB237_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB237_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i64* %ptr, i64 %val release @@ -4005,14 +3981,14 @@ define i64 @test237(i64* %ptr, i64 %val) { define i64 @test238(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test238: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB238_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB238_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4022,14 +3998,14 @@ define i64 @test238(i64* %ptr, i64 %val) { define i64 @test239(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test239: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB239_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB239_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4039,13 +4015,13 @@ define i64 @test239(i64* %ptr, i64 %val) { define i8 @test240(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test240: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB240_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB240_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i8* %ptr, i8 %val monotonic @@ -4054,14 +4030,14 @@ define i8 @test240(i8* %ptr, i8 %val) { define i8 @test241(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test241: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB241_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB241_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i8* %ptr, i8 %val acquire @@ -4070,14 +4046,14 @@ define i8 @test241(i8* %ptr, i8 %val) { define i8 @test242(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test242: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB242_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB242_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i8* %ptr, i8 %val release @@ -4086,14 +4062,14 @@ define i8 @test242(i8* %ptr, i8 %val) { define i8 @test243(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test243: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB243_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB243_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4103,14 +4079,14 @@ define i8 @test243(i8* %ptr, i8 %val) { define i8 @test244(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test244: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB244_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB244_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4120,13 +4096,13 @@ define i8 @test244(i8* %ptr, i8 %val) { define i16 @test245(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test245: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB245_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB245_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i16* %ptr, i16 %val monotonic @@ -4135,14 +4111,14 @@ define i16 @test245(i16* %ptr, i16 %val) { define i16 @test246(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test246: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB246_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB246_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i16* %ptr, i16 %val acquire @@ -4151,14 +4127,14 @@ define i16 @test246(i16* %ptr, i16 %val) { define i16 @test247(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test247: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB247_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB247_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i16* %ptr, i16 %val release @@ -4167,14 +4143,14 @@ define i16 @test247(i16* %ptr, i16 %val) { define i16 @test248(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test248: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB248_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB248_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4184,14 +4160,14 @@ define i16 @test248(i16* %ptr, i16 %val) { define i16 @test249(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test249: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB249_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB249_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4201,13 +4177,13 @@ define i16 @test249(i16* %ptr, i16 %val) { define i32 @test250(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test250: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB250_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB250_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i32* %ptr, i32 %val monotonic @@ -4216,14 +4192,14 @@ define i32 @test250(i32* %ptr, i32 %val) { define i32 @test251(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test251: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB251_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB251_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i32* %ptr, i32 %val acquire @@ -4232,14 +4208,14 @@ define i32 @test251(i32* %ptr, i32 %val) { define i32 @test252(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test252: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB252_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB252_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i32* %ptr, i32 %val release @@ -4248,14 +4224,14 @@ define i32 @test252(i32* %ptr, i32 %val) { define i32 @test253(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test253: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB253_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB253_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4265,14 +4241,14 @@ define i32 @test253(i32* %ptr, i32 %val) { define i32 @test254(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test254: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB254_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB254_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4282,13 +4258,13 @@ define i32 @test254(i32* %ptr, i32 %val) { define i64 @test255(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test255: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB255_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB255_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i64* %ptr, i64 %val monotonic @@ -4297,14 +4273,14 @@ define i64 @test255(i64* %ptr, i64 %val) { define i64 @test256(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test256: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB256_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB256_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i64* %ptr, i64 %val acquire @@ -4313,14 +4289,14 @@ define i64 @test256(i64* %ptr, i64 %val) { define i64 @test257(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test257: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB257_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB257_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i64* %ptr, i64 %val release @@ -4329,14 +4305,14 @@ define i64 @test257(i64* %ptr, i64 %val) { define i64 @test258(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test258: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB258_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB258_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4346,14 +4322,14 @@ define i64 @test258(i64* %ptr, i64 %val) { define i64 @test259(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test259: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB259_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB259_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4363,13 +4339,13 @@ define i64 @test259(i64* %ptr, i64 %val) { define i8 @test260(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test260: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB260_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB260_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB260_1 ; PPC64LE-NEXT: .LBB260_3: @@ -4381,14 +4357,14 @@ define i8 @test260(i8* %ptr, i8 %val) { define i8 @test261(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test261: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB261_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: extsb 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB261_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB261_1 ; PPC64LE-NEXT: .LBB261_3: @@ -4400,14 +4376,14 @@ define i8 @test261(i8* %ptr, i8 %val) { define i8 @test262(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test262: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB262_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB262_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB262_1 ; PPC64LE-NEXT: .LBB262_3: @@ -4419,14 +4395,14 @@ define i8 @test262(i8* %ptr, i8 %val) { define i8 @test263(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test263: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB263_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB263_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB263_1 ; PPC64LE-NEXT: .LBB263_3: @@ -4439,14 +4415,14 @@ define i8 @test263(i8* %ptr, i8 %val) { define i8 @test264(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test264: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB264_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB264_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB264_1 ; PPC64LE-NEXT: .LBB264_3: @@ -4459,13 +4435,13 @@ define i8 @test264(i8* %ptr, i8 %val) { define i16 @test265(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test265: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB265_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB265_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB265_1 ; PPC64LE-NEXT: .LBB265_3: @@ -4477,14 +4453,14 @@ define i16 @test265(i16* %ptr, i16 %val) { define i16 @test266(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test266: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB266_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: extsh 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB266_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB266_1 ; PPC64LE-NEXT: .LBB266_3: @@ -4496,14 +4472,14 @@ define i16 @test266(i16* %ptr, i16 %val) { define i16 @test267(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test267: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB267_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB267_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB267_1 ; PPC64LE-NEXT: .LBB267_3: @@ -4515,14 +4491,14 @@ define i16 @test267(i16* %ptr, i16 %val) { define i16 @test268(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test268: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB268_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB268_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB268_1 ; PPC64LE-NEXT: .LBB268_3: @@ -4535,14 +4511,14 @@ define i16 @test268(i16* %ptr, i16 %val) { define i16 @test269(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test269: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB269_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB269_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB269_1 ; PPC64LE-NEXT: .LBB269_3: @@ -4555,12 +4531,12 @@ define i16 @test269(i16* %ptr, i16 %val) { define i32 @test270(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test270: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB270_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB270_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB270_1 ; PPC64LE-NEXT: .LBB270_3: @@ -4572,13 +4548,13 @@ define i32 @test270(i32* %ptr, i32 %val) { define i32 @test271(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test271: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB271_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmpw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB271_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB271_1 ; PPC64LE-NEXT: .LBB271_3: @@ -4590,13 +4566,13 @@ define i32 @test271(i32* %ptr, i32 %val) { define i32 @test272(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test272: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB272_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB272_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB272_1 ; PPC64LE-NEXT: .LBB272_3: @@ -4608,13 +4584,13 @@ define i32 @test272(i32* %ptr, i32 %val) { define i32 @test273(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test273: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB273_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB273_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB273_1 ; PPC64LE-NEXT: .LBB273_3: @@ -4627,13 +4603,13 @@ define i32 @test273(i32* %ptr, i32 %val) { define i32 @test274(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test274: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB274_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB274_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB274_1 ; PPC64LE-NEXT: .LBB274_3: @@ -4646,12 +4622,12 @@ define i32 @test274(i32* %ptr, i32 %val) { define i64 @test275(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test275: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB275_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB275_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB275_1 ; PPC64LE-NEXT: .LBB275_3: @@ -4663,13 +4639,13 @@ define i64 @test275(i64* %ptr, i64 %val) { define i64 @test276(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test276: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB276_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpd 4, 3 ; PPC64LE-NEXT: ble 0, .LBB276_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB276_1 ; PPC64LE-NEXT: .LBB276_3: @@ -4681,13 +4657,13 @@ define i64 @test276(i64* %ptr, i64 %val) { define i64 @test277(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test277: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB277_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB277_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB277_1 ; PPC64LE-NEXT: .LBB277_3: @@ -4699,13 +4675,13 @@ define i64 @test277(i64* %ptr, i64 %val) { define i64 @test278(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test278: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB278_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB278_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB278_1 ; PPC64LE-NEXT: .LBB278_3: @@ -4718,13 +4694,13 @@ define i64 @test278(i64* %ptr, i64 %val) { define i64 @test279(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test279: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB279_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB279_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB279_1 ; PPC64LE-NEXT: .LBB279_3: @@ -4737,13 +4713,13 @@ define i64 @test279(i64* %ptr, i64 %val) { define i8 @test280(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test280: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB280_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB280_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB280_1 ; PPC64LE-NEXT: .LBB280_3: @@ -4755,14 +4731,14 @@ define i8 @test280(i8* %ptr, i8 %val) { define i8 @test281(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test281: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB281_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: extsb 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB281_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB281_1 ; PPC64LE-NEXT: .LBB281_3: @@ -4774,14 +4750,14 @@ define i8 @test281(i8* %ptr, i8 %val) { define i8 @test282(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test282: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB282_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB282_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB282_1 ; PPC64LE-NEXT: .LBB282_3: @@ -4793,14 +4769,14 @@ define i8 @test282(i8* %ptr, i8 %val) { define i8 @test283(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test283: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB283_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB283_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB283_1 ; PPC64LE-NEXT: .LBB283_3: @@ -4813,14 +4789,14 @@ define i8 @test283(i8* %ptr, i8 %val) { define i8 @test284(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test284: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB284_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB284_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB284_1 ; PPC64LE-NEXT: .LBB284_3: @@ -4833,13 +4809,13 @@ define i8 @test284(i8* %ptr, i8 %val) { define i16 @test285(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test285: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB285_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB285_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB285_1 ; PPC64LE-NEXT: .LBB285_3: @@ -4851,14 +4827,14 @@ define i16 @test285(i16* %ptr, i16 %val) { define i16 @test286(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test286: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB286_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: extsh 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB286_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB286_1 ; PPC64LE-NEXT: .LBB286_3: @@ -4870,14 +4846,14 @@ define i16 @test286(i16* %ptr, i16 %val) { define i16 @test287(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test287: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB287_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB287_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB287_1 ; PPC64LE-NEXT: .LBB287_3: @@ -4889,14 +4865,14 @@ define i16 @test287(i16* %ptr, i16 %val) { define i16 @test288(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test288: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB288_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB288_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB288_1 ; PPC64LE-NEXT: .LBB288_3: @@ -4909,14 +4885,14 @@ define i16 @test288(i16* %ptr, i16 %val) { define i16 @test289(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test289: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB289_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB289_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB289_1 ; PPC64LE-NEXT: .LBB289_3: @@ -4929,12 +4905,12 @@ define i16 @test289(i16* %ptr, i16 %val) { define i32 @test290(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test290: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB290_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB290_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB290_1 ; PPC64LE-NEXT: .LBB290_3: @@ -4946,13 +4922,13 @@ define i32 @test290(i32* %ptr, i32 %val) { define i32 @test291(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test291: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB291_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmpw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB291_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB291_1 ; PPC64LE-NEXT: .LBB291_3: @@ -4964,13 +4940,13 @@ define i32 @test291(i32* %ptr, i32 %val) { define i32 @test292(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test292: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB292_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB292_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB292_1 ; PPC64LE-NEXT: .LBB292_3: @@ -4982,13 +4958,13 @@ define i32 @test292(i32* %ptr, i32 %val) { define i32 @test293(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test293: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB293_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB293_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB293_1 ; PPC64LE-NEXT: .LBB293_3: @@ -5001,13 +4977,13 @@ define i32 @test293(i32* %ptr, i32 %val) { define i32 @test294(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test294: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB294_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB294_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB294_1 ; PPC64LE-NEXT: .LBB294_3: @@ -5020,12 +4996,12 @@ define i32 @test294(i32* %ptr, i32 %val) { define i64 @test295(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test295: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB295_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB295_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB295_1 ; PPC64LE-NEXT: .LBB295_3: @@ -5037,13 +5013,13 @@ define i64 @test295(i64* %ptr, i64 %val) { define i64 @test296(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test296: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB296_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpd 4, 3 ; PPC64LE-NEXT: bge 0, .LBB296_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB296_1 ; PPC64LE-NEXT: .LBB296_3: @@ -5055,13 +5031,13 @@ define i64 @test296(i64* %ptr, i64 %val) { define i64 @test297(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test297: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB297_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB297_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB297_1 ; PPC64LE-NEXT: .LBB297_3: @@ -5073,13 +5049,13 @@ define i64 @test297(i64* %ptr, i64 %val) { define i64 @test298(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test298: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB298_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB298_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB298_1 ; PPC64LE-NEXT: .LBB298_3: @@ -5092,13 +5068,13 @@ define i64 @test298(i64* %ptr, i64 %val) { define i64 @test299(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test299: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB299_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB299_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB299_1 ; PPC64LE-NEXT: .LBB299_3: @@ -5111,12 +5087,12 @@ define i64 @test299(i64* %ptr, i64 %val) { define i8 @test300(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test300: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB300_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB300_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB300_1 ; PPC64LE-NEXT: .LBB300_3: @@ -5128,13 +5104,13 @@ define i8 @test300(i8* %ptr, i8 %val) { define i8 @test301(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test301: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB301_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB301_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB301_1 ; PPC64LE-NEXT: .LBB301_3: @@ -5146,13 +5122,13 @@ define i8 @test301(i8* %ptr, i8 %val) { define i8 @test302(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test302: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB302_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB302_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB302_1 ; PPC64LE-NEXT: .LBB302_3: @@ -5164,13 +5140,13 @@ define i8 @test302(i8* %ptr, i8 %val) { define i8 @test303(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test303: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB303_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB303_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB303_1 ; PPC64LE-NEXT: .LBB303_3: @@ -5183,13 +5159,13 @@ define i8 @test303(i8* %ptr, i8 %val) { define i8 @test304(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test304: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB304_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB304_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB304_1 ; PPC64LE-NEXT: .LBB304_3: @@ -5202,12 +5178,12 @@ define i8 @test304(i8* %ptr, i8 %val) { define i16 @test305(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test305: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB305_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB305_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB305_1 ; PPC64LE-NEXT: .LBB305_3: @@ -5219,13 +5195,13 @@ define i16 @test305(i16* %ptr, i16 %val) { define i16 @test306(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test306: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB306_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB306_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB306_1 ; PPC64LE-NEXT: .LBB306_3: @@ -5237,13 +5213,13 @@ define i16 @test306(i16* %ptr, i16 %val) { define i16 @test307(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test307: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB307_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB307_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB307_1 ; PPC64LE-NEXT: .LBB307_3: @@ -5255,13 +5231,13 @@ define i16 @test307(i16* %ptr, i16 %val) { define i16 @test308(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test308: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB308_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB308_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB308_1 ; PPC64LE-NEXT: .LBB308_3: @@ -5274,13 +5250,13 @@ define i16 @test308(i16* %ptr, i16 %val) { define i16 @test309(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test309: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB309_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB309_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB309_1 ; PPC64LE-NEXT: .LBB309_3: @@ -5293,12 +5269,12 @@ define i16 @test309(i16* %ptr, i16 %val) { define i32 @test310(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test310: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB310_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB310_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB310_1 ; PPC64LE-NEXT: .LBB310_3: @@ -5310,13 +5286,13 @@ define i32 @test310(i32* %ptr, i32 %val) { define i32 @test311(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test311: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB311_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB311_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB311_1 ; PPC64LE-NEXT: .LBB311_3: @@ -5328,13 +5304,13 @@ define i32 @test311(i32* %ptr, i32 %val) { define i32 @test312(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test312: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB312_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB312_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB312_1 ; PPC64LE-NEXT: .LBB312_3: @@ -5346,13 +5322,13 @@ define i32 @test312(i32* %ptr, i32 %val) { define i32 @test313(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test313: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB313_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB313_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB313_1 ; PPC64LE-NEXT: .LBB313_3: @@ -5365,13 +5341,13 @@ define i32 @test313(i32* %ptr, i32 %val) { define i32 @test314(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test314: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB314_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB314_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB314_1 ; PPC64LE-NEXT: .LBB314_3: @@ -5384,12 +5360,12 @@ define i32 @test314(i32* %ptr, i32 %val) { define i64 @test315(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test315: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB315_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB315_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB315_1 ; PPC64LE-NEXT: .LBB315_3: @@ -5401,13 +5377,13 @@ define i64 @test315(i64* %ptr, i64 %val) { define i64 @test316(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test316: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB316_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpld 4, 3 ; PPC64LE-NEXT: ble 0, .LBB316_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB316_1 ; PPC64LE-NEXT: .LBB316_3: @@ -5419,13 +5395,13 @@ define i64 @test316(i64* %ptr, i64 %val) { define i64 @test317(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test317: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB317_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB317_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB317_1 ; PPC64LE-NEXT: .LBB317_3: @@ -5437,13 +5413,13 @@ define i64 @test317(i64* %ptr, i64 %val) { define i64 @test318(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test318: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB318_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB318_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB318_1 ; PPC64LE-NEXT: .LBB318_3: @@ -5456,13 +5432,13 @@ define i64 @test318(i64* %ptr, i64 %val) { define i64 @test319(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test319: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB319_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB319_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB319_1 ; PPC64LE-NEXT: .LBB319_3: @@ -5475,12 +5451,12 @@ define i64 @test319(i64* %ptr, i64 %val) { define i8 @test320(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test320: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB320_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB320_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB320_1 ; PPC64LE-NEXT: .LBB320_3: @@ -5492,13 +5468,13 @@ define i8 @test320(i8* %ptr, i8 %val) { define i8 @test321(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test321: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB321_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB321_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB321_1 ; PPC64LE-NEXT: .LBB321_3: @@ -5510,13 +5486,13 @@ define i8 @test321(i8* %ptr, i8 %val) { define i8 @test322(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test322: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB322_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB322_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB322_1 ; PPC64LE-NEXT: .LBB322_3: @@ -5528,13 +5504,13 @@ define i8 @test322(i8* %ptr, i8 %val) { define i8 @test323(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test323: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB323_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB323_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB323_1 ; PPC64LE-NEXT: .LBB323_3: @@ -5547,13 +5523,13 @@ define i8 @test323(i8* %ptr, i8 %val) { define i8 @test324(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test324: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB324_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB324_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB324_1 ; PPC64LE-NEXT: .LBB324_3: @@ -5566,12 +5542,12 @@ define i8 @test324(i8* %ptr, i8 %val) { define i16 @test325(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test325: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB325_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB325_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB325_1 ; PPC64LE-NEXT: .LBB325_3: @@ -5583,13 +5559,13 @@ define i16 @test325(i16* %ptr, i16 %val) { define i16 @test326(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test326: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB326_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB326_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB326_1 ; PPC64LE-NEXT: .LBB326_3: @@ -5601,13 +5577,13 @@ define i16 @test326(i16* %ptr, i16 %val) { define i16 @test327(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test327: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB327_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB327_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB327_1 ; PPC64LE-NEXT: .LBB327_3: @@ -5619,13 +5595,13 @@ define i16 @test327(i16* %ptr, i16 %val) { define i16 @test328(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test328: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB328_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB328_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB328_1 ; PPC64LE-NEXT: .LBB328_3: @@ -5638,13 +5614,13 @@ define i16 @test328(i16* %ptr, i16 %val) { define i16 @test329(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test329: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB329_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB329_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB329_1 ; PPC64LE-NEXT: .LBB329_3: @@ -5657,12 +5633,12 @@ define i16 @test329(i16* %ptr, i16 %val) { define i32 @test330(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test330: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB330_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB330_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB330_1 ; PPC64LE-NEXT: .LBB330_3: @@ -5674,13 +5650,13 @@ define i32 @test330(i32* %ptr, i32 %val) { define i32 @test331(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test331: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB331_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB331_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB331_1 ; PPC64LE-NEXT: .LBB331_3: @@ -5692,13 +5668,13 @@ define i32 @test331(i32* %ptr, i32 %val) { define i32 @test332(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test332: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB332_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB332_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB332_1 ; PPC64LE-NEXT: .LBB332_3: @@ -5710,13 +5686,13 @@ define i32 @test332(i32* %ptr, i32 %val) { define i32 @test333(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test333: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB333_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB333_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB333_1 ; PPC64LE-NEXT: .LBB333_3: @@ -5729,13 +5705,13 @@ define i32 @test333(i32* %ptr, i32 %val) { define i32 @test334(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test334: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB334_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB334_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB334_1 ; PPC64LE-NEXT: .LBB334_3: @@ -5748,12 +5724,12 @@ define i32 @test334(i32* %ptr, i32 %val) { define i64 @test335(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test335: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB335_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB335_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB335_1 ; PPC64LE-NEXT: .LBB335_3: @@ -5765,13 +5741,13 @@ define i64 @test335(i64* %ptr, i64 %val) { define i64 @test336(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test336: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB336_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpld 4, 3 ; PPC64LE-NEXT: bge 0, .LBB336_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB336_1 ; PPC64LE-NEXT: .LBB336_3: @@ -5783,13 +5759,13 @@ define i64 @test336(i64* %ptr, i64 %val) { define i64 @test337(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test337: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB337_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB337_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB337_1 ; PPC64LE-NEXT: .LBB337_3: @@ -5801,13 +5777,13 @@ define i64 @test337(i64* %ptr, i64 %val) { define i64 @test338(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test338: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB338_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB338_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB338_1 ; PPC64LE-NEXT: .LBB338_3: @@ -5820,13 +5796,13 @@ define i64 @test338(i64* %ptr, i64 %val) { define i64 @test339(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test339: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB339_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB339_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB339_1 ; PPC64LE-NEXT: .LBB339_3: @@ -5839,12 +5815,12 @@ define i64 @test339(i64* %ptr, i64 %val) { define i8 @test340(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test340: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB340_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB340_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") monotonic @@ -5853,13 +5829,13 @@ define i8 @test340(i8* %ptr, i8 %val) { define i8 @test341(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test341: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB341_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB341_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") acquire @@ -5868,13 +5844,13 @@ define i8 @test341(i8* %ptr, i8 %val) { define i8 @test342(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test342: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB342_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB342_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") release @@ -5883,13 +5859,13 @@ define i8 @test342(i8* %ptr, i8 %val) { define i8 @test343(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test343: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB343_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB343_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5899,13 +5875,13 @@ define i8 @test343(i8* %ptr, i8 %val) { define i8 @test344(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test344: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB344_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB344_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5915,12 +5891,12 @@ define i8 @test344(i8* %ptr, i8 %val) { define i16 @test345(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test345: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB345_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB345_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") monotonic @@ -5929,13 +5905,13 @@ define i16 @test345(i16* %ptr, i16 %val) { define i16 @test346(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test346: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB346_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB346_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") acquire @@ -5944,13 +5920,13 @@ define i16 @test346(i16* %ptr, i16 %val) { define i16 @test347(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test347: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB347_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB347_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") release @@ -5959,13 +5935,13 @@ define i16 @test347(i16* %ptr, i16 %val) { define i16 @test348(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test348: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB348_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB348_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5975,13 +5951,13 @@ define i16 @test348(i16* %ptr, i16 %val) { define i16 @test349(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test349: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB349_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB349_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5991,12 +5967,12 @@ define i16 @test349(i16* %ptr, i16 %val) { define i32 @test350(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test350: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB350_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB350_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") monotonic @@ -6005,13 +5981,13 @@ define i32 @test350(i32* %ptr, i32 %val) { define i32 @test351(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test351: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB351_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB351_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") acquire @@ -6020,13 +5996,13 @@ define i32 @test351(i32* %ptr, i32 %val) { define i32 @test352(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test352: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB352_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB352_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") release @@ -6035,13 +6011,13 @@ define i32 @test352(i32* %ptr, i32 %val) { define i32 @test353(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test353: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB353_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB353_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6051,13 +6027,13 @@ define i32 @test353(i32* %ptr, i32 %val) { define i32 @test354(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test354: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB354_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB354_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6067,12 +6043,12 @@ define i32 @test354(i32* %ptr, i32 %val) { define i64 @test355(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test355: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB355_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB355_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") monotonic @@ -6081,13 +6057,13 @@ define i64 @test355(i64* %ptr, i64 %val) { define i64 @test356(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test356: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB356_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB356_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") acquire @@ -6096,13 +6072,13 @@ define i64 @test356(i64* %ptr, i64 %val) { define i64 @test357(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test357: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB357_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB357_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") release @@ -6111,13 +6087,13 @@ define i64 @test357(i64* %ptr, i64 %val) { define i64 @test358(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test358: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB358_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB358_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6127,13 +6103,13 @@ define i64 @test358(i64* %ptr, i64 %val) { define i64 @test359(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test359: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB359_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB359_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6143,13 +6119,13 @@ define i64 @test359(i64* %ptr, i64 %val) { define i8 @test360(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test360: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB360_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB360_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") monotonic @@ -6158,14 +6134,14 @@ define i8 @test360(i8* %ptr, i8 %val) { define i8 @test361(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test361: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB361_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB361_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") acquire @@ -6174,14 +6150,14 @@ define i8 @test361(i8* %ptr, i8 %val) { define i8 @test362(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test362: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB362_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB362_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") release @@ -6190,14 +6166,14 @@ define i8 @test362(i8* %ptr, i8 %val) { define i8 @test363(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test363: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB363_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB363_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6207,14 +6183,14 @@ define i8 @test363(i8* %ptr, i8 %val) { define i8 @test364(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test364: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB364_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB364_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6224,13 +6200,13 @@ define i8 @test364(i8* %ptr, i8 %val) { define i16 @test365(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test365: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB365_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB365_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") monotonic @@ -6239,14 +6215,14 @@ define i16 @test365(i16* %ptr, i16 %val) { define i16 @test366(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test366: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB366_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB366_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") acquire @@ -6255,14 +6231,14 @@ define i16 @test366(i16* %ptr, i16 %val) { define i16 @test367(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test367: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB367_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB367_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") release @@ -6271,14 +6247,14 @@ define i16 @test367(i16* %ptr, i16 %val) { define i16 @test368(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test368: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB368_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB368_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6288,14 +6264,14 @@ define i16 @test368(i16* %ptr, i16 %val) { define i16 @test369(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test369: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB369_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB369_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6305,13 +6281,13 @@ define i16 @test369(i16* %ptr, i16 %val) { define i32 @test370(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test370: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB370_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB370_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") monotonic @@ -6320,14 +6296,14 @@ define i32 @test370(i32* %ptr, i32 %val) { define i32 @test371(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test371: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB371_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB371_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") acquire @@ -6336,14 +6312,14 @@ define i32 @test371(i32* %ptr, i32 %val) { define i32 @test372(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test372: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB372_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB372_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") release @@ -6352,14 +6328,14 @@ define i32 @test372(i32* %ptr, i32 %val) { define i32 @test373(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test373: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB373_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB373_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6369,14 +6345,14 @@ define i32 @test373(i32* %ptr, i32 %val) { define i32 @test374(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test374: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB374_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB374_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6386,13 +6362,13 @@ define i32 @test374(i32* %ptr, i32 %val) { define i64 @test375(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test375: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB375_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB375_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") monotonic @@ -6401,14 +6377,14 @@ define i64 @test375(i64* %ptr, i64 %val) { define i64 @test376(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test376: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB376_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB376_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") acquire @@ -6417,14 +6393,14 @@ define i64 @test376(i64* %ptr, i64 %val) { define i64 @test377(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test377: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB377_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB377_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") release @@ -6433,14 +6409,14 @@ define i64 @test377(i64* %ptr, i64 %val) { define i64 @test378(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test378: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB378_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB378_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6450,14 +6426,14 @@ define i64 @test378(i64* %ptr, i64 %val) { define i64 @test379(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test379: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB379_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB379_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6467,13 +6443,13 @@ define i64 @test379(i64* %ptr, i64 %val) { define i8 @test380(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test380: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB380_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB380_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") monotonic @@ -6482,14 +6458,14 @@ define i8 @test380(i8* %ptr, i8 %val) { define i8 @test381(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test381: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB381_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: subf 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB381_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") acquire @@ -6498,14 +6474,14 @@ define i8 @test381(i8* %ptr, i8 %val) { define i8 @test382(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test382: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB382_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB382_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") release @@ -6514,14 +6490,14 @@ define i8 @test382(i8* %ptr, i8 %val) { define i8 @test383(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test383: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB383_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB383_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6531,14 +6507,14 @@ define i8 @test383(i8* %ptr, i8 %val) { define i8 @test384(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test384: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB384_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB384_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6548,13 +6524,13 @@ define i8 @test384(i8* %ptr, i8 %val) { define i16 @test385(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test385: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB385_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB385_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") monotonic @@ -6563,14 +6539,14 @@ define i16 @test385(i16* %ptr, i16 %val) { define i16 @test386(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test386: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB386_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: subf 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB386_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") acquire @@ -6579,14 +6555,14 @@ define i16 @test386(i16* %ptr, i16 %val) { define i16 @test387(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test387: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB387_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB387_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") release @@ -6595,14 +6571,14 @@ define i16 @test387(i16* %ptr, i16 %val) { define i16 @test388(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test388: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB388_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB388_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6612,14 +6588,14 @@ define i16 @test388(i16* %ptr, i16 %val) { define i16 @test389(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test389: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB389_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB389_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6629,13 +6605,13 @@ define i16 @test389(i16* %ptr, i16 %val) { define i32 @test390(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test390: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB390_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB390_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") monotonic @@ -6644,14 +6620,14 @@ define i32 @test390(i32* %ptr, i32 %val) { define i32 @test391(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test391: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB391_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: subf 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB391_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") acquire @@ -6660,14 +6636,14 @@ define i32 @test391(i32* %ptr, i32 %val) { define i32 @test392(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test392: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB392_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB392_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") release @@ -6676,14 +6652,14 @@ define i32 @test392(i32* %ptr, i32 %val) { define i32 @test393(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test393: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB393_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB393_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6693,14 +6669,14 @@ define i32 @test393(i32* %ptr, i32 %val) { define i32 @test394(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test394: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB394_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB394_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6710,13 +6686,13 @@ define i32 @test394(i32* %ptr, i32 %val) { define i64 @test395(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test395: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB395_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB395_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") monotonic @@ -6725,14 +6701,14 @@ define i64 @test395(i64* %ptr, i64 %val) { define i64 @test396(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test396: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB396_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: sub 6, 3, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB396_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") acquire @@ -6741,14 +6717,14 @@ define i64 @test396(i64* %ptr, i64 %val) { define i64 @test397(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test397: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB397_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB397_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") release @@ -6757,14 +6733,14 @@ define i64 @test397(i64* %ptr, i64 %val) { define i64 @test398(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test398: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB398_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB398_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6774,14 +6750,14 @@ define i64 @test398(i64* %ptr, i64 %val) { define i64 @test399(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test399: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB399_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB399_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6791,13 +6767,13 @@ define i64 @test399(i64* %ptr, i64 %val) { define i8 @test400(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test400: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB400_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB400_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") monotonic @@ -6806,14 +6782,14 @@ define i8 @test400(i8* %ptr, i8 %val) { define i8 @test401(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test401: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB401_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB401_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") acquire @@ -6822,14 +6798,14 @@ define i8 @test401(i8* %ptr, i8 %val) { define i8 @test402(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test402: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB402_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB402_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") release @@ -6838,14 +6814,14 @@ define i8 @test402(i8* %ptr, i8 %val) { define i8 @test403(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test403: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB403_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB403_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6855,14 +6831,14 @@ define i8 @test403(i8* %ptr, i8 %val) { define i8 @test404(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test404: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB404_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB404_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6872,13 +6848,13 @@ define i8 @test404(i8* %ptr, i8 %val) { define i16 @test405(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test405: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB405_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB405_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") monotonic @@ -6887,14 +6863,14 @@ define i16 @test405(i16* %ptr, i16 %val) { define i16 @test406(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test406: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB406_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB406_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") acquire @@ -6903,14 +6879,14 @@ define i16 @test406(i16* %ptr, i16 %val) { define i16 @test407(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test407: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB407_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB407_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") release @@ -6919,14 +6895,14 @@ define i16 @test407(i16* %ptr, i16 %val) { define i16 @test408(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test408: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB408_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB408_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6936,14 +6912,14 @@ define i16 @test408(i16* %ptr, i16 %val) { define i16 @test409(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test409: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB409_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB409_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6953,13 +6929,13 @@ define i16 @test409(i16* %ptr, i16 %val) { define i32 @test410(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test410: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB410_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB410_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") monotonic @@ -6968,14 +6944,14 @@ define i32 @test410(i32* %ptr, i32 %val) { define i32 @test411(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test411: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB411_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB411_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") acquire @@ -6984,14 +6960,14 @@ define i32 @test411(i32* %ptr, i32 %val) { define i32 @test412(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test412: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB412_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB412_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") release @@ -7000,14 +6976,14 @@ define i32 @test412(i32* %ptr, i32 %val) { define i32 @test413(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test413: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB413_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB413_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7017,14 +6993,14 @@ define i32 @test413(i32* %ptr, i32 %val) { define i32 @test414(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test414: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB414_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB414_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7034,13 +7010,13 @@ define i32 @test414(i32* %ptr, i32 %val) { define i64 @test415(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test415: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB415_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB415_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") monotonic @@ -7049,14 +7025,14 @@ define i64 @test415(i64* %ptr, i64 %val) { define i64 @test416(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test416: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB416_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB416_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") acquire @@ -7065,14 +7041,14 @@ define i64 @test416(i64* %ptr, i64 %val) { define i64 @test417(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test417: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB417_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB417_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") release @@ -7081,14 +7057,14 @@ define i64 @test417(i64* %ptr, i64 %val) { define i64 @test418(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test418: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB418_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB418_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7098,14 +7074,14 @@ define i64 @test418(i64* %ptr, i64 %val) { define i64 @test419(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test419: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB419_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB419_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7115,13 +7091,13 @@ define i64 @test419(i64* %ptr, i64 %val) { define i8 @test420(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test420: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB420_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB420_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") monotonic @@ -7130,14 +7106,14 @@ define i8 @test420(i8* %ptr, i8 %val) { define i8 @test421(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test421: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB421_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB421_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") acquire @@ -7146,14 +7122,14 @@ define i8 @test421(i8* %ptr, i8 %val) { define i8 @test422(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test422: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB422_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB422_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") release @@ -7162,14 +7138,14 @@ define i8 @test422(i8* %ptr, i8 %val) { define i8 @test423(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test423: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB423_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB423_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7179,14 +7155,14 @@ define i8 @test423(i8* %ptr, i8 %val) { define i8 @test424(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test424: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB424_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB424_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7196,13 +7172,13 @@ define i8 @test424(i8* %ptr, i8 %val) { define i16 @test425(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test425: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB425_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB425_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") monotonic @@ -7211,14 +7187,14 @@ define i16 @test425(i16* %ptr, i16 %val) { define i16 @test426(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test426: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB426_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB426_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") acquire @@ -7227,14 +7203,14 @@ define i16 @test426(i16* %ptr, i16 %val) { define i16 @test427(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test427: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB427_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB427_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") release @@ -7243,14 +7219,14 @@ define i16 @test427(i16* %ptr, i16 %val) { define i16 @test428(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test428: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB428_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB428_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7260,14 +7236,14 @@ define i16 @test428(i16* %ptr, i16 %val) { define i16 @test429(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test429: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB429_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB429_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7277,13 +7253,13 @@ define i16 @test429(i16* %ptr, i16 %val) { define i32 @test430(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test430: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB430_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB430_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") monotonic @@ -7292,14 +7268,14 @@ define i32 @test430(i32* %ptr, i32 %val) { define i32 @test431(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test431: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB431_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB431_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") acquire @@ -7308,14 +7284,14 @@ define i32 @test431(i32* %ptr, i32 %val) { define i32 @test432(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test432: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB432_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB432_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") release @@ -7324,14 +7300,14 @@ define i32 @test432(i32* %ptr, i32 %val) { define i32 @test433(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test433: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB433_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB433_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7341,14 +7317,14 @@ define i32 @test433(i32* %ptr, i32 %val) { define i32 @test434(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test434: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB434_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB434_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7358,13 +7334,13 @@ define i32 @test434(i32* %ptr, i32 %val) { define i64 @test435(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test435: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB435_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB435_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") monotonic @@ -7373,14 +7349,14 @@ define i64 @test435(i64* %ptr, i64 %val) { define i64 @test436(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test436: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB436_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB436_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") acquire @@ -7389,14 +7365,14 @@ define i64 @test436(i64* %ptr, i64 %val) { define i64 @test437(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test437: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB437_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB437_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") release @@ -7405,14 +7381,14 @@ define i64 @test437(i64* %ptr, i64 %val) { define i64 @test438(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test438: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB438_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB438_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7422,14 +7398,14 @@ define i64 @test438(i64* %ptr, i64 %val) { define i64 @test439(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test439: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB439_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB439_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7439,13 +7415,13 @@ define i64 @test439(i64* %ptr, i64 %val) { define i8 @test440(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test440: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB440_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB440_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") monotonic @@ -7454,14 +7430,14 @@ define i8 @test440(i8* %ptr, i8 %val) { define i8 @test441(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test441: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB441_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB441_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") acquire @@ -7470,14 +7446,14 @@ define i8 @test441(i8* %ptr, i8 %val) { define i8 @test442(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test442: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB442_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB442_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") release @@ -7486,14 +7462,14 @@ define i8 @test442(i8* %ptr, i8 %val) { define i8 @test443(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test443: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB443_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB443_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7503,14 +7479,14 @@ define i8 @test443(i8* %ptr, i8 %val) { define i8 @test444(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test444: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB444_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB444_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7520,13 +7496,13 @@ define i8 @test444(i8* %ptr, i8 %val) { define i16 @test445(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test445: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB445_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB445_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") monotonic @@ -7535,14 +7511,14 @@ define i16 @test445(i16* %ptr, i16 %val) { define i16 @test446(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test446: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB446_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB446_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") acquire @@ -7551,14 +7527,14 @@ define i16 @test446(i16* %ptr, i16 %val) { define i16 @test447(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test447: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB447_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB447_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") release @@ -7567,14 +7543,14 @@ define i16 @test447(i16* %ptr, i16 %val) { define i16 @test448(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test448: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB448_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB448_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7584,14 +7560,14 @@ define i16 @test448(i16* %ptr, i16 %val) { define i16 @test449(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test449: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB449_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB449_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7601,13 +7577,13 @@ define i16 @test449(i16* %ptr, i16 %val) { define i32 @test450(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test450: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB450_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB450_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") monotonic @@ -7616,14 +7592,14 @@ define i32 @test450(i32* %ptr, i32 %val) { define i32 @test451(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test451: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB451_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB451_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") acquire @@ -7632,14 +7608,14 @@ define i32 @test451(i32* %ptr, i32 %val) { define i32 @test452(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test452: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB452_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB452_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") release @@ -7648,14 +7624,14 @@ define i32 @test452(i32* %ptr, i32 %val) { define i32 @test453(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test453: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB453_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB453_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7665,14 +7641,14 @@ define i32 @test453(i32* %ptr, i32 %val) { define i32 @test454(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test454: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB454_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB454_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7682,13 +7658,13 @@ define i32 @test454(i32* %ptr, i32 %val) { define i64 @test455(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test455: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB455_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB455_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") monotonic @@ -7697,14 +7673,14 @@ define i64 @test455(i64* %ptr, i64 %val) { define i64 @test456(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test456: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB456_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB456_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") acquire @@ -7713,14 +7689,14 @@ define i64 @test456(i64* %ptr, i64 %val) { define i64 @test457(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test457: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB457_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB457_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") release @@ -7729,14 +7705,14 @@ define i64 @test457(i64* %ptr, i64 %val) { define i64 @test458(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test458: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB458_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB458_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7746,14 +7722,14 @@ define i64 @test458(i64* %ptr, i64 %val) { define i64 @test459(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test459: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB459_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB459_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7763,13 +7739,13 @@ define i64 @test459(i64* %ptr, i64 %val) { define i8 @test460(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test460: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB460_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB460_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") monotonic @@ -7778,14 +7754,14 @@ define i8 @test460(i8* %ptr, i8 %val) { define i8 @test461(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test461: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB461_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB461_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") acquire @@ -7794,14 +7770,14 @@ define i8 @test461(i8* %ptr, i8 %val) { define i8 @test462(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test462: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB462_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB462_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") release @@ -7810,14 +7786,14 @@ define i8 @test462(i8* %ptr, i8 %val) { define i8 @test463(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test463: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB463_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB463_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7827,14 +7803,14 @@ define i8 @test463(i8* %ptr, i8 %val) { define i8 @test464(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test464: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB464_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB464_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7844,13 +7820,13 @@ define i8 @test464(i8* %ptr, i8 %val) { define i16 @test465(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test465: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB465_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB465_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") monotonic @@ -7859,14 +7835,14 @@ define i16 @test465(i16* %ptr, i16 %val) { define i16 @test466(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test466: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB466_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB466_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") acquire @@ -7875,14 +7851,14 @@ define i16 @test466(i16* %ptr, i16 %val) { define i16 @test467(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test467: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB467_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB467_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") release @@ -7891,14 +7867,14 @@ define i16 @test467(i16* %ptr, i16 %val) { define i16 @test468(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test468: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB468_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB468_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7908,14 +7884,14 @@ define i16 @test468(i16* %ptr, i16 %val) { define i16 @test469(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test469: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB469_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB469_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7925,13 +7901,13 @@ define i16 @test469(i16* %ptr, i16 %val) { define i32 @test470(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test470: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB470_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB470_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") monotonic @@ -7940,14 +7916,14 @@ define i32 @test470(i32* %ptr, i32 %val) { define i32 @test471(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test471: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB471_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB471_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") acquire @@ -7956,14 +7932,14 @@ define i32 @test471(i32* %ptr, i32 %val) { define i32 @test472(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test472: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB472_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB472_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") release @@ -7972,14 +7948,14 @@ define i32 @test472(i32* %ptr, i32 %val) { define i32 @test473(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test473: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB473_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB473_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7989,14 +7965,14 @@ define i32 @test473(i32* %ptr, i32 %val) { define i32 @test474(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test474: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB474_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB474_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -8006,13 +7982,13 @@ define i32 @test474(i32* %ptr, i32 %val) { define i64 @test475(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test475: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB475_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB475_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") monotonic @@ -8021,14 +7997,14 @@ define i64 @test475(i64* %ptr, i64 %val) { define i64 @test476(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test476: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB476_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB476_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") acquire @@ -8037,14 +8013,14 @@ define i64 @test476(i64* %ptr, i64 %val) { define i64 @test477(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test477: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB477_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB477_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") release @@ -8053,14 +8029,14 @@ define i64 @test477(i64* %ptr, i64 %val) { define i64 @test478(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test478: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB478_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB478_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -8070,14 +8046,14 @@ define i64 @test478(i64* %ptr, i64 %val) { define i64 @test479(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test479: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB479_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB479_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -8087,13 +8063,13 @@ define i64 @test479(i64* %ptr, i64 %val) { define i8 @test480(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test480: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB480_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB480_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB480_1 ; PPC64LE-NEXT: .LBB480_3: @@ -8105,14 +8081,14 @@ define i8 @test480(i8* %ptr, i8 %val) { define i8 @test481(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test481: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB481_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: extsb 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB481_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB481_1 ; PPC64LE-NEXT: .LBB481_3: @@ -8124,14 +8100,14 @@ define i8 @test481(i8* %ptr, i8 %val) { define i8 @test482(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test482: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB482_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB482_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB482_1 ; PPC64LE-NEXT: .LBB482_3: @@ -8143,14 +8119,14 @@ define i8 @test482(i8* %ptr, i8 %val) { define i8 @test483(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test483: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB483_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB483_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB483_1 ; PPC64LE-NEXT: .LBB483_3: @@ -8163,14 +8139,14 @@ define i8 @test483(i8* %ptr, i8 %val) { define i8 @test484(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test484: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB484_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB484_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB484_1 ; PPC64LE-NEXT: .LBB484_3: @@ -8183,13 +8159,13 @@ define i8 @test484(i8* %ptr, i8 %val) { define i16 @test485(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test485: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB485_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB485_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB485_1 ; PPC64LE-NEXT: .LBB485_3: @@ -8201,14 +8177,14 @@ define i16 @test485(i16* %ptr, i16 %val) { define i16 @test486(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test486: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB486_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: extsh 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB486_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB486_1 ; PPC64LE-NEXT: .LBB486_3: @@ -8220,14 +8196,14 @@ define i16 @test486(i16* %ptr, i16 %val) { define i16 @test487(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test487: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB487_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB487_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB487_1 ; PPC64LE-NEXT: .LBB487_3: @@ -8239,14 +8215,14 @@ define i16 @test487(i16* %ptr, i16 %val) { define i16 @test488(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test488: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB488_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB488_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB488_1 ; PPC64LE-NEXT: .LBB488_3: @@ -8259,14 +8235,14 @@ define i16 @test488(i16* %ptr, i16 %val) { define i16 @test489(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test489: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB489_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB489_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB489_1 ; PPC64LE-NEXT: .LBB489_3: @@ -8279,12 +8255,12 @@ define i16 @test489(i16* %ptr, i16 %val) { define i32 @test490(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test490: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB490_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB490_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB490_1 ; PPC64LE-NEXT: .LBB490_3: @@ -8296,13 +8272,13 @@ define i32 @test490(i32* %ptr, i32 %val) { define i32 @test491(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test491: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB491_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmpw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB491_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB491_1 ; PPC64LE-NEXT: .LBB491_3: @@ -8314,13 +8290,13 @@ define i32 @test491(i32* %ptr, i32 %val) { define i32 @test492(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test492: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB492_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB492_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB492_1 ; PPC64LE-NEXT: .LBB492_3: @@ -8332,13 +8308,13 @@ define i32 @test492(i32* %ptr, i32 %val) { define i32 @test493(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test493: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB493_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB493_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB493_1 ; PPC64LE-NEXT: .LBB493_3: @@ -8351,13 +8327,13 @@ define i32 @test493(i32* %ptr, i32 %val) { define i32 @test494(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test494: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB494_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB494_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB494_1 ; PPC64LE-NEXT: .LBB494_3: @@ -8370,12 +8346,12 @@ define i32 @test494(i32* %ptr, i32 %val) { define i64 @test495(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test495: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB495_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB495_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB495_1 ; PPC64LE-NEXT: .LBB495_3: @@ -8387,13 +8363,13 @@ define i64 @test495(i64* %ptr, i64 %val) { define i64 @test496(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test496: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB496_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpd 4, 3 ; PPC64LE-NEXT: ble 0, .LBB496_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB496_1 ; PPC64LE-NEXT: .LBB496_3: @@ -8405,13 +8381,13 @@ define i64 @test496(i64* %ptr, i64 %val) { define i64 @test497(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test497: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB497_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB497_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB497_1 ; PPC64LE-NEXT: .LBB497_3: @@ -8423,13 +8399,13 @@ define i64 @test497(i64* %ptr, i64 %val) { define i64 @test498(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test498: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB498_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB498_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB498_1 ; PPC64LE-NEXT: .LBB498_3: @@ -8442,13 +8418,13 @@ define i64 @test498(i64* %ptr, i64 %val) { define i64 @test499(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test499: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB499_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB499_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB499_1 ; PPC64LE-NEXT: .LBB499_3: @@ -8461,13 +8437,13 @@ define i64 @test499(i64* %ptr, i64 %val) { define i8 @test500(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test500: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB500_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB500_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB500_1 ; PPC64LE-NEXT: .LBB500_3: @@ -8479,14 +8455,14 @@ define i8 @test500(i8* %ptr, i8 %val) { define i8 @test501(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test501: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB501_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: extsb 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB501_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB501_1 ; PPC64LE-NEXT: .LBB501_3: @@ -8498,14 +8474,14 @@ define i8 @test501(i8* %ptr, i8 %val) { define i8 @test502(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test502: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB502_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB502_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB502_1 ; PPC64LE-NEXT: .LBB502_3: @@ -8517,14 +8493,14 @@ define i8 @test502(i8* %ptr, i8 %val) { define i8 @test503(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test503: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB503_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB503_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB503_1 ; PPC64LE-NEXT: .LBB503_3: @@ -8537,14 +8513,14 @@ define i8 @test503(i8* %ptr, i8 %val) { define i8 @test504(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test504: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB504_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB504_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB504_1 ; PPC64LE-NEXT: .LBB504_3: @@ -8557,13 +8533,13 @@ define i8 @test504(i8* %ptr, i8 %val) { define i16 @test505(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test505: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB505_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB505_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB505_1 ; PPC64LE-NEXT: .LBB505_3: @@ -8575,14 +8551,14 @@ define i16 @test505(i16* %ptr, i16 %val) { define i16 @test506(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test506: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB506_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: extsh 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB506_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB506_1 ; PPC64LE-NEXT: .LBB506_3: @@ -8594,14 +8570,14 @@ define i16 @test506(i16* %ptr, i16 %val) { define i16 @test507(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test507: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB507_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB507_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB507_1 ; PPC64LE-NEXT: .LBB507_3: @@ -8613,14 +8589,14 @@ define i16 @test507(i16* %ptr, i16 %val) { define i16 @test508(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test508: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB508_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB508_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB508_1 ; PPC64LE-NEXT: .LBB508_3: @@ -8633,14 +8609,14 @@ define i16 @test508(i16* %ptr, i16 %val) { define i16 @test509(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test509: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB509_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB509_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB509_1 ; PPC64LE-NEXT: .LBB509_3: @@ -8653,12 +8629,12 @@ define i16 @test509(i16* %ptr, i16 %val) { define i32 @test510(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test510: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB510_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB510_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB510_1 ; PPC64LE-NEXT: .LBB510_3: @@ -8670,13 +8646,13 @@ define i32 @test510(i32* %ptr, i32 %val) { define i32 @test511(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test511: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB511_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmpw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB511_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB511_1 ; PPC64LE-NEXT: .LBB511_3: @@ -8688,13 +8664,13 @@ define i32 @test511(i32* %ptr, i32 %val) { define i32 @test512(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test512: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB512_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB512_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB512_1 ; PPC64LE-NEXT: .LBB512_3: @@ -8706,13 +8682,13 @@ define i32 @test512(i32* %ptr, i32 %val) { define i32 @test513(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test513: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB513_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB513_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB513_1 ; PPC64LE-NEXT: .LBB513_3: @@ -8725,13 +8701,13 @@ define i32 @test513(i32* %ptr, i32 %val) { define i32 @test514(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test514: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB514_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB514_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB514_1 ; PPC64LE-NEXT: .LBB514_3: @@ -8744,12 +8720,12 @@ define i32 @test514(i32* %ptr, i32 %val) { define i64 @test515(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test515: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB515_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB515_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB515_1 ; PPC64LE-NEXT: .LBB515_3: @@ -8761,13 +8737,13 @@ define i64 @test515(i64* %ptr, i64 %val) { define i64 @test516(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test516: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB516_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpd 4, 3 ; PPC64LE-NEXT: bge 0, .LBB516_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB516_1 ; PPC64LE-NEXT: .LBB516_3: @@ -8779,13 +8755,13 @@ define i64 @test516(i64* %ptr, i64 %val) { define i64 @test517(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test517: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB517_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB517_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB517_1 ; PPC64LE-NEXT: .LBB517_3: @@ -8797,13 +8773,13 @@ define i64 @test517(i64* %ptr, i64 %val) { define i64 @test518(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test518: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB518_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB518_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB518_1 ; PPC64LE-NEXT: .LBB518_3: @@ -8816,13 +8792,13 @@ define i64 @test518(i64* %ptr, i64 %val) { define i64 @test519(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test519: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB519_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB519_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB519_1 ; PPC64LE-NEXT: .LBB519_3: @@ -8835,12 +8811,12 @@ define i64 @test519(i64* %ptr, i64 %val) { define i8 @test520(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test520: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB520_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB520_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB520_1 ; PPC64LE-NEXT: .LBB520_3: @@ -8852,13 +8828,13 @@ define i8 @test520(i8* %ptr, i8 %val) { define i8 @test521(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test521: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB521_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB521_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB521_1 ; PPC64LE-NEXT: .LBB521_3: @@ -8870,13 +8846,13 @@ define i8 @test521(i8* %ptr, i8 %val) { define i8 @test522(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test522: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB522_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB522_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB522_1 ; PPC64LE-NEXT: .LBB522_3: @@ -8888,13 +8864,13 @@ define i8 @test522(i8* %ptr, i8 %val) { define i8 @test523(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test523: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB523_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB523_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB523_1 ; PPC64LE-NEXT: .LBB523_3: @@ -8907,13 +8883,13 @@ define i8 @test523(i8* %ptr, i8 %val) { define i8 @test524(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test524: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB524_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB524_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB524_1 ; PPC64LE-NEXT: .LBB524_3: @@ -8926,12 +8902,12 @@ define i8 @test524(i8* %ptr, i8 %val) { define i16 @test525(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test525: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB525_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB525_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB525_1 ; PPC64LE-NEXT: .LBB525_3: @@ -8943,13 +8919,13 @@ define i16 @test525(i16* %ptr, i16 %val) { define i16 @test526(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test526: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB526_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB526_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB526_1 ; PPC64LE-NEXT: .LBB526_3: @@ -8961,13 +8937,13 @@ define i16 @test526(i16* %ptr, i16 %val) { define i16 @test527(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test527: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB527_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB527_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB527_1 ; PPC64LE-NEXT: .LBB527_3: @@ -8979,13 +8955,13 @@ define i16 @test527(i16* %ptr, i16 %val) { define i16 @test528(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test528: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB528_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB528_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB528_1 ; PPC64LE-NEXT: .LBB528_3: @@ -8998,13 +8974,13 @@ define i16 @test528(i16* %ptr, i16 %val) { define i16 @test529(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test529: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB529_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB529_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB529_1 ; PPC64LE-NEXT: .LBB529_3: @@ -9017,12 +8993,12 @@ define i16 @test529(i16* %ptr, i16 %val) { define i32 @test530(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test530: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB530_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB530_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB530_1 ; PPC64LE-NEXT: .LBB530_3: @@ -9034,13 +9010,13 @@ define i32 @test530(i32* %ptr, i32 %val) { define i32 @test531(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test531: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB531_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB531_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB531_1 ; PPC64LE-NEXT: .LBB531_3: @@ -9052,13 +9028,13 @@ define i32 @test531(i32* %ptr, i32 %val) { define i32 @test532(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test532: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB532_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB532_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB532_1 ; PPC64LE-NEXT: .LBB532_3: @@ -9070,13 +9046,13 @@ define i32 @test532(i32* %ptr, i32 %val) { define i32 @test533(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test533: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB533_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB533_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB533_1 ; PPC64LE-NEXT: .LBB533_3: @@ -9089,13 +9065,13 @@ define i32 @test533(i32* %ptr, i32 %val) { define i32 @test534(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test534: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB534_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB534_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB534_1 ; PPC64LE-NEXT: .LBB534_3: @@ -9108,12 +9084,12 @@ define i32 @test534(i32* %ptr, i32 %val) { define i64 @test535(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test535: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB535_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB535_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB535_1 ; PPC64LE-NEXT: .LBB535_3: @@ -9125,13 +9101,13 @@ define i64 @test535(i64* %ptr, i64 %val) { define i64 @test536(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test536: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB536_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpld 4, 3 ; PPC64LE-NEXT: ble 0, .LBB536_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB536_1 ; PPC64LE-NEXT: .LBB536_3: @@ -9143,13 +9119,13 @@ define i64 @test536(i64* %ptr, i64 %val) { define i64 @test537(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test537: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB537_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB537_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB537_1 ; PPC64LE-NEXT: .LBB537_3: @@ -9161,13 +9137,13 @@ define i64 @test537(i64* %ptr, i64 %val) { define i64 @test538(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test538: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB538_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB538_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB538_1 ; PPC64LE-NEXT: .LBB538_3: @@ -9180,13 +9156,13 @@ define i64 @test538(i64* %ptr, i64 %val) { define i64 @test539(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test539: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB539_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB539_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB539_1 ; PPC64LE-NEXT: .LBB539_3: @@ -9199,12 +9175,12 @@ define i64 @test539(i64* %ptr, i64 %val) { define i8 @test540(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test540: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB540_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB540_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB540_1 ; PPC64LE-NEXT: .LBB540_3: @@ -9216,13 +9192,13 @@ define i8 @test540(i8* %ptr, i8 %val) { define i8 @test541(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test541: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB541_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB541_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB541_1 ; PPC64LE-NEXT: .LBB541_3: @@ -9234,13 +9210,13 @@ define i8 @test541(i8* %ptr, i8 %val) { define i8 @test542(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test542: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB542_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB542_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB542_1 ; PPC64LE-NEXT: .LBB542_3: @@ -9252,13 +9228,13 @@ define i8 @test542(i8* %ptr, i8 %val) { define i8 @test543(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test543: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB543_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB543_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB543_1 ; PPC64LE-NEXT: .LBB543_3: @@ -9271,13 +9247,13 @@ define i8 @test543(i8* %ptr, i8 %val) { define i8 @test544(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test544: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB544_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB544_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB544_1 ; PPC64LE-NEXT: .LBB544_3: @@ -9290,12 +9266,12 @@ define i8 @test544(i8* %ptr, i8 %val) { define i16 @test545(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test545: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB545_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB545_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB545_1 ; PPC64LE-NEXT: .LBB545_3: @@ -9307,13 +9283,13 @@ define i16 @test545(i16* %ptr, i16 %val) { define i16 @test546(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test546: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB546_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB546_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB546_1 ; PPC64LE-NEXT: .LBB546_3: @@ -9325,13 +9301,13 @@ define i16 @test546(i16* %ptr, i16 %val) { define i16 @test547(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test547: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB547_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB547_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB547_1 ; PPC64LE-NEXT: .LBB547_3: @@ -9343,13 +9319,13 @@ define i16 @test547(i16* %ptr, i16 %val) { define i16 @test548(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test548: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB548_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB548_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB548_1 ; PPC64LE-NEXT: .LBB548_3: @@ -9362,13 +9338,13 @@ define i16 @test548(i16* %ptr, i16 %val) { define i16 @test549(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test549: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB549_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB549_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB549_1 ; PPC64LE-NEXT: .LBB549_3: @@ -9381,12 +9357,12 @@ define i16 @test549(i16* %ptr, i16 %val) { define i32 @test550(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test550: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB550_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB550_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB550_1 ; PPC64LE-NEXT: .LBB550_3: @@ -9398,13 +9374,13 @@ define i32 @test550(i32* %ptr, i32 %val) { define i32 @test551(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test551: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB551_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB551_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB551_1 ; PPC64LE-NEXT: .LBB551_3: @@ -9416,13 +9392,13 @@ define i32 @test551(i32* %ptr, i32 %val) { define i32 @test552(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test552: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB552_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB552_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB552_1 ; PPC64LE-NEXT: .LBB552_3: @@ -9434,13 +9410,13 @@ define i32 @test552(i32* %ptr, i32 %val) { define i32 @test553(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test553: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB553_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB553_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB553_1 ; PPC64LE-NEXT: .LBB553_3: @@ -9453,13 +9429,13 @@ define i32 @test553(i32* %ptr, i32 %val) { define i32 @test554(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test554: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB554_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB554_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB554_1 ; PPC64LE-NEXT: .LBB554_3: @@ -9472,12 +9448,12 @@ define i32 @test554(i32* %ptr, i32 %val) { define i64 @test555(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test555: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB555_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB555_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB555_1 ; PPC64LE-NEXT: .LBB555_3: @@ -9489,13 +9465,13 @@ define i64 @test555(i64* %ptr, i64 %val) { define i64 @test556(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test556: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB556_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpld 4, 3 ; PPC64LE-NEXT: bge 0, .LBB556_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB556_1 ; PPC64LE-NEXT: .LBB556_3: @@ -9507,13 +9483,13 @@ define i64 @test556(i64* %ptr, i64 %val) { define i64 @test557(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test557: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB557_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB557_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB557_1 ; PPC64LE-NEXT: .LBB557_3: @@ -9525,13 +9501,13 @@ define i64 @test557(i64* %ptr, i64 %val) { define i64 @test558(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test558: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB558_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB558_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB558_1 ; PPC64LE-NEXT: .LBB558_3: @@ -9544,13 +9520,13 @@ define i64 @test558(i64* %ptr, i64 %val) { define i64 @test559(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test559: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB559_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB559_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB559_1 ; PPC64LE-NEXT: .LBB559_3: @@ -9564,7 +9540,7 @@ define i64 @test559(i64* %ptr, i64 %val) { ; The second load should never be scheduled before isync. define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) { ; PPC64LE-LABEL: test_ordering0: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwz 4, 0(3) ; PPC64LE-NEXT: cmpd 7, 4, 4 ; PPC64LE-NEXT: bne- 7, .+4 @@ -9581,7 +9557,7 @@ define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) { ; The second store should never be scheduled before isync. define i32 @test_ordering1(i32* %ptr1, i32 %val1, i32* %ptr2) { ; PPC64LE-LABEL: test_ordering1: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwz 3, 0(3) ; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 diff --git a/test/CodeGen/PowerPC/atomics.ll b/test/CodeGen/PowerPC/atomics.ll index 61d54534f5fd1..5037fbf8bcee8 100644 --- a/test/CodeGen/PowerPC/atomics.ll +++ b/test/CodeGen/PowerPC/atomics.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32 +; RUN: llc < %s -mtriple=powerpc-apple-darwin -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32 ; FIXME: -verify-machineinstrs currently fail on ppc64 (mismatched register/instruction). ; This is already checked for in Atomics-64.ll -; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc64 | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64 +; RUN: llc < %s -mtriple=powerpc64-apple-darwin | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64 ; FIXME: we don't currently check for the operations themselves with CHECK-NEXT, ; because they are implemented in a very messy way with lwarx/stwcx. diff --git a/test/CodeGen/PowerPC/big-endian-actual-args.ll b/test/CodeGen/PowerPC/big-endian-actual-args.ll index 6b82cc2dad9e2..e38f28bf9030b 100644 --- a/test/CodeGen/PowerPC/big-endian-actual-args.ll +++ b/test/CodeGen/PowerPC/big-endian-actual-args.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: grep "addc 4, 4, 6" -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: grep "adde 3, 3, 5" define i64 @foo(i64 %x, i64 %y) { diff --git a/test/CodeGen/PowerPC/big-endian-call-result.ll b/test/CodeGen/PowerPC/big-endian-call-result.ll index 8273a94bb3b86..9d9dc6e8ff624 100644 --- a/test/CodeGen/PowerPC/big-endian-call-result.ll +++ b/test/CodeGen/PowerPC/big-endian-call-result.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: grep "addic 4, 4, 1" -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: grep "addze 3, 3" declare i64 @foo() diff --git a/test/CodeGen/PowerPC/big-endian-formal-args.ll b/test/CodeGen/PowerPC/big-endian-formal-args.ll index 3bf2817e035da..868a2612e6cc1 100644 --- a/test/CodeGen/PowerPC/big-endian-formal-args.ll +++ b/test/CodeGen/PowerPC/big-endian-formal-args.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s declare void @bar(i64 %x, i64 %y) diff --git a/test/CodeGen/PowerPC/blockaddress.ll b/test/CodeGen/PowerPC/blockaddress.ll index 3519ffd960c72..a367622b76405 100644 --- a/test/CodeGen/PowerPC/blockaddress.ll +++ b/test/CodeGen/PowerPC/blockaddress.ll @@ -1,9 +1,9 @@ -; RUN: llc -verify-machineinstrs < %s -code-model=small -march=ppc64 -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=SMALL -; RUN: llc -verify-machineinstrs < %s -code-model=medium -march=ppc64 -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=MEDIUM -; RUN: llc -verify-machineinstrs < %s -code-model=large -march=ppc64 -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=MEDIUM -; RUN: llc -verify-machineinstrs < %s -code-model=small -march=ppc64 -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=SMALL -; RUN: llc -verify-machineinstrs < %s -code-model=medium -march=ppc64 -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=MEDIUM -; RUN: llc -verify-machineinstrs < %s -code-model=large -march=ppc64 -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=MEDIUM +; RUN: llc -verify-machineinstrs < %s -code-model=small -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=SMALL +; RUN: llc -verify-machineinstrs < %s -code-model=medium -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=MEDIUM +; RUN: llc -verify-machineinstrs < %s -code-model=large -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=MEDIUM +; RUN: llc -verify-machineinstrs < %s -code-model=small -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=SMALL +; RUN: llc -verify-machineinstrs < %s -code-model=medium -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=MEDIUM +; RUN: llc -verify-machineinstrs < %s -code-model=large -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=MEDIUM define i8* @test() { entry: diff --git a/test/CodeGen/PowerPC/branch-opt.ll b/test/CodeGen/PowerPC/branch-opt.ll index e714972b17eab..dd46b63346471 100644 --- a/test/CodeGen/PowerPC/branch-opt.ll +++ b/test/CodeGen/PowerPC/branch-opt.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s | FileCheck %s target datalayout = "E-p:32:32" target triple = "powerpc-apple-darwin8.7.0" diff --git a/test/CodeGen/PowerPC/branch_coalesce.ll b/test/CodeGen/PowerPC/branch_coalesce.ll index deb6d898c2e0b..a57dec111bca9 100644 --- a/test/CodeGen/PowerPC/branch_coalesce.ll +++ b/test/CodeGen/PowerPC/branch_coalesce.ll @@ -1,26 +1,19 @@ -; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -enable-branch-coalesce=true < %s | FileCheck %s -; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -enable-branch-coalesce=true < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s ; Function Attrs: nounwind define double @testBranchCoal(double %a, double %b, double %c, i32 %x) { -entry: - %test = icmp eq i32 %x, 0 - %tmp1 = select i1 %test, double %a, double 2.000000e-03 - %tmp2 = select i1 %test, double %b, double 0.000000e+00 - %tmp3 = select i1 %test, double %c, double 5.000000e-03 - %res1 = fadd double %tmp1, %tmp2 - %result = fadd double %res1, %tmp3 - ret double %result - -; CHECK-LABEL: @testBranchCoal +; CHECK-LABEL: @testBranchCoal ; CHECK: cmplwi [[CMPR:[0-7]+]], 6, 0 ; CHECK: beq [[CMPR]], .LBB[[LAB1:[0-9_]+]] ; CHECK-DAG: addis [[LD1REG:[0-9]+]], 2, .LCPI0_0@toc@ha ; CHECK-DAG: addis [[LD2REG:[0-9]+]], 2, .LCPI0_1@toc@ha ; CHECK-DAG: xxlxor 2, 2, 2 -; CHECK-NOT: beq -; CHECK-DAG: addi [[LD1BASE:[0-9]+]], [[LD1REG]] +; CHECK-NOT: beq +; CHECK-DAG: addi [[LD1BASE:[0-9]+]], [[LD1REG]] ; CHECK-DAG: addi [[LD2BASE:[0-9]+]], [[LD2REG]] ; CHECK-DAG: lxsdx 1, 0, [[LD1BASE]] ; CHECK-DAG: lxsdx 3, 0, [[LD2BASE]] @@ -28,4 +21,40 @@ entry: ; CHECK: xsadddp 0, 1, 2 ; CHECK: xsadddp 1, 0, 3 ; CHECK: blr + +; CHECK-NOCOALESCE-LABEL: testBranchCoal: +; CHECK-NOCOALESCE: # %bb.0: # %entry +; CHECK-NOCOALESCE-NEXT: cmplwi 0, 6, 0 +; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_5 +; CHECK-NOCOALESCE-NEXT: # %bb.1: # %entry +; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_6 +; CHECK-NOCOALESCE-NEXT: .LBB0_2: # %entry +; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_4 +; CHECK-NOCOALESCE-NEXT: .LBB0_3: # %entry +; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_1@toc@ha +; CHECK-NOCOALESCE-NEXT: addi 3, 3, .LCPI0_1@toc@l +; CHECK-NOCOALESCE-NEXT: lxsdx 3, 0, 3 +; CHECK-NOCOALESCE-NEXT: .LBB0_4: # %entry +; CHECK-NOCOALESCE-NEXT: xsadddp 0, 1, 2 +; CHECK-NOCOALESCE-NEXT: xsadddp 1, 0, 3 +; CHECK-NOCOALESCE-NEXT: blr +; CHECK-NOCOALESCE-NEXT: .LBB0_5: # %entry +; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_0@toc@ha +; CHECK-NOCOALESCE-NEXT: addi 3, 3, .LCPI0_0@toc@l +; CHECK-NOCOALESCE-NEXT: lxsdx 1, 0, 3 +; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_2 +; CHECK-NOCOALESCE-NEXT: .LBB0_6: # %entry +; CHECK-NOCOALESCE-NEXT: xxlxor 2, 2, 2 +; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_3 +; CHECK-NOCOALESCE-NEXT: b .LBB0_4 + entry: + + %test = icmp eq i32 %x, 0 + %tmp1 = select i1 %test, double %a, double 2.000000e-03 + %tmp2 = select i1 %test, double %b, double 0.000000e+00 + %tmp3 = select i1 %test, double %c, double 5.000000e-03 + + %res1 = fadd double %tmp1, %tmp2 + %result = fadd double %res1, %tmp3 + ret double %result } diff --git a/test/CodeGen/PowerPC/bswap-load-store.ll b/test/CodeGen/PowerPC/bswap-load-store.ll index 89ce5e8d35058..093f7f5563570 100644 --- a/test/CodeGen/PowerPC/bswap-load-store.ll +++ b/test/CodeGen/PowerPC/bswap-load-store.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=ppc32 | FileCheck %s -check-prefix=X32 -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=ppc64 | FileCheck %s -check-prefix=X64 -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s -check-prefix=PWR7 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=pwr7 | FileCheck %s -check-prefix=X32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=ppc32 | FileCheck %s -check-prefix=X32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=ppc64 | FileCheck %s -check-prefix=X64 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=pwr7 | FileCheck %s -check-prefix=PWR7 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=pwr7 | FileCheck %s -check-prefix=X32 define void @STWBRX(i32 %i, i8* %ptr, i32 %off) { diff --git a/test/CodeGen/PowerPC/bswap64.ll b/test/CodeGen/PowerPC/bswap64.ll new file mode 100644 index 0000000000000..0a78aa2dc548b --- /dev/null +++ b/test/CodeGen/PowerPC/bswap64.ll @@ -0,0 +1,13 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64le-- -mcpu=pwr9 | FileCheck %s + +declare i64 @llvm.bswap.i64(i64) + +; CHECK: mtvsrdd +; CHECK: xxbrd +; CHECK: mfvsrd +define i64 @bswap64(i64 %x) { +entry: + %0 = call i64 @llvm.bswap.i64(i64 %x) + ret i64 %0 +} + diff --git a/test/CodeGen/PowerPC/build-vector-tests.ll b/test/CodeGen/PowerPC/build-vector-tests.ll index 3ad432872c0e1..16b562bfb9f53 100644 --- a/test/CodeGen/PowerPC/build-vector-tests.ll +++ b/test/CodeGen/PowerPC/build-vector-tests.ll @@ -1,11 +1,15 @@ -; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown \ -; RUN: < %s | FileCheck %s -check-prefix=P9BE -implicit-check-not frsp -; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \ -; RUN: < %s | FileCheck %s -check-prefix=P9LE -implicit-check-not frsp -; RUN: llc -mcpu=pwr8 -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown \ -; RUN: < %s | FileCheck %s -check-prefix=P8BE -implicit-check-not frsp -; RUN: llc -mcpu=pwr8 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \ -; RUN: < %s | FileCheck %s -check-prefix=P8LE -implicit-check-not frsp +; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ +; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ +; RUN: -check-prefix=P9BE -implicit-check-not frsp +; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ +; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ +; RUN: -check-prefix=P9LE -implicit-check-not frsp +; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ +; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ +; RUN: -check-prefix=P8BE -implicit-check-not frsp +; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ +; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ +; RUN: -check-prefix=P8LE -implicit-check-not frsp ; This test case comes from the following C test case (included as it may be ; slightly more readable than the LLVM IR. @@ -1481,10 +1485,10 @@ entry: ; P9BE: xvcvspsxws v2, [[REG1]] ; P9LE: [[REG1:[vs0-9]+]], 0, r3 ; P9LE: xvcvspsxws v2, [[REG1]] -; P8BE: lxsspx [[REG1:f[0-9]+]], 0, r3 +; P8BE: lfsx [[REG1:f[0-9]+]], 0, r3 ; P8BE: xscvdpsxws f[[REG2:[0-9]+]], [[REG1]] ; P8BE: xxspltw v2, vs[[REG2]], 1 -; P8LE: lxsspx [[REG1:f[0-9]+]], 0, r3 +; P8LE: lfsx [[REG1:f[0-9]+]], 0, r3 ; P8LE: xscvdpsxws f[[REG2:[vs0-9]+]], [[REG1]] ; P8LE: xxspltw v2, vs[[REG2]], 1 } @@ -1876,11 +1880,11 @@ entry: ; P9LE: xscvdpsxws ; P9LE: xxspltw ; P9LE: blr -; P8BE: lxsdx +; P8BE: lfdx ; P8BE: xscvdpsxws ; P8BE: xxspltw ; P8BE: blr -; P8LE: lxsdx +; P8LE: lfdx ; P8LE: xscvdpsxws ; P8LE: xxspltw ; P8LE: blr @@ -2641,10 +2645,10 @@ entry: ; P9BE: xvcvspuxws v2, [[REG1]] ; P9LE: [[REG1:[vs0-9]+]], 0, r3 ; P9LE: xvcvspuxws v2, [[REG1]] -; P8BE: lxsspx [[REG1:f[0-9]+]], 0, r3 +; P8BE: lfsx [[REG1:f[0-9]+]], 0, r3 ; P8BE: xscvdpuxws f[[REG2:[0-9]+]], [[REG1]] ; P8BE: xxspltw v2, vs[[REG2]], 1 -; P8LE: lxsspx [[REG1:f[0-9]+]], 0, r3 +; P8LE: lfsx [[REG1:f[0-9]+]], 0, r3 ; P8LE: xscvdpuxws f[[REG2:[vs0-9]+]], [[REG1]] ; P8LE: xxspltw v2, vs[[REG2]], 1 } @@ -3036,11 +3040,11 @@ entry: ; P9LE: xscvdpuxws ; P9LE: xxspltw ; P9LE: blr -; P8BE: lxsdx +; P8BE: lfdx ; P8BE: xscvdpuxws ; P8BE: xxspltw ; P8BE: blr -; P8LE: lxsdx +; P8LE: lfdx ; P8LE: xscvdpuxws ; P8LE: xxspltw ; P8LE: blr @@ -3504,13 +3508,13 @@ entry: ; P9LE: xxmrghd ; P9LE-NEXT: xvcvdpsxds v2 ; P9LE-NEXT: blr -; P8BE: lxsspx -; P8BE: lxsspx +; P8BE: lfs +; P8BE: lfs ; P8BE: xxmrghd ; P8BE-NEXT: xvcvdpsxds v2 ; P8BE-NEXT: blr -; P8LE: lxsspx -; P8LE: lxsspx +; P8LE: lfs +; P8LE: lfs ; P8LE: xxmrghd ; P8LE-NEXT: xvcvdpsxds v2 ; P8LE-NEXT: blr @@ -3542,13 +3546,13 @@ entry: ; P9LE: xxmrghd ; P9LE-NEXT: xvcvdpsxds v2 ; P9LE-NEXT: blr -; P8BE: lxsspx -; P8BE: lxsspx +; P8BE: lfs +; P8BE: lfs ; P8BE: xxmrghd ; P8BE-NEXT: xvcvdpsxds v2 ; P8BE-NEXT: blr -; P8LE: lxsspx -; P8LE: lxsspx +; P8LE: lfs +; P8LE: lfs ; P8LE: xxmrghd ; P8LE-NEXT: xvcvdpsxds v2 ; P8LE-NEXT: blr @@ -3587,13 +3591,13 @@ entry: ; P9LE-NEXT: blr ; P8BE: sldi ; P8BE: lfsux -; P8BE: lxsspx +; P8BE: lfs ; P8BE: xxmrghd ; P8BE-NEXT: xvcvdpsxds v2 ; P8BE-NEXT: blr ; P8LE: sldi ; P8LE: lfsux -; P8LE: lxsspx +; P8LE: lfs ; P8LE: xxmrghd ; P8LE-NEXT: xvcvdpsxds v2 ; P8LE-NEXT: blr @@ -3632,13 +3636,13 @@ entry: ; P9LE-NEXT: blr ; P8BE: sldi ; P8BE: lfsux -; P8BE: lxsspx +; P8BE: lfs ; P8BE: xxmrghd ; P8BE-NEXT: xvcvdpsxds v2 ; P8BE-NEXT: blr ; P8LE: sldi ; P8LE: lfsux -; P8LE: lxsspx +; P8LE: lfs ; P8LE: xxmrghd ; P8LE-NEXT: xvcvdpsxds v2 ; P8LE-NEXT: blr @@ -3689,11 +3693,11 @@ entry: ; P9LE-NEXT: xscvdpsxds ; P9LE-NEXT: xxspltd v2 ; P9LE-NEXT: blr -; P8BE: lxsspx +; P8BE: lfs ; P8BE-NEXT: xscvdpsxds ; P8BE-NEXT: xxspltd v2 ; P8BE-NEXT: blr -; P8LE: lxsspx +; P8LE: lfs ; P8LE-NEXT: xscvdpsxds ; P8LE-NEXT: xxspltd v2 ; P8LE-NEXT: blr @@ -4408,13 +4412,13 @@ entry: ; P9LE: xxmrghd ; P9LE-NEXT: xvcvdpuxds v2 ; P9LE-NEXT: blr -; P8BE: lxsspx -; P8BE: lxsspx +; P8BE: lfs +; P8BE: lfs ; P8BE: xxmrghd ; P8BE-NEXT: xvcvdpuxds v2 ; P8BE-NEXT: blr -; P8LE: lxsspx -; P8LE: lxsspx +; P8LE: lfs +; P8LE: lfs ; P8LE: xxmrghd ; P8LE-NEXT: xvcvdpuxds v2 ; P8LE-NEXT: blr @@ -4446,13 +4450,13 @@ entry: ; P9LE: xxmrghd ; P9LE-NEXT: xvcvdpuxds v2 ; P9LE-NEXT: blr -; P8BE: lxsspx -; P8BE: lxsspx +; P8BE: lfs +; P8BE: lfs ; P8BE: xxmrghd ; P8BE-NEXT: xvcvdpuxds v2 ; P8BE-NEXT: blr -; P8LE: lxsspx -; P8LE: lxsspx +; P8LE: lfs +; P8LE: lfs ; P8LE: xxmrghd ; P8LE-NEXT: xvcvdpuxds v2 ; P8LE-NEXT: blr @@ -4491,13 +4495,13 @@ entry: ; P9LE-NEXT: blr ; P8BE: sldi ; P8BE: lfsux -; P8BE: lxsspx +; P8BE: lfs ; P8BE: xxmrghd ; P8BE-NEXT: xvcvdpuxds v2 ; P8BE-NEXT: blr ; P8LE: sldi ; P8LE: lfsux -; P8LE: lxsspx +; P8LE: lfs ; P8LE: xxmrghd ; P8LE-NEXT: xvcvdpuxds v2 ; P8LE-NEXT: blr @@ -4536,13 +4540,13 @@ entry: ; P9LE-NEXT: blr ; P8BE: sldi ; P8BE: lfsux -; P8BE: lxsspx +; P8BE: lfs ; P8BE: xxmrghd ; P8BE-NEXT: xvcvdpuxds v2 ; P8BE-NEXT: blr ; P8LE: sldi ; P8LE: lfsux -; P8LE: lxsspx +; P8LE: lfs ; P8LE: xxmrghd ; P8LE-NEXT: xvcvdpuxds v2 ; P8LE-NEXT: blr @@ -4593,11 +4597,11 @@ entry: ; P9LE-NEXT: xscvdpuxds ; P9LE-NEXT: xxspltd v2 ; P9LE-NEXT: blr -; P8BE: lxsspx +; P8BE: lfs ; P8BE-NEXT: xscvdpuxds ; P8BE-NEXT: xxspltd v2 ; P8BE-NEXT: blr -; P8LE: lxsspx +; P8LE: lfs ; P8LE-NEXT: xscvdpuxds ; P8LE-NEXT: xxspltd v2 ; P8LE-NEXT: blr diff --git a/test/CodeGen/PowerPC/buildvec_canonicalize.ll b/test/CodeGen/PowerPC/buildvec_canonicalize.ll index e5a5c29d5a755..c59415874489f 100644 --- a/test/CodeGen/PowerPC/buildvec_canonicalize.ll +++ b/test/CodeGen/PowerPC/buildvec_canonicalize.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+altivec --enable-unsafe-fp-math | FileCheck %s define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) { %tmp = load <4 x float>, <4 x float>* %P3 ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/PowerPC/byval-agg-info.ll b/test/CodeGen/PowerPC/byval-agg-info.ll index df87896e37537..6e0b167757f63 100644 --- a/test/CodeGen/PowerPC/byval-agg-info.ll +++ b/test/CodeGen/PowerPC/byval-agg-info.ll @@ -13,5 +13,5 @@ entry: ; Make sure that the MMO on the store has no offset from the byval ; variable itself (we used to have mem:ST8[%v+64]). -; CHECK: STD %X5<kill>, 176, %X1; mem:ST8[%v](align=16) +; CHECK: STD killed renamable %x5, 176, %x1; mem:ST8[%v](align=16) diff --git a/test/CodeGen/PowerPC/calls.ll b/test/CodeGen/PowerPC/calls.ll index 4c1b6e2b1a003..1fff0eaf237c5 100644 --- a/test/CodeGen/PowerPC/calls.ll +++ b/test/CodeGen/PowerPC/calls.ll @@ -1,10 +1,10 @@ ; Test various forms of calls. -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: grep "bl " | count 1 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: grep "bctrl" | count 1 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: grep "bla " | count 1 declare void @foo() diff --git a/test/CodeGen/PowerPC/cmp-cmp.ll b/test/CodeGen/PowerPC/cmp-cmp.ll index a8bb42a4902b4..b7090054289db 100644 --- a/test/CodeGen/PowerPC/cmp-cmp.ll +++ b/test/CodeGen/PowerPC/cmp-cmp.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep mfcr +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep mfcr define void @test(i64 %X) { %tmp1 = and i64 %X, 3 ; <i64> [#uses=1] diff --git a/test/CodeGen/PowerPC/cmp_elimination.ll b/test/CodeGen/PowerPC/cmp_elimination.ll new file mode 100644 index 0000000000000..3251ae2881b93 --- /dev/null +++ b/test/CodeGen/PowerPC/cmp_elimination.ll @@ -0,0 +1,757 @@ +; XFAIL: * +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s + +; Test cases for compare elimination in PPCMIPeephole pass + +define void @func1(i32 signext %a) { +; We should have only one compare instruction +; CHECK-LABEL: @func1 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp eq i32 %a, 100 + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp slt i32 %a, 100 + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func2(i32 signext %a) { +; CHECK-LABEL: @func2 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp slt i32 %a, 100 + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp eq i32 %a, 100 + br i1 %cmp1, label %if.end3, label %if.then2 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func3(i32 signext %a) { +; CHECK-LABEL: @func3 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp sgt i32 %a, 100 + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp eq i32 %a, 100 + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func4(i32 zeroext %a) { +; CHECK-LABEL: @func4 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp eq i32 %a, 100 + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp ult i32 %a, 100 + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func5(i32 zeroext %a) { +; CHECK-LABEL: @func5 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp ult i32 %a, 100 + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp eq i32 %a, 100 + br i1 %cmp1, label %if.end3, label %if.then2 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func6(i32 zeroext %a) { +; CHECK-LABEL: @func6 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp ugt i32 %a, 100 + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp eq i32 %a, 100 + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func7(i64 %a) { +; CHECK-LABEL: @func7 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp eq i64 %a, 100 + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp slt i64 %a, 100 + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func8(i64 %a) { +; CHECK-LABEL: @func8 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp slt i64 %a, 100 + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp eq i64 %a, 100 + br i1 %cmp1, label %if.end3, label %if.then2 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func9(i64 %a) { +; CHECK-LABEL: @func9 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp sgt i64 %a, 100 + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp eq i64 %a, 100 + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func10(i64 %a) { +; CHECK-LABEL: @func10 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp eq i64 %a, 100 + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp ult i64 %a, 100 + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func11(i64 %a) { +; CHECK-LABEL: @func11 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp ult i64 %a, 100 + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp eq i64 %a, 100 + br i1 %cmp1, label %if.end3, label %if.then2 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func12(i64 %a) { +; CHECK-LABEL: @func12 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp ugt i64 %a, 100 + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp eq i64 %a, 100 + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func13(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: @func13 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp eq i32 %a, %b + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp slt i32 %a, %b + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func14(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: @func14 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp slt i32 %a, %b + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp sgt i32 %a, %b + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func15(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: @func15 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp slt i32 %b, %a + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp eq i32 %a, %b + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func16(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: @func16 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp eq i32 %a, %b + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp ult i32 %a, %b + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func17(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: @func17 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp ult i32 %a, %b + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp ugt i32 %a, %b + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func18(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: @func18 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp ult i32 %b, %a + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp eq i32 %a, %b + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func19(i64 %a, i64 %b) { +; CHECK-LABEL: @func19 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp eq i64 %a, %b + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp slt i64 %a, %b + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func20(i64 %a, i64 %b) { +; CHECK-LABEL: @func20 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp slt i64 %a, %b + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp sgt i64 %a, %b + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func21(i64 %a, i64 %b) { +; CHECK-LABEL: @func21 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp slt i64 %b, %a + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp eq i64 %a, %b + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func22(i64 %a, i64 %b) { +; CHECK-LABEL: @func22 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp eq i64 %a, %b + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp ult i64 %a, %b + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func23(i64 %a, i64 %b) { +; CHECK-LABEL: @func23 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp ult i64 %a, %b + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp ugt i64 %a, %b + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func24(i64 %a, i64 %b) { +; CHECK-LABEL: @func24 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp ult i64 %b, %a + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void @dummy1() + br label %if.end3 + +if.else: + %cmp1 = icmp eq i64 %a, %b + br i1 %cmp1, label %if.then2, label %if.end3 + +if.then2: + tail call void @dummy2() + br label %if.end3 + +if.end3: + ret void +} + + +define void @func25(i64 %a, i64 %b) { +; CHECK-LABEL: @func25 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp slt i64 %b, %a + br i1 %cmp, label %if.then, label %if.else, !prof !1 + +if.then: + tail call void @dummy1() + br label %if.end6 + +if.else: + %cmp2 = icmp eq i64 %a, %b + br i1 %cmp2, label %if.then4, label %if.else5 + +if.then4: + tail call void @dummy2() + br label %if.end6 + +if.else5: + tail call void @dummy3() + br label %if.end6 + +if.end6: + ret void +} + + +define void @func26(i32 signext %a) { +; CHECK-LABEL: @func26 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: blr +entry: + %cmp = icmp sgt i32 %a, 0 + br i1 %cmp, label %if.then, label %if.else, !prof !2 + +if.then: + tail call void @dummy1() + br label %if.end9 + +if.else: + %cmp2 = icmp eq i32 %a, 0 + br i1 %cmp2, label %if.then7, label %if.else8, !prof !2 + +if.then7: + tail call void @dummy2() + br label %if.end9 + +if.else8: + tail call void @dummy3() + br label %if.end9 + +if.end9: + ret void +} + +@g1 = external local_unnamed_addr global i32, align 4 +@g2 = external local_unnamed_addr global i32, align 4 + +define void @func27(i32 signext %a) { +; CHECK-LABEL: @func27 +; CHECK: cmp +; CHECK: beq +; CHECK-NOT: cmp +; CHECK: bgelr +; CHECK: blr +entry: + %cmp = icmp eq i32 %a, 0 + br i1 %cmp, label %if.end3.sink.split, label %if.else + +if.else: + %cmp1 = icmp slt i32 %a, 0 + br i1 %cmp1, label %if.end3.sink.split, label %if.end + +if.end3.sink.split: + %g2.sink = phi i32* [ @g2, %if.else ], [ @g1, %entry ] + store i32 0, i32* %g2.sink, align 4 + br label %if.end + +if.end: + ret void +} + +; partially redundant case +define void @func28(i32 signext %a) { +; CHECK-LABEL: @func28 +; CHECK: cmplwi [[REG1:[0-9]+]], [[REG2:[0-9]+]] +; CHECK: .[[LABEL1:[A-Z0-9_]+]]: +; CHECK-NOT: cmp +; CHECK: bne 0, .[[LABEL2:[A-Z0-9_]+]] +; CHECK: bl dummy1 +; CHECK: .[[LABEL2]]: +; CHECK: cmpwi [[REG1]], [[REG2]] +; CHECK: bgt 0, .[[LABEL1]] +; CHECK: blr +entry: + br label %do.body + +do.body: + %a.addr.0 = phi i32 [ %a, %entry ], [ %call, %if.end ] + %cmp = icmp eq i32 %a.addr.0, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: + tail call void @dummy1() #2 + br label %if.end + +if.end: + %call = tail call signext i32 @func(i32 signext %a.addr.0) #2 + %cmp1 = icmp sgt i32 %call, 0 + br i1 %cmp1, label %do.body, label %do.end + +do.end: + ret void +} + +declare void @dummy1() +declare void @dummy2() +declare void @dummy3() +declare signext i32 @func(i32 signext) + +!1 = !{!"branch_weights", i32 2000, i32 1} +!2 = !{!"branch_weights", i32 1, i32 2000} diff --git a/test/CodeGen/PowerPC/coal-sections.ll b/test/CodeGen/PowerPC/coal-sections.ll index e7bac74e15a92..3676f6016a06a 100644 --- a/test/CodeGen/PowerPC/coal-sections.ll +++ b/test/CodeGen/PowerPC/coal-sections.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple powerpc-apple-darwin8 -march=ppc32 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple powerpc-apple-darwin8 | FileCheck %s ; Check that *coal* sections are emitted. diff --git a/test/CodeGen/PowerPC/coalesce-ext.ll b/test/CodeGen/PowerPC/coalesce-ext.ll index ed1c670d9b44d..253df9d0a181f 100644 --- a/test/CodeGen/PowerPC/coalesce-ext.ll +++ b/test/CodeGen/PowerPC/coalesce-ext.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -march=ppc64 -mcpu=g5 -mtriple=powerpc64-apple-darwin < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=g5 -mtriple=powerpc64-apple-darwin < %s | FileCheck %s ; Check that the peephole optimizer knows about sext and zext instructions. ; CHECK: test1sext define i32 @test1sext(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind { diff --git a/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll b/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll new file mode 100644 index 0000000000000..0f8f18a178795 --- /dev/null +++ b/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll @@ -0,0 +1,21 @@ +; RUN: llc -verify-machineinstrs -O0 -mcpu=g4 -mtriple=powerpc-apple-darwin8 < %s -debug -stop-after=machineverifier 2>&1 | FileCheck %s + +; REQUIRES: asserts + +define i64 @func1(i64 %p1, i64 %p2, i64 %p3, i64 %p4, { i64, i8* } %struct) { +; Verify that we get a combine on the build_pair, creating a LD8 load somewhere +; between "Initial selection DAG" and "Optimized lowered selection DAG". +; The target is big-endian, and stack grows towards higher addresses, +; so we expect the LD8 to load from the address used in the original HIBITS +; load. +; CHECK-LABEL: Initial selection DAG: +; CHECK-DAG: [[LOBITS:t[0-9]+]]: i32,ch = load<LD4[FixedStack-2]> +; CHECK-DAG: [[HIBITS:t[0-9]+]]: i32,ch = load<LD4[FixedStack-1]> +; CHECK: Combining: t{{[0-9]+}}: i64 = build_pair [[LOBITS]], [[HIBITS]] +; CHECK-NEXT: into +; CHECK-SAME: load<LD8[FixedStack-1] +; CHECK-LABEL: Optimized lowered selection DAG: + %result = extractvalue {i64, i8* } %struct, 0 + ret i64 %result +} + diff --git a/test/CodeGen/PowerPC/compare-simm.ll b/test/CodeGen/PowerPC/compare-simm.ll index c5114fd730379..bc2572b51127e 100644 --- a/test/CodeGen/PowerPC/compare-simm.ll +++ b/test/CodeGen/PowerPC/compare-simm.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 | FileCheck %s define i32 @test(i32 %x) nounwind { ; CHECK-LABEL: @test diff --git a/test/CodeGen/PowerPC/constants.ll b/test/CodeGen/PowerPC/constants.ll index 32eee549df61d..9091747a8ed2d 100644 --- a/test/CodeGen/PowerPC/constants.ll +++ b/test/CodeGen/PowerPC/constants.ll @@ -1,9 +1,9 @@ ; All of these routines should be perform optimal load of constants. -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: grep lis | count 5 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: grep ori | count 3 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: grep "li " | count 4 define i32 @f1() { diff --git a/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir b/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir new file mode 100644 index 0000000000000..754f83825a2cb --- /dev/null +++ b/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir @@ -0,0 +1,436 @@ +# RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole %s -o - | FileCheck %s +--- | + ; ModuleID = 'a.ll' + source_filename = "a.c" + target datalayout = "e-m:e-i64:64-n32:64" + target triple = "powerpc64le-unknown-linux-gnu" + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @unsafeAddR0R3(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { + entry: + %add = add nsw i32 %b, %a + ret i32 %add + } + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @unsafeAddR3R0(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { + entry: + %add = add nsw i32 %b, %a + ret i32 %add + } + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @safeAddR0R3(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { + entry: + %add = add nsw i32 %b, %a + ret i32 %add + } + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @safeAddR3R0(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { + entry: + %add = add nsw i32 %b, %a + ret i32 %add + } + + ; Function Attrs: norecurse nounwind readonly + define i64 @unsafeLDXR3R0(i64* nocapture readonly %ptr, i64 %off) local_unnamed_addr #1 { + entry: + %0 = bitcast i64* %ptr to i8* + %add.ptr = getelementptr inbounds i8, i8* %0, i64 %off + %1 = bitcast i8* %add.ptr to i64* + %2 = load i64, i64* %1, align 8, !tbaa !3 + ret i64 %2 + } + + ; Function Attrs: norecurse nounwind readonly + define i64 @safeLDXZeroR3(i64* nocapture readonly %ptr, i64 %off) local_unnamed_addr #1 { + entry: + %0 = bitcast i64* %ptr to i8* + %add.ptr = getelementptr inbounds i8, i8* %0, i64 %off + %1 = bitcast i8* %add.ptr to i64* + %2 = load i64, i64* %1, align 8, !tbaa !3 + ret i64 %2 + } + + ; Function Attrs: norecurse nounwind readonly + define i64 @safeLDXR3R0(i64* nocapture readonly %ptr, i64 %off) local_unnamed_addr #1 { + entry: + %0 = bitcast i64* %ptr to i8* + %add.ptr = getelementptr inbounds i8, i8* %0, i64 %off + %1 = bitcast i8* %add.ptr to i64* + %2 = load i64, i64* %1, align 8, !tbaa !3 + ret i64 %2 + } + + attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #1 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" } + + !llvm.module.flags = !{!0, !1} + !llvm.ident = !{!2} + + !0 = !{i32 1, !"wchar_size", i32 4} + !1 = !{i32 7, !"PIC Level", i32 2} + !2 = !{!"clang version 6.0.0 (trunk 318832)"} + !3 = !{!4, !4, i64 0} + !4 = !{!"long long", !5, i64 0} + !5 = !{!"omnipotent char", !6, i64 0} + !6 = !{!"Simple C/C++ TBAA"} + +... +--- +name: unsafeAddR0R3 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x0, %x4 + + %1:g8rc = COPY %x4 + %0:g8rc = COPY %x0 + %2:gprc = LI 44 + %3:gprc = COPY %1.sub_32 + %4:gprc = ADD4 killed %r0, killed %2 + ; CHECK: li 3, 44 + ; CHECK: add 3, 0, 3 + %5:g8rc = EXTSW_32_64 killed %4 + %x3 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: unsafeAddR3R0 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x0, %x4 + + %1:g8rc = COPY %x4 + %0:g8rc = COPY %x0 + %2:gprc = COPY %0.sub_32 + %3:gprc = LI 44 + %4:gprc = ADD4 killed %3, killed %r0 + ; CHECK: li 3, 44 + ; CHECK: add 3, 3, 0 + %5:g8rc = EXTSW_32_64 killed %4 + %x3 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: safeAddR0R3 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1:g8rc = COPY %x4 + %0:g8rc = COPY %x3 + %2:gprc = COPY %0.sub_32 + %r0 = LI 44 + %4:gprc = ADD4 killed %r0, killed %2 + ; CHECK: addi 3, 3, 44 + %5:g8rc = EXTSW_32_64 killed %4 + %x3 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: safeAddR3R0 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1:g8rc = COPY %x4 + %0:g8rc = COPY %x3 + %2:gprc = COPY %0.sub_32 + %r0 = LI 44 + %4:gprc = ADD4 killed %2, killed %r0 + ; CHECK: addi 3, 3, 44 + %5:g8rc = EXTSW_32_64 killed %4 + %x3 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: unsafeLDXR3R0 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x0', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x0, %x4 + + %1:g8rc = COPY %x4 + %0:g8rc_and_g8rc_nox0 = LI8 44 + %2:g8rc = LDX %0, %x0 :: (load 8 from %ir.1, !tbaa !3) + ; CHECK: li 3, 44 + ; CHECK: ldx 3, 3, 0 + %x3 = COPY %2 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: safeLDXZeroR3 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1:g8rc = LI8 44 + %0:g8rc_and_g8rc_nox0 = LI8 44 + %2:g8rc = LDX %zero8, %1 :: (load 8 from %ir.1, !tbaa !3) + ; CHECK: ld 3, 44(0) + %x3 = COPY %2 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: safeLDXR3R0 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %x0 = LI8 44 + %0:g8rc_and_g8rc_nox0 = COPY %x3 + %2:g8rc = LDX %0, %x0 :: (load 8 from %ir.1, !tbaa !3) + ; CHECK: ld 3, 44(3) + %x3 = COPY %2 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... diff --git a/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir new file mode 100644 index 0000000000000..c4783de4a18fe --- /dev/null +++ b/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir @@ -0,0 +1,6129 @@ +# RUN: llc -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri %s -o - | FileCheck %s +# RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole %s -o - | FileCheck %s --check-prefix=CHECK-LATE + +--- | + ; ModuleID = 'convert-rr-to-ri-instrs.ll' + source_filename = "convert-rr-to-ri-instrs.c" + target datalayout = "e-m:e-i64:64-n32:64" + target triple = "powerpc64le-unknown-linux-gnu" + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @testADD4(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { + entry: + %add = add nsw i32 %a, 33 + %add1 = add nsw i32 %add, %b + ret i32 %add1 + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testADD8(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %add = add nsw i64 %a, 33 + %add1 = add nsw i64 %add, %b + ret i64 %add1 + } + + ; Function Attrs: norecurse nounwind readnone + define i128 @testADDC(i128 %a, i128 %b) local_unnamed_addr #0 { + entry: + %add = add nsw i128 %b, %a + ret i128 %add + } + + ; Function Attrs: norecurse nounwind readnone + define i128 @testADDC8(i128 %a, i128 %b) local_unnamed_addr #0 { + entry: + %add = add nsw i128 %b, %a + ret i128 %add + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testADDCo(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %add = add nsw i64 %b, %a + %cmp = icmp eq i64 %add, 0 + %neg = sext i1 %cmp to i64 + %retval.0 = xor i64 %add, %neg + ret i64 %retval.0 + } + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @testADDI(i32 signext %a) local_unnamed_addr #0 { + entry: + %add = add nsw i32 %a, 44 + ret i32 %add + } + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @testADDI8(i32 signext %a) local_unnamed_addr #0 { + entry: + %add = add nsw i32 %a, 44 + ret i32 %add + } + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @testANDo(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %and = and i64 %b, %a + %tobool = icmp eq i64 %and, 0 + %cond = select i1 %tobool, i64 %b, i64 %a + %conv = trunc i64 %cond to i32 + ret i32 %conv + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testAND8o(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %and = and i64 %b, %a + %tobool = icmp eq i64 %and, 0 + %cond = select i1 %tobool, i64 %b, i64 %a + ret i64 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testCMPD(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %cmp = icmp sgt i64 %a, %b + %add = select i1 %cmp, i64 0, i64 %a + %cond = add nsw i64 %add, %b + ret i64 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testCMPDI(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %cmp = icmp sgt i64 %a, 87 + %add = select i1 %cmp, i64 0, i64 %a + %cond = add nsw i64 %add, %b + ret i64 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testCMPDI_F(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %cmp = icmp sgt i64 %a, 87 + %add = select i1 %cmp, i64 0, i64 %a + %cond = add nsw i64 %add, %b + ret i64 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testCMPLD(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %cmp = icmp ugt i64 %a, %b + %add = select i1 %cmp, i64 0, i64 %a + %cond = add i64 %add, %b + ret i64 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testCMPLDI(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %cmp = icmp ugt i64 %a, 87 + %add = select i1 %cmp, i64 0, i64 %a + %cond = add i64 %add, %b + ret i64 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @testCMPW(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { + entry: + %cmp = icmp sgt i32 %a, %b + %add = select i1 %cmp, i32 0, i32 %a + %cond = add nsw i32 %add, %b + ret i32 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @testCMPWI(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { + entry: + %cmp = icmp sgt i32 %a, 87 + %add = select i1 %cmp, i32 0, i32 %a + %cond = add nsw i32 %add, %b + ret i32 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define zeroext i32 @testCMPLW(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 { + entry: + %cmp = icmp ugt i32 %a, %b + %add = select i1 %cmp, i32 0, i32 %a + %cond = add i32 %add, %b + ret i32 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define zeroext i32 @testCMPLWI(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 { + entry: + %cmp = icmp ugt i32 %a, 87 + %add = select i1 %cmp, i32 0, i32 %a + %cond = add i32 %add, %b + ret i32 %cond + } + + ; Function Attrs: norecurse nounwind readonly + define zeroext i8 @testLBZUX(i8* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i8, i8* %ptr, i64 %idxprom + %0 = load i8, i8* %arrayidx, align 1, !tbaa !3 + %conv = zext i8 %0 to i32 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i8, i8* %ptr, i64 %idxprom2 + %1 = load i8, i8* %arrayidx3, align 1, !tbaa !3 + %conv4 = zext i8 %1 to i32 + %add5 = add nuw nsw i32 %conv4, %conv + %conv6 = trunc i32 %add5 to i8 + ret i8 %conv6 + } + + ; Function Attrs: norecurse nounwind readonly + define zeroext i8 @testLBZX(i8* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i8, i8* %ptr, i64 %idxprom + %0 = load i8, i8* %arrayidx, align 1, !tbaa !3 + %conv = zext i8 %0 to i32 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i8, i8* %ptr, i64 %idxprom2 + %1 = load i8, i8* %arrayidx3, align 1, !tbaa !3 + %conv4 = zext i8 %1 to i32 + %add5 = add nuw nsw i32 %conv4, %conv + %conv6 = trunc i32 %add5 to i8 + ret i8 %conv6 + } + + ; Function Attrs: norecurse nounwind readonly + define zeroext i16 @testLHZUX(i16* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i16, i16* %ptr, i64 %idxprom + %0 = load i16, i16* %arrayidx, align 2, !tbaa !6 + %conv = zext i16 %0 to i32 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i16, i16* %ptr, i64 %idxprom2 + %1 = load i16, i16* %arrayidx3, align 2, !tbaa !6 + %conv4 = zext i16 %1 to i32 + %add5 = add nuw nsw i32 %conv4, %conv + %conv6 = trunc i32 %add5 to i16 + ret i16 %conv6 + } + + ; Function Attrs: norecurse nounwind readonly + define zeroext i16 @testLHZX(i16* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i16, i16* %ptr, i64 %idxprom + %0 = load i16, i16* %arrayidx, align 2, !tbaa !6 + %conv = zext i16 %0 to i32 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i16, i16* %ptr, i64 %idxprom2 + %1 = load i16, i16* %arrayidx3, align 2, !tbaa !6 + %conv4 = zext i16 %1 to i32 + %add5 = add nuw nsw i32 %conv4, %conv + %conv6 = trunc i32 %add5 to i16 + ret i16 %conv6 + } + + ; Function Attrs: norecurse nounwind readonly + define signext i16 @testLHAUX(i16* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i16, i16* %ptr, i64 %idxprom + %0 = load i16, i16* %arrayidx, align 2, !tbaa !6 + %conv9 = zext i16 %0 to i32 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i16, i16* %ptr, i64 %idxprom2 + %1 = load i16, i16* %arrayidx3, align 2, !tbaa !6 + %conv410 = zext i16 %1 to i32 + %add5 = add nuw nsw i32 %conv410, %conv9 + %conv6 = trunc i32 %add5 to i16 + ret i16 %conv6 + } + + ; Function Attrs: norecurse nounwind readonly + define signext i16 @testLHAX(i16* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i16, i16* %ptr, i64 %idxprom + %0 = load i16, i16* %arrayidx, align 2, !tbaa !6 + %conv9 = zext i16 %0 to i32 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i16, i16* %ptr, i64 %idxprom2 + %1 = load i16, i16* %arrayidx3, align 2, !tbaa !6 + %conv410 = zext i16 %1 to i32 + %add5 = add nuw nsw i32 %conv410, %conv9 + %conv6 = trunc i32 %add5 to i16 + ret i16 %conv6 + } + + ; Function Attrs: norecurse nounwind readonly + define zeroext i32 @testLWZUX(i32* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i32, i32* %ptr, i64 %idxprom + %0 = load i32, i32* %arrayidx, align 4, !tbaa !8 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i32, i32* %ptr, i64 %idxprom2 + %1 = load i32, i32* %arrayidx3, align 4, !tbaa !8 + %add4 = add i32 %1, %0 + ret i32 %add4 + } + + ; Function Attrs: norecurse nounwind readonly + define zeroext i32 @testLWZX(i32* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i32, i32* %ptr, i64 %idxprom + %0 = load i32, i32* %arrayidx, align 4, !tbaa !8 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i32, i32* %ptr, i64 %idxprom2 + %1 = load i32, i32* %arrayidx3, align 4, !tbaa !8 + %add4 = add i32 %1, %0 + ret i32 %add4 + } + + ; Function Attrs: norecurse nounwind readonly + define i64 @testLWAX(i32* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i32, i32* %ptr, i64 %idxprom + %0 = load i32, i32* %arrayidx, align 4, !tbaa !8 + %conv = sext i32 %0 to i64 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i32, i32* %ptr, i64 %idxprom2 + %1 = load i32, i32* %arrayidx3, align 4, !tbaa !8 + %conv4 = sext i32 %1 to i64 + %add5 = add nsw i64 %conv4, %conv + ret i64 %add5 + } + + ; Function Attrs: norecurse nounwind readonly + define i64 @testLDUX(i64* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i64, i64* %ptr, i64 %idxprom + %0 = load i64, i64* %arrayidx, align 8, !tbaa !10 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i64, i64* %ptr, i64 %idxprom2 + %1 = load i64, i64* %arrayidx3, align 8, !tbaa !10 + %add4 = add i64 %1, %0 + ret i64 %add4 + } + + ; Function Attrs: norecurse nounwind readonly + define i64 @testLDX(i64* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i64, i64* %ptr, i64 %idxprom + %0 = load i64, i64* %arrayidx, align 8, !tbaa !10 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i64, i64* %ptr, i64 %idxprom2 + %1 = load i64, i64* %arrayidx3, align 8, !tbaa !10 + %add4 = add i64 %1, %0 + ret i64 %add4 + } + + ; Function Attrs: norecurse nounwind readonly + define double @testLFDUX(double* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #2 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds double, double* %ptr, i64 %idxprom + %0 = load double, double* %arrayidx, align 8, !tbaa !12 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds double, double* %ptr, i64 %idxprom2 + %1 = load double, double* %arrayidx3, align 8, !tbaa !12 + %add4 = fadd double %0, %1 + ret double %add4 + } + + ; Function Attrs: norecurse nounwind readonly + define double @testLFDX(double* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #2 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds double, double* %ptr, i64 %idxprom + %0 = load double, double* %arrayidx, align 8, !tbaa !12 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds double, double* %ptr, i64 %idxprom2 + %1 = load double, double* %arrayidx3, align 8, !tbaa !12 + %add4 = fadd double %0, %1 + ret double %add4 + } + + ; Function Attrs: norecurse nounwind readonly + define <4 x float> @testLFSUX(float* nocapture readonly %ptr, i32 signext %idx) local_unnamed_addr #2 { + entry: + %idxprom = sext i32 %idx to i64 + %arrayidx = getelementptr inbounds float, float* %ptr, i64 %idxprom + %0 = load float, float* %arrayidx, align 4, !tbaa !14 + %conv = fptoui float %0 to i32 + %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 + %1 = bitcast float* %ptr to i8* + %2 = shl i64 %idxprom, 2 + %uglygep = getelementptr i8, i8* %1, i64 %2 + %uglygep2 = getelementptr i8, i8* %uglygep, i64 4 + %3 = bitcast i8* %uglygep2 to float* + %4 = load float, float* %3, align 4, !tbaa !14 + %conv3 = fptoui float %4 to i32 + %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 + %uglygep5 = getelementptr i8, i8* %uglygep, i64 8 + %5 = bitcast i8* %uglygep5 to float* + %6 = load float, float* %5, align 4, !tbaa !14 + %conv8 = fptoui float %6 to i32 + %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 + %uglygep8 = getelementptr i8, i8* %uglygep, i64 12 + %7 = bitcast i8* %uglygep8 to float* + %8 = load float, float* %7, align 4, !tbaa !14 + %conv13 = fptoui float %8 to i32 + %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 + %9 = bitcast <4 x i32> %vecinit14 to <4 x float> + ret <4 x float> %9 + } + + ; Function Attrs: norecurse nounwind readonly + define float @testLFSX(float* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #2 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds float, float* %ptr, i64 %idxprom + %0 = load float, float* %arrayidx, align 4, !tbaa !14 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds float, float* %ptr, i64 %idxprom2 + %1 = load float, float* %arrayidx3, align 4, !tbaa !14 + %add4 = fadd float %0, %1 + ret float %add4 + } + + ; Function Attrs: norecurse nounwind readonly + define double @testLXSDX(double* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds double, double* %ptr, i64 %idxprom + %0 = load double, double* %arrayidx, align 8, !tbaa !12 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds double, double* %ptr, i64 %idxprom2 + %1 = load double, double* %arrayidx3, align 8, !tbaa !12 + %add4 = fadd double %0, %1 + ret double %add4 + } + + ; Function Attrs: norecurse nounwind readonly + define float @testLXSSPX(float* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds float, float* %ptr, i64 %idxprom + %0 = load float, float* %arrayidx, align 4, !tbaa !14 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds float, float* %ptr, i64 %idxprom2 + %1 = load float, float* %arrayidx3, align 4, !tbaa !14 + %add4 = fadd float %0, %1 + ret float %add4 + } + + ; Function Attrs: norecurse nounwind readonly + define <4 x i32> @testLXVX(<4 x i32>* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds <4 x i32>, <4 x i32>* %ptr, i64 %idxprom + %0 = load <4 x i32>, <4 x i32>* %arrayidx, align 16, !tbaa !3 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds <4 x i32>, <4 x i32>* %ptr, i64 %idxprom2 + %1 = load <4 x i32>, <4 x i32>* %arrayidx3, align 16, !tbaa !3 + %add4 = add <4 x i32> %1, %0 + ret <4 x i32> %add4 + } + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @testOR(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { + entry: + %or = or i32 %b, %a + ret i32 %or + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testOR8(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %or = or i64 %b, %a + ret i64 %or + } + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @testORI(i32 signext %a) local_unnamed_addr #0 { + entry: + %or = or i32 %a, 88 + ret i32 %or + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testORI8(i64 %a) local_unnamed_addr #0 { + entry: + %or = or i64 %a, 99 + ret i64 %or + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testRLDCL(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %and = and i64 %b, 63 + %shl = shl i64 %a, %and + %sub = sub nsw i64 64, %and + %shr = lshr i64 %a, %sub + %or = or i64 %shr, %shl + ret i64 %or + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testRLDCLo(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %and = and i64 %b, 63 + %shl = shl i64 %a, %and + %sub = sub nsw i64 64, %and + %shr = lshr i64 %a, %sub + %or = or i64 %shr, %shl + %tobool = icmp eq i64 %or, 0 + %cond = select i1 %tobool, i64 %and, i64 %a + ret i64 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testRLDCR(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %and = and i64 %b, 63 + %shl = shl i64 %a, %and + %sub = sub nsw i64 64, %and + %shr = lshr i64 %a, %sub + %or = or i64 %shr, %shl + ret i64 %or + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testRLDCRo(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %and = and i64 %b, 63 + %shl = shl i64 %a, %and + %sub = sub nsw i64 64, %and + %shr = lshr i64 %a, %sub + %or = or i64 %shr, %shl + %tobool = icmp eq i64 %or, 0 + %cond = select i1 %tobool, i64 %and, i64 %a + ret i64 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testRLDICL(i64 %a) local_unnamed_addr #0 { + entry: + %shr = lshr i64 %a, 11 + %and = and i64 %shr, 16777215 + ret i64 %and + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testRLDICLo(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %shr = lshr i64 %a, 11 + %and = and i64 %shr, 16777215 + %tobool = icmp eq i64 %and, 0 + %cond = select i1 %tobool, i64 %b, i64 %and + ret i64 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define zeroext i32 @testRLWINM(i32 zeroext %a) local_unnamed_addr #0 { + entry: + %shl = shl i32 %a, 4 + %and = and i32 %shl, 4080 + ret i32 %and + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testRLWINM8(i64 %a) local_unnamed_addr #0 { + entry: + %shl = shl i64 %a, 4 + %and = and i64 %shl, 4080 + ret i64 %and + } + + ; Function Attrs: norecurse nounwind readnone + define zeroext i32 @testRLWINMo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 { + entry: + %and = and i32 %a, 255 + %tobool = icmp eq i32 %and, 0 + %cond = select i1 %tobool, i32 %b, i32 %a + ret i32 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testRLWINM8o(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %a.tr = trunc i64 %a to i32 + %0 = shl i32 %a.tr, 4 + %conv = and i32 %0, 4080 + %tobool = icmp eq i32 %conv, 0 + %conv1 = zext i32 %conv to i64 + %cond = select i1 %tobool, i64 %b, i64 %conv1 + ret i64 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testSLD(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %shl = shl i64 %a, %b + ret i64 %shl + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testSLDo(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %shl = shl i64 %a, %b + %tobool = icmp eq i64 %shl, 0 + %cond = select i1 %tobool, i64 %b, i64 %a + ret i64 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testSRD(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %shr = lshr i64 %a, %b + ret i64 %shr + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testSRDo(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %shr = lshr i64 %a, %b + %tobool = icmp eq i64 %shr, 0 + %cond = select i1 %tobool, i64 %b, i64 %a + ret i64 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define zeroext i32 @testSLW(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 { + entry: + %shl = shl i32 %a, %b + ret i32 %shl + } + + ; Function Attrs: norecurse nounwind readnone + define zeroext i32 @testSLWo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 { + entry: + %shl = shl i32 %a, %b + %tobool = icmp eq i32 %shl, 0 + %cond = select i1 %tobool, i32 %b, i32 %a + ret i32 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define zeroext i32 @testSRW(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 { + entry: + %shr = lshr i32 %a, %b + ret i32 %shr + } + + ; Function Attrs: norecurse nounwind readnone + define zeroext i32 @testSRWo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 { + entry: + %shr = lshr i32 %a, %b + %tobool = icmp eq i32 %shr, 0 + %cond = select i1 %tobool, i32 %b, i32 %a + ret i32 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @testSRAW(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { + entry: + %shr = ashr i32 %a, %b + ret i32 %shr + } + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @testSRAWo(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { + entry: + %shr = ashr i32 %a, %b + %tobool = icmp eq i32 %shr, 0 + %cond = select i1 %tobool, i32 %b, i32 %shr + ret i32 %cond + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testSRAD(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %shr = ashr i64 %a, %b + ret i64 %shr + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testSRADo(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %shr = ashr i64 %a, %b + %tobool = icmp eq i64 %shr, 0 + %cond = select i1 %tobool, i64 %b, i64 %shr + ret i64 %cond + } + + ; Function Attrs: norecurse nounwind + define void @testSTBUX(i8* nocapture %ptr, i8 zeroext %a, i32 zeroext %idx) local_unnamed_addr #3 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i8, i8* %ptr, i64 %idxprom + store i8 %a, i8* %arrayidx, align 1, !tbaa !3 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i8, i8* %ptr, i64 %idxprom2 + store i8 %a, i8* %arrayidx3, align 1, !tbaa !3 + ret void + } + + ; Function Attrs: norecurse nounwind + define void @testSTBX(i8* nocapture %ptr, i8 zeroext %a, i32 zeroext %idx) local_unnamed_addr #3 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i8, i8* %ptr, i64 %idxprom + store i8 %a, i8* %arrayidx, align 1, !tbaa !3 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i8, i8* %ptr, i64 %idxprom2 + store i8 %a, i8* %arrayidx3, align 1, !tbaa !3 + ret void + } + + ; Function Attrs: norecurse nounwind + define void @testSTHUX(i16* nocapture %ptr, i16 zeroext %a, i32 zeroext %idx) local_unnamed_addr #3 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i16, i16* %ptr, i64 %idxprom + store i16 %a, i16* %arrayidx, align 2, !tbaa !6 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i16, i16* %ptr, i64 %idxprom2 + store i16 %a, i16* %arrayidx3, align 2, !tbaa !6 + ret void + } + + ; Function Attrs: norecurse nounwind + define void @testSTHX(i16* nocapture %ptr, i16 zeroext %a, i32 zeroext %idx) local_unnamed_addr #3 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i16, i16* %ptr, i64 %idxprom + store i16 %a, i16* %arrayidx, align 1, !tbaa !3 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i16, i16* %ptr, i64 %idxprom2 + store i16 %a, i16* %arrayidx3, align 1, !tbaa !3 + ret void + } + + ; Function Attrs: norecurse nounwind + define void @testSTWUX(i32* nocapture %ptr, i32 zeroext %a, i32 zeroext %idx) local_unnamed_addr #3 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i32, i32* %ptr, i64 %idxprom + store i32 %a, i32* %arrayidx, align 4, !tbaa !8 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i32, i32* %ptr, i64 %idxprom2 + store i32 %a, i32* %arrayidx3, align 4, !tbaa !8 + ret void + } + + ; Function Attrs: norecurse nounwind + define void @testSTWX(i32* nocapture %ptr, i32 zeroext %a, i32 zeroext %idx) local_unnamed_addr #3 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i32, i32* %ptr, i64 %idxprom + store i32 %a, i32* %arrayidx, align 4, !tbaa !8 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i32, i32* %ptr, i64 %idxprom2 + store i32 %a, i32* %arrayidx3, align 4, !tbaa !8 + ret void + } + + ; Function Attrs: norecurse nounwind + define void @testSTDUX(i64* nocapture %ptr, i64 %a, i32 zeroext %idx) local_unnamed_addr #3 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i64, i64* %ptr, i64 %idxprom + store i64 %a, i64* %arrayidx, align 8, !tbaa !10 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i64, i64* %ptr, i64 %idxprom2 + store i64 %a, i64* %arrayidx3, align 8, !tbaa !10 + ret void + } + + ; Function Attrs: norecurse nounwind + define void @testSTDX(i64* nocapture %ptr, i64 %a, i32 zeroext %idx) local_unnamed_addr #3 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds i64, i64* %ptr, i64 %idxprom + store i64 %a, i64* %arrayidx, align 8, !tbaa !10 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds i64, i64* %ptr, i64 %idxprom2 + store i64 %a, i64* %arrayidx3, align 8, !tbaa !10 + ret void + } + + ; Function Attrs: norecurse nounwind readonly + define void @testSTFSX(float* nocapture %ptr, float %a, i32 zeroext %idx) local_unnamed_addr #2 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds float, float* %ptr, i64 %idxprom + store float %a, float* %arrayidx, align 4, !tbaa !14 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds float, float* %ptr, i64 %idxprom2 + store float %a, float* %arrayidx3, align 4, !tbaa !14 + ret void + } + + ; Function Attrs: norecurse nounwind readonly + define void @testSTFSUX(float* nocapture %ptr, float %a, i32 zeroext %idx) local_unnamed_addr #2 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds float, float* %ptr, i64 %idxprom + store float %a, float* %arrayidx, align 4, !tbaa !14 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds float, float* %ptr, i64 %idxprom2 + store float %a, float* %arrayidx3, align 4, !tbaa !14 + ret void + } + + ; Function Attrs: norecurse nounwind readonly + define void @testSTFDX(double* nocapture %ptr, double %a, i32 zeroext %idx) local_unnamed_addr #2 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds double, double* %ptr, i64 %idxprom + store double %a, double* %arrayidx, align 8, !tbaa !12 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds double, double* %ptr, i64 %idxprom2 + store double %a, double* %arrayidx3, align 8, !tbaa !12 + ret void + } + + ; Function Attrs: norecurse nounwind readonly + define void @testSTFDUX(double* nocapture %ptr, double %a, i32 zeroext %idx) local_unnamed_addr #2 { + entry: + %add = add i32 %idx, 1 + %idxprom = zext i32 %add to i64 + %arrayidx = getelementptr inbounds double, double* %ptr, i64 %idxprom + store double %a, double* %arrayidx, align 8, !tbaa !12 + %add1 = add i32 %idx, 2 + %idxprom2 = zext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds double, double* %ptr, i64 %idxprom2 + store double %a, double* %arrayidx3, align 8, !tbaa !12 + ret void + } + + ; Function Attrs: norecurse nounwind + define void @testSTXSSPX(float* nocapture %ptr, float %a, i32 zeroext %idx) local_unnamed_addr #3 { + entry: + %idxprom = zext i32 %idx to i64 + %arrayidx = getelementptr inbounds float, float* %ptr, i64 %idxprom + store float %a, float* %arrayidx, align 4, !tbaa !14 + ret void + } + + ; Function Attrs: norecurse nounwind + define void @testSTXSDX(double* nocapture %ptr, double %a, i32 zeroext %idx) local_unnamed_addr #3 { + entry: + %idxprom = zext i32 %idx to i64 + %arrayidx = getelementptr inbounds double, double* %ptr, i64 %idxprom + store double %a, double* %arrayidx, align 8, !tbaa !12 + ret void + } + + ; Function Attrs: norecurse nounwind + define void @testSTXVX(<4 x i32>* nocapture %ptr, <4 x i32> %a, i32 zeroext %idx) local_unnamed_addr #3 { + entry: + %idxprom = zext i32 %idx to i64 + %arrayidx = getelementptr inbounds <4 x i32>, <4 x i32>* %ptr, i64 %idxprom + store <4 x i32> %a, <4 x i32>* %arrayidx, align 16, !tbaa !3 + ret void + } + + ; Function Attrs: norecurse nounwind readnone + define i128 @testSUBFC(i128 %a, i128 %b) local_unnamed_addr #0 { + entry: + %sub = sub nsw i128 %a, %b + ret i128 %sub + } + + ; Function Attrs: norecurse nounwind readnone + define i128 @testSUBFC8(i128 %a, i128 %b) local_unnamed_addr #0 { + entry: + %sub = sub nsw i128 %a, %b + ret i128 %sub + } + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @testXOR(i32 signext %a, i32 signext %b) local_unnamed_addr #0 { + entry: + %xor = xor i32 %b, %a + ret i32 %xor + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testXOR8(i64 %a, i64 %b) local_unnamed_addr #0 { + entry: + %xor = xor i64 %b, %a + ret i64 %xor + } + + ; Function Attrs: norecurse nounwind readnone + define signext i32 @testXORI(i32 signext %a) local_unnamed_addr #0 { + entry: + %xor = xor i32 %a, 17 + ret i32 %xor + } + + ; Function Attrs: norecurse nounwind readnone + define i64 @testXOR8I(i64 %a) local_unnamed_addr #0 { + entry: + %xor = xor i64 %a, 17 + ret i64 %xor + } + + attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #1 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #2 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,-vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #3 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" } + + !llvm.module.flags = !{!0, !1} + !llvm.ident = !{!2} + + !0 = !{i32 1, !"wchar_size", i32 4} + !1 = !{i32 7, !"PIC Level", i32 2} + !2 = !{!"clang version 6.0.0 (trunk 316067)"} + !3 = !{!4, !4, i64 0} + !4 = !{!"omnipotent char", !5, i64 0} + !5 = !{!"Simple C/C++ TBAA"} + !6 = !{!7, !7, i64 0} + !7 = !{!"short", !4, i64 0} + !8 = !{!9, !9, i64 0} + !9 = !{!"int", !4, i64 0} + !10 = !{!11, !11, i64 0} + !11 = !{!"long long", !4, i64 0} + !12 = !{!13, !13, i64 0} + !13 = !{!"double", !4, i64 0} + !14 = !{!15, !15, i64 0} + !15 = !{!"float", !4, i64 0} + +... +--- +name: testADD4 +# CHECK-ALL: name: testADD4 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 5, class: gprc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI 33 + %3 = COPY %0.sub_32 + %4 = ADD4 killed %3, %2 + %5 = ADD4 killed %2, killed %4 + ; CHECK: ADDI killed %3, 33 + ; CHECK: ADDI killed %4, 33 + ; CHECK-LATE: addi 3, 3, 33 + ; CHECK-LATE: addi 3, 3, 33 + %6 = EXTSW_32_64 killed %5 + %x3 = COPY %6 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testADD8 +# CHECK-ALL: name: testADD8 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = LI8 33 + %0 = COPY %x3 + %2 = ADD8 %0, %1 + %3 = ADD8 killed %1, killed %2 + ; CHECK: ADDI8 %0, 33 + ; CHECK: ADDI8 killed %2, 33 + ; CHECK-LATE: addi 3, 3, 33 + ; CHECK-LATE: addi 3, 3, 33 + %x3 = COPY %3 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testADDC +# CHECK-ALL: name: testADDC +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: gprc, preferred-register: '' } + - { id: 6, class: gprc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } + - { reg: '%x6', virtual-reg: '%3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4, %x5, %x6 + + %3 = COPY %x6 + %2 = COPY %x5 + %1 = COPY %x4 + %0 = COPY %x3 + %4 = COPY %0.sub_32 + %5 = LI 55 + %6 = ADDC %5, %4, implicit-def %carry + ; CHECK: ADDIC %4, 55, implicit-def %carry + ; CHECK-LATE: addic 3, 3, 55 + %7 = ADDE8 %3, %1, implicit-def dead %carry, implicit %carry + %8 = EXTSW_32_64 %6 + %x3 = COPY %8 + %x4 = COPY %7 + BLR8 implicit %lr8, implicit %rm, implicit %x3, implicit %x4 + +... +--- +name: testADDC8 +# CHECK-ALL: name: testADDC8 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } + - { reg: '%x6', virtual-reg: '%3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4, %x5, %x6 + + %3 = COPY %x6 + %2 = COPY %x5 + %1 = COPY %x4 + %0 = LI8 777 + %4 = ADDC8 %2, %0, implicit-def %carry + ; CHECK: ADDIC8 %2, 777, implicit-def %carry + ; CHECK-LATE: addic 3, 5, 777 + %5 = ADDE8 %3, %1, implicit-def dead %carry, implicit %carry + %x3 = COPY %4 + %x4 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3, implicit %x4 + +... +--- +name: testADDCo +# CHECK-ALL: name: testADDCo +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: gprc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: crrc, preferred-register: '' } + - { id: 5, class: crbitrc, preferred-register: '' } + - { id: 6, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 7, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = LI 433 + %0 = COPY %x3 + %2 = COPY %0.sub_32 + %3 = ADDCo %1, %2, implicit-def %cr0, implicit-def %carry + ; CHECK: ADDICo %2, 433, implicit-def %cr0, implicit-def %carry + ; CHECK-LATE: addic. 3, 3, 433 + %4 = COPY killed %cr0 + %5 = COPY %4.sub_eq + %6 = LI8 0 + %7 = LI8 -1 + %8 = ISEL8 %7, %6, %5 + %x3 = COPY %8 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testADDI +# CHECK-ALL: name: testADDI +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3 + + %0 = COPY %x3 + %1 = LI 77 + %2 = ADDI killed %1, 44 + %3 = EXTSW_32_64 killed %2 + ; CHECK: LI 121 + ; CHECK-LATE: li 3, 121 + %x3 = COPY %3 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testADDI8 +# CHECK-ALL: name: testADDI8 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3 + + %0 = COPY %x3 + %1 = LI8 333 + %2 = ADDI8 killed %1, 44 + ; CHECK: LI8 377 + ; CHECK-LATE: li 3, 377 + %3 = EXTSW killed %2 + %x3 = COPY %3 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testANDo +# CHECK-ALL: name: testANDo +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: gprc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: crrc, preferred-register: '' } + - { id: 5, class: gprc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = LI 78 + %0 = COPY %x3 + %2 = COPY %0.sub_32 + %3 = ANDo %1, %2, implicit-def %cr0 + ; CHECK: ANDIo %2, 78, implicit-def %cr0 + ; CHECK-LATE: andi. 5, 3, 78 + %4 = COPY killed %cr0 + %5 = ISEL %2, %1, %4.sub_eq + %6 = EXTSW_32_64 killed %5 + %x3 = COPY %6 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testAND8o +# CHECK-ALL: name: testAND8o +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: crrc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = LI8 321 + %0 = COPY %x3 + %2 = AND8o %1, %0, implicit-def %cr0 + ; CHECK: ANDIo8 %0, 321, implicit-def %cr0 + ; CHECK-LATE: andi. 5, 3, 321 + %3 = COPY killed %cr0 + %4 = ISEL8 %1, %0, %3.sub_eq + %x3 = COPY %4 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testCMPD +# CHECK-ALL: name: testCMPD +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: crrc, preferred-register: '' } + - { id: 3, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = LI8 65533 + %0 = COPY %x3 + %2 = CMPD %0, %1 + ; CHECK: CMPDI %0, -3 + ; CHECK-LATE: cmpdi 3, -3 + %4 = ISEL8 %zero8, %0, %2.sub_gt + %5 = ADD8 killed %4, %1 + %x3 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testCMPDI +# CHECK-ALL: name: testCMPDI +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: crrc, preferred-register: '' } + - { id: 3, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = LI8 89 + %2 = CMPDI %0, 87 + %4 = ISEL8 %zero8, %0, %2.sub_gt + ; CHECK: LI8 0 + %5 = ADD8 killed %4, %1 + %x3 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testCMPDI_F +# CHECK-ALL: name: testCMPDI_F +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: crrc, preferred-register: '' } + - { id: 3, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = LI8 87 + %2 = CMPDI %0, 87 + %4 = ISEL8 %zero8, %0, %2.sub_gt + ; CHECK: COPY %0 + %5 = ADD8 killed %4, %1 + %x3 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testCMPLD +# CHECK-ALL: name: testCMPLD +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: crrc, preferred-register: '' } + - { id: 3, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = LI8 99 + %0 = COPY %x3 + %2 = CMPLD %0, %1 + ; CHECK: CMPLDI %0, 99 + ; CHECK-LATE: cmpldi 3, 99 + %4 = ISEL8 %zero8, %0, %2.sub_gt + %5 = ADD8 killed %4, %1 + %x3 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testCMPLDI +# CHECK-ALL: name: testCMPLDI +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: crrc, preferred-register: '' } + - { id: 3, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = LI8 65534 + %2 = CMPLDI %0, 65535 + %4 = ISEL8 %zero8, %0, %2.sub_gt + ; CHECK: COPY %0 + %5 = ADD8 killed %4, %1 + %x3 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testCMPW +# CHECK-ALL: name: testCMPW +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 4, class: crrc, preferred-register: '' } + - { id: 5, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 6, class: gprc, preferred-register: '' } + - { id: 7, class: gprc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI -1 + %3 = COPY %0.sub_32 + %4 = CMPW %3, %2 + ; CHECK: CMPWI %3, -1 + %6 = ISEL %zero, %3, %4.sub_gt + %7 = ADD4 killed %6, %2 + %8 = EXTSW_32_64 killed %7 + %x3 = COPY %8 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testCMPWI +# CHECK-ALL: name: testCMPWI +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 4, class: crrc, preferred-register: '' } + - { id: 5, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 6, class: gprc, preferred-register: '' } + - { id: 7, class: gprc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = LI -3 + %4 = CMPWI %3, 87 + %6 = ISEL %zero, %3, %4.sub_gt + ; CHECK: COPY %3 + %7 = ADD4 killed %6, killed %2 + %8 = EXTSW_32_64 killed %7 + %x3 = COPY %8 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testCMPLW +# CHECK-ALL: name: testCMPLW +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 4, class: crrc, preferred-register: '' } + - { id: 5, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 6, class: gprc, preferred-register: '' } + - { id: 7, class: gprc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI 32767 + %3 = COPY %0.sub_32 + %4 = CMPLW %3, %2 + ; CHECK: CMPLWI %3, 32767 + ; CHECK-LATE: cmplwi 3, 32767 + %6 = ISEL %zero, %3, %4.sub_gt + %7 = ADD4 killed %6, %2 + %9 = IMPLICIT_DEF + %8 = INSERT_SUBREG %9, killed %7, 1 + %10 = RLDICL killed %8, 0, 32 + %x3 = COPY %10 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testCMPLWI +# CHECK-ALL: name: testCMPLWI +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 4, class: crrc, preferred-register: '' } + - { id: 5, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 6, class: gprc, preferred-register: '' } + - { id: 7, class: gprc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = LI -3 + %4 = CMPLWI %3, 87 + %6 = ISEL %zero, %3, %4.sub_gt + ; CHECK: LI 0 + %7 = ADD4 killed %6, killed %2 + %9 = IMPLICIT_DEF + %8 = INSERT_SUBREG %9, killed %7, 1 + %10 = RLDICL killed %8, 0, 32 + %x3 = COPY %10 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testLBZUX +# CHECK-ALL: name: testLBZUX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: gprc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: gprc, preferred-register: '' } + - { id: 13, class: gprc, preferred-register: '' } + - { id: 14, class: g8rc, preferred-register: '' } + - { id: 15, class: g8rc, preferred-register: '' } + - { id: 16, class: g8rc, preferred-register: '' } + - { id: 17, class: g8rc_and_g8rc_nox0, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = RLDICL killed %4, 0, 32 + %7 = LBZX %0, killed %6 :: (load 1 from %ir.arrayidx, !tbaa !3) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 -15 + %12,%17 = LBZUX %0, killed %11 :: (load 1 from %ir.arrayidx3, !tbaa !3) + ; CHECK: LBZU -15, %0 + ; CHECK-LATE: lbzu 5, -15(3) + %13 = ADD4 killed %12, killed %7 + %15 = IMPLICIT_DEF + %14 = INSERT_SUBREG %15, killed %13, 1 + %16 = RLWINM8 killed %14, 0, 24, 31 + %x3 = COPY %16 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testLBZX +# CHECK-ALL: name: testLBZX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: gprc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: gprc, preferred-register: '' } + - { id: 13, class: gprc, preferred-register: '' } + - { id: 14, class: g8rc, preferred-register: '' } + - { id: 15, class: g8rc, preferred-register: '' } + - { id: 16, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = LI8 45 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = RLDICL killed %4, 0, 32 + %7 = LBZX %0, killed %6 :: (load 1 from %ir.arrayidx, !tbaa !3) + ; CHECK: LBZ 45, killed %6 + ; CHECK-LATE: lbz 5, 45(5) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = RLDICL killed %9, 0, 32 + %12 = LBZX %0, killed %11 :: (load 1 from %ir.arrayidx3, !tbaa !3) + ; CHECK: LBZ 45, killed %11 + ; CHECK-LATE: lbz 3, 45(4) + %13 = ADD4 killed %12, killed %7 + %15 = IMPLICIT_DEF + %14 = INSERT_SUBREG %15, killed %13, 1 + %16 = RLWINM8 killed %14, 0, 24, 31 + %x3 = COPY %16 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testLHZUX +# CHECK-ALL: name: testLHZUX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: gprc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: gprc, preferred-register: '' } + - { id: 13, class: gprc, preferred-register: '' } + - { id: 14, class: g8rc, preferred-register: '' } + - { id: 15, class: g8rc, preferred-register: '' } + - { id: 16, class: g8rc, preferred-register: '' } + - { id: 17, class: g8rc_and_g8rc_nox0, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = RLDIC killed %4, 1, 31 + %7 = LHZX %0, killed %6 :: (load 2 from %ir.arrayidx, !tbaa !6) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 31440 + %12,%17 = LHZUX %0, killed %11 :: (load 2 from %ir.arrayidx3, !tbaa !6) + ; CHECK: LHZU 31440, %0 + ; CHECK-LATE: lhzu 5, 31440(3) + %13 = ADD4 killed %12, killed %7 + %15 = IMPLICIT_DEF + %14 = INSERT_SUBREG %15, killed %13, 1 + %16 = RLWINM8 killed %14, 0, 16, 31 + %x3 = COPY %16 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testLHZX +# CHECK-ALL: name: testLHZX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: gprc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: gprc, preferred-register: '' } + - { id: 13, class: gprc, preferred-register: '' } + - { id: 14, class: g8rc, preferred-register: '' } + - { id: 15, class: g8rc, preferred-register: '' } + - { id: 16, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = RLDIC killed %4, 1, 31 + %7 = LHZX %0, killed %6 :: (load 2 from %ir.arrayidx, !tbaa !6) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 882 + %12 = LHZX %0, killed %11 :: (load 2 from %ir.arrayidx3, !tbaa !6) + ; CHECK: LHZ 882, %0 + ; CHECK-LATE: lhz 3, 882(3) + %13 = ADD4 killed %12, killed %7 + %15 = IMPLICIT_DEF + %14 = INSERT_SUBREG %15, killed %13, 1 + %16 = RLWINM8 killed %14, 0, 16, 31 + %x3 = COPY %16 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testLHAUX +# CHECK-ALL: name: testLHAUX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: gprc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: gprc, preferred-register: '' } + - { id: 13, class: gprc, preferred-register: '' } + - { id: 14, class: g8rc, preferred-register: '' } + - { id: 15, class: g8rc, preferred-register: '' } + - { id: 16, class: g8rc, preferred-register: '' } + - { id: 17, class: g8rc_and_g8rc_nox0, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = RLDIC %4, 1, 31 + %7 = LHZX %0, killed %6 :: (load 2 from %ir.arrayidx, !tbaa !6) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 400 + %12,%17 = LHAUX %0, killed %11 :: (load 2 from %ir.arrayidx3, !tbaa !6) + ; CHECK: LHAU 400, %0 + ; CHECK-LATE: lhau 5, 400(3) + %13 = ADD4 killed %12, killed %7 + %15 = IMPLICIT_DEF + %14 = INSERT_SUBREG %15, killed %13, 1 + %16 = EXTSH8 killed %14 + %x3 = COPY %16 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testLHAX +# CHECK-ALL: name: testLHAX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: gprc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: gprc, preferred-register: '' } + - { id: 13, class: gprc, preferred-register: '' } + - { id: 14, class: g8rc, preferred-register: '' } + - { id: 15, class: g8rc, preferred-register: '' } + - { id: 16, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = LI8 -999 + %7 = LHAX %0, killed %6 :: (load 2 from %ir.arrayidx, !tbaa !6) + ; CHECK: LHA -999, %0 + ; CHECK-LATE: lha 4, -999(3) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 999 + %12 = LHAX %0, killed %11 :: (load 2 from %ir.arrayidx3, !tbaa !6) + ; CHECK: LHA 999, %0 + ; CHECK-LATE: lha 3, 999(3) + %13 = ADD4 killed %12, killed %7 + %15 = IMPLICIT_DEF + %14 = INSERT_SUBREG %15, killed %13, 1 + %16 = EXTSH8 killed %14 + %x3 = COPY %16 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testLWZUX +# CHECK-ALL: name: testLWZUX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: gprc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: gprc, preferred-register: '' } + - { id: 13, class: gprc, preferred-register: '' } + - { id: 14, class: g8rc, preferred-register: '' } + - { id: 15, class: g8rc, preferred-register: '' } + - { id: 16, class: g8rc, preferred-register: '' } + - { id: 17, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 18, class: g8rc_and_g8rc_nox0, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = LI8 889 + %7,%17 = LWZUX %0, killed %6 :: (load 4 from %ir.arrayidx, !tbaa !8) + ; CHECK: LWZU 889, %0 + ; CHECK-LATE: lwzu 5, 889(4) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 -2 + %12,%18 = LWZUX %0, killed %11 :: (load 4 from %ir.arrayidx3, !tbaa !8) + ; CHECK: LWZU -2, %0 + ; CHECK-LATE: lwzu 4, -2(3) + %13 = ADD4 killed %12, killed %7 + %15 = IMPLICIT_DEF + %14 = INSERT_SUBREG %15, killed %13, 1 + %16 = RLDICL killed %14, 0, 32 + %x3 = COPY %16 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testLWZX +# CHECK-ALL: name: testLWZX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: gprc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: gprc, preferred-register: '' } + - { id: 13, class: gprc, preferred-register: '' } + - { id: 14, class: g8rc, preferred-register: '' } + - { id: 15, class: g8rc, preferred-register: '' } + - { id: 16, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = LI8 1000 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = RLDIC %4, 2, 30 + %7 = LWZX %0, killed %6 :: (load 4 from %ir.arrayidx, !tbaa !8) + ; CHECK: LWZ 1000, killed %6 + ; CHECK-LATE: lwz 5, 1000(5) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = RLDIC %9, 2, 30 + %12 = LWZX %0, killed %11 :: (load 4 from %ir.arrayidx3, !tbaa !8) + ; CHECK: LWZ 1000, killed %11 + ; CHECK-LATE: lwz 3, 1000(4) + %13 = ADD4 killed %12, killed %7 + %15 = IMPLICIT_DEF + %14 = INSERT_SUBREG %15, killed %13, 1 + %16 = RLDICL killed %14, 0, 32 + %x3 = COPY %16 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testLWAX +# CHECK-ALL: name: testLWAX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: g8rc, preferred-register: '' } + - { id: 13, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = LI8 444 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = RLDIC %4, 2, 30 + %7 = LWAX %0, killed %6 :: (load 4 from %ir.arrayidx, !tbaa !8) + ; CHECK: LWA 444, killed %6 + ; CHECK-LATE: lwa 5, 444(5) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = RLDIC %9, 2, 30 + %12 = LWAX %0, killed %11 :: (load 4 from %ir.arrayidx3, !tbaa !8) + ; CHECK: LWA 444, killed %11 + ; CHECK-LATE: lwa 3, 444(4) + %13 = ADD8 killed %12, killed %7 + %x3 = COPY %13 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testLDUX +# CHECK-ALL: name: testLDUX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: g8rc, preferred-register: '' } + - { id: 13, class: g8rc, preferred-register: '' } + - { id: 14, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 15, class: g8rc_and_g8rc_nox0, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = LI8 100 + %7,%14 = LDUX %0, killed %6 :: (load 8 from %ir.arrayidx, !tbaa !10) + ; CHECK: LDU 100, %0 + ; CHECK-LATE: ldu 5, 100(4) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 200 + %12,%15 = LDUX %0, killed %11 :: (load 8 from %ir.arrayidx3, !tbaa !10) + ; CHECK: LDU 200, %0 + ; CHECK-LATE: ldu 4, 200(3) + %13 = ADD8 killed %12, killed %7 + %x3 = COPY %13 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testLDX +# CHECK-ALL: name: testLDX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: g8rc, preferred-register: '' } + - { id: 13, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = LI8 120 + %7 = LDX %0, killed %6 :: (load 8 from %ir.arrayidx, !tbaa !10) + ; CHECK: LD 120, %0 + ; CHECK-LATE: ld 4, 120(3) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 280 + %12 = LDX %0, killed %11 :: (load 8 from %ir.arrayidx3, !tbaa !10) + ; CHECK: LD 280, %0 + ; CHECK-LATE: ld 12, 280(3) + %13 = ADD8 killed %12, killed %7 + %x3 = COPY %13 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testLFDUX +# CHECK-ALL: name: testLFDUX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: f8rc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: f8rc, preferred-register: '' } + - { id: 13, class: f8rc, preferred-register: '' } + - { id: 14, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 15, class: g8rc_and_g8rc_nox0, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = LI8 440 + %7,%14 = LFDUX %0, killed %6 :: (load 8 from %ir.arrayidx, !tbaa !12) + ; CHECK: LFDU 440, %0 + ; CHECK-LATE: lfdu 0, 440(4) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 16 + %12,%15 = LFDUX %0, killed %11 :: (load 8 from %ir.arrayidx3, !tbaa !12) + ; CHECK: LFDU 16, %0 + ; CHECK-LATE: lfdu 1, 16(3) + %13 = FADD killed %7, killed %12, implicit %rm + %f1 = COPY %13 + BLR8 implicit %lr8, implicit %rm, implicit %f1 + +... +--- +name: testLFDX +# CHECK-ALL: name: testLFDX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: f8rc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: f8rc, preferred-register: '' } + - { id: 13, class: f8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = LI8 -20 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = RLDIC %4, 3, 29 + %7 = LFDX %0, killed %6 :: (load 8 from %ir.arrayidx, !tbaa !12) + ; CHECK: LFD -20, killed %6 + ; CHECK-LATE: lfd 0, -20(5) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = RLDIC %9, 3, 29 + %12 = LFDX %0, killed %11 :: (load 8 from %ir.arrayidx3, !tbaa !12) + ; CHECK: LFD -20, killed %11 + ; CHECK-LATE: lfd 1, -20(4) + %13 = FADD killed %7, killed %12, implicit %rm + %f1 = COPY %13 + BLR8 implicit %lr8, implicit %rm, implicit %f1 + +... +--- +name: testLFSUX +# CHECK-ALL: name: testLFSUX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: f8rc, preferred-register: '' } + - { id: 4, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 5, class: f8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: gprc, preferred-register: '' } + - { id: 8, class: f8rc, preferred-register: '' } + - { id: 9, class: f8rc, preferred-register: '' } + - { id: 10, class: f8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: gprc, preferred-register: '' } + - { id: 13, class: f8rc, preferred-register: '' } + - { id: 14, class: f8rc, preferred-register: '' } + - { id: 15, class: f8rc, preferred-register: '' } + - { id: 16, class: g8rc, preferred-register: '' } + - { id: 17, class: gprc, preferred-register: '' } + - { id: 18, class: f8rc, preferred-register: '' } + - { id: 19, class: f8rc, preferred-register: '' } + - { id: 20, class: f8rc, preferred-register: '' } + - { id: 21, class: g8rc, preferred-register: '' } + - { id: 22, class: gprc, preferred-register: '' } + - { id: 23, class: g8rc, preferred-register: '' } + - { id: 24, class: vrrc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 16 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: + - { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 16, + stack-id: 0, callee-saved-register: '', callee-saved-restored: true, + local-offset: -16, di-variable: '', di-expression: '', di-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: 0, callee-saved-register: '', callee-saved-restored: true, + local-offset: -20, di-variable: '', di-expression: '', di-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: 0, callee-saved-register: '', callee-saved-restored: true, + local-offset: -24, di-variable: '', di-expression: '', di-location: '' } + - { id: 3, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: 0, callee-saved-register: '', callee-saved-restored: true, + local-offset: -28, di-variable: '', di-expression: '', di-location: '' } + - { id: 4, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: 0, callee-saved-register: '', callee-saved-restored: true, + local-offset: -32, di-variable: '', di-expression: '', di-location: '' } +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI8 72 + %3, %4 = LFSUX %0, killed %2 :: (load 4 from %ir.arrayidx, !tbaa !14) + ; CHECK: LFSU 72, %0 + ; CHECK-LATE: lfsu 0, 72(3) + %5 = FCTIWUZ killed %3, implicit %rm + %6 = ADDI8 %stack.4, 0 + STFIWX killed %5, %zero8, killed %6 + %7 = LWZ 0, %stack.4 :: (load 4 from %stack.4) + %8 = LFS 4, %4 :: (load 4 from %ir.3, !tbaa !14) + %10 = FCTIWUZ %8, implicit %rm + %11 = ADDI8 %stack.1, 0 + STFIWX killed %10, %zero8, killed %11 + %12 = LWZ 0, %stack.1 :: (load 4 from %stack.1) + %13 = LFS 8, %4 :: (load 4 from %ir.5, !tbaa !14) + %15 = FCTIWUZ %13, implicit %rm + %16 = ADDI8 %stack.2, 0 + STFIWX killed %15, %zero8, killed %16 + %17 = LWZ 0, %stack.2 :: (load 4 from %stack.2) + %18 = LFS 12, %4 :: (load 4 from %ir.7, !tbaa !14) + %20 = FCTIWUZ %18, implicit %rm + %21 = ADDI8 %stack.3, 0 + STFIWX killed %20, %zero8, killed %21 + %22 = LWZ 0, %stack.3 :: (load 4 from %stack.3) + STW killed %7, 0, %stack.0 :: (store 4 into %stack.0, align 16) + STW killed %22, 12, %stack.0 :: (store 4 into %stack.0 + 12) + STW killed %17, 8, %stack.0 :: (store 4 into %stack.0 + 8, align 8) + STW killed %12, 4, %stack.0 :: (store 4 into %stack.0 + 4) + %23 = ADDI8 %stack.0, 0 + %24 = LVX %zero8, killed %23 :: (load 16 from %stack.0) + %v2 = COPY %24 + BLR8 implicit %lr8, implicit %rm, implicit %v2 + +... +--- +name: testLFSX +# CHECK-ALL: name: testLFSX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: f4rc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: f4rc, preferred-register: '' } + - { id: 13, class: f4rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = LI8 88 + %7 = LFSX %0, killed %6 :: (load 4 from %ir.arrayidx, !tbaa !14) + ; CHECK: LFS 88, %0 + ; CHECK-LATE: lfs 0, 88(3) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 -88 + %12 = LFSX %0, killed %11 :: (load 4 from %ir.arrayidx3, !tbaa !14) + ; CHECK: LFS -88, %0 + ; CHECK-LATE: lfs 1, -88(3) + %13 = FADDS killed %7, killed %12, implicit %rm + %f1 = COPY %13 + BLR8 implicit %lr8, implicit %rm, implicit %f1 + +... +--- +name: testLXSDX +# CHECK-ALL: name: testLXSDX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: vsfrc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: vsfrc, preferred-register: '' } + - { id: 13, class: vsfrc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = LI8 100 + %7 = LXSDX %0, killed %6, implicit %rm :: (load 8 from %ir.arrayidx, !tbaa !12) + ; CHECK: LXSD 100, %0 + ; CHECK-LATE: lxsd 0, 100(3) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 -120 + %12 = LXSDX %0, killed %11, implicit %rm :: (load 8 from %ir.arrayidx3, !tbaa !12) + ; CHECK: LXSD -120, %0 + ; CHECK-LATE: lxsd 1, -120(3) + %13 = XSADDDP killed %7, killed %12, implicit %rm + %f1 = COPY %13 + BLR8 implicit %lr8, implicit %rm, implicit %f1 + +... +--- +name: testLXSSPX +# CHECK-ALL: name: testLXSSPX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: vssrc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: vssrc, preferred-register: '' } + - { id: 13, class: vssrc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = LI8 96 + %7 = LXSSPX %0, killed %6 :: (load 4 from %ir.arrayidx, !tbaa !14) + ; CHECK: LXSSP 96, %0 + ; CHECK-LATE: lxssp 0, 96(3) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 -92 + %12 = LXSSPX %0, killed %11 :: (load 4 from %ir.arrayidx3, !tbaa !14) + ; CHECK: LXSSP -92, %0 + ; CHECK-LATE: lxssp 1, -92(3) + %13 = XSADDSP killed %7, killed %12 + %f1 = COPY %13 + BLR8 implicit %lr8, implicit %rm, implicit %f1 + +... +--- +name: testLXVX +# CHECK-ALL: name: testLXVX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: vrrc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: vrrc, preferred-register: '' } + - { id: 13, class: vrrc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = ADDI %2, 1 + %5 = IMPLICIT_DEF + %4 = INSERT_SUBREG %5, killed %3, 1 + %6 = LI8 32 + %7 = LXVX %0, killed %6 :: (load 16 from %ir.arrayidx, !tbaa !3) + ; CHECK: LXV 32, %0 + ; CHECK-LATE: lxv 34, 32(3) + %8 = ADDI %2, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 -16 + %12 = LXVX %0, killed %11 :: (load 16 from %ir.arrayidx3, !tbaa !3) + ; CHECK: LXV -16, %0 + ; CHECK-LATE: lxv 35, -16(3) + %13 = VADDUWM killed %12, killed %7 + %v2 = COPY %13 + BLR8 implicit %lr8, implicit %rm, implicit %v2 + +... +--- +name: testOR +# CHECK-ALL: name: testOR +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gprc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = LI 99 + %3 = COPY %1.sub_32 + %2 = OR %0, %3 + ; CHECK: ORI %3, 99 + ; CHECK-LATE: ori 3, 4, 99 + %x3 = EXTSW_32_64 %2 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testOR8 +# CHECK-ALL: name: testOR8 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = LI8 777 + %2 = OR8 %1, %0 + ; CHECK: ORI8 %1, 777 + ; CHECK-LATE: ori 3, 4, 777 + %x3 = COPY %2 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testORI +# CHECK-ALL: name: testORI +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gprc, preferred-register: '' } + - { id: 1, class: gprc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3 + + %0 = LI 777 + %1 = ORI %0, 88 + ; CHECK: LI 857 + ; CHECK-LATE: li 3, 857 + %x3 = EXTSW_32_64 %1 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testORI8 +# CHECK-ALL: name: testORI8 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3 + + %0 = LI8 8721 + %1 = ORI8 %0, 99 + ; CHECK: LI8 8819 + ; CHECK-LATE: li 3, 8819 + %x3 = COPY %1 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testRLDCL +# CHECK-ALL: name: testRLDCL +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = LI 14 + %4 = RLDCL %0, killed %3, 0 + ; CHECK: RLDICL %0, 14, 0 + ; CHECK-LATE: rotldi 3, 3, 14 + %x3 = COPY %4 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testRLDCLo +# CHECK-ALL: name: testRLDCLo +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: crrc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = RLDICL %1, 0, 58 + %3 = LI 37 + %4 = RLDCLo %0, killed %3, 0, implicit-def %cr0 + ; CHECK: RLDICLo %0, 37, 0, implicit-def %cr0 + ; CHECK-LATE: rldicl. 5, 3, 37, 0 + %5 = COPY killed %cr0 + %6 = ISEL8 %2, %0, %5.sub_eq + %x3 = COPY %6 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testRLDCR +# CHECK-ALL: name: testRLDCR +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = LI 0 + %4 = RLDCR %0, killed %3, 0 + ; CHECK: RLDICR %0, 0, 0 + ; CHECK-LATE: rldicr 3, 3, 0, 0 + %x3 = COPY %4 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testRLDCRo +# CHECK-ALL: name: testRLDCRo +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: crrc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = RLDICL %1, 0, 58 + %3 = LI 18 + %4 = RLDCRo %0, killed %3, 0, implicit-def %cr0 + ; CHECK: RLDICRo %0, 18, 0, implicit-def %cr0 + ; CHECK-LATE: rldicr. 5, 3, 18, 0 + %5 = COPY killed %cr0 + %6 = ISEL8 %2, %0, %5.sub_eq + %x3 = COPY %6 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testRLDICL +# CHECK-ALL: name: testRLDICL +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3 + + %0 = LI8 -1 + %1 = RLDICL %0, 53, 49 + ; CHECK: LI8 32767 + ; CHECK-LATE: li 3, 32767 + %x3 = COPY %1 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testRLDICLo +# CHECK-ALL: name: testRLDICLo +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 3, class: crrc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = LI8 -1 + %2 = RLDICLo %0, 53, 48, implicit-def %cr0 + ; CHECK: ANDIo8 %0, 65535 + ; CHECK-LATE: li 3, -1 + ; CHECK-LATE: andi. 3, 3, 65535 + %3 = COPY killed %cr0 + %4 = ISEL8 %1, %2, %3.sub_eq + %x3 = COPY %4 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testRLWINM +# CHECK-ALL: name: testRLWINM +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: gprc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3 + + %0 = COPY %x3 + %1 = COPY %0.sub_32 + %3 = IMPLICIT_DEF + %2 = LI 17 + %4 = RLWINM killed %2, 4, 20, 27 + ; CHECK: LI 272 + ; CHECK-LATE: li 3, 272 + %x3 = EXTSW_32_64 %4 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testRLWINM8 +# CHECK-ALL: name: testRLWINM8 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3 + + %0 = LI8 234 + %1 = RLWINM8 %0, 4, 20, 27 + ; CHECK: LI8 3744 + ; CHECK-LATE: li 3, 3744 + %x3 = COPY %1 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testRLWINMo +# CHECK-ALL: name: testRLWINMo +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: crrc, preferred-register: '' } + - { id: 6, class: gprc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %3 = LI -22 + %4 = RLWINMo %3, 0, 24, 31, implicit-def %cr0 + ; CHECK: ANDIo %3, 234 + ; CHECK-LATE: li 3, -22 + ; CHECK-LATE: andi. 5, 3, 234 + %5 = COPY killed %cr0 + %6 = ISEL %2, %3, %5.sub_eq + %8 = IMPLICIT_DEF + %7 = INSERT_SUBREG %8, killed %6, 1 + %9 = RLDICL killed %7, 0, 32 + %x3 = COPY %9 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testRLWINM8o +# CHECK-ALL: name: testRLWINM8o +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 7, class: crrc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI8 -18 + %3 = RLWINM8o %2, 4, 20, 27, implicit-def %cr0 + ; CHECK: ANDIo8 %2, 3808 + ; CHECK-LATE: li 3, -18 + ; CHECK-LATE: andi. 3, 3, 3808 + %7 = COPY killed %cr0 + %6 = RLDICL killed %3, 0, 32 + %8 = ISEL8 %1, %6, %7.sub_eq + %x3 = COPY %8 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testSLD +# CHECK-ALL: name: testSLD +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI 13 + %3 = SLD %0, killed %2 + ; CHECK: RLDICR %0, 13, 50 + ; CHECK-LATE: sldi 3, 3, 13 + %x3 = COPY %3 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testSLDo +# CHECK-ALL: name: testSLDo +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } + - { id: 4, class: crrc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI 17 + %3 = SLDo %0, killed %2, implicit-def %cr0 + ; CHECK: RLDICRo %0, 17, 46, implicit-def %cr0 + ; CHECK-LATE: rldicr. 5, 3, 17, 46 + %4 = COPY killed %cr0 + %5 = ISEL8 %1, %0, %4.sub_eq + %x3 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testSRD +# CHECK-ALL: name: testSRD +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI 4 + %3 = SRD %0, killed %2 + ; CHECK: RLDICL %0, 60, 4 + ; CHECK-LATE: rldicl 3, 3, 60, 4 + %x3 = COPY %3 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testSRDo +# CHECK-ALL: name: testSRDo +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } + - { id: 4, class: crrc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI 17 + %3 = SRDo %0, killed %2, implicit-def %cr0 + ; CHECK: RLDICLo %0, 47, 17, implicit-def %cr0 + ; CHECK-LATE: rldicl. 5, 3, 47, 17 + %4 = COPY killed %cr0 + %5 = ISEL8 %1, %0, %4.sub_eq + %x3 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testSLW +# CHECK-ALL: name: testSLW +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: gprc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = COPY %1.sub_32 + %5 = LI 21 + %8 = SLW killed %2, killed %5 + ; CHECK: RLWINM killed %2, 21, 0, 10 + ; CHECK-LATE: slwi 3, 4, 21 + %x3 = EXTSW_32_64 %8 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testSLWo +# CHECK-ALL: name: testSLWo +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: crrc, preferred-register: '' } + - { id: 6, class: gprc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI 11 + %3 = COPY %0.sub_32 + %4 = SLWo %3, %2, implicit-def %cr0 + ; CHECK: RLWINMo %3, 11, 0, 20, implicit-def %cr0 + ; CHECK-LATE: rlwinm. 5, 3, 11, 0, 20 + %5 = COPY killed %cr0 + %6 = ISEL %2, %3, %5.sub_eq + %8 = IMPLICIT_DEF + %7 = INSERT_SUBREG %8, killed %6, 1 + %9 = RLDICL killed %7, 0, 32 + %x3 = COPY %9 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testSRW +# CHECK-ALL: name: testSRW +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: gprc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI 8 + %5 = COPY %0.sub_32 + %8 = SRW killed %5, killed %2 + ; CHECK: RLWINM killed %5, 24, 8, 31 + ; CHECK-LATE: srwi 3, 3, 8 + %x3 = EXTSW_32_64 %8 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testSRWo +# CHECK-ALL: name: testSRWo +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: crrc, preferred-register: '' } + - { id: 6, class: gprc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI 7 + %3 = COPY %0.sub_32 + %4 = SRWo %3, %2, implicit-def %cr0 + ; CHECK: RLWINMo %3, 25, 7, 31 + ; CHECK-LATE: rlwinm. 5, 3, 25, 7, 31 + %5 = COPY killed %cr0 + %6 = ISEL %2, %3, %5.sub_eq + %8 = IMPLICIT_DEF + %7 = INSERT_SUBREG %8, killed %6, 1 + %9 = RLDICL killed %7, 0, 32 + %x3 = COPY %9 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testSRAW +# CHECK-ALL: name: testSRAW +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI 15 + %3 = COPY %0.sub_32 + %4 = SRAW killed %3, killed %2, implicit-def dead %carry + ; CHECK: SRAWI killed %3, 15, implicit-def dead %carry + ; CHECK-LATE: srawi 3, 3, 15 + %5 = EXTSW_32_64 killed %4 + %x3 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testSRAWo +# CHECK-ALL: name: testSRAWo +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 5, class: crrc, preferred-register: '' } + - { id: 6, class: gprc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI 8 + %3 = COPY %0.sub_32 + %4 = SRAWo killed %3, %2, implicit-def dead %carry, implicit-def %cr0 + ; CHECK: SRAWIo killed %3, 8, implicit-def dead %carry, implicit-def %cr0 + ; CHECK-LATE: srawi. 3, 3, 8 + %5 = COPY killed %cr0 + %6 = ISEL %2, %4, %5.sub_eq + %7 = EXTSW_32_64 killed %6 + %x3 = COPY %7 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testSRAD +# CHECK-ALL: name: testSRAD +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI 44 + %3 = SRAD %0, killed %2, implicit-def dead %carry + ; CHECK: SRADI %0, 44, implicit-def dead %carry + ; CHECK-LATE: sradi 3, 3, 44 + %x3 = COPY %3 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testSRADo +# CHECK-ALL: name: testSRADo +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 4, class: crrc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = COPY %x3 + %2 = LI 61 + %3 = SRADo %0, killed %2, implicit-def dead %carry, implicit-def %cr0 + ; CHECK: SRADIo %0, 61, implicit-def dead %carry, implicit-def %cr0 + ; CHECK-LATE: sradi. 3, 3, 61 + %4 = COPY killed %cr0 + %5 = ISEL8 %1, %3, %4.sub_eq + %x3 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testSTBUX +# CHECK-ALL: name: testSTBUX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 5, class: gprc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } + - { id: 9, class: gprc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: g8rc, preferred-register: '' } + - { id: 13, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 14, class: g8rc_and_g8rc_nox0, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4, %x5 + + %2 = COPY %x5 + %1 = COPY %x4 + %0 = COPY %x3 + %3 = COPY %1.sub_32 + %4 = COPY %2.sub_32 + %5 = ADDI %4, 1 + %7 = IMPLICIT_DEF + %6 = INSERT_SUBREG %7, killed %5, 1 + %8 = LI8 966 + %13 = STBUX %3, %0, killed %8 :: (store 1 into %ir.arrayidx, !tbaa !3) + ; CHECK: STBU %3, 966, %0 + ; CHECK-LATE: 4, 966(5) + %9 = ADDI %4, 2 + %11 = IMPLICIT_DEF + %10 = INSERT_SUBREG %11, killed %9, 1 + %12 = LI8 777 + %14 = STBUX %3, %0, killed %12 :: (store 1 into %ir.arrayidx3, !tbaa !3) + ; CHECK: STBU %3, 777, %0 + ; CHECK-LATE: 4, 777(3) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSTBX +# CHECK-ALL: name: testSTBX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 5, class: gprc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } + - { id: 9, class: gprc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4, %x5 + + %2 = COPY %x5 + %1 = COPY %x4 + %0 = LI8 975 + %3 = COPY %1.sub_32 + %4 = COPY %2.sub_32 + %5 = ADDI %4, 1 + %7 = IMPLICIT_DEF + %6 = INSERT_SUBREG %7, killed %5, 1 + %8 = RLDICL killed %6, 0, 32 + STBX %3, %0, killed %8 :: (store 1 into %ir.arrayidx, !tbaa !3) + ; CHECK: STB %3, 975, killed %8 + ; CHECK-LATE: stb 4, 975(6) + %9 = ADDI %4, 2 + %11 = IMPLICIT_DEF + %10 = INSERT_SUBREG %11, killed %9, 1 + %12 = RLDICL killed %10, 0, 32 + STBX %3, %0, killed %12 :: (store 1 into %ir.arrayidx3, !tbaa !3) + ; CHECK: STB %3, 975, killed %12 + ; CHECK-LATE: stb 4, 975(5) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSTHUX +# CHECK-ALL: name: testSTHUX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 5, class: gprc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } + - { id: 9, class: gprc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: g8rc, preferred-register: '' } + - { id: 13, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 14, class: g8rc_and_g8rc_nox0, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4, %x5 + + %2 = COPY %x5 + %1 = COPY %x4 + %0 = COPY %x3 + %3 = COPY %1.sub_32 + %4 = COPY %2.sub_32 + %5 = ADDI %4, 1 + %7 = IMPLICIT_DEF + %6 = INSERT_SUBREG %7, killed %5, 1 + %8 = LI8 32000 + %13 = STHUX %3, %0, killed %8 :: (store 2 into %ir.arrayidx, !tbaa !6) + ; CHECK: STHU %3, 32000, %0 + ; CHECK-LATE: sthu 4, 32000(5) + %9 = ADDI %4, 2 + %11 = IMPLICIT_DEF + %10 = INSERT_SUBREG %11, killed %9, 1 + %12 = LI8 -761 + %14 = STHUX %3, %0, killed %12 :: (store 2 into %ir.arrayidx3, !tbaa !6) + ; CHECK: STHU %3, -761, %0 + ; CHECK-LATE: sthu 4, -761(3) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSTHX +# CHECK-ALL: name: testSTHX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 5, class: gprc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } + - { id: 9, class: gprc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4, %x5 + + %2 = COPY %x5 + %1 = COPY %x4 + %0 = COPY %x3 + %3 = COPY %1.sub_32 + %4 = COPY %2.sub_32 + %5 = ADDI %4, 1 + %7 = IMPLICIT_DEF + %6 = INSERT_SUBREG %7, killed %5, 1 + %8 = LI8 900 + STHX %3, %0, killed %8 :: (store 1 into %ir.arrayidx, !tbaa !3) + ; CHECK: STH %3, 900, %0 + ; CHECK-LATE: sth 4, 900(3) + %9 = ADDI %4, 2 + %11 = IMPLICIT_DEF + %10 = INSERT_SUBREG %11, killed %9, 1 + %12 = LI8 -900 + STHX %3, %0, killed %12 :: (store 1 into %ir.arrayidx3, !tbaa !3) + ; CHECK: STH %3, -900, %0 + ; CHECK-LATE: sth 4, -900(3) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSTWUX +# CHECK-ALL: name: testSTWUX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 5, class: gprc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } + - { id: 9, class: gprc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: g8rc, preferred-register: '' } + - { id: 13, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 14, class: g8rc_and_g8rc_nox0, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4, %x5 + + %2 = COPY %x5 + %1 = COPY %x4 + %0 = COPY %x3 + %3 = COPY %1.sub_32 + %4 = COPY %2.sub_32 + %5 = ADDI %4, 1 + %7 = IMPLICIT_DEF + %6 = INSERT_SUBREG %7, killed %5, 1 + %8 = LI8 111 + %13 = STWUX %3, %0, killed %8 :: (store 4 into %ir.arrayidx, !tbaa !8) + ; CHECK: STWU %3, 111, %0 + ; CHECK-LATE: stwu 4, 111(5) + %9 = ADDI %4, 2 + %11 = IMPLICIT_DEF + %10 = INSERT_SUBREG %11, killed %9, 1 + %12 = LI8 0 + %14 = STWUX %3, %0, killed %12 :: (store 4 into %ir.arrayidx3, !tbaa !8) + ; CHECK: STWU %3, 0, %0 + ; CHECK-LATE: stwu 4, 0(3) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSTWX +# CHECK-ALL: name: testSTWX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } + - { id: 4, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 5, class: gprc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: g8rc, preferred-register: '' } + - { id: 9, class: gprc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4, %x5 + + %2 = COPY %x5 + %1 = COPY %x4 + %0 = COPY %x3 + %3 = COPY %1.sub_32 + %4 = COPY %2.sub_32 + %5 = ADDI %4, 1 + %7 = IMPLICIT_DEF + %6 = INSERT_SUBREG %7, killed %5, 1 + %8 = LI8 2 + STWX %3, %0, killed %8 :: (store 4 into %ir.arrayidx, !tbaa !8) + ; CHECK: STW %3, 2, %0 + ; CHECK-LATE: stw 4, 2(3) + %9 = ADDI %4, 2 + %11 = IMPLICIT_DEF + %10 = INSERT_SUBREG %11, killed %9, 1 + %12 = LI8 99 + STWX %3, %0, killed %12 :: (store 4 into %ir.arrayidx3, !tbaa !8) + ; CHECK: STW %3, 99, %0 + ; CHECK-LATE: stw 4, 99(3) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSTDUX +# CHECK-ALL: name: testSTDUX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 13, class: g8rc_and_g8rc_nox0, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4, %x5 + + %2 = COPY %x5 + %1 = COPY %x4 + %0 = COPY %x3 + %3 = COPY %2.sub_32 + %4 = ADDI %3, 1 + %6 = IMPLICIT_DEF + %5 = INSERT_SUBREG %6, killed %4, 1 + %7 = LI8 444 + %12 = STDUX %1, %0, killed %7 :: (store 8 into %ir.arrayidx, !tbaa !10) + ; CHECK: STDU %1, 444, %0 + ; CHECK-LATE: stdu 4, 444(5) + %8 = ADDI %3, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 -8 + %13 = STDUX %1, %0, killed %11 :: (store 8 into %ir.arrayidx3, !tbaa !10) + ; CHECK: STDU %1, -8, %0 + ; CHECK-LATE: stdu 4, -8(3) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSTDX +# CHECK-ALL: name: testSTDX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4, %x5 + + %2 = COPY %x5 + %1 = COPY %x4 + %0 = LI8 1000 + %3 = COPY %2.sub_32 + %4 = ADDI %3, 1 + %6 = IMPLICIT_DEF + %5 = INSERT_SUBREG %6, killed %4, 1 + %7 = LI8 900 + STDX %1, %0, killed %7 :: (store 8 into %ir.arrayidx, !tbaa !10) + ; CHECK: STD %1, 1000, killed %7 + ; CHECK-LATE: 4, 1000(5) + %8 = ADDI %3, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 -900 + STDX %1, %0, killed %11 :: (store 8 into %ir.arrayidx3, !tbaa !10) + ; CHECK: STD %1, 1000, killed %11 + ; CHECK-LATE: 4, 1000(6) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSTFSX +# CHECK-ALL: name: testSTFSX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: f4rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%f1', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %f1, %x5 + + %2 = COPY %x5 + %1 = COPY %f1 + %0 = COPY %x3 + %3 = COPY %2.sub_32 + %4 = ADDI %3, 1 + %6 = IMPLICIT_DEF + %5 = INSERT_SUBREG %6, killed %4, 1 + %7 = LI8 400 + STFSX %1, %0, killed %7 :: (store 4 into %ir.arrayidx, !tbaa !14) + ; CHECK: STFS %1, 400, %0 + ; CHECK-LATE: stfs 1, 400(3) + %8 = ADDI %3, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 -401 + STFSX %1, %0, killed %11 :: (store 4 into %ir.arrayidx3, !tbaa !14) + ; CHECK: STFS %1, -401, %0 + ; CHECK-LATE: stfs 1, -401(3) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSTFSUX +# CHECK-ALL: name: testSTFSUX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: f4rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 13, class: g8rc_and_g8rc_nox0, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%f1', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %f1, %x5 + + %2 = COPY %x5 + %1 = COPY %f1 + %0 = COPY %x3 + %3 = COPY %2.sub_32 + %4 = ADDI %3, 1 + %6 = IMPLICIT_DEF + %5 = INSERT_SUBREG %6, killed %4, 1 + %7 = LI8 111 + %12 = STFSUX %1, %0, killed %7 :: (store 4 into %ir.arrayidx, !tbaa !14) + ; CHECK: STFSU %1, 111, %0 + ; CHECK-LATE: stfsu 1, 111(4) + %8 = ADDI %3, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 987 + %13 = STFSUX %1, %0, killed %11 :: (store 4 into %ir.arrayidx3, !tbaa !14) + ; CHECK: STFSU %1, 987, %0 + ; CHECK-LATE: stfsu 1, 987(3) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSTFDX +# CHECK-ALL: name: testSTFDX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: f8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%f1', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %f1, %x5 + + %2 = COPY %x5 + %1 = COPY %f1 + %0 = COPY %x3 + %3 = COPY %2.sub_32 + %4 = ADDI %3, 1 + %6 = IMPLICIT_DEF + %5 = INSERT_SUBREG %6, killed %4, 1 + %7 = LI8 876 + STFDX %1, %0, killed %7 :: (store 8 into %ir.arrayidx, !tbaa !12) + ; CHECK: STFD %1, 876, %0 + ; CHECK-LATE: stfd 1, 876(3) + %8 = ADDI %3, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 -873 + STFDX %1, %0, killed %11 :: (store 8 into %ir.arrayidx3, !tbaa !12) + ; CHECK: STFD %1, -873, %0 + ; CHECK-LATE: stfd 1, -873(3) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSTFDUX +# CHECK-ALL: name: testSTFDUX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: f8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: g8rc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } + - { id: 9, class: g8rc, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: g8rc, preferred-register: '' } + - { id: 12, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 13, class: g8rc_and_g8rc_nox0, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%f1', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %f1, %x5 + + %2 = COPY %x5 + %1 = COPY %f1 + %0 = COPY %x3 + %3 = COPY %2.sub_32 + %4 = ADDI %3, 1 + %6 = IMPLICIT_DEF + %5 = INSERT_SUBREG %6, killed %4, 1 + %7 = LI8 -9038 + %12 = STFDUX %1, %0, killed %7 :: (store 8 into %ir.arrayidx, !tbaa !12) + ; CHECK: STFDU %1, -9038, %0 + ; CHECK-LATE: stfdu 1, -9038(4) + %8 = ADDI %3, 2 + %10 = IMPLICIT_DEF + %9 = INSERT_SUBREG %10, killed %8, 1 + %11 = LI8 6477 + %13 = STFDUX %1, %0, killed %11 :: (store 8 into %ir.arrayidx3, !tbaa !12) + ; CHECK: STFDU %1, 6477, %0 + ; CHECK-LATE: stfdu 1, 6477(3) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSTXSSPX +# CHECK-ALL: name: testSTXSSPX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: vssrc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%f1', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %f1, %x5 + + %2 = COPY %x5 + %1 = COPY %f1 + %0 = COPY %x3 + %3 = LI8 444 + STXSSPX %1, %0, killed %3 :: (store 4 into %ir.arrayidx, !tbaa !14) + ; CHECK: STXSSP %1, 444, %0 + ; CHECK-LATE: stxssp 1, 444(3) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSTXSDX +# CHECK-ALL: name: testSTXSDX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: vsfrc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%f1', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %f1, %x5 + + %2 = COPY %x5 + %1 = COPY %f1 + %0 = COPY %x3 + %3 = LI8 4 + STXSDX %1, %0, killed %3, implicit %rm :: (store 8 into %ir.arrayidx, !tbaa !12) + ; CHECK: STXSD %1, 4, %0 + ; CHECK-LATE: stxsd 1, 4(3) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSTXVX +# CHECK-ALL: name: testSTXVX +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 1, class: vrrc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%v2', virtual-reg: '%1' } + - { reg: '%x7', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %v2, %x7 + + %2 = COPY %x7 + %1 = COPY %v2 + %0 = LI8 16 + %3 = RLDICR %2, 4, 59 + STXVX %1, %0, killed %3 :: (store 16 into %ir.arrayidx, !tbaa !3) + ; CHECK: STXV %1, 16, killed %3 + ; CHECK-LATE: stxv 34, 16(4) + BLR8 implicit %lr8, implicit %rm + +... +--- +name: testSUBFC +# CHECK-ALL: name: testSUBFC +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gprc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } + - { id: 4, class: gprc, preferred-register: '' } + - { id: 5, class: gprc, preferred-register: '' } + - { id: 6, class: gprc, preferred-register: '' } + - { id: 7, class: gprc, preferred-register: '' } + - { id: 8, class: gprc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } + - { reg: '%x6', virtual-reg: '%3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4, %x5, %x6 + + %3 = COPY %x6 + %2 = COPY %x5 + %1 = COPY %x4 + %6 = COPY %3.sub_32 + %7 = COPY %2.sub_32 + %8 = COPY %1.sub_32 + %0 = LI 55 + %4 = SUBFC %7, %0, implicit-def %carry + ; CHECK: SUBFIC %7, 55 + ; CHECK-LATE: subfic 3, 5, 55 + %5 = SUBFE %6, %8, implicit-def dead %carry, implicit %carry + %x3 = EXTSW_32_64 %4 + %x4 = EXTSW_32_64 %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3, implicit %x4 + +... +--- +name: testSUBFC8 +# CHECK-ALL: name: testSUBFC8 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: g8rc, preferred-register: '' } + - { id: 4, class: g8rc, preferred-register: '' } + - { id: 5, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } + - { reg: '%x5', virtual-reg: '%2' } + - { reg: '%x6', virtual-reg: '%3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4, %x5, %x6 + + %3 = COPY %x6 + %2 = COPY %x5 + %1 = COPY %x4 + %0 = LI8 7635 + %4 = SUBFC8 %2, %0, implicit-def %carry + ; CHECK: SUBFIC8 %2, 7635 + ; CHECK-LATE: subfic 3, 5, 7635 + %5 = SUBFE8 %3, %1, implicit-def dead %carry, implicit %carry + %x3 = COPY %4 + %x4 = COPY %5 + BLR8 implicit %lr8, implicit %rm, implicit %x3, implicit %x4 + +... +--- +name: testXOR +# CHECK-ALL: name: testXOR +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: gprc, preferred-register: '' } + - { id: 2, class: gprc, preferred-register: '' } + - { id: 3, class: gprc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = LI 10101 + %0 = COPY %x3 + %3 = COPY %0.sub_32 + %2 = XOR %1, %3 + ; CHECK: XORI %3, 10101 + ; CHECK-LATE: 3, 3, 10101 + %x3 = EXTSW_32_64 %2 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testXOR8 +# CHECK-ALL: name: testXOR8 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } + - { reg: '%x4', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3, %x4 + + %1 = COPY %x4 + %0 = LI8 5535 + %2 = XOR8 %1, %0 + ; CHECK: XORI8 %1, 5535 + ; CHECK-LATE: xori 3, 4, 5535 + %x3 = COPY %2 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testXORI +# CHECK-ALL: name: testXORI +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gprc, preferred-register: '' } + - { id: 1, class: gprc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3 + + %0 = LI 871 + %1 = XORI %0, 17 + ; CHECK: LI 886 + ; CHECK-LATE: li 3, 886 + %x3 = EXTSW_32_64 %1 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... +--- +name: testXOR8I +# CHECK-ALL: name: testXOR8I +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: g8rc, preferred-register: '' } + - { id: 1, class: g8rc, preferred-register: '' } +liveins: + - { reg: '%x3', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %x3 + + %0 = LI8 453 + %1 = XORI8 %0, 17 + ; CHECK: LI8 468 + ; CHECK-LATE: li 3, 468 + %x3 = COPY %1 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + +... diff --git a/test/CodeGen/PowerPC/cr_spilling.ll b/test/CodeGen/PowerPC/cr_spilling.ll index 8ac4e7271ac66..12ac6dc39bd14 100644 --- a/test/CodeGen/PowerPC/cr_spilling.ll +++ b/test/CodeGen/PowerPC/cr_spilling.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 -regalloc=fast -O0 -relocation-model=pic -o - +; RUN: llc < %s -mtriple=ppc32-- -regalloc=fast -O0 -relocation-model=pic -o - ; PR1638 @.str242 = external constant [3 x i8] ; <[3 x i8]*> [#uses=1] diff --git a/test/CodeGen/PowerPC/crbits.ll b/test/CodeGen/PowerPC/crbits.ll index 4ae91d1163a4a..18d149558635b 100644 --- a/test/CodeGen/PowerPC/crbits.ll +++ b/test/CodeGen/PowerPC/crbits.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/ctr-minmaxnum.ll b/test/CodeGen/PowerPC/ctr-minmaxnum.ll index 2b0a7cceb68d3..e38f851620b73 100644 --- a/test/CodeGen/PowerPC/ctr-minmaxnum.ll +++ b/test/CodeGen/PowerPC/ctr-minmaxnum.ll @@ -1,6 +1,5 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=a2q < %s | FileCheck %s --check-prefix=QPX -target triple = "powerpc64-unknown-linux-gnu" +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -mcpu=a2q < %s | FileCheck %s --check-prefix=QPX declare float @fabsf(float) @@ -38,6 +37,9 @@ loop_exit: ; CHECK-LABEL: test1: ; CHECK-NOT: mtctr ; CHECK: bl fminf +; CHECK-NOT: bl fminf +; CHECK-NOT: mtctr +; CHECK: blr define void @test1v(<4 x float> %f, <4 x float>* %fp) { entry: @@ -48,7 +50,7 @@ loop_body: %0 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %f, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>) store <4 x float> %0, <4 x float>* %fp, align 16 %1 = add i64 %invar_address.dim.0.01, 1 - %2 = icmp eq i64 %1, 2 + %2 = icmp eq i64 %1, 4 br i1 %2, label %loop_exit, label %loop_body loop_exit: @@ -56,8 +58,15 @@ loop_exit: } ; CHECK-LABEL: test1v: +; CHECK: bl fminf +; CHECK-NOT: mtctr +; CHECK: bl fminf ; CHECK-NOT: mtctr ; CHECK: bl fminf +; CHECK-NOT: mtctr +; CHECK: bl fminf +; CHECK-NOT: bl fminf +; CHECK: blr ; QPX-LABEL: test1v: ; QPX: mtctr @@ -83,6 +92,9 @@ loop_exit: ; CHECK-LABEL: test1a: ; CHECK-NOT: mtctr ; CHECK: bl fminf +; CHECK-NOT: bl fminf +; CHECK-NOT: mtctr +; CHECK: blr define void @test2(float %f, float* %fp) { entry: @@ -103,6 +115,9 @@ loop_exit: ; CHECK-LABEL: test2: ; CHECK-NOT: mtctr ; CHECK: bl fmaxf +; CHECK-NOT: bl fmaxf +; CHECK-NOT: mtctr +; CHECK: blr define void @test2v(<4 x double> %f, <4 x double>* %fp) { entry: @@ -113,7 +128,7 @@ loop_body: %0 = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %f, <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>) store <4 x double> %0, <4 x double>* %fp, align 16 %1 = add i64 %invar_address.dim.0.01, 1 - %2 = icmp eq i64 %1, 2 + %2 = icmp eq i64 %1, 4 br i1 %2, label %loop_exit, label %loop_body loop_exit: @@ -121,8 +136,15 @@ loop_exit: } ; CHECK-LABEL: test2v: +; CHECK: bl fmax +; CHECK-NOT: mtctr +; CHECK: bl fmax +; CHECK-NOT: mtctr +; CHECK: bl fmax ; CHECK-NOT: mtctr ; CHECK: bl fmax +; CHECK-NOT: bl fmax +; CHECK: blr ; QPX-LABEL: test2v: ; QPX: mtctr @@ -148,6 +170,9 @@ loop_exit: ; CHECK-LABEL: test2a: ; CHECK-NOT: mtctr ; CHECK: bl fmaxf +; CHECK-NOT: bl fmaxf +; CHECK-NOT: mtctr +; CHECK: blr define void @test3(double %f, double* %fp) { entry: @@ -168,6 +193,9 @@ loop_exit: ; CHECK-LABEL: test3: ; CHECK-NOT: mtctr ; CHECK: bl fmin +; CHECK-NOT: bl fmin +; CHECK-NOT: mtctr +; CHECK: blr define void @test3a(double %f, double* %fp) { entry: @@ -188,6 +216,9 @@ loop_exit: ; CHECK-LABEL: test3a: ; CHECK-NOT: mtctr ; CHECK: bl fmin +; CHECK-NOT: bl fmin +; CHECK-NOT: mtctr +; CHECK: blr define void @test4(double %f, double* %fp) { entry: @@ -208,6 +239,9 @@ loop_exit: ; CHECK-LABEL: test4: ; CHECK-NOT: mtctr ; CHECK: bl fmax +; CHECK-NOT: bl fmax +; CHECK-NOT: mtctr +; CHECK: blr define void @test4a(double %f, double* %fp) { entry: @@ -228,4 +262,7 @@ loop_exit: ; CHECK-LABEL: test4a: ; CHECK-NOT: mtctr ; CHECK: bl fmax +; CHECK-NOT: bl fmax +; CHECK-NOT: mtctr +; CHECK: blr diff --git a/test/CodeGen/PowerPC/ctrloop-asm.ll b/test/CodeGen/PowerPC/ctrloop-asm.ll index 3c7abd2615295..390dd2be20856 100644 --- a/test/CodeGen/PowerPC/ctrloop-asm.ll +++ b/test/CodeGen/PowerPC/ctrloop-asm.ll @@ -1,6 +1,6 @@ +; RUN: llc -verify-machineinstrs < %s | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-freebsd10.0" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | FileCheck %s define void @test1(i32 %c) nounwind { entry: diff --git a/test/CodeGen/PowerPC/ctrloop-le.ll b/test/CodeGen/PowerPC/ctrloop-le.ll index 2586fcd7d59ed..9fad3cb150c1f 100644 --- a/test/CodeGen/PowerPC/ctrloop-le.ll +++ b/test/CodeGen/PowerPC/ctrloop-le.ll @@ -1,6 +1,6 @@ +; RUN: llc -verify-machineinstrs < %s | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | FileCheck %s ; XFAIL: * ; SE needs improvement diff --git a/test/CodeGen/PowerPC/ctrloop-lt.ll b/test/CodeGen/PowerPC/ctrloop-lt.ll index 5dddc85719a8a..b1ef8586050e7 100644 --- a/test/CodeGen/PowerPC/ctrloop-lt.ll +++ b/test/CodeGen/PowerPC/ctrloop-lt.ll @@ -1,6 +1,6 @@ +; RUN: llc -verify-machineinstrs < %s | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | FileCheck %s ; XFAIL: * ; SE needs improvement diff --git a/test/CodeGen/PowerPC/ctrloop-ne.ll b/test/CodeGen/PowerPC/ctrloop-ne.ll index afb6f100091ad..253b8d020adb8 100644 --- a/test/CodeGen/PowerPC/ctrloop-ne.ll +++ b/test/CodeGen/PowerPC/ctrloop-ne.ll @@ -1,6 +1,6 @@ +; RUN: llc -verify-machineinstrs < %s | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | FileCheck %s ; CHECK: test_pos1_ir_ne ; CHECK: bdnz diff --git a/test/CodeGen/PowerPC/ctrloop-reg.ll b/test/CodeGen/PowerPC/ctrloop-reg.ll index 8a2074f472fc5..477d2aacdf4c3 100644 --- a/test/CodeGen/PowerPC/ctrloop-reg.ll +++ b/test/CodeGen/PowerPC/ctrloop-reg.ll @@ -1,7 +1,7 @@ +; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; ModuleID = 'bugpoint-reduced-simplified.bc' target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | FileCheck %s %struct.ref_s.1.49.91.115.121.139.145.151.157.163.169.175.181.211 = type { %union.v.0.48.90.114.120.138.144.150.156.162.168.174.180.210, i16, i16 } %union.v.0.48.90.114.120.138.144.150.156.162.168.174.180.210 = type { i64 } diff --git a/test/CodeGen/PowerPC/ctrloop-s000.ll b/test/CodeGen/PowerPC/ctrloop-s000.ll index 17dbc0b3e8fb6..ea682c88ec01c 100644 --- a/test/CodeGen/PowerPC/ctrloop-s000.ll +++ b/test/CodeGen/PowerPC/ctrloop-s000.ll @@ -1,7 +1,7 @@ +; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; ModuleID = 'tsc_s000.c' target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | FileCheck %s @Y = common global [16000 x double] zeroinitializer, align 32 @X = common global [16000 x double] zeroinitializer, align 32 diff --git a/test/CodeGen/PowerPC/ctrloop-shortLoops.ll b/test/CodeGen/PowerPC/ctrloop-shortLoops.ll new file mode 100644 index 0000000000000..481ec54e79a4b --- /dev/null +++ b/test/CodeGen/PowerPC/ctrloop-shortLoops.ll @@ -0,0 +1,116 @@ +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -mcpu=pwr8 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -mcpu=a2q | FileCheck %s + +; Verify that we do NOT generate the mtctr instruction for loop trip counts < 4 +; The latency of the mtctr is only justified if there are more than 4 comparisons that are removed as a result. + +@a = common local_unnamed_addr global i32 0, align 4 +@arr = common local_unnamed_addr global [5 x i32] zeroinitializer, align 4 + +; Function Attrs: norecurse nounwind readonly +define signext i32 @testTripCount2(i32 signext %a) { + +; CHECK-LABEL: testTripCount2: +; CHECK-NOT: mtctr +; CHECK: blr + +entry: + br label %for.body + +for.cond.cleanup: ; preds = %for.body + ret i32 %add + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i64 [ 1, %entry ], [ %indvars.iv.next, %for.body ] + %Sum.05 = phi i32 [ 0, %entry ], [ %add, %for.body ] + %arrayidx = getelementptr inbounds [5 x i32], [5 x i32]* @arr, i64 0, i64 %indvars.iv + %0 = load i32, i32* %arrayidx, align 4 + %add = add nsw i32 %0, %Sum.05 + %indvars.iv.next = add nsw i64 %indvars.iv, -1 + %tobool = icmp eq i64 %indvars.iv, 0 + br i1 %tobool, label %for.cond.cleanup, label %for.body +} + +; Function Attrs: norecurse nounwind readonly +define signext i32 @testTripCount3(i32 signext %a) { + +; CHECK-LABEL: testTripCount3: +; CHECK-NOT: mtctr +; CHECK: blr + +entry: + br label %for.body + +for.cond.cleanup: ; preds = %for.body + ret i32 %add + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i64 [ 2, %entry ], [ %indvars.iv.next, %for.body ] + %Sum.05 = phi i32 [ 0, %entry ], [ %add, %for.body ] + %arrayidx = getelementptr inbounds [5 x i32], [5 x i32]* @arr, i64 0, i64 %indvars.iv + %0 = load i32, i32* %arrayidx, align 4 + %add = add nsw i32 %0, %Sum.05 + %indvars.iv.next = add nsw i64 %indvars.iv, -1 + %tobool = icmp eq i64 %indvars.iv, 0 + br i1 %tobool, label %for.cond.cleanup, label %for.body +} + +; Function Attrs: norecurse nounwind readonly + +define signext i32 @testTripCount4(i32 signext %a) { + +; CHECK-LABEL: testTripCount4: +; CHECK: mtctr +; CHECK: bdnz + +entry: + br label %for.body + +for.cond.cleanup: ; preds = %for.body + ret i32 %add + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i64 [ 3, %entry ], [ %indvars.iv.next, %for.body ] + %Sum.05 = phi i32 [ 0, %entry ], [ %add, %for.body ] + %arrayidx = getelementptr inbounds [5 x i32], [5 x i32]* @arr, i64 0, i64 %indvars.iv + %0 = load i32, i32* %arrayidx, align 4 + %add = add nsw i32 %0, %Sum.05 + %indvars.iv.next = add nsw i64 %indvars.iv, -1 + %tobool = icmp eq i64 %indvars.iv, 0 + br i1 %tobool, label %for.cond.cleanup, label %for.body +} + +; Function Attrs: norecurse nounwind +define signext i32 @testTripCount2NonSmallLoop() { + +; CHECK-LABEL: testTripCount2NonSmallLoop: +; CHECK: mtctr +; CHECK: blr + +entry: + %.pre = load i32, i32* @a, align 4 + br label %for.body + +for.body: ; preds = %entry, %if.end + %0 = phi i32 [ %.pre, %entry ], [ %1, %if.end ] + %dec4 = phi i32 [ 1, %entry ], [ %dec, %if.end ] + %b.03 = phi i8 [ 0, %entry ], [ %b.1, %if.end ] + %tobool1 = icmp eq i32 %0, 0 + br i1 %tobool1, label %if.end, label %if.then + +if.then: ; preds = %for.body + store i32 2, i32* @a, align 4 + br label %if.end + +if.end: ; preds = %for.body, %if.then + %1 = phi i32 [ 2, %if.then ], [ 0, %for.body ] + %b.1 = phi i8 [ 2, %if.then ], [ %b.03, %for.body ] + %dec = add nsw i32 %dec4, -1 + %tobool = icmp eq i32 %dec4, 0 + br i1 %tobool, label %for.end, label %for.body + +for.end: ; preds = %if.end + %conv = zext i8 %b.1 to i32 + ret i32 %conv +} + diff --git a/test/CodeGen/PowerPC/ctrloop-sums.ll b/test/CodeGen/PowerPC/ctrloop-sums.ll index 0f6fdcfad23b9..5e127307f66c9 100644 --- a/test/CodeGen/PowerPC/ctrloop-sums.ll +++ b/test/CodeGen/PowerPC/ctrloop-sums.ll @@ -1,7 +1,7 @@ +; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; ModuleID = 'SingleSource/Regression/C/sumarray2d.c' target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | FileCheck %s @.str = private unnamed_addr constant [23 x i8] c"Sum(Array[%d,%d] = %d\0A\00", align 1 diff --git a/test/CodeGen/PowerPC/ctrloop-udivti3.ll b/test/CodeGen/PowerPC/ctrloop-udivti3.ll index e3f6838d06703..54abd181f82cf 100644 --- a/test/CodeGen/PowerPC/ctrloop-udivti3.ll +++ b/test/CodeGen/PowerPC/ctrloop-udivti3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc64 | FileCheck %s +; RUN: llc < %s | FileCheck %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/ctrloops.ll b/test/CodeGen/PowerPC/ctrloops.ll index ac592207308ae..6e84ecfee0525 100644 --- a/test/CodeGen/PowerPC/ctrloops.ll +++ b/test/CodeGen/PowerPC/ctrloops.ll @@ -1,6 +1,6 @@ +; RUN: llc -verify-machineinstrs < %s -relocation-model=pic | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-freebsd10.0" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -relocation-model=pic | FileCheck %s @a = common global i32 0, align 4 diff --git a/test/CodeGen/PowerPC/cttz.ll b/test/CodeGen/PowerPC/cttz.ll index 1effc6fcd93ab..0cf910d6788d7 100644 --- a/test/CodeGen/PowerPC/cttz.ll +++ b/test/CodeGen/PowerPC/cttz.ll @@ -1,5 +1,5 @@ ; Make sure this testcase does not use ctpop -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | FileCheck %s declare i32 @llvm.cttz.i32(i32, i1) diff --git a/test/CodeGen/PowerPC/cxx_tlscc64.ll b/test/CodeGen/PowerPC/cxx_tlscc64.ll index 0f45652cd29e3..cfa243f200af7 100644 --- a/test/CodeGen/PowerPC/cxx_tlscc64.ll +++ b/test/CodeGen/PowerPC/cxx_tlscc64.ll @@ -40,4 +40,4 @@ define cxx_fast_tlscc i32* @_ZTW4sum2() #0 { ret i32* @sum1 } -attributes #0 = { nounwind "no-frame-pointer-elim"="true" }
\ No newline at end of file +attributes #0 = { nounwind "no-frame-pointer-elim"="true" } diff --git a/test/CodeGen/PowerPC/dbg.ll b/test/CodeGen/PowerPC/dbg.ll index 6089e27ac678d..9f387460d24be 100644 --- a/test/CodeGen/PowerPC/dbg.ll +++ b/test/CodeGen/PowerPC/dbg.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -break-anti-dependencies=all -march=ppc64 -mcpu=g5 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -break-anti-dependencies=all -mcpu=g5 | FileCheck %s ; CHECK-LABEL: main: target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" diff --git a/test/CodeGen/PowerPC/debuginfo-split-int.ll b/test/CodeGen/PowerPC/debuginfo-split-int.ll new file mode 100644 index 0000000000000..e6f0ee2020823 --- /dev/null +++ b/test/CodeGen/PowerPC/debuginfo-split-int.ll @@ -0,0 +1,66 @@ +; RUN: llc < %s -stop-before=expand-isel-pseudos -o - | FileCheck %s + +source_filename = "foo.c" +target datalayout = "E-m:e-p:32:32-i64:64-n32" +target triple = "ppc32" + +; Verify that, when handling split-up integers, the +; transferring of debug info takes the endianness +; into consideration. +; +; The fragment expression at offset 0 should correspond +; to the high part of the value on big-endian targets. + +; This basis of this ll file was created by running: +; clang --target=powerpc -O1 -S -g -emit-llvm foo.c +; +; with foo.c being the program: +; unsigned long long foo(void); +; void bar() { +; volatile unsigned long long result = foo(); +; } +; +; This file is a slight tweak of that output, with irrelevant +; lifetime intrinsics, metadata, and debug info being removed. + +; CHECK: [[DL:![0-9]+]] = !DILocalVariable(name: "result" +; +; High 32 bits in R3, low 32 bits in R4 +; CHECK: %0:gprc = COPY %r3 +; CHECK: DBG_VALUE debug-use %0, debug-use %noreg, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 0, 32) +; CHECK: %1:gprc = COPY %r4 +; CHECK: DBG_VALUE debug-use %1, debug-use %noreg, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 32, 32) +define void @bar() local_unnamed_addr #0 !dbg !6 { + %1 = alloca i64, align 8 + %2 = tail call i64 @foo() + tail call void @llvm.dbg.value(metadata i64 %2, metadata !10, metadata !DIExpression()), !dbg !13 + store volatile i64 %2, i64* %1, align 8 + ret void +} + +declare i64 @foo() local_unnamed_addr + +; Function Attrs: nounwind readnone speculatable +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone speculatable } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4} +!llvm.ident = !{!5} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 6.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: "foo.c", directory: "/") +!2 = !{} +!3 = !{i32 2, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{!"clang version 6.0.0"} +!6 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 2, type: !7, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: true, unit: !0, variables: !9) +!7 = !DISubroutineType(types: !8) +!8 = !{null} +!9 = !{!10} +!10 = !DILocalVariable(name: "result", scope: !6, file: !1, line: 3, type: !11) +!11 = !DIDerivedType(tag: DW_TAG_volatile_type, baseType: !12) +!12 = !DIBasicType(name: "long long unsigned int", size: 64, encoding: DW_ATE_unsigned) +!13 = !DILocation(line: 3, column: 31, scope: !6) diff --git a/test/CodeGen/PowerPC/debuginfo-stackarg.ll b/test/CodeGen/PowerPC/debuginfo-stackarg.ll new file mode 100644 index 0000000000000..1db55dc7e65dc --- /dev/null +++ b/test/CodeGen/PowerPC/debuginfo-stackarg.ll @@ -0,0 +1,87 @@ +; RUN: llc < %s -O1 -stop-after=livedebugvalues -o - | FileCheck %s + +; This ll-file was created by: +; clang --target=powerpc-apple-darwin9 -O1 -S -g -emit-llvm debuginfo-stackarg.c +; +; with debuginfo-stackarg.c being the program: +; long long foo(long long bar1, long long bar2, long long bar3, long long bar4, long long bar5) +; { +; return bar1 + bar2 + bar3 + bar4 + bar5; +; } + +; ModuleID = 'debuginfo-stackarg.c' +source_filename = "debuginfo-stackarg.c" +target datalayout = "E-m:o-p:32:32-f64:32:64-n32" +target triple = "powerpc-apple-macosx10.5.0" + +; Function Attrs: nounwind readnone ssp uwtable +define i64 @foo(i64 %bar1, i64 %bar2, i64 %bar3, i64 %bar4, i64 %bar5) local_unnamed_addr #0 !dbg !8 { +; Variable bar5 should be associated with a position on the stack (offset relative r1). +; Let's verify that we point out the start address (lowest address). +; +; First find the metadata id for bar5. +; CHECK: !17 = !DILocalVariable(name: "bar5", arg: 5 +; +; Now check that we got two entries on the fixed stack with "expected" offsets. +; CHECK-LABEL: fixedStack: +; CHECK: id: 0, type: default, offset: 60, size: 4 +; CHECK: id: 1, type: default, offset: 56, size: 4 +; CHECK-NOT: id: 2 +; CHECK-LABEL: stack: +; +; Finally check the resulting function body. +; We expect to find a DBG_VALUE refering to the metadata id for bar5, using the lowest +; of the two fixed stack offsets found earlier. +; CHECK-LABEL: body: +; CHECK: DBG_VALUE %r1, 0, !17, !DIExpression(DW_OP_plus_uconst, 56) +entry: + tail call void @llvm.dbg.value(metadata i64 %bar1, metadata !13, metadata !DIExpression()), !dbg !18 + tail call void @llvm.dbg.value(metadata i64 %bar2, metadata !14, metadata !DIExpression()), !dbg !19 + tail call void @llvm.dbg.value(metadata i64 %bar3, metadata !15, metadata !DIExpression()), !dbg !20 + tail call void @llvm.dbg.value(metadata i64 %bar4, metadata !16, metadata !DIExpression()), !dbg !21 + tail call void @llvm.dbg.value(metadata i64 %bar5, metadata !17, metadata !DIExpression()), !dbg !22 + %add = add nsw i64 %bar2, %bar1, !dbg !23 + %add1 = add nsw i64 %add, %bar3, !dbg !24 + %add2 = add nsw i64 %add1, %bar4, !dbg !25 + %add3 = add nsw i64 %add2, %bar5, !dbg !26 + ret i64 %add3, !dbg !27 +} + +; Function Attrs: nounwind readnone speculatable +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind readnone ssp uwtable } +attributes #1 = { nounwind readnone speculatable } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5, !6} +!llvm.ident = !{!7} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 6.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: "debuginfo-stackarg.c", directory: "/repo") +!2 = !{} +!3 = !{i32 2, !"Dwarf Version", i32 2} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 4} +!6 = !{i32 7, !"PIC Level", i32 2} +!7 = !{!"clang version 6.0.0"} +!8 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !9, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !12) +!9 = !DISubroutineType(types: !10) +!10 = !{!11, !11, !11, !11, !11, !11} +!11 = !DIBasicType(name: "long long int", size: 64, encoding: DW_ATE_signed) +!12 = !{!13, !14, !15, !16, !17} +!13 = !DILocalVariable(name: "bar1", arg: 1, scope: !8, file: !1, line: 1, type: !11) +!14 = !DILocalVariable(name: "bar2", arg: 2, scope: !8, file: !1, line: 1, type: !11) +!15 = !DILocalVariable(name: "bar3", arg: 3, scope: !8, file: !1, line: 1, type: !11) +!16 = !DILocalVariable(name: "bar4", arg: 4, scope: !8, file: !1, line: 1, type: !11) +!17 = !DILocalVariable(name: "bar5", arg: 5, scope: !8, file: !1, line: 1, type: !11) +!18 = !DILocation(line: 1, column: 25, scope: !8) +!19 = !DILocation(line: 1, column: 41, scope: !8) +!20 = !DILocation(line: 1, column: 57, scope: !8) +!21 = !DILocation(line: 1, column: 73, scope: !8) +!22 = !DILocation(line: 1, column: 89, scope: !8) +!23 = !DILocation(line: 3, column: 15, scope: !8) +!24 = !DILocation(line: 3, column: 22, scope: !8) +!25 = !DILocation(line: 3, column: 29, scope: !8) +!26 = !DILocation(line: 3, column: 36, scope: !8) +!27 = !DILocation(line: 3, column: 3, scope: !8) diff --git a/test/CodeGen/PowerPC/delete-node.ll b/test/CodeGen/PowerPC/delete-node.ll index 631ea82a3fabd..ce8a6e765e3be 100644 --- a/test/CodeGen/PowerPC/delete-node.ll +++ b/test/CodeGen/PowerPC/delete-node.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- ; The DAGCombiner leaves behind a dead node in this testcase. Currently ; ISel is ignoring dead nodes, though it would be preferable for diff --git a/test/CodeGen/PowerPC/direct-move-profit.ll b/test/CodeGen/PowerPC/direct-move-profit.ll index 423f0ff0e37ad..7205d11a10512 100644 --- a/test/CodeGen/PowerPC/direct-move-profit.ll +++ b/test/CodeGen/PowerPC/direct-move-profit.ll @@ -17,7 +17,7 @@ entry: ; CHECK-NOT: mtvsrwa ; CHECK-NOT: mtfprwa -; CHECK: lxsiwax [[REG:[0-9]+]], {{.*}} +; CHECK: lfiwax [[REG:[0-9]+]], {{.*}} ; CHECK-NOT: mtvsrwa ; CHECK-NOT: mtfprwa ; CHECK: xscvsxdsp {{.*}}, [[REG]] @@ -40,7 +40,7 @@ entry: ; CHECK-NOT: mtvsrwa ; CHECK-NOT: mtfprwa -; CHECK: lxsiwax [[REG:[0-9]+]], {{.*}} +; CHECK: lfiwax [[REG:[0-9]+]], {{.*}} ; CHECK-NOT: mtvsrwa ; CHECK-NOT: mtfprwa ; CHECK: xscvsxdsp {{.*}}, [[REG]] diff --git a/test/CodeGen/PowerPC/div-2.ll b/test/CodeGen/PowerPC/div-2.ll index ca11aed8d617e..81f8d448091e0 100644 --- a/test/CodeGen/PowerPC/div-2.ll +++ b/test/CodeGen/PowerPC/div-2.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep srawi -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep blr +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep srawi +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep blr define i32 @test1(i32 %X) { %Y = and i32 %X, 15 ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/duplicate-returns-for-tailcall.ll b/test/CodeGen/PowerPC/duplicate-returns-for-tailcall.ll new file mode 100644 index 0000000000000..520efd8106f47 --- /dev/null +++ b/test/CodeGen/PowerPC/duplicate-returns-for-tailcall.ll @@ -0,0 +1,63 @@ +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -stop-after codegenprepare -mtriple=powerpc64le-unknown-gnu-linux < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -stop-after codegenprepare -mtriple=powerpc64-unknown-gnu-linux < %s | FileCheck %s + +; Function Attrs: noinline norecurse nounwind readnone +define hidden signext i32 @call1(i32 signext %a, i32 signext %b, i32 signext %c) local_unnamed_addr #0 { +entry: + %add = add nsw i32 %b, %a + %add1 = add nsw i32 %add, %c + ret i32 %add1 +} + +; Function Attrs: nounwind +define signext i32 @test(i32 signext %a, i32 signext %b, i32 signext %c) local_unnamed_addr #1 { +entry: + %cmp = icmp eq i32 %a, %b + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = tail call signext i32 @call1(i32 signext %a, i32 signext %b, i32 signext %c) + br label %return +; The return should get duplciated here to enable a tail-call opportunity. +; CHECK-LABEL: if.then: +; CHECK-NEXT: %[[T1:[a-zA-Z0-9]+]] = tail call signext i32 @call1 +; CHECK-NEXT: ret i32 %[[T1]] + +if.end: ; preds = %entry + %cmp1 = icmp slt i32 %a, %b + br i1 %cmp1, label %if.then2, label %if.end4 + +if.then2: ; preds = %if.end + %call3 = tail call signext i32 @call2(i32 signext %a, i32 signext %b, i32 signext %c) #3 + br label %return +; No duplication here since we cannot tail-call an external function anyway. +; CHECK-LABEL: if.then2: +; CHECK-NEXT: tail call signext i32 @call2 +; CHECK-NEXT: br + +if.end4: ; preds = %if.end + %cmp5 = icmp sgt i32 %b, %c + br i1 %cmp5, label %if.then6, label %return + +if.then6: ; preds = %if.end4 + %call7 = tail call fastcc signext i32 @call3(i32 signext %a, i32 signext %b, i32 signext %c) + br label %return +; No duplication here because the calling convention mismatch means we won't tail-call +; CHECK_LABEL: if.then13: +; CHECK: tail call fastcc signext i32 @call3 +; CHECK-NEXT: br + +return: ; preds = %if.end4, %if.then6, %if.then2, %if.then + %retval.0 = phi i32 [ %call, %if.then ], [ %call3, %if.then2 ], [ %call7, %if.then6 ], [ %c, %if.end4 ] + ret i32 %retval.0 +} + +declare signext i32 @call2(i32 signext, i32 signext, i32 signext) local_unnamed_addr #2 + +; Function Attrs: noinline norecurse nounwind readnone +define internal fastcc signext i32 @call3(i32 signext %a, i32 signext %b, i32 signext %c) unnamed_addr #0 { +entry: + %mul = mul nsw i32 %b, %a + %mul1 = mul nsw i32 %mul, %c + ret i32 %mul1 +} diff --git a/test/CodeGen/PowerPC/empty-functions.ll b/test/CodeGen/PowerPC/empty-functions.ll index b8394e14318fb..160345c97d919 100644 --- a/test/CodeGen/PowerPC/empty-functions.ll +++ b/test/CodeGen/PowerPC/empty-functions.ll @@ -31,9 +31,7 @@ entry: ; LINUX-FP-NEXT: {{^}}# ; LINUX-FP-NEXT: stwu 1, -16(1) ; LINUX-FP-NEXT: stw 31, 12(1) -; LINUX-FP-NEXT: {{^}}.L{{.*}}:{{$}} ; LINUX-FP-NEXT: .cfi_def_cfa_offset 16 -; LINUX-FP-NEXT: {{^}}.L{{.*}}:{{$}} ; LINUX-FP-NEXT: .cfi_offset r31, -4 ; LINUX-FP-NEXT: mr 31, 1 ; LINUX-FP-NEXT: {{^}}.L[[END:.*]]:{{$}} diff --git a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll index 2fc8624a09e9a..a82424a7ea569 100644 --- a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll +++ b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll @@ -1,12 +1,12 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: grep eqv | count 3 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | \ ; RUN: grep andc | count 3 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: grep orc | count 2 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | \ ; RUN: grep nor | count 3 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: grep nand | count 1 define i32 @EQV1(i32 %X, i32 %Y) nounwind { diff --git a/test/CodeGen/PowerPC/expand-contiguous-isel.ll b/test/CodeGen/PowerPC/expand-contiguous-isel.ll index 5fe69ebcf58ee..86caedcc09f0d 100644 --- a/test/CodeGen/PowerPC/expand-contiguous-isel.ll +++ b/test/CodeGen/PowerPC/expand-contiguous-isel.ll @@ -1,55 +1,66 @@ target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" ; This file mainly tests that one of the ISEL instruction in the group uses the same register for operand RT, RA, RB +; This redudant ISEL is introduced during simple register coalescing stage. + +; Simple register coalescing first create the foldable ISEL instruction as we have seen in expand-foldable-isel.ll: +; %vreg85<def> = ISEL8 %vreg83, %vreg83, %vreg33:sub_eq + +; Later the register coalescer figures out it could further coalesce %vreg85 with %vreg83: +; merge %vreg85:1@2288r into %vreg83:5@400B --> @400B +; erased: 2288r %vreg85<def> = COPY %vreg83 + +; After that we have: +; updated: 1504B %vreg83<def> = ISEL8 %vreg83, %vreg83, %vreg33:sub_eq + ; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=true < %s | FileCheck %s --check-prefix=CHECK-GEN-ISEL-TRUE ; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel -; Function Attrs: norecurse nounwind readnone + @.str = private unnamed_addr constant [3 x i8] c"]]\00", align 1 @.str.1 = private unnamed_addr constant [35 x i8] c"Index < Length && \22Invalid index!\22\00", align 1 @.str.2 = private unnamed_addr constant [50 x i8] c"/home/jtony/src/llvm/include/llvm/ADT/StringRef.h\00", align 1 @__PRETTY_FUNCTION__._ZNK4llvm9StringRefixEm = private unnamed_addr constant [47 x i8] c"char llvm::StringRef::operator[](size_t) const\00", align 1 @.str.3 = private unnamed_addr constant [95 x i8] c"(data || length == 0) && \22StringRef cannot be built from a NULL argument with non-null length\22\00", align 1 @__PRETTY_FUNCTION__._ZN4llvm9StringRefC2EPKcm = private unnamed_addr constant [49 x i8] c"llvm::StringRef::StringRef(const char *, size_t)\00", align 1 -; Function Attrs: nounwind -define i64 @_Z3fn1N4llvm9StringRefE([2 x i64] %Str.coerce) local_unnamed_addr #0 { +define i64 @_Z3fn1N4llvm9StringRefE([2 x i64] %Str.coerce) { entry: %Str.coerce.fca.0.extract = extractvalue [2 x i64] %Str.coerce, 0 %Str.coerce.fca.1.extract = extractvalue [2 x i64] %Str.coerce, 1 br label %while.cond.outer -while.cond.outer: ; preds = %_ZNK4llvm9StringRef6substrEmm.exit, %entry +while.cond.outer: %Str.sroa.0.0.ph = phi i64 [ %8, %_ZNK4llvm9StringRef6substrEmm.exit ], [ %Str.coerce.fca.0.extract, %entry ] %.sink.ph = phi i64 [ %sub.i, %_ZNK4llvm9StringRef6substrEmm.exit ], [ %Str.coerce.fca.1.extract, %entry ] %BracketDepth.0.ph = phi i64 [ %BracketDepth.1, %_ZNK4llvm9StringRef6substrEmm.exit ], [ undef, %entry ] %cmp65 = icmp eq i64 %BracketDepth.0.ph, 0 br i1 %cmp65, label %while.cond.us.preheader, label %while.cond.preheader -while.cond.us.preheader: ; preds = %while.cond.outer +while.cond.us.preheader: br label %while.cond.us -while.cond.preheader: ; preds = %while.cond.outer +while.cond.preheader: %cmp.i34129 = icmp eq i64 %.sink.ph, 0 br i1 %cmp.i34129, label %cond.false.i.loopexit135, label %_ZNK4llvm9StringRefixEm.exit.preheader -_ZNK4llvm9StringRefixEm.exit.preheader: ; preds = %while.cond.preheader +_ZNK4llvm9StringRefixEm.exit.preheader: br label %_ZNK4llvm9StringRefixEm.exit -while.cond.us: ; preds = %while.cond.us.preheader, %_ZNK4llvm9StringRef6substrEmm.exit50.us +while.cond.us: %Str.sroa.0.0.us = phi i64 [ %3, %_ZNK4llvm9StringRef6substrEmm.exit50.us ], [ %Str.sroa.0.0.ph, %while.cond.us.preheader ] %.sink.us = phi i64 [ %sub.i41.us, %_ZNK4llvm9StringRef6substrEmm.exit50.us ], [ %.sink.ph, %while.cond.us.preheader ] %cmp.i30.us = icmp ult i64 %.sink.us, 2 br i1 %cmp.i30.us, label %if.end.us, label %if.end.i.i.us -if.end.i.i.us: ; preds = %while.cond.us +if.end.i.i.us: %0 = inttoptr i64 %Str.sroa.0.0.us to i8* - %call.i.i.us = tail call signext i32 @memcmp(i8* %0, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i64 0, i64 0), i64 2) #3 + %call.i.i.us = tail call signext i32 @memcmp(i8* %0, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i64 0, i64 0), i64 2) %phitmp.i.us = icmp eq i32 %call.i.i.us, 0 br i1 %phitmp.i.us, label %if.then, label %_ZNK4llvm9StringRefixEm.exit.us -if.end.us: ; preds = %while.cond.us +if.end.us: %cmp.i34.us = icmp eq i64 %.sink.us, 0 br i1 %cmp.i34.us, label %cond.false.i.loopexit, label %_ZNK4llvm9StringRefixEm.exit.us -_ZNK4llvm9StringRefixEm.exit.us: ; preds = %if.end.i.i.us, %if.end.us +_ZNK4llvm9StringRefixEm.exit.us: %1 = inttoptr i64 %Str.sroa.0.0.us to i8* - %2 = load i8, i8* %1, align 1, !tbaa !2 + %2 = load i8, i8* %1, align 1 switch i8 %2, label %_ZNK4llvm9StringRef6substrEmm.exit.loopexit [ i8 92, label %if.then4.us i8 93, label %if.then9 ] -if.then4.us: ; preds = %_ZNK4llvm9StringRefixEm.exit.us +if.then4.us: %.sroa.speculated12.i38.us = select i1 %cmp.i30.us, i64 %.sink.us, i64 2 %add.ptr.i40.us = getelementptr inbounds i8, i8* %1, i64 %.sroa.speculated12.i38.us %sub.i41.us = sub i64 %.sink.us, %.sroa.speculated12.i38.us @@ -57,30 +68,30 @@ if.then4.us: ; preds = %_ZNK4llvm9StringRef %cmp.i4.i45.us = icmp eq i64 %sub.i41.us, 0 %or.cond.i.i46.us = or i1 %tobool.i.i44.us, %cmp.i4.i45.us br i1 %or.cond.i.i46.us, label %_ZNK4llvm9StringRef6substrEmm.exit50.us, label %cond.false.i.i47.loopexit -_ZNK4llvm9StringRef6substrEmm.exit50.us: ; preds = %if.then4.us +_ZNK4llvm9StringRef6substrEmm.exit50.us: %3 = ptrtoint i8* %add.ptr.i40.us to i64 br label %while.cond.us -if.then: ; preds = %if.end.i.i.us +if.then: ret i64 undef -cond.false.i.loopexit: ; preds = %if.end.us +cond.false.i.loopexit: br label %cond.false.i -cond.false.i.loopexit134: ; preds = %_ZNK4llvm9StringRef6substrEmm.exit50 +cond.false.i.loopexit134: br label %cond.false.i -cond.false.i.loopexit135: ; preds = %while.cond.preheader +cond.false.i.loopexit135: br label %cond.false.i -cond.false.i: ; preds = %cond.false.i.loopexit135, %cond.false.i.loopexit134, %cond.false.i.loopexit - tail call void @__assert_fail(i8* getelementptr inbounds ([35 x i8], [35 x i8]* @.str.1, i64 0, i64 0), i8* getelementptr inbounds ([50 x i8], [50 x i8]* @.str.2, i64 0, i64 0), i32 zeroext 225, i8* getelementptr inbounds ([47 x i8], [47 x i8]* @__PRETTY_FUNCTION__._ZNK4llvm9StringRefixEm, i64 0, i64 0)) #4 +cond.false.i: + tail call void @__assert_fail(i8* getelementptr inbounds ([35 x i8], [35 x i8]* @.str.1, i64 0, i64 0), i8* getelementptr inbounds ([50 x i8], [50 x i8]* @.str.2, i64 0, i64 0), i32 zeroext 225, i8* getelementptr inbounds ([47 x i8], [47 x i8]* @__PRETTY_FUNCTION__._ZNK4llvm9StringRefixEm, i64 0, i64 0)) unreachable -_ZNK4llvm9StringRefixEm.exit: ; preds = %_ZNK4llvm9StringRefixEm.exit.preheader, %_ZNK4llvm9StringRef6substrEmm.exit50 +_ZNK4llvm9StringRefixEm.exit: %.sink131 = phi i64 [ %sub.i41, %_ZNK4llvm9StringRef6substrEmm.exit50 ], [ %.sink.ph, %_ZNK4llvm9StringRefixEm.exit.preheader ] %Str.sroa.0.0130 = phi i64 [ %6, %_ZNK4llvm9StringRef6substrEmm.exit50 ], [ %Str.sroa.0.0.ph, %_ZNK4llvm9StringRefixEm.exit.preheader ] %4 = inttoptr i64 %Str.sroa.0.0130 to i8* - %5 = load i8, i8* %4, align 1, !tbaa !2 + %5 = load i8, i8* %4, align 1 switch i8 %5, label %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132 [ i8 92, label %if.then4 i8 93, label %if.end10 ] -if.then4: ; preds = %_ZNK4llvm9StringRefixEm.exit +if.then4: %cmp.i.i37 = icmp ult i64 %.sink131, 2 %.sroa.speculated12.i38 = select i1 %cmp.i.i37, i64 %.sink131, i64 2 %add.ptr.i40 = getelementptr inbounds i8, i8* %4, i64 %.sroa.speculated12.i38 @@ -89,28 +100,28 @@ if.then4: ; preds = %_ZNK4llvm9StringRef %cmp.i4.i45 = icmp eq i64 %sub.i41, 0 %or.cond.i.i46 = or i1 %tobool.i.i44, %cmp.i4.i45 br i1 %or.cond.i.i46, label %_ZNK4llvm9StringRef6substrEmm.exit50, label %cond.false.i.i47.loopexit133 -cond.false.i.i47.loopexit: ; preds = %if.then4.us +cond.false.i.i47.loopexit: br label %cond.false.i.i47 -cond.false.i.i47.loopexit133: ; preds = %if.then4 +cond.false.i.i47.loopexit133: br label %cond.false.i.i47 -cond.false.i.i47: ; preds = %cond.false.i.i47.loopexit133, %cond.false.i.i47.loopexit - tail call void @__assert_fail(i8* getelementptr inbounds ([95 x i8], [95 x i8]* @.str.3, i64 0, i64 0), i8* getelementptr inbounds ([50 x i8], [50 x i8]* @.str.2, i64 0, i64 0), i32 zeroext 90, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @__PRETTY_FUNCTION__._ZN4llvm9StringRefC2EPKcm, i64 0, i64 0)) #4 +cond.false.i.i47: + tail call void @__assert_fail(i8* getelementptr inbounds ([95 x i8], [95 x i8]* @.str.3, i64 0, i64 0), i8* getelementptr inbounds ([50 x i8], [50 x i8]* @.str.2, i64 0, i64 0), i32 zeroext 90, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @__PRETTY_FUNCTION__._ZN4llvm9StringRefC2EPKcm, i64 0, i64 0)) unreachable -_ZNK4llvm9StringRef6substrEmm.exit50: ; preds = %if.then4 +_ZNK4llvm9StringRef6substrEmm.exit50: %6 = ptrtoint i8* %add.ptr.i40 to i64 %cmp.i34 = icmp eq i64 %sub.i41, 0 br i1 %cmp.i34, label %cond.false.i.loopexit134, label %_ZNK4llvm9StringRefixEm.exit -if.then9: ; preds = %_ZNK4llvm9StringRefixEm.exit.us - tail call void @exit(i32 signext 1) #4 +if.then9: + tail call void @exit(i32 signext 1) unreachable -if.end10: ; preds = %_ZNK4llvm9StringRefixEm.exit +if.end10: %dec = add i64 %BracketDepth.0.ph, -1 br label %_ZNK4llvm9StringRef6substrEmm.exit -_ZNK4llvm9StringRef6substrEmm.exit.loopexit: ; preds = %_ZNK4llvm9StringRefixEm.exit.us +_ZNK4llvm9StringRef6substrEmm.exit.loopexit: br label %_ZNK4llvm9StringRef6substrEmm.exit -_ZNK4llvm9StringRef6substrEmm.exit.loopexit132: ; preds = %_ZNK4llvm9StringRefixEm.exit +_ZNK4llvm9StringRef6substrEmm.exit.loopexit132: br label %_ZNK4llvm9StringRef6substrEmm.exit -_ZNK4llvm9StringRef6substrEmm.exit: ; preds = %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit, %if.end10 +_ZNK4llvm9StringRef6substrEmm.exit: %.sink76 = phi i64 [ %.sink131, %if.end10 ], [ %.sink.us, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit ], [ %.sink131, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132 ] %7 = phi i8* [ %4, %if.end10 ], [ %1, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit ], [ %4, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132 ] %BracketDepth.1 = phi i64 [ %dec, %if.end10 ], [ 0, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit ], [ %BracketDepth.0.ph, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132 ] @@ -120,9 +131,10 @@ _ZNK4llvm9StringRef6substrEmm.exit: ; preds = %_ZNK4llvm9StringRef br label %while.cond.outer ; CHECK-LABEL: @_Z3fn1N4llvm9StringRefE -; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], [[SAME]], [[SAME]] +; Unecessary ISEL (all the registers are the same) is always removed +; CHECK-GEN-ISEL-TRUE-NOT: isel [[SAME:r[0-9]+]], [[SAME]], [[SAME]] ; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], {{r[0-9]+}}, [[SAME]] -; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]] +; CHECK: bc 12, eq, [[TRUE:.LBB[0-9]+]] ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-NEXT: [[TRUE]] ; CHECK-NEXT: addi {{r[0-9]+}}, {{r[0-9]+}}, 0 @@ -131,21 +143,6 @@ _ZNK4llvm9StringRef6substrEmm.exit: ; preds = %_ZNK4llvm9StringRef -; Function Attrs: noreturn nounwind -declare void @exit(i32 signext) local_unnamed_addr #1 -; Function Attrs: nounwind readonly -declare signext i32 @memcmp(i8* nocapture, i8* nocapture, i64) local_unnamed_addr #2 -; Function Attrs: noreturn nounwind -declare void @__assert_fail(i8*, i8*, i32 zeroext, i8*) local_unnamed_addr #1 -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { noreturn nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #3 = { nounwind readonly } -attributes #4 = { noreturn nounwind } -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} -!0 = !{i32 1, !"PIC Level", i32 2} -!1 = !{!"clang version 4.0.0 (trunk 286863) (llvm/trunk 286967)"} -!2 = !{!3, !3, i64 0} -!3 = !{!"omnipotent char", !4, i64 0} -!4 = !{!"Simple C++ TBAA"} +declare void @exit(i32 signext) +declare signext i32 @memcmp(i8* nocapture, i8* nocapture, i64) +declare void @__assert_fail(i8*, i8*, i32 zeroext, i8*) diff --git a/test/CodeGen/PowerPC/expand-foldable-isel.ll b/test/CodeGen/PowerPC/expand-foldable-isel.ll new file mode 100644 index 0000000000000..2e4993ea44039 --- /dev/null +++ b/test/CodeGen/PowerPC/expand-foldable-isel.ll @@ -0,0 +1,71 @@ +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" +; This file mainly tests the case that the two input registers of the ISEL instruction are the same register. +; The foldable ISEL in this test case is introduced at simple register coalescing stage. + +; Before that stage we have: +; %vreg18<def> = ISEL8 %vreg5, %vreg2, %vreg15<undef>; + +; At simple register coalescing stage, the register coalescer figures out it could remove the copy +; from %vreg2 to %vreg5, put the original value %X3 into %vreg5 directly +; erased: 336r %vreg5<def> = COPY %vreg2 +; updated: 288B %vreg5<def> = COPY %X3; + +; After that we have: +; updated: 416B %vreg18<def> = ISEL8 %vreg5, %vreg5, %vreg15<undef>; + +; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=true < %s | FileCheck %s --check-prefix=CHECK-GEN-ISEL-TRUE +; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel +%"struct.pov::ot_block_struct" = type { %"struct.pov::ot_block_struct"*, [3 x double], [3 x double], float, float, float, float, float, float, float, float, float, [3 x float], float, float, [3 x double], i16 } +%"struct.pov::ot_node_struct" = type { %"struct.pov::ot_id_struct", %"struct.pov::ot_block_struct"*, [8 x %"struct.pov::ot_node_struct"*] } +%"struct.pov::ot_id_struct" = type { i32, i32, i32, i32 } + +define void @_ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE(%"struct.pov::ot_block_struct"* %new_block) { +; CHECK-GEN-ISEL-TRUE-LABEL: _ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE: +; Note: the following line fold the original isel (isel r4, r3, r3) +; CHECK-GEN-ISEL-TRUE: mr r4, r3 +; CHECK-GEN-ISEL-TRUE: isel r29, r5, r6, 4*cr5+lt +; CHECK-GEN-ISEL-TRUE: blr +; +; CHECK-LABEL: _ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE: +; CHECK: mr r4, r3 +; CHECK: bc 12, 4*cr5+lt, .LBB0_3 +; CHECK: # %bb.2: +; CHECK: ori r29, r6, 0 +; CHECK: b .LBB0_4 +; CHECK: .LBB0_3: +; CHECK: addi r29, r5, 0 +; CHECK: .LBB0_4: +; CHECK: blr +entry: + br label %while.cond11 + +while.cond11: + %this_node.0250 = phi %"struct.pov::ot_node_struct"* [ undef, %entry ], [ %1, %cond.false21.i156 ], [ %1, %cond.true18.i153 ] + %temp_id.sroa.21.1 = phi i32 [ undef, %entry ], [ %shr2039.i152, %cond.true18.i153 ], [ %div24.i155, %cond.false21.i156 ] + %0 = load i32, i32* undef, align 4 + %cmp17 = icmp eq i32 0, %0 + br i1 %cmp17, label %lor.rhs, label %while.body21 + +lor.rhs: + %Values = getelementptr inbounds %"struct.pov::ot_node_struct", %"struct.pov::ot_node_struct"* %this_node.0250, i64 0, i32 1 + store %"struct.pov::ot_block_struct"* %new_block, %"struct.pov::ot_block_struct"** %Values, align 8 + ret void + +while.body21: + %call.i84 = tail call i8* @ZN3pov10pov_callocEmmPKciS1_pov() + store i8* %call.i84, i8** undef, align 8 + %1 = bitcast i8* %call.i84 to %"struct.pov::ot_node_struct"* + br i1 undef, label %cond.true18.i153, label %cond.false21.i156 + +cond.true18.i153: + %shr2039.i152 = lshr i32 %temp_id.sroa.21.1, 1 + br label %while.cond11 + +cond.false21.i156: + %add23.i154 = add nsw i32 %temp_id.sroa.21.1, 1 + %div24.i155 = sdiv i32 %add23.i154, 2 + br label %while.cond11 +} + +declare i8* @ZN3pov10pov_callocEmmPKciS1_pov() diff --git a/test/CodeGen/PowerPC/expand-isel-10.mir b/test/CodeGen/PowerPC/expand-isel-10.mir new file mode 100644 index 0000000000000..017b51252b7bd --- /dev/null +++ b/test/CodeGen/PowerPC/expand-isel-10.mir @@ -0,0 +1,54 @@ +# This file tests the scenario: ISEL RX, RX, RX, CR (X != 0), +# which is redudant and removed. +# RUN: llc -ppc-gen-isel=true -run-pass ppc-expand-isel -o - %s | FileCheck %s + +--- | + target datalayout = "E-m:e-i64:64-n32:64" + target triple = "powerpc64-unknown-linux-gnu" + define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) { + entry: + %cmp = icmp sgt i32 %i, 0 + %add = add nsw i32 %i, 1 + %cond = select i1 %cmp, i32 %add, i32 %j + ret i32 %cond + } + +... +--- +name: testExpandISEL +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +liveins: + - { reg: '%x3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %x3 + + %r5 = ADDI %r3, 1 + %cr0 = CMPWI %r3, 0 + %r3 = ISEL %r3, %r3, %cr0gt + %x3 = EXTSW_32_64 %r3 + ; CHECK: %r5 = ADDI %r3, 1 + ; CHECK: %cr0 = CMPWI %r3, 0 + ; CHECK-NOT: %r3 = ISEL %r3, %r3, %cr0gt + ; CHECK: %x3 = EXTSW_32_64 %r3 + +... diff --git a/test/CodeGen/PowerPC/expand-isel-9.mir b/test/CodeGen/PowerPC/expand-isel-9.mir new file mode 100644 index 0000000000000..5062ddba778ef --- /dev/null +++ b/test/CodeGen/PowerPC/expand-isel-9.mir @@ -0,0 +1,54 @@ +# This file tests the scenario: ISEL RX, RY, RY, CR (X != 0 && Y != 0) +# It is folded into a copy (%RX = OR %RY, %RY) +# RUN: llc -ppc-gen-isel=true -run-pass ppc-expand-isel -o - %s | FileCheck %s + +--- | + target datalayout = "E-m:e-i64:64-n32:64" + target triple = "powerpc64-unknown-linux-gnu" + define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) { + entry: + %cmp = icmp sgt i32 %i, 0 + %add = add nsw i32 %i, 1 + %cond = select i1 %cmp, i32 %add, i32 %j + ret i32 %cond + } + +... +--- +name: testExpandISEL +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +liveins: + - { reg: '%x3' } + - { reg: '%x4' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %x3, %x4 + + %r5 = ADDI %r3, 1 + %cr0 = CMPWI %r3, 0 + %r3 = ISEL %r4, %r4, %cr0gt + ; Test fold ISEL to a copy + ; CHECK: %r3 = OR %r4, %r4 + + %x3 = EXTSW_32_64 %r3 + +... diff --git a/test/CodeGen/PowerPC/expand-isel.ll b/test/CodeGen/PowerPC/expand-isel.ll index c8707bda8e84a..50db7e334baae 100644 --- a/test/CodeGen/PowerPC/expand-isel.ll +++ b/test/CodeGen/PowerPC/expand-isel.ll @@ -1,7 +1,7 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel -; Function Attrs: norecurse nounwind readnone +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel + define signext i32 @testExpandISELToIfElse(i32 signext %i, i32 signext %j) { entry: %cmp = icmp sgt i32 %i, 0 @@ -12,7 +12,7 @@ entry: ; CHECK-LABEL: @testExpandISELToIfElse ; CHECK: addi r5, r3, 1 ; CHECK-NEXT: cmpwi cr0, r3, 0 -; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]] +; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK: ori r3, r4, 0 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-NEXT: [[TRUE]] @@ -23,7 +23,6 @@ entry: } -; Function Attrs: norecurse nounwind readnone define signext i32 @testExpandISELToIf(i32 signext %i, i32 signext %j) { entry: %cmp = icmp sgt i32 %i, 0 @@ -32,14 +31,13 @@ entry: ; CHECK-LABEL: @testExpandISELToIf ; CHECK: cmpwi r3, 0 -; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]] +; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK-NEXT: blr ; CHECK-NEXT: [[TRUE]] ; CHECK-NEXT: addi r3, r4, 0 ; CHECK-NEXT: blr } -; Function Attrs: norecurse nounwind readnone define signext i32 @testExpandISELToElse(i32 signext %i, i32 signext %j) { entry: %cmp = icmp sgt i32 %i, 0 @@ -48,27 +46,12 @@ entry: ; CHECK-LABEL: @testExpandISELToElse ; CHECK: cmpwi r3, 0 -; CHECK-NEXT: bclr 12, 1, 0 +; CHECK-NEXT: bclr 12, gt, 0 ; CHECK: ori r3, r4, 0 ; CHECK-NEXT: blr } -; Function Attrs: norecurse nounwind readnone -define signext i32 @testReplaceISELWithCopy(i32 signext %i, i32 signext %j) { -entry: - %cmp = icmp sgt i32 %i, 0 - %cond = select i1 %cmp, i32 %j, i32 %j - ret i32 %cond - -; CHECK-LABEL: @testReplaceISELWithCopy - -; Fix me should really check: addi r3, r4, 0 -; but for some reason it's optimized to mr r3, r4 -; CHECK: mr r3, r4 -; CHECK-NEXT: blr -} -; Function Attrs: norecurse nounwind readnone define signext i32 @testExpandISELToNull(i32 signext %i, i32 signext %j) { entry: %cmp = icmp sgt i32 %i, 0 @@ -81,7 +64,6 @@ entry: ; CHECK: blr } -; Function Attrs: norecurse nounwind readnone define signext i32 @testExpandISELsTo2ORIs2ADDIs (i32 signext %a, i32 signext %b, i32 signext %d, i32 signext %f, i32 signext %g) { @@ -95,7 +77,7 @@ entry: ; CHECK-LABEL: @testExpandISELsTo2ORIs2ADDIs ; CHECK: cmpwi r7, 0 -; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]] +; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK: ori r3, r4, 0 ; CHECK-NEXT: ori r12, r6, 0 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] @@ -108,7 +90,6 @@ entry: ; CHECK-NEXT: blr } -; Function Attrs: norecurse nounwind readnone define signext i32 @testExpandISELsTo2ORIs1ADDI (i32 signext %a, i32 signext %b, i32 signext %d, i32 signext %f, i32 signext %g) { @@ -121,7 +102,7 @@ entry: ; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI ; CHECK: cmpwi cr0, r7, 0 -; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]] +; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK: ori r3, r4, 0 ; CHECK-NEXT: ori r12, r6, 0 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] @@ -133,7 +114,6 @@ entry: ; CHECK-NEXT: blr } -; Function Attrs: norecurse nounwind readnone define signext i32 @testExpandISELsTo1ORI1ADDI (i32 signext %a, i32 signext %b, i32 signext %d, i32 signext %f, i32 signext %g) { @@ -148,7 +128,7 @@ entry: ; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI ; CHECK: cmpwi cr0, r7, 0 -; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]] +; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK: ori r5, r6, 0 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-NEXT: [[TRUE]] @@ -160,7 +140,6 @@ entry: ; CHECK-NEXT: blr } -; Function Attrs: norecurse nounwind readnone define signext i32 @testExpandISELsTo0ORI2ADDIs (i32 signext %a, i32 signext %b, i32 signext %d, i32 signext %f, i32 signext %g) { @@ -176,7 +155,7 @@ entry: ; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs ; CHECK: cmpwi cr0, r7, 0 -; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]] +; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-NEXT: [[TRUE]] ; CHECK-NEXT: addi r4, r3, 0 @@ -212,11 +191,12 @@ cleanup: ret i32 %retval.0 ; CHECK-LABEL: @testComplexISEL -; CHECK-DAG: [[LI:r[0-9]+]], 1 -; CHECK-DAG: cmplwi [[LD:r[0-9]+]], 0 -; CHECK: beq cr0, [[EQ:.LBB[0-9_]+]] +; CHECK: cmplwi r3, 0 +; CHECK: li r3, 1 +; CHECK: beq cr0, [[TGT:.LBB[0-9_]+]] +; CHECK: clrldi r3, r3, 32 ; CHECK: blr -; CHECK: [[EQ]] +; CHECK: [[TGT]] ; CHECK: xor [[XOR:r[0-9]+]] ; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]] ; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63 diff --git a/test/CodeGen/PowerPC/extsh.ll b/test/CodeGen/PowerPC/extsh.ll index 0d8945cb1cd30..f4c83ec9d0cf3 100644 --- a/test/CodeGen/PowerPC/extsh.ll +++ b/test/CodeGen/PowerPC/extsh.ll @@ -1,5 +1,5 @@ ; This should turn into a single extsh -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep extsh | count 1 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep extsh | count 1 define i32 @test(i32 %X) { %tmp.81 = shl i32 %X, 16 ; <i32> [#uses=1] %tmp.82 = ashr i32 %tmp.81, 16 ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/fabs.ll b/test/CodeGen/PowerPC/fabs.ll index 6dedfa90a627b..369803af9794b 100644 --- a/test/CodeGen/PowerPC/fabs.ll +++ b/test/CodeGen/PowerPC/fabs.ll @@ -1,8 +1,8 @@ -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=powerpc-apple-darwin | FileCheck %s define double @fabs(double %f) { ; CHECK-LABEL: fabs: -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK-NEXT: fabs f1, f1 ; CHECK-NEXT: blr ; @@ -12,7 +12,7 @@ define double @fabs(double %f) { define float @bitcast_fabs(float %x) { ; CHECK-LABEL: bitcast_fabs: -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK-NEXT: stfs f1, -8(r1) ; CHECK-NEXT: nop ; CHECK-NEXT: nop diff --git a/test/CodeGen/PowerPC/fast-isel-call.ll b/test/CodeGen/PowerPC/fast-isel-call.ll index 4526db021a2e2..a080baedd8e43 100644 --- a/test/CodeGen/PowerPC/fast-isel-call.ll +++ b/test/CodeGen/PowerPC/fast-isel-call.ll @@ -2,7 +2,7 @@ ; registers and with -fast-isel-abort=1 turned on the test case will then fail. ; When fastisel better supports VSX fix up this test case. ; -; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 +; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-late-peephole=true | FileCheck %s --check-prefix=ELF64 define i32 @t1(i8 signext %a) nounwind { %1 = sext i8 %a to i32 @@ -29,17 +29,21 @@ define void @foo(i8 %a, i16 %b) nounwind { %1 = call i32 @t1(i8 signext %a) ; ELF64: extsb %2 = call i32 @t2(i8 zeroext %a) -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 %3 = call i32 @t3(i16 signext %b) ; ELF64: extsh %4 = call i32 @t4(i16 zeroext %b) -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ;; A few test to check materialization %5 = call i32 @t2(i8 zeroext 255) -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64: li 3, 255 +; ELF64-NOT: clrldi %6 = call i32 @t4(i16 zeroext 65535) -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: lis 3, 0 +; ELF64: ori 3, 3, 65535 +; ELF64: clrldi 3, 3, 48 +; ELF64: bl t4 ret void } @@ -66,12 +70,8 @@ entry: ; ELF64: li 6, 28 ; ELF64: li 7, 40 ; ELF64: li 8, 186 -; ELF64: rldicl 3, 3, 0, 56 -; ELF64: rldicl 4, 4, 0, 56 -; ELF64: rldicl 5, 5, 0, 56 -; ELF64: rldicl 6, 6, 0, 56 -; ELF64: rldicl 7, 7, 0, 56 -; ELF64: rldicl 8, 8, 0, 56 +; ELF64-NOT: clrldi +; ELF64: bl bar ret i32 0 } diff --git a/test/CodeGen/PowerPC/fast-isel-conversion.ll b/test/CodeGen/PowerPC/fast-isel-conversion.ll index a9324592aeab7..3dd53e7f81760 100644 --- a/test/CodeGen/PowerPC/fast-isel-conversion.ll +++ b/test/CodeGen/PowerPC/fast-isel-conversion.ll @@ -2,8 +2,8 @@ ; registers and with -fast-isel-abort=1 turned on the test case will then fail. ; When fastisel better supports VSX fix up this test case. ; -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s --check-prefix=ELF64LE +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970 ;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt @@ -13,17 +13,13 @@ define void @sitofp_single_i64(i64 %a, float %b) nounwind { entry: -; ELF64: sitofp_single_i64 -; ELF64LE: sitofp_single_i64 +; CHECK: sitofp_single_i64 ; PPC970: sitofp_single_i64 %b.addr = alloca float, align 4 %conv = sitofp i64 %a to float -; ELF64: std -; ELF64: lfd -; ELF64: fcfids -; ELF64LE: std -; ELF64LE: lfd -; ELF64LE: fcfids +; CHECK: std +; CHECK: lfd +; CHECK: fcfids ; PPC970: std ; PPC970: lfd ; PPC970: fcfid @@ -34,21 +30,14 @@ entry: define void @sitofp_single_i32(i32 %a, float %b) nounwind { entry: -; ELF64: sitofp_single_i32 -; ELF64LE: sitofp_single_i32 +; CHECK: sitofp_single_i32 ; PPC970: sitofp_single_i32 %b.addr = alloca float, align 4 %conv = sitofp i32 %a to float -; ELF64: std -; stack offset used to load the float: 65524 = -16 + 4 -; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524 -; ELF64: lfiwax -; ELF64: fcfids -; ELF64LE: std -; stack offset used to load the float: 65520 = -16 + 0 -; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520 -; ELF64LE: lfiwax -; ELF64LE: fcfids +; CHECK: std +; CHECK-NEXT: li +; CHECK-NEXT: lfiwax +; CHECK-NEXT: fcfids ; PPC970: std ; PPC970: lfd ; PPC970: fcfid @@ -59,19 +48,14 @@ entry: define void @sitofp_single_i16(i16 %a, float %b) nounwind { entry: -; ELF64: sitofp_single_i16 -; ELF64LE: sitofp_single_i16 +; CHECK: sitofp_single_i16 ; PPC970: sitofp_single_i16 %b.addr = alloca float, align 4 %conv = sitofp i16 %a to float -; ELF64: extsh -; ELF64: std -; ELF64: lfd -; ELF64: fcfids -; ELF64LE: extsh -; ELF64LE: std -; ELF64LE: lfd -; ELF64LE: fcfids +; CHECK: extsh +; CHECK: std +; CHECK: lfd +; CHECK: fcfids ; PPC970: extsh ; PPC970: std ; PPC970: lfd @@ -83,19 +67,14 @@ entry: define void @sitofp_single_i8(i8 %a) nounwind { entry: -; ELF64: sitofp_single_i8 -; ELF64LE: sitofp_single_i8 +; CHECK: sitofp_single_i8 ; PPC970: sitofp_single_i8 %b.addr = alloca float, align 4 %conv = sitofp i8 %a to float -; ELF64: extsb -; ELF64: std -; ELF64: lfd -; ELF64: fcfids -; ELF64LE: extsb -; ELF64LE: std -; ELF64LE: lfd -; ELF64LE: fcfids +; CHECK: extsb +; CHECK: std +; CHECK: lfd +; CHECK: fcfids ; PPC970: extsb ; PPC970: std ; PPC970: lfd @@ -107,21 +86,16 @@ entry: define void @sitofp_double_i32(i32 %a, double %b) nounwind { entry: -; ELF64: sitofp_double_i32 -; ELF64LE: sitofp_double_i32 +; CHECK: sitofp_double_i32 ; PPC970: sitofp_double_i32 %b.addr = alloca double, align 8 %conv = sitofp i32 %a to double -; ELF64: std -; stack offset used to load the float: 65524 = -16 + 4 -; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524 -; ELF64: lfiwax -; ELF64: fcfid -; ELF64LE: std -; stack offset used to load the float: 65520 = -16 + 0 -; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520 -; ELF64LE: lfiwax -; ELF64LE: fcfid +; CHECK: std +; CHECK-NOT: ori +; CHECK: li +; CHECK-NOT: ori +; CHECK: lfiwax +; CHECK: fcfid ; PPC970: std ; PPC970: lfd ; PPC970: fcfid @@ -131,17 +105,13 @@ entry: define void @sitofp_double_i64(i64 %a, double %b) nounwind { entry: -; ELF64: sitofp_double_i64 -; ELF64LE: sitofp_double_i64 +; CHECK: sitofp_double_i64 ; PPC970: sitofp_double_i64 %b.addr = alloca double, align 8 %conv = sitofp i64 %a to double -; ELF64: std -; ELF64: lfd -; ELF64: fcfid -; ELF64LE: std -; ELF64LE: lfd -; ELF64LE: fcfid +; CHECK: std +; CHECK: lfd +; CHECK: fcfid ; PPC970: std ; PPC970: lfd ; PPC970: fcfid @@ -151,19 +121,14 @@ entry: define void @sitofp_double_i16(i16 %a, double %b) nounwind { entry: -; ELF64: sitofp_double_i16 -; ELF64LE: sitofp_double_i16 +; CHECK: sitofp_double_i16 ; PPC970: sitofp_double_i16 %b.addr = alloca double, align 8 %conv = sitofp i16 %a to double -; ELF64: extsh -; ELF64: std -; ELF64: lfd -; ELF64: fcfid -; ELF64LE: extsh -; ELF64LE: std -; ELF64LE: lfd -; ELF64LE: fcfid +; CHECK: extsh +; CHECK: std +; CHECK: lfd +; CHECK: fcfid ; PPC970: extsh ; PPC970: std ; PPC970: lfd @@ -174,19 +139,14 @@ entry: define void @sitofp_double_i8(i8 %a, double %b) nounwind { entry: -; ELF64: sitofp_double_i8 -; ELF64LE: sitofp_double_i8 +; CHECK: sitofp_double_i8 ; PPC970: sitofp_double_i8 %b.addr = alloca double, align 8 %conv = sitofp i8 %a to double -; ELF64: extsb -; ELF64: std -; ELF64: lfd -; ELF64: fcfid -; ELF64LE: extsb -; ELF64LE: std -; ELF64LE: lfd -; ELF64LE: fcfid +; CHECK: extsb +; CHECK: std +; CHECK: lfd +; CHECK: fcfid ; PPC970: extsb ; PPC970: std ; PPC970: lfd @@ -199,17 +159,13 @@ entry: define void @uitofp_single_i64(i64 %a, float %b) nounwind { entry: -; ELF64: uitofp_single_i64 -; ELF64LE: uitofp_single_i64 +; CHECK: uitofp_single_i64 ; PPC970: uitofp_single_i64 %b.addr = alloca float, align 4 %conv = uitofp i64 %a to float -; ELF64: std -; ELF64: lfd -; ELF64: fcfidus -; ELF64LE: std -; ELF64LE: lfd -; ELF64LE: fcfidus +; CHECK: std +; CHECK: lfd +; CHECK: fcfidus ; PPC970-NOT: fcfidus store float %conv, float* %b.addr, align 4 ret void @@ -217,21 +173,16 @@ entry: define void @uitofp_single_i32(i32 %a, float %b) nounwind { entry: -; ELF64: uitofp_single_i32 -; ELF64LE: uitofp_single_i32 +; CHECK: uitofp_single_i32 ; PPC970: uitofp_single_i32 %b.addr = alloca float, align 4 %conv = uitofp i32 %a to float -; ELF64: std -; stack offset used to load the float: 65524 = -16 + 4 -; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524 -; ELF64: lfiwzx -; ELF64: fcfidus -; ELF64LE: std -; stack offset used to load the float: 65520 = -16 + 0 -; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520 -; ELF64LE: lfiwzx -; ELF64LE: fcfidus +; CHECK: std +; CHECK-NOT: ori +; CHECK: li +; CHECK-NOT: ori +; CHECK: lfiwzx +; CHECK: fcfidus ; PPC970-NOT: lfiwzx ; PPC970-NOT: fcfidus store float %conv, float* %b.addr, align 4 @@ -240,19 +191,14 @@ entry: define void @uitofp_single_i16(i16 %a, float %b) nounwind { entry: -; ELF64: uitofp_single_i16 -; ELF64LE: uitofp_single_i16 +; CHECK: uitofp_single_i16 ; PPC970: uitofp_single_i16 %b.addr = alloca float, align 4 %conv = uitofp i16 %a to float -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 -; ELF64: std -; ELF64: lfd -; ELF64: fcfidus -; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 -; ELF64LE: std -; ELF64LE: lfd -; ELF64LE: fcfidus +; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 +; CHECK: std +; CHECK: lfd +; CHECK: fcfidus ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 ; PPC970: std ; PPC970: lfd @@ -264,19 +210,14 @@ entry: define void @uitofp_single_i8(i8 %a) nounwind { entry: -; ELF64: uitofp_single_i8 -; ELF64LE: uitofp_single_i8 +; CHECK: uitofp_single_i8 ; PPC970: uitofp_single_i8 %b.addr = alloca float, align 4 %conv = uitofp i8 %a to float -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 -; ELF64: std -; ELF64: lfd -; ELF64: fcfidus -; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 -; ELF64LE: std -; ELF64LE: lfd -; ELF64LE: fcfidus +; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 +; CHECK: std +; CHECK: lfd +; CHECK: fcfidus ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 ; PPC970: std ; PPC970: lfd @@ -288,17 +229,13 @@ entry: define void @uitofp_double_i64(i64 %a, double %b) nounwind { entry: -; ELF64: uitofp_double_i64 -; ELF64LE: uitofp_double_i64 +; CHECK: uitofp_double_i64 ; PPC970: uitofp_double_i64 %b.addr = alloca double, align 8 %conv = uitofp i64 %a to double -; ELF64: std -; ELF64: lfd -; ELF64: fcfidu -; ELF64LE: std -; ELF64LE: lfd -; ELF64LE: fcfidu +; CHECK: std +; CHECK: lfd +; CHECK: fcfidu ; PPC970-NOT: fcfidu store double %conv, double* %b.addr, align 8 ret void @@ -306,21 +243,15 @@ entry: define void @uitofp_double_i32(i32 %a, double %b) nounwind { entry: -; ELF64: uitofp_double_i32 -; ELF64LE: uitofp_double_i32 +; CHECK: uitofp_double_i32 ; PPC970: uitofp_double_i32 %b.addr = alloca double, align 8 %conv = uitofp i32 %a to double -; ELF64: std -; stack offset used to load the float: 65524 = -16 + 4 -; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524 -; ELF64: lfiwzx -; ELF64: fcfidu -; ELF64LE: std -; stack offset used to load the float: 65520 = -16 + 0 -; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520 -; ELF64LE: lfiwzx -; ELF64LE: fcfidu +; CHECK: std +; CHECK-NEXT: li +; CHECK-NEXT: lfiwzx +; CHECK-NEXT: fcfidu +; CHECKLE: fcfidu ; PPC970-NOT: lfiwzx ; PPC970-NOT: fcfidu store double %conv, double* %b.addr, align 8 @@ -329,19 +260,14 @@ entry: define void @uitofp_double_i16(i16 %a, double %b) nounwind { entry: -; ELF64: uitofp_double_i16 -; ELF64LE: uitofp_double_i16 +; CHECK: uitofp_double_i16 ; PPC970: uitofp_double_i16 %b.addr = alloca double, align 8 %conv = uitofp i16 %a to double -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 -; ELF64: std -; ELF64: lfd -; ELF64: fcfidu -; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 -; ELF64LE: std -; ELF64LE: lfd -; ELF64LE: fcfidu +; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 +; CHECK: std +; CHECK: lfd +; CHECK: fcfidu ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 ; PPC970: std ; PPC970: lfd @@ -352,19 +278,14 @@ entry: define void @uitofp_double_i8(i8 %a, double %b) nounwind { entry: -; ELF64: uitofp_double_i8 -; ELF64LE: uitofp_double_i8 +; CHECK: uitofp_double_i8 ; PPC970: uitofp_double_i8 %b.addr = alloca double, align 8 %conv = uitofp i8 %a to double -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 -; ELF64: std -; ELF64: lfd -; ELF64: fcfidu -; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 -; ELF64LE: std -; ELF64LE: lfd -; ELF64LE: fcfidu +; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 +; CHECK: std +; CHECK: lfd +; CHECK: fcfidu ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 ; PPC970: std ; PPC970: lfd @@ -377,17 +298,13 @@ entry: define void @fptosi_float_i32(float %a) nounwind { entry: -; ELF64: fptosi_float_i32 -; ELF64LE: fptosi_float_i32 +; CHECK: fptosi_float_i32 ; PPC970: fptosi_float_i32 %b.addr = alloca i32, align 4 %conv = fptosi float %a to i32 -; ELF64: fctiwz -; ELF64: stfd -; ELF64: lwa -; ELF64LE: fctiwz -; ELF64LE: stfd -; ELF64LE: lwa +; CHECK: fctiwz +; CHECK: stfd +; CHECK: lwa ; PPC970: fctiwz ; PPC970: stfd ; PPC970: lwa @@ -397,17 +314,13 @@ entry: define void @fptosi_float_i64(float %a) nounwind { entry: -; ELF64: fptosi_float_i64 -; ELF64LE: fptosi_float_i64 +; CHECK: fptosi_float_i64 ; PPC970: fptosi_float_i64 %b.addr = alloca i64, align 4 %conv = fptosi float %a to i64 -; ELF64: fctidz -; ELF64: stfd -; ELF64: ld -; ELF64LE: fctidz -; ELF64LE: stfd -; ELF64LE: ld +; CHECK: fctidz +; CHECK: stfd +; CHECK: ld ; PPC970: fctidz ; PPC970: stfd ; PPC970: ld @@ -417,17 +330,13 @@ entry: define void @fptosi_double_i32(double %a) nounwind { entry: -; ELF64: fptosi_double_i32 -; ELF64LE: fptosi_double_i32 +; CHECK: fptosi_double_i32 ; PPC970: fptosi_double_i32 %b.addr = alloca i32, align 8 %conv = fptosi double %a to i32 -; ELF64: fctiwz -; ELF64: stfd -; ELF64: lwa -; ELF64LE: fctiwz -; ELF64LE: stfd -; ELF64LE: lwa +; CHECK: fctiwz +; CHECK: stfd +; CHECK: lwa ; PPC970: fctiwz ; PPC970: stfd ; PPC970: lwa @@ -437,17 +346,13 @@ entry: define void @fptosi_double_i64(double %a) nounwind { entry: -; ELF64: fptosi_double_i64 -; ELF64LE: fptosi_double_i64 +; CHECK: fptosi_double_i64 ; PPC970: fptosi_double_i64 %b.addr = alloca i64, align 8 %conv = fptosi double %a to i64 -; ELF64: fctidz -; ELF64: stfd -; ELF64: ld -; ELF64LE: fctidz -; ELF64LE: stfd -; ELF64LE: ld +; CHECK: fctidz +; CHECK: stfd +; CHECK: ld ; PPC970: fctidz ; PPC970: stfd ; PPC970: ld @@ -459,17 +364,13 @@ entry: define void @fptoui_float_i32(float %a) nounwind { entry: -; ELF64: fptoui_float_i32 -; ELF64LE: fptoui_float_i32 +; CHECK: fptoui_float_i32 ; PPC970: fptoui_float_i32 %b.addr = alloca i32, align 4 %conv = fptoui float %a to i32 -; ELF64: fctiwuz -; ELF64: stfd -; ELF64: lwz -; ELF64LE: fctiwuz -; ELF64LE: stfd -; ELF64LE: lwz +; CHECK: fctiwuz +; CHECK: stfd +; CHECK: lwz ; PPC970: fctidz ; PPC970: stfd ; PPC970: lwz @@ -479,17 +380,13 @@ entry: define void @fptoui_float_i64(float %a) nounwind { entry: -; ELF64: fptoui_float_i64 -; ELF64LE: fptoui_float_i64 +; CHECK: fptoui_float_i64 ; PPC970: fptoui_float_i64 %b.addr = alloca i64, align 4 %conv = fptoui float %a to i64 -; ELF64: fctiduz -; ELF64: stfd -; ELF64: ld -; ELF64LE: fctiduz -; ELF64LE: stfd -; ELF64LE: ld +; CHECK: fctiduz +; CHECK: stfd +; CHECK: ld ; PPC970-NOT: fctiduz store i64 %conv, i64* %b.addr, align 4 ret void @@ -497,17 +394,13 @@ entry: define void @fptoui_double_i32(double %a) nounwind { entry: -; ELF64: fptoui_double_i32 -; ELF64LE: fptoui_double_i32 +; CHECK: fptoui_double_i32 ; PPC970: fptoui_double_i32 %b.addr = alloca i32, align 8 %conv = fptoui double %a to i32 -; ELF64: fctiwuz -; ELF64: stfd -; ELF64: lwz -; ELF64LE: fctiwuz -; ELF64LE: stfd -; ELF64LE: lwz +; CHECK: fctiwuz +; CHECK: stfd +; CHECK: lwz ; PPC970: fctidz ; PPC970: stfd ; PPC970: lwz @@ -517,17 +410,13 @@ entry: define void @fptoui_double_i64(double %a) nounwind { entry: -; ELF64: fptoui_double_i64 -; ELF64LE: fptoui_double_i64 +; CHECK: fptoui_double_i64 ; PPC970: fptoui_double_i64 %b.addr = alloca i64, align 8 %conv = fptoui double %a to i64 -; ELF64: fctiduz -; ELF64: stfd -; ELF64: ld -; ELF64LE: fctiduz -; ELF64LE: stfd -; ELF64LE: ld +; CHECK: fctiduz +; CHECK: stfd +; CHECK: ld ; PPC970-NOT: fctiduz store i64 %conv, i64* %b.addr, align 8 ret void diff --git a/test/CodeGen/PowerPC/fast-isel-ext.ll b/test/CodeGen/PowerPC/fast-isel-ext.ll index ce8ac440b79cb..510f14888385e 100644 --- a/test/CodeGen/PowerPC/fast-isel-ext.ll +++ b/test/CodeGen/PowerPC/fast-isel-ext.ll @@ -19,21 +19,21 @@ define i32 @zext_16_32(i16 %a) nounwind { define i64 @zext_8_64(i8 %a) nounwind { ; ELF64: zext_8_64 %r = zext i8 %a to i64 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 ret i64 %r } define i64 @zext_16_64(i16 %a) nounwind { ; ELF64: zext_16_64 %r = zext i16 %a to i64 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ret i64 %r } define i64 @zext_32_64(i32 %a) nounwind { ; ELF64: zext_32_64 %r = zext i32 %a to i64 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32 ret i64 %r } diff --git a/test/CodeGen/PowerPC/fast-isel-ret.ll b/test/CodeGen/PowerPC/fast-isel-ret.ll index 0adb5a9351090..4c499e44e4f04 100644 --- a/test/CodeGen/PowerPC/fast-isel-ret.ll +++ b/test/CodeGen/PowerPC/fast-isel-ret.ll @@ -47,7 +47,7 @@ entry: define zeroext i8 @ret3(i8 signext %a) nounwind { entry: ; ELF64-LABEL: ret3 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 ; ELF64: blr ret i8 %a } @@ -63,7 +63,7 @@ entry: define zeroext i16 @ret5(i16 signext %a) nounwind { entry: ; ELF64-LABEL: ret5 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ; ELF64: blr ret i16 %a } @@ -71,7 +71,7 @@ entry: define i16 @ret6(i16 %a) nounwind { entry: ; ELF64-LABEL: ret6 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ; ELF64: blr ret i16 %a } @@ -87,7 +87,7 @@ entry: define zeroext i32 @ret8(i32 signext %a) nounwind { entry: ; ELF64-LABEL: ret8 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32 ; ELF64: blr ret i32 %a } @@ -95,7 +95,7 @@ entry: define i32 @ret9(i32 %a) nounwind { entry: ; ELF64-LABEL: ret9 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32 ; ELF64: blr ret i32 %a } @@ -104,6 +104,7 @@ define i64 @ret10(i64 %a) nounwind { entry: ; ELF64-LABEL: ret10 ; ELF64-NOT: exts +; ELF64-NOT: clrldi ; ELF64-NOT: rldicl ; ELF64: blr ret i64 %a diff --git a/test/CodeGen/PowerPC/fma-aggr-FMF.ll b/test/CodeGen/PowerPC/fma-aggr-FMF.ll index 8e97115bd1f2b..e861c9df37aba 100644 --- a/test/CodeGen/PowerPC/fma-aggr-FMF.ll +++ b/test/CodeGen/PowerPC/fma-aggr-FMF.ll @@ -3,7 +3,7 @@ define float @can_fma_with_fewer_uses(float %f1, float %f2, float %f3, float %f4) { ; CHECK-LABEL: can_fma_with_fewer_uses: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xsmulsp 0, 1, 2 ; CHECK-NEXT: fmr 1, 0 ; CHECK-NEXT: xsmaddasp 1, 3, 4 @@ -21,7 +21,7 @@ define float @can_fma_with_fewer_uses(float %f1, float %f2, float %f3, float %f4 ; around beside the fma. define float @no_fma_with_fewer_uses(float %f1, float %f2, float %f3, float %f4) { ; CHECK-LABEL: no_fma_with_fewer_uses: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xsmulsp 0, 3, 4 ; CHECK-NEXT: xsmulsp 13, 1, 2 ; CHECK-NEXT: xsmaddasp 0, 1, 2 diff --git a/test/CodeGen/PowerPC/fma-assoc.ll b/test/CodeGen/PowerPC/fma-assoc.ll index 5080e5b250e92..ffa3c22fd8302 100644 --- a/test/CodeGen/PowerPC/fma-assoc.ll +++ b/test/CodeGen/PowerPC/fma-assoc.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -fp-contract=fast -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SAFE %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -fp-contract=fast -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SAFE %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-VSX -check-prefix=CHECK-VSX-SAFE %s -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -fp-contract=fast -enable-unsafe-fp-math -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK -check-prefix=CHECK-UNSAFE %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -fp-contract=fast -enable-unsafe-fp-math -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK -check-prefix=CHECK-UNSAFE %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -enable-unsafe-fp-math -mattr=+vsx -mcpu=pwr7 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-VSX -check-prefix=CHECK-UNSAFE-VSX %s define double @test_FMADD_ASSOC1(double %A, double %B, double %C, diff --git a/test/CodeGen/PowerPC/fma-ext.ll b/test/CodeGen/PowerPC/fma-ext.ll index 73ceebb5b613c..57771d3a453c5 100644 --- a/test/CodeGen/PowerPC/fma-ext.ll +++ b/test/CodeGen/PowerPC/fma-ext.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -fp-contract=fast -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -fp-contract=fast -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-VSX %s define double @test_FMADD_EXT1(float %A, float %B, double %C) { diff --git a/test/CodeGen/PowerPC/fma.ll b/test/CodeGen/PowerPC/fma.ll index 9def59d4de3f9..f6c5774518928 100644 --- a/test/CodeGen/PowerPC/fma.ll +++ b/test/CodeGen/PowerPC/fma.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -fp-contract=fast -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -fp-contract=fast -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-VSX %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mcpu=pwr8 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-P8 %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -fp-contract=fast -mcpu=pwr8 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-P8 %s diff --git a/test/CodeGen/PowerPC/fmaxnum.ll b/test/CodeGen/PowerPC/fmaxnum.ll index 5d16ad8722aa3..e62ab6dcdde8d 100644 --- a/test/CodeGen/PowerPC/fmaxnum.ll +++ b/test/CodeGen/PowerPC/fmaxnum.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -march=ppc32 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s declare float @fmaxf(float, float) declare double @fmax(double, double) diff --git a/test/CodeGen/PowerPC/fminnum.ll b/test/CodeGen/PowerPC/fminnum.ll index 706e742e50e4e..6b1661965f4db 100644 --- a/test/CodeGen/PowerPC/fminnum.ll +++ b/test/CodeGen/PowerPC/fminnum.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -march=ppc32 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s declare float @fminf(float, float) declare double @fmin(double, double) diff --git a/test/CodeGen/PowerPC/fnabs.ll b/test/CodeGen/PowerPC/fnabs.ll index aa4a63e05557a..d71f5457e9bb1 100644 --- a/test/CodeGen/PowerPC/fnabs.ll +++ b/test/CodeGen/PowerPC/fnabs.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 | grep fnabs +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- | grep fnabs declare double @fabs(double) diff --git a/test/CodeGen/PowerPC/fneg.ll b/test/CodeGen/PowerPC/fneg.ll index c34a7b19503b0..1a4f48c11421f 100644 --- a/test/CodeGen/PowerPC/fneg.ll +++ b/test/CodeGen/PowerPC/fneg.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep fneg +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep fneg define double @test1(double %a, double %b, double %c, double %d) { entry: diff --git a/test/CodeGen/PowerPC/fold-li.ll b/test/CodeGen/PowerPC/fold-li.ll index 4e46ffd3dc0e8..43da003a8fa3f 100644 --- a/test/CodeGen/PowerPC/fold-li.ll +++ b/test/CodeGen/PowerPC/fold-li.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: grep -v align | not grep li ;; Test that immediates are folded into these instructions correctly. diff --git a/test/CodeGen/PowerPC/fp-branch.ll b/test/CodeGen/PowerPC/fp-branch.ll index cb8acc5edc197..ba8052d93cb98 100644 --- a/test/CodeGen/PowerPC/fp-branch.ll +++ b/test/CodeGen/PowerPC/fp-branch.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 | grep fcmp | count 1 +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- | grep fcmp | count 1 declare i1 @llvm.isunordered.f64(double, double) diff --git a/test/CodeGen/PowerPC/fp-int-fp.ll b/test/CodeGen/PowerPC/fp-int-fp.ll index 0f5ed25cf4d6b..186539260e596 100644 --- a/test/CodeGen/PowerPC/fp-int-fp.ll +++ b/test/CodeGen/PowerPC/fp-int-fp.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | not grep r1 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | not grep r1 define double @test1(double %X) { %Y = fptosi double %X to i64 ; <i64> [#uses=1] diff --git a/test/CodeGen/PowerPC/fp-splat.ll b/test/CodeGen/PowerPC/fp-splat.ll new file mode 100644 index 0000000000000..9b1ab21aaa408 --- /dev/null +++ b/test/CodeGen/PowerPC/fp-splat.ll @@ -0,0 +1,27 @@ +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK-P8 -check-prefix=CHECK +; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK-P7 -check-prefix=CHECK + +define <4 x float> @test1(float %a) { +entry: +; CHECK-LABEL: test1 + %vecins = insertelement <4 x float> undef, float %a, i32 0 + %vecins1 = insertelement <4 x float> %vecins, float %a, i32 1 + %vecins2 = insertelement <4 x float> %vecins1, float %a, i32 2 + %vecins3 = insertelement <4 x float> %vecins2, float %a, i32 3 + ret <4 x float> %vecins3 +; CHECK-P8: xscvdpspn +; CHECK-P7-NOT: xscvdpspn +; CHECK: blr +} + +define <2 x double> @test2(double %a) { +entry: +; CHECK-LABEL: test2 + %vecins = insertelement <2 x double> undef, double %a, i32 0 + %vecins1 = insertelement <2 x double> %vecins, double %a, i32 1 + ret <2 x double> %vecins1 +; CHECK-P8: xxspltd +; CHECK-P7: xxspltd +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/fp64-to-int16.ll b/test/CodeGen/PowerPC/fp64-to-int16.ll index 10d58c2d76692..360a98665182e 100644 --- a/test/CodeGen/PowerPC/fp64-to-int16.ll +++ b/test/CodeGen/PowerPC/fp64-to-int16.ll @@ -4,13 +4,13 @@ target triple = "powerpc64le--linux-gnu" define i1 @Test(double %a) { ; CHECK-LABEL: Test: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xscvdpsxws 1, 1 ; CHECK-NEXT: mfvsrwz 3, 1 ; CHECK-NEXT: xori 3, 3, 65534 ; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: srwi 3, 3, 5 -; CHECK-NEXT: # implicit-def: %X4 +; CHECK-NEXT: # implicit-def: %x4 ; CHECK-NEXT: mr 4, 3 ; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: blr diff --git a/test/CodeGen/PowerPC/fp_to_uint.ll b/test/CodeGen/PowerPC/fp_to_uint.ll index 676b37c1462eb..637294d0f2429 100644 --- a/test/CodeGen/PowerPC/fp_to_uint.ll +++ b/test/CodeGen/PowerPC/fp_to_uint.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 | grep fctiwz | count 1 +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- | grep fctiwz | count 1 define i16 @foo(float %a) { diff --git a/test/CodeGen/PowerPC/fpcopy.ll b/test/CodeGen/PowerPC/fpcopy.ll index ad814a5420e62..1416423357acb 100644 --- a/test/CodeGen/PowerPC/fpcopy.ll +++ b/test/CodeGen/PowerPC/fpcopy.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep fmr +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep fmr define double @test(float %F) { %F.upgrd.1 = fpext float %F to double ; <double> [#uses=1] diff --git a/test/CodeGen/PowerPC/frounds.ll b/test/CodeGen/PowerPC/frounds.ll index 24292d23dff83..8286d8299c4ab 100644 --- a/test/CodeGen/PowerPC/frounds.ll +++ b/test/CodeGen/PowerPC/frounds.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- define i32 @foo() { entry: diff --git a/test/CodeGen/PowerPC/fsqrt.ll b/test/CodeGen/PowerPC/fsqrt.ll index 4cc9be9cbaddb..d7b8e57523bc9 100644 --- a/test/CodeGen/PowerPC/fsqrt.ll +++ b/test/CodeGen/PowerPC/fsqrt.ll @@ -1,13 +1,13 @@ ; fsqrt should be generated when the fsqrt feature is enabled, but not ; otherwise. -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \ +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \ ; RUN: grep "fsqrt f1, f1" -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \ +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \ ; RUN: grep "fsqrt f1, f1" -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \ +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \ ; RUN: not grep "fsqrt f1, f1" -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \ +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \ ; RUN: not grep "fsqrt f1, f1" declare double @llvm.sqrt.f64(double) diff --git a/test/CodeGen/PowerPC/gpr-vsr-spill.ll b/test/CodeGen/PowerPC/gpr-vsr-spill.ll new file mode 100644 index 0000000000000..218241ae0a798 --- /dev/null +++ b/test/CodeGen/PowerPC/gpr-vsr-spill.ll @@ -0,0 +1,24 @@ +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -ppc-enable-gpr-to-vsr-spills < %s | FileCheck %s +define signext i32 @foo(i32 signext %a, i32 signext %b) { +entry: + %cmp = icmp slt i32 %a, %b + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29}"(i32 %a, i32 %b) + %mul = mul nsw i32 %0, %a + %add = add i32 %b, %a + %tmp = add i32 %add, %mul + br label %if.end + +if.end: ; preds = %if.then, %entry + %e.0 = phi i32 [ %tmp, %if.then ], [ undef, %entry ] + ret i32 %e.0 +; CHECK: @foo +; CHECK: mr [[NEWREG:[0-9]+]], 3 +; CHECK: mtvsrd [[NEWREG2:[0-9]+]], 4 +; CHECK: mffprd [[REG1:[0-9]+]], [[NEWREG2]] +; CHECK: add {{[0-9]+}}, [[NEWREG]], [[REG1]] +; CHECK: mffprd [[REG2:[0-9]+]], [[NEWREG2]] +; CHECK: add {{[0-9]+}}, [[REG2]], [[NEWREG]] +} diff --git a/test/CodeGen/PowerPC/hello-reloc.s b/test/CodeGen/PowerPC/hello-reloc.s index bbf1e7cacbd46..66bc9a84f5c20 100644 --- a/test/CodeGen/PowerPC/hello-reloc.s +++ b/test/CodeGen/PowerPC/hello-reloc.s @@ -11,7 +11,7 @@ .globl _main .align 4 _main: ; @main -; BB#0: ; %entry +; %bb.0: ; %entry mflr r0 stw r31, -4(r1) stw r0, 8(r1) diff --git a/test/CodeGen/PowerPC/hello.ll b/test/CodeGen/PowerPC/hello.ll index 91133c47de8fa..23b2e0702656e 100644 --- a/test/CodeGen/PowerPC/hello.ll +++ b/test/CodeGen/PowerPC/hello.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -; RUN: llc -verify-machineinstrs < %s -march=ppc64 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- ; PR1399 @.str = internal constant [13 x i8] c"Hello World!\00" diff --git a/test/CodeGen/PowerPC/i1-to-double.ll b/test/CodeGen/PowerPC/i1-to-double.ll index 7871ac7ae05b3..bb595e3ad1ce7 100644 --- a/test/CodeGen/PowerPC/i1-to-double.ll +++ b/test/CodeGen/PowerPC/i1-to-double.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -march=ppc32 -mcpu=ppc32 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=ppc32 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s define double @test(i1 %X) { %Y = uitofp i1 %X to double ret double %Y diff --git a/test/CodeGen/PowerPC/i128-and-beyond.ll b/test/CodeGen/PowerPC/i128-and-beyond.ll index acdea09f447eb..073a943ee1098 100644 --- a/test/CodeGen/PowerPC/i128-and-beyond.ll +++ b/test/CodeGen/PowerPC/i128-and-beyond.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep 4294967295 | count 28 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep 4294967295 | count 28 ; These static initializers are too big to hand off to assemblers ; as monolithic blobs. diff --git a/test/CodeGen/PowerPC/i64_fp.ll b/test/CodeGen/PowerPC/i64_fp.ll index 99f331d737e41..b9456150df7b8 100644 --- a/test/CodeGen/PowerPC/i64_fp.ll +++ b/test/CodeGen/PowerPC/i64_fp.ll @@ -1,21 +1,21 @@ ; fcfid and fctid should be generated when the 64bit feature is enabled, but not ; otherwise. -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mattr=+64bit | \ +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+64bit | \ ; RUN: grep fcfid -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mattr=+64bit | \ +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=+64bit | \ ; RUN: grep fctidz -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mcpu=g5 | \ +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mcpu=g5 | \ ; RUN: grep fcfid -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mcpu=g5 | \ +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mcpu=g5 | \ ; RUN: grep fctidz -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mattr=-64bit | \ +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=-64bit | \ ; RUN: not grep fcfid -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mattr=-64bit | \ +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mattr=-64bit | \ ; RUN: not grep fctidz -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mcpu=g4 | \ +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mcpu=g4 | \ ; RUN: not grep fcfid -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -mcpu=g4 | \ +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -mcpu=g4 | \ ; RUN: not grep fctidz define double @X(double %Y) { diff --git a/test/CodeGen/PowerPC/iabs.ll b/test/CodeGen/PowerPC/iabs.ll index e37ed107bfa06..fb9948ec3df8b 100644 --- a/test/CodeGen/PowerPC/iabs.ll +++ b/test/CodeGen/PowerPC/iabs.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -stats 2>&1 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -stats 2>&1 | \ ; RUN: grep "4 .*Number of machine instrs printed" ;; Integer absolute value, should produce something as good as: diff --git a/test/CodeGen/PowerPC/illegal-element-type.ll b/test/CodeGen/PowerPC/illegal-element-type.ll index 48107efbd4588..5ac7085be3c74 100644 --- a/test/CodeGen/PowerPC/illegal-element-type.ll +++ b/test/CodeGen/PowerPC/illegal-element-type.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g3 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g3 define void @foo() { entry: diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll index c040d7859a8b0..4727e22730a13 100644 --- a/test/CodeGen/PowerPC/indirectbr.ll +++ b/test/CodeGen/PowerPC/indirectbr.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -relocation-model=pic -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s -check-prefix=PIC -; RUN: llc < %s -relocation-model=static -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s -check-prefix=STATIC -; RUN: llc < %s -relocation-model=pic -march=ppc64 -mtriple=powerpc64-apple-darwin | FileCheck %s -check-prefix=PPC64 +; RUN: llc < %s -relocation-model=pic -mtriple=powerpc-apple-darwin | FileCheck %s -check-prefix=PIC +; RUN: llc < %s -relocation-model=static -mtriple=powerpc-apple-darwin | FileCheck %s -check-prefix=STATIC +; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64-apple-darwin | FileCheck %s -check-prefix=PPC64 @nextaddr = global i8* null ; <i8**> [#uses=2] @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] diff --git a/test/CodeGen/PowerPC/inlineasm-copy.ll b/test/CodeGen/PowerPC/inlineasm-copy.ll index 0d5f6a6aeb97b..36fed54ba4efb 100644 --- a/test/CodeGen/PowerPC/inlineasm-copy.ll +++ b/test/CodeGen/PowerPC/inlineasm-copy.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 -no-integrated-as -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=ppc32-- -no-integrated-as -verify-machineinstrs | FileCheck %s ; CHECK-NOT: mr define i32 @test(i32 %Y, i32 %X) { diff --git a/test/CodeGen/PowerPC/int-fp-conv-0.ll b/test/CodeGen/PowerPC/int-fp-conv-0.ll index 2bf671be3e5bd..5b549003912a7 100644 --- a/test/CodeGen/PowerPC/int-fp-conv-0.ll +++ b/test/CodeGen/PowerPC/int-fp-conv-0.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 > %t +; RUN: llc -verify-machineinstrs < %s > %t ; RUN: grep __floattitf %t ; RUN: grep __fixunstfti %t diff --git a/test/CodeGen/PowerPC/int-fp-conv-1.ll b/test/CodeGen/PowerPC/int-fp-conv-1.ll index c73f540e3a139..0f201f598691d 100644 --- a/test/CodeGen/PowerPC/int-fp-conv-1.ll +++ b/test/CodeGen/PowerPC/int-fp-conv-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- | FileCheck %s ; CHECK-NOT: __floatditf define i64 @__fixunstfdi(ppc_fp128 %a) nounwind { diff --git a/test/CodeGen/PowerPC/inverted-bool-compares.ll b/test/CodeGen/PowerPC/inverted-bool-compares.ll index 4b964b7c8114c..f35d6edf22a59 100644 --- a/test/CodeGen/PowerPC/inverted-bool-compares.ll +++ b/test/CodeGen/PowerPC/inverted-bool-compares.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep xori +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep xori define i32 @test(i1 %B, i32* %P) { br i1 %B, label %T, label %F diff --git a/test/CodeGen/PowerPC/ispositive.ll b/test/CodeGen/PowerPC/ispositive.ll index c3eb7a295d914..824f721402e5c 100644 --- a/test/CodeGen/PowerPC/ispositive.ll +++ b/test/CodeGen/PowerPC/ispositive.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 | \ ; RUN: grep "srwi r3, r3, 31" define i32 @test1(i32 %X) { diff --git a/test/CodeGen/PowerPC/itofp128.ll b/test/CodeGen/PowerPC/itofp128.ll index ea8ba33a460ae..1336ba7c62616 100644 --- a/test/CodeGen/PowerPC/itofp128.ll +++ b/test/CodeGen/PowerPC/itofp128.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 +; RUN: llc -verify-machineinstrs < %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc64-apple-darwin9.2.0" diff --git a/test/CodeGen/PowerPC/lha.ll b/test/CodeGen/PowerPC/lha.ll index 1412582588d5c..e85f462350a79 100644 --- a/test/CodeGen/PowerPC/lha.ll +++ b/test/CodeGen/PowerPC/lha.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep lha +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep lha define i32 @test(i16* %a) { %tmp.1 = load i16, i16* %a ; <i16> [#uses=1] diff --git a/test/CodeGen/PowerPC/licm-remat.ll b/test/CodeGen/PowerPC/licm-remat.ll index cbd1af62b8429..f9c1405245210 100644 --- a/test/CodeGen/PowerPC/licm-remat.ll +++ b/test/CodeGen/PowerPC/licm-remat.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -ppc-reduce-cr-logicals \ +; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; Test case is reduced from the snappy benchmark. ; Verify MachineLICM will always hoist trivially rematerializable instructions even when register pressure is high. @@ -18,11 +19,11 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture r define linkonce_odr void @ZN6snappyDecompressor_(%"class.snappy::SnappyDecompressor"* %this, %"class.snappy::SnappyIOVecWriter"* %writer) { ; CHECK-LABEL: ZN6snappyDecompressor_: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: addis 3, 2, _ZN6snappy8internalL8wordmaskE@toc@ha ; CHECK-DAG: addi 25, 3, _ZN6snappy8internalL8wordmaskE@toc@l -; CHECK-DAG: addis 4, 2, _ZN6snappy8internalL10char_tableE@toc@ha -; CHECK-DAG: addi 24, 4, _ZN6snappy8internalL10char_tableE@toc@l +; CHECK-DAG: addis 5, 2, _ZN6snappy8internalL10char_tableE@toc@ha +; CHECK-DAG: addi 24, 5, _ZN6snappy8internalL10char_tableE@toc@l ; CHECK: b .LBB0_2 ; CHECK: .LBB0_2: # %for.cond ; CHECK-NOT: addis {{[0-9]+}}, 2, _ZN6snappy8internalL8wordmaskE@toc@ha diff --git a/test/CodeGen/PowerPC/licm-tocReg.ll b/test/CodeGen/PowerPC/licm-tocReg.ll index ecdfcba6e3b7a..efbec9091a5a2 100644 --- a/test/CodeGen/PowerPC/licm-tocReg.ll +++ b/test/CodeGen/PowerPC/licm-tocReg.ll @@ -1,20 +1,20 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -; The instructions ADDIStocHA/LDtocL are used to calculate the address of -; globals. The ones that are in bb.3.if.end could not be hoisted by Machine +; The instructions ADDIStocHA/LDtocL are used to calculate the address of +; globals. The ones that are in bb.3.if.end could not be hoisted by Machine ; LICM due to BCTRL_LDinto_toc in bb2.if.then. This call causes the compiler ; to insert a save TOC to stack before the call and load into X2 to restore TOC -; after. By communicating to Machine LICM that X2 is guaranteed to have the +; after. By communicating to Machine LICM that X2 is guaranteed to have the ; same value before and after BCTRL_LDinto_toc, these instructions can be ; hoisted out of bb.3.if.end to outside of the loop. ; Pre Machine LICM MIR ; -;body: +;body: ; bb.0.entry: ; successors: %bb.2.if.then(0x40000000), %bb.3.if.end(0x40000000) ; liveins: %x3 -; +; ; %4 = COPY %x3 ; %5 = ADDIStocHA %x2, @ga ; %6 = LDtocL @ga, killed %5 :: (load 8 from got) @@ -26,7 +26,7 @@ ; %11 = CMPW killed %7, killed %10 ; BCC 44, killed %11, %bb.2.if.then ; B %bb.3.if.end -; +; ; bb.2.if.then: ; %1 = PHI %0, %bb.0.entry, %3, %bb.3.if.end ; ADJCALLSTACKDOWN 32, 0, implicit-def dead %r1, implicit %r1 @@ -41,10 +41,10 @@ ; %22 = COPY %x3 ; %x3 = COPY %22 ; BLR8 implicit %lr8, implicit %rm, implicit %x3 -; +; ; bb.3.if.end: ; successors: %bb.2.if.then(0x04000000), %bb.3.if.end(0x7c000000) -; +; ; %2 = PHI %0, %bb.0.entry, %3, %bb.3.if.end ; %12 = ADDI %2, 1 ; %13 = ADDIStocHA %x2, @ga @@ -62,27 +62,23 @@ @ga = external global i32, align 4 @gb = external global i32, align 4 -; Function Attrs: nounwind define signext i32 @test(i32 (i32)* nocapture %FP) local_unnamed_addr #0 { ; CHECK-LABEL: test: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis 4, 2, .LC0@toc@ha -; CHECK-NEXT: addis 5, 2, .LC1@toc@ha -; CHECK-NEXT: ld 4, .LC0@toc@l(4) -; CHECK-NEXT: ld 5, .LC1@toc@l(5) -; CHECK-NEXT: lwz 6, 0(4) -; CHECK-NEXT: lwz 5, 0(5) -; CHECK-NEXT: cmpw 6, 5 -; CHECK-NEXT: lwz 5, 0(4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis 6, 2, .LC0@toc@ha +; CHECK-NEXT: addis 4, 2, .LC1@toc@ha +; CHECK-NEXT: ld 5, .LC1@toc@l(4) +; CHECK-NEXT: ld 6, .LC0@toc@l(6) +; CHECK-NEXT: lwz 4, 0(5) +; CHECK-NEXT: lwz 7, 0(6) +; CHECK-NEXT: cmpw 4, 7 +; CHECK-NEXT: lwz 7, 0(5) ; CHECK-NEXT: mr 4, 3 -; CHECK-NEXT: bgt 0, .LBB0_3 -; CHECK-NEXT: # BB#1: -; CHECK-NEXT: addis 3, 2, .LC0@toc@ha -; CHECK-NEXT: addis 6, 2, .LC1@toc@ha -; CHECK-NEXT: ld 3, .LC0@toc@l(3) -; CHECK-NEXT: ld 6, .LC1@toc@l(6) +; CHECK-NEXT: bgt 0, .LBB0_2 +; CHECK-NOT: addis {{[0-9]+}}, 2, .LC0@toc@ha +; CHECK-NOT: addis {{[0-9]+}}, 2, .LC1@toc@ha ; CHECK-NEXT: .p2align 5 -; CHECK-NEXT: .LBB0_2: # %if.end +; CHECK-NEXT: .LBB0_1: # %if.end ; CHECK-NOT: addis {{[0-9]+}}, 2, .LC0@toc@ha ; CHECK-NOT: addis {{[0-9]+}}, 2, .LC1@toc@ha ; CHECK: blr diff --git a/test/CodeGen/PowerPC/load-constant-addr.ll b/test/CodeGen/PowerPC/load-constant-addr.ll index f2c69eb2b4ac0..4e97925eca9f9 100644 --- a/test/CodeGen/PowerPC/load-constant-addr.ll +++ b/test/CodeGen/PowerPC/load-constant-addr.ll @@ -1,6 +1,6 @@ ; Should fold the ori into the lfs. -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep lfs -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep ori +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep lfs +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep ori define float @test() { %tmp.i = load float, float* inttoptr (i32 186018016 to float*) ; <float> [#uses=1] diff --git a/test/CodeGen/PowerPC/logic-ops-on-compares.ll b/test/CodeGen/PowerPC/logic-ops-on-compares.ll index df021c20ea86e..b1b26f0ab7607 100644 --- a/test/CodeGen/PowerPC/logic-ops-on-compares.ll +++ b/test/CodeGen/PowerPC/logic-ops-on-compares.ll @@ -1,3 +1,4 @@ +; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ @@ -18,7 +19,7 @@ define signext i32 @logic_ne_32(i32 signext %a, i32 signext %b, i32 signext %c) ; CHECK-NEXT: srwi r6, r6, 5 ; CHECK-NEXT: srwi r5, r5, 5 ; CHECK-NEXT: or. r5, r6, r5 -; CHECK-NEXT: bc 4, 1 +; CHECK-NEXT: bc 4, gt entry: %tobool = icmp eq i32 %a, %b %tobool1 = icmp eq i32 %b, 0 @@ -40,14 +41,13 @@ return: ; preds = %if.end, %if.then ret i32 %retval.0 } -define void @neg_truncate_i32(i32 *%ptr) { -; CHECK-LABEL: neg_truncate_i32: -; CHECK: # BB#0: # %entry +define void @neg_truncate_i32_eq(i32 *%ptr) { +; CHECK-LABEL: neg_truncate_i32_eq: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lwz r3, 0(r3) ; CHECK-NEXT: rldicl. r3, r3, 0, 63 -; CHECK-NEXT: bclr 12, 2, 0 -; CHECK-NEXT: # BB#1: # %if.end29.thread136 -; CHECK-NEXT: .LBB1_2: # %if.end29 +; CHECK-NEXT: bclr 12, eq, 0 +; CHECK-NEXT: # %bb.1: # %if.end29.thread136 entry: %0 = load i32, i32* %ptr, align 4 %rem17127 = and i32 %0, 1 @@ -66,8 +66,8 @@ if.end29: ; preds = %if.else } ; Function Attrs: nounwind -define i64 @logic_ne_64(i64 %a, i64 %b, i64 %c) { -; CHECK-LABEL: logic_ne_64: +define i64 @logic_eq_64(i64 %a, i64 %b, i64 %c) { +; CHECK-LABEL: logic_eq_64: ; CHECK: xor r7, r3, r4 ; CHECK-NEXT: li r6, 55 ; CHECK-NEXT: xor r5, r5, r6 @@ -77,7 +77,7 @@ define i64 @logic_ne_64(i64 %a, i64 %b, i64 %c) { ; CHECK-NEXT: rldicl r6, r6, 58, 63 ; CHECK-NEXT: rldicl r5, r5, 58, 63 ; CHECK-NEXT: or. r5, r6, r5 -; CHECK-NEXT: bc 4, 1 +; CHECK-NEXT: bc 4, gt entry: %tobool = icmp eq i64 %a, %b %tobool1 = icmp eq i64 %b, 0 @@ -99,14 +99,13 @@ return: ; preds = %if.end, %if.then ret i64 %retval.0 } -define void @neg_truncate_i64(i64 *%ptr) { -; CHECK-LABEL: neg_truncate_i64: -; CHECK: # BB#0: # %entry +define void @neg_truncate_i64_eq(i64 *%ptr) { +; CHECK-LABEL: neg_truncate_i64_eq: +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld r3, 0(r3) ; CHECK-NEXT: rldicl. r3, r3, 0, 63 -; CHECK-NEXT: bclr 12, 2, 0 -; CHECK-NEXT: # BB#1: # %if.end29.thread136 -; CHECK-NEXT: .LBB3_2: # %if.end29 +; CHECK-NEXT: bclr 12, eq, 0 +; CHECK-NEXT: # %bb.1: # %if.end29.thread136 entry: %0 = load i64, i64* %ptr, align 4 %rem17127 = and i64 %0, 1 @@ -124,6 +123,66 @@ if.end29: ; preds = %if.else } +; Function Attrs: nounwind +define i64 @logic_ne_64(i64 %a, i64 %b, i64 %c) { +; CHECK-LABEL: logic_ne_64: +; CHECK: xor r7, r3, r4 +; CHECK-NEXT: li r6, 55 +; CHECK-NEXT: addic r8, r7, -1 +; CHECK-NEXT: xor r5, r5, r6 +; CHECK-NEXT: subfe r7, r8, r7 +; CHECK-NEXT: cntlzd r5, r5 +; CHECK-NEXT: addic r12, r4, -1 +; CHECK-NEXT: rldicl r5, r5, 58, 63 +; CHECK-NEXT: subfe r6, r12, r4 +; CHECK-NEXT: and r6, r7, r6 +; CHECK-NEXT: or. r5, r6, r5 +; CHECK-NEXT: bc 4, gt +entry: + %tobool = icmp ne i64 %a, %b + %tobool1 = icmp ne i64 %b, 0 + %or.cond = and i1 %tobool, %tobool1 + %tobool3 = icmp eq i64 %c, 55 + %or.cond5 = or i1 %or.cond, %tobool3 + br i1 %or.cond5, label %if.end, label %if.then + +if.then: ; preds = %entry + %call = tail call i64 @foo64(i64 %a) #2 + br label %return + +if.end: ; preds = %entry + %call4 = tail call i64 @bar64(i64 %b) #2 + br label %return + +return: ; preds = %if.end, %if.then + %retval.0 = phi i64 [ %call4, %if.end ], [ %call, %if.then ] + ret i64 %retval.0 +} + +define void @neg_truncate_i64_ne(i64 *%ptr) { +; CHECK-LABEL: neg_truncate_i64_ne: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: ld r3, 0(r3) +; CHECK-NEXT: andi. r3, r3, 1 +; CHECK-NEXT: bclr 12, gt, 0 +; CHECK-NEXT: # %bb.1: # %if.end29.thread136 +entry: + %0 = load i64, i64* %ptr, align 4 + %rem17127 = and i64 %0, 1 + %cmp18 = icmp ne i64 %rem17127, 0 + br label %if.else + +if.else: ; preds = %entry + br i1 %cmp18, label %if.end29, label %if.end29.thread136 + +if.end29.thread136: ; preds = %if.else + unreachable + +if.end29: ; preds = %if.else + ret void + +} + declare signext i32 @foo(i32 signext) declare signext i32 @bar(i32 signext) declare i64 @foo64(i64) diff --git a/test/CodeGen/PowerPC/long-compare.ll b/test/CodeGen/PowerPC/long-compare.ll index 2a4877721a733..7a06b3ed60537 100644 --- a/test/CodeGen/PowerPC/long-compare.ll +++ b/test/CodeGen/PowerPC/long-compare.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep cntlzw -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep xori -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep "li " -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep "mr " +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep cntlzw +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep xori +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep "li " +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep "mr " define i1 @test(i64 %x) { %tmp = icmp ult i64 %x, 4294967296 diff --git a/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll b/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll new file mode 100644 index 0000000000000..9c5432578b4ed --- /dev/null +++ b/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll @@ -0,0 +1,46 @@ +; RUN: llc -O3 -o - %s | FileCheck %s +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +%class1 = type { %union1 } +%union1 = type { i64, [24 x i8] } +%class2 = type { %class3 } +%class3 = type { %class4 } +%class4 = type { %class5, i64, %union.anon } +%class5 = type { i8* } +%union.anon = type { i64, [8 x i8] } + +@ext = external global %"class1", align 8 + +; We can't select lxv for this because even though we're accessing an offset of +; 16 from the stack slot, the stack slot is only guaranteed to be 8-byte +; aligned. When the frame is finalized it is converted to lxv (frame-reg) + +; (offset + 16). Because offset isn't guaranteed to be 16-byte aligned, we may +; end up needing to translate the lxv instruction to lxvx +; CHECK-LABEL: unaligned_slot: +; CHECK-NOT: lxv {{[0-9]+}}, {{[-0-9]+}}({{[0-9]+}}) +; CHECK: blr +define void @unaligned_slot() #0 { + %1 = alloca %class2, align 8 + %2 = getelementptr inbounds %class2, %class2* %1, i64 0, i32 0, i32 0, i32 2 + %3 = bitcast %union.anon* %2 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull getelementptr inbounds (%class1, %class1* @ext, i64 0, i32 0, i32 1, i64 8), i8* nonnull %3, i64 16, i32 8, i1 false) #2 + ret void +} +; CHECK-LABEL: aligned_slot: +; CHECK: lxv {{[0-9]+}}, {{[-0-9]+}}({{[0-9]+}}) +; CHECK: blr +define void @aligned_slot() #0 { + %1 = alloca %class2, align 16 + %2 = getelementptr inbounds %class2, %class2* %1, i64 0, i32 0, i32 0, i32 2 + %3 = bitcast %union.anon* %2 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull getelementptr inbounds (%class1, %class1* @ext, i64 0, i32 0, i32 1, i64 8), i8* nonnull %3, i64 16, i32 8, i1 false) #2 + ret void +} + +; Function Attrs: argmemonly nounwind +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #1 + +attributes #0 = { nounwind "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { argmemonly nounwind } +attributes #2 = { nounwind } diff --git a/test/CodeGen/PowerPC/machine-combiner.ll b/test/CodeGen/PowerPC/machine-combiner.ll index e026017710ef3..c7337e3637e31 100644 --- a/test/CodeGen/PowerPC/machine-combiner.ll +++ b/test/CodeGen/PowerPC/machine-combiner.ll @@ -8,7 +8,7 @@ target triple = "powerpc64-unknown-linux-gnu" define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) { ; CHECK-LABEL: reassociate_adds1: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK: fadds [[REG0:[0-9]+]], 1, 2 ; CHECK: fadds [[REG1:[0-9]+]], 3, 4 ; CHECK: fadds 1, [[REG0]], [[REG1]] @@ -22,7 +22,7 @@ define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) { define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) { ; CHECK-LABEL: reassociate_adds2: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK: fadds [[REG0:[0-9]+]], 1, 2 ; CHECK: fadds [[REG1:[0-9]+]], 3, 4 ; CHECK: fadds 1, [[REG0]], [[REG1]] @@ -36,7 +36,7 @@ define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) { define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) { ; CHECK-LABEL: reassociate_adds3: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK: fadds [[REG0:[0-9]+]], 1, 2 ; CHECK: fadds [[REG1:[0-9]+]], 3, 4 ; CHECK: fadds 1, [[REG0]], [[REG1]] @@ -50,7 +50,7 @@ define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) { define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) { ; CHECK-LABEL: reassociate_adds4: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK: fadds [[REG0:[0-9]+]], 1, 2 ; CHECK: fadds [[REG1:[0-9]+]], 3, 4 ; CHECK: fadds 1, [[REG0]], [[REG1]] @@ -67,7 +67,7 @@ define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) { define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) { ; CHECK-LABEL: reassociate_adds5: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK: fadds [[REG12:[0-9]+]], 5, 6 ; CHECK: fadds [[REG0:[0-9]+]], 1, 2 ; CHECK: fadds [[REG11:[0-9]+]], 3, 4 @@ -91,7 +91,7 @@ define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, floa define <4 x float> @vector_reassociate_adds1(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { ; CHECK-LABEL: vector_reassociate_adds1: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 ; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 ; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] @@ -108,7 +108,7 @@ define <4 x float> @vector_reassociate_adds1(<4 x float> %x0, <4 x float> %x1, < define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { ; CHECK-LABEL: vector_reassociate_adds2: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 ; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 ; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] @@ -125,7 +125,7 @@ define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, < define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { ; CHECK-LABEL: vector_reassociate_adds3: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 ; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 ; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] @@ -142,7 +142,7 @@ define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, < define <4 x float> @vector_reassociate_adds4(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { ; CHECK-LABEL: vector_reassociate_adds4: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 ; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 ; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] diff --git a/test/CodeGen/PowerPC/mature-mc-support.ll b/test/CodeGen/PowerPC/mature-mc-support.ll index 543877d60cfae..eab05157ca271 100644 --- a/test/CodeGen/PowerPC/mature-mc-support.ll +++ b/test/CodeGen/PowerPC/mature-mc-support.ll @@ -4,26 +4,26 @@ ; so we only test that -filetype=obj tries to parse the assembly. ; FIXME: PowerPC doesn't appear to support -filetype=obj for ppc64le -; SKIP: not llc -march=ppc32 < %s > /dev/null 2> %t1 +; SKIP: not llc -mtriple=ppc32-- < %s > /dev/null 2> %t1 ; SKIP: FileCheck %s < %t1 -; RUN: not llc -march=ppc32 -filetype=obj < %s > /dev/null 2> %t2 +; RUN: not llc -mtriple=ppc32-- -filetype=obj < %s > /dev/null 2> %t2 ; RUN: FileCheck %s < %t2 ; Test that we don't try to produce COFF for ppc. ; RUN: not llc -mtriple=powerpc-mingw32 -filetype=obj < %s > /dev/null 2> %t2 ; RUN: FileCheck %s < %t2 -; SKIP: not llc -march=ppc64 < %s > /dev/null 2> %t3 +; SKIP: not llc -mtriple=ppc64-- < %s > /dev/null 2> %t3 ; SKIP: FileCheck %s < %t3 -; RUN: not llc -march=ppc64 -filetype=obj < %s > /dev/null 2> %t4 +; RUN: not llc -mtriple=ppc64-- -filetype=obj < %s > /dev/null 2> %t4 ; RUN: FileCheck %s < %t4 -; SKIP: not llc -march=ppc64le < %s > /dev/null 2> %t5 +; SKIP: not llc -mtriple=ppc64--le < %s > /dev/null 2> %t5 ; SKIP: FileCheck %s < %t5 -; SKIP: not llc -march=ppc64le -filetype=obj < %s > /dev/null 2> %t6 +; SKIP: not llc -mtriple=ppc64--le -filetype=obj < %s > /dev/null 2> %t6 ; SKIP: FileCheck %s < %t6 module asm " .this_directive_is_very_unlikely_to_exist" diff --git a/test/CodeGen/PowerPC/mcount-insertion.ll b/test/CodeGen/PowerPC/mcount-insertion.ll index 04e8571d6f4bb..cbb7947be2198 100644 --- a/test/CodeGen/PowerPC/mcount-insertion.ll +++ b/test/CodeGen/PowerPC/mcount-insertion.ll @@ -1,16 +1,46 @@ -; RUN: llc < %s | FileCheck %s +; RUN: opt -ee-instrument < %s | opt -inline | llc | FileCheck %s + +; The run-line mimics how Clang might run the instrumentation passes. + target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-bgq-linux" -define void @test1() #0 { + +define void @leaf_function() #0 { entry: ret void -; CHECK-LABEL: @test1 +; CHECK-LABEL: leaf_function: ; CHECK: bl mcount -; CHECK-NOT: mcount +; CHECK-NOT: bl +; CHECK: bl __cyg_profile_func_enter +; CHECK-NOT: bl +; CHECK: bl __cyg_profile_func_exit +; CHECK-NOT: bl ; CHECK: blr } -attributes #0 = { "counting-function"="mcount" } +define void @root_function() #0 { +entry: + call void @leaf_function() + ret void + +; CHECK-LABEL: root_function: +; CHECK: bl mcount +; CHECK-NOT: bl +; CHECK: bl __cyg_profile_func_enter +; CHECK-NOT: bl + +; Entry and exit calls, inlined from @leaf_function() +; CHECK: bl __cyg_profile_func_enter +; CHECK-NOT: bl +; CHECK: bl __cyg_profile_func_exit +; CHECK-NOT: bl + +; CHECK: bl __cyg_profile_func_exit +; CHECK-NOT: bl +; CHECK: blr +} + +attributes #0 = { "instrument-function-entry-inlined"="mcount" "instrument-function-entry"="__cyg_profile_func_enter" "instrument-function-exit"="__cyg_profile_func_exit" } diff --git a/test/CodeGen/PowerPC/mem-rr-addr-mode.ll b/test/CodeGen/PowerPC/mem-rr-addr-mode.ll index 26c3cc881b392..e8c12cc36bda5 100644 --- a/test/CodeGen/PowerPC/mem-rr-addr-mode.ll +++ b/test/CodeGen/PowerPC/mem-rr-addr-mode.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | grep li.*16 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | not grep addi +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | grep li.*16 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | not grep addi ; Codegen lvx (R+16) as t = li 16, lvx t,R ; This shares the 16 between the two loads. diff --git a/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll index 059665adc351f..3bfc0de1b8724 100644 --- a/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll +++ b/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" @@ -17,7 +17,7 @@ declare signext i32 @memcmp(i8* nocapture, i8* nocapture, i64) local_unnamed_add ; Check 4 bytes - requires 1 load for each param. define signext i32 @zeroEqualityTest02(i8* %x, i8* %y) { ; CHECK-LABEL: zeroEqualityTest02: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: xor 3, 3, 4 @@ -34,12 +34,12 @@ define signext i32 @zeroEqualityTest02(i8* %x, i8* %y) { ; Check 16 bytes - requires 2 loads for each param (or use vectors?). define signext i32 @zeroEqualityTest01(i8* %x, i8* %y) { ; CHECK-LABEL: zeroEqualityTest01: -; CHECK: # BB#0: # %loadbb +; CHECK: # %bb.0: ; CHECK-NEXT: ld 5, 0(3) ; CHECK-NEXT: ld 6, 0(4) ; CHECK-NEXT: cmpld 5, 6 ; CHECK-NEXT: bne 0, .LBB1_2 -; CHECK-NEXT: # BB#1: # %loadbb1 +; CHECK-NEXT: # %bb.1: # %loadbb1 ; CHECK-NEXT: ld 3, 8(3) ; CHECK-NEXT: ld 4, 8(4) ; CHECK-NEXT: cmpld 3, 4 @@ -47,8 +47,6 @@ define signext i32 @zeroEqualityTest01(i8* %x, i8* %y) { ; CHECK-NEXT: beq 0, .LBB1_3 ; CHECK-NEXT: .LBB1_2: # %res_block ; CHECK-NEXT: li 3, 1 -; CHECK-NEXT: clrldi 3, 3, 32 -; CHECK-NEXT: blr ; CHECK-NEXT: .LBB1_3: # %endblock ; CHECK-NEXT: clrldi 3, 3, 32 ; CHECK-NEXT: blr @@ -61,17 +59,17 @@ define signext i32 @zeroEqualityTest01(i8* %x, i8* %y) { ; Check 7 bytes - requires 3 loads for each param. define signext i32 @zeroEqualityTest03(i8* %x, i8* %y) { ; CHECK-LABEL: zeroEqualityTest03: -; CHECK: # BB#0: # %loadbb +; CHECK: # %bb.0: ; CHECK-NEXT: lwz 5, 0(3) ; CHECK-NEXT: lwz 6, 0(4) ; CHECK-NEXT: cmplw 5, 6 ; CHECK-NEXT: bne 0, .LBB2_3 -; CHECK-NEXT: # BB#1: # %loadbb1 +; CHECK-NEXT: # %bb.1: # %loadbb1 ; CHECK-NEXT: lhz 5, 4(3) ; CHECK-NEXT: lhz 6, 4(4) ; CHECK-NEXT: cmplw 5, 6 ; CHECK-NEXT: bne 0, .LBB2_3 -; CHECK-NEXT: # BB#2: # %loadbb2 +; CHECK-NEXT: # %bb.2: # %loadbb2 ; CHECK-NEXT: lbz 3, 6(3) ; CHECK-NEXT: lbz 4, 6(4) ; CHECK-NEXT: cmplw 3, 4 @@ -79,8 +77,6 @@ define signext i32 @zeroEqualityTest03(i8* %x, i8* %y) { ; CHECK-NEXT: beq 0, .LBB2_4 ; CHECK-NEXT: .LBB2_3: # %res_block ; CHECK-NEXT: li 3, 1 -; CHECK-NEXT: clrldi 3, 3, 32 -; CHECK-NEXT: blr ; CHECK-NEXT: .LBB2_4: # %endblock ; CHECK-NEXT: clrldi 3, 3, 32 ; CHECK-NEXT: blr @@ -93,7 +89,7 @@ define signext i32 @zeroEqualityTest03(i8* %x, i8* %y) { ; Validate with > 0 define signext i32 @zeroEqualityTest04() { ; CHECK-LABEL: zeroEqualityTest04: -; CHECK: # BB#0: # %loadbb +; CHECK: # %bb.0: ; CHECK-NEXT: addis 3, 2, .LzeroEqualityTest02.buffer1@toc@ha ; CHECK-NEXT: addis 4, 2, .LzeroEqualityTest02.buffer2@toc@ha ; CHECK-NEXT: addi 6, 3, .LzeroEqualityTest02.buffer1@toc@l @@ -102,7 +98,7 @@ define signext i32 @zeroEqualityTest04() { ; CHECK-NEXT: ldbrx 4, 0, 5 ; CHECK-NEXT: cmpld 3, 4 ; CHECK-NEXT: bne 0, .LBB3_2 -; CHECK-NEXT: # BB#1: # %loadbb1 +; CHECK-NEXT: # %bb.1: # %loadbb1 ; CHECK-NEXT: li 4, 8 ; CHECK-NEXT: ldbrx 3, 6, 4 ; CHECK-NEXT: ldbrx 4, 5, 4 @@ -115,10 +111,10 @@ define signext i32 @zeroEqualityTest04() { ; CHECK-NEXT: li 12, -1 ; CHECK-NEXT: isel 5, 12, 11, 0 ; CHECK-NEXT: .LBB3_3: # %endblock -; CHECK-NEXT: cmpwi 5, 1 -; CHECK-NEXT: li 3, 0 -; CHECK-NEXT: li 4, 1 -; CHECK-NEXT: isel 3, 4, 3, 0 +; CHECK-NEXT: extsw 3, 5 +; CHECK-NEXT: neg 3, 3 +; CHECK-NEXT: rldicl 3, 3, 1, 63 +; CHECK-NEXT: xori 3, 3, 1 ; CHECK-NEXT: blr %call = tail call signext i32 @memcmp(i8* bitcast ([4 x i32]* @zeroEqualityTest02.buffer1 to i8*), i8* bitcast ([4 x i32]* @zeroEqualityTest02.buffer2 to i8*), i64 16) %not.cmp = icmp slt i32 %call, 1 @@ -129,7 +125,7 @@ define signext i32 @zeroEqualityTest04() { ; Validate with < 0 define signext i32 @zeroEqualityTest05() { ; CHECK-LABEL: zeroEqualityTest05: -; CHECK: # BB#0: # %loadbb +; CHECK: # %bb.0: ; CHECK-NEXT: addis 3, 2, .LzeroEqualityTest03.buffer1@toc@ha ; CHECK-NEXT: addis 4, 2, .LzeroEqualityTest03.buffer2@toc@ha ; CHECK-NEXT: addi 6, 3, .LzeroEqualityTest03.buffer1@toc@l @@ -138,7 +134,7 @@ define signext i32 @zeroEqualityTest05() { ; CHECK-NEXT: ldbrx 4, 0, 5 ; CHECK-NEXT: cmpld 3, 4 ; CHECK-NEXT: bne 0, .LBB4_2 -; CHECK-NEXT: # BB#1: # %loadbb1 +; CHECK-NEXT: # %bb.1: # %loadbb1 ; CHECK-NEXT: li 4, 8 ; CHECK-NEXT: ldbrx 3, 6, 4 ; CHECK-NEXT: ldbrx 4, 5, 4 @@ -164,7 +160,7 @@ define signext i32 @zeroEqualityTest05() { ; Validate with memcmp()?: define signext i32 @equalityFoldTwoConstants() { ; CHECK-LABEL: equalityFoldTwoConstants: -; CHECK: # BB#0: # %endblock +; CHECK: # %bb.0: # %endblock ; CHECK-NEXT: li 3, 1 ; CHECK-NEXT: blr %call = tail call signext i32 @memcmp(i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer1 to i8*), i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer2 to i8*), i64 16) @@ -175,13 +171,13 @@ define signext i32 @equalityFoldTwoConstants() { define signext i32 @equalityFoldOneConstant(i8* %X) { ; CHECK-LABEL: equalityFoldOneConstant: -; CHECK: # BB#0: # %loadbb -; CHECK-NEXT: li 4, 1 -; CHECK-NEXT: ld 5, 0(3) -; CHECK-NEXT: sldi 4, 4, 32 -; CHECK-NEXT: cmpld 5, 4 +; CHECK: # %bb.0: +; CHECK-NEXT: li 5, 1 +; CHECK-NEXT: ld 4, 0(3) +; CHECK-NEXT: sldi 5, 5, 32 +; CHECK-NEXT: cmpld 4, 5 ; CHECK-NEXT: bne 0, .LBB6_2 -; CHECK-NEXT: # BB#1: # %loadbb1 +; CHECK-NEXT: # %bb.1: # %loadbb1 ; CHECK-NEXT: li 4, 3 ; CHECK-NEXT: ld 3, 8(3) ; CHECK-NEXT: sldi 4, 4, 32 @@ -203,13 +199,11 @@ define signext i32 @equalityFoldOneConstant(i8* %X) { define i1 @length2_eq_nobuiltin_attr(i8* %X, i8* %Y) { ; CHECK-LABEL: length2_eq_nobuiltin_attr: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: mflr 0 ; CHECK-NEXT: std 0, 16(1) ; CHECK-NEXT: stdu 1, -32(1) -; CHECK-NEXT: .Lcfi0: ; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: .Lcfi1: ; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: li 5, 2 ; CHECK-NEXT: bl memcmp diff --git a/test/CodeGen/PowerPC/mem_update.ll b/test/CodeGen/PowerPC/mem_update.ll index 6d4a787ce0273..e02c639c1fdb3 100644 --- a/test/CodeGen/PowerPC/mem_update.ll +++ b/test/CodeGen/PowerPC/mem_update.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \ ; RUN: not grep addi -; RUN: llc -verify-machineinstrs -code-model=small < %s -march=ppc64 | \ +; RUN: llc -verify-machineinstrs -code-model=small < %s -mtriple=ppc64-- | \ ; RUN: not grep addi @Glob = global i64 4 diff --git a/test/CodeGen/PowerPC/memcmp.ll b/test/CodeGen/PowerPC/memcmp.ll index fbaaa8bb74c98..4aa5b400dd7c4 100644 --- a/test/CodeGen/PowerPC/memcmp.ll +++ b/test/CodeGen/PowerPC/memcmp.ll @@ -3,14 +3,17 @@ define signext i32 @memcmp8(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { ; CHECK-LABEL: memcmp8: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: ldbrx 3, 0, 3 ; CHECK-NEXT: ldbrx 4, 0, 4 -; CHECK-NEXT: li 5, 1 -; CHECK-NEXT: li 12, -1 -; CHECK-NEXT: cmpld 3, 4 -; CHECK-NEXT: isel 3, 12, 5, 0 -; CHECK-NEXT: isel 3, 0, 3, 2 +; CHECK-NEXT: subfc 5, 3, 4 +; CHECK-NEXT: subfe 5, 4, 4 +; CHECK-NEXT: subfc 4, 4, 3 +; CHECK-NEXT: subfe 3, 3, 3 +; CHECK-NEXT: neg 4, 5 +; CHECK-NEXT: neg 3, 3 +; CHECK-NEXT: subf 3, 3, 4 +; CHECK-NEXT: extsw 3, 3 ; CHECK-NEXT: blr %t0 = bitcast i32* %buffer1 to i8* %t1 = bitcast i32* %buffer2 to i8* @@ -20,14 +23,15 @@ define signext i32 @memcmp8(i32* nocapture readonly %buffer1, i32* nocapture rea define signext i32 @memcmp4(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { ; CHECK-LABEL: memcmp4: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: lwbrx 3, 0, 3 ; CHECK-NEXT: lwbrx 4, 0, 4 -; CHECK-NEXT: li 5, 1 -; CHECK-NEXT: li 12, -1 -; CHECK-NEXT: cmplw 3, 4 -; CHECK-NEXT: isel 3, 12, 5, 0 -; CHECK-NEXT: isel 3, 0, 3, 2 +; CHECK-NEXT: sub 5, 4, 3 +; CHECK-NEXT: sub 3, 3, 4 +; CHECK-NEXT: rldicl 4, 5, 1, 63 +; CHECK-NEXT: rldicl 3, 3, 1, 63 +; CHECK-NEXT: subf 3, 3, 4 +; CHECK-NEXT: extsw 3, 3 ; CHECK-NEXT: blr %t0 = bitcast i32* %buffer1 to i8* %t1 = bitcast i32* %buffer2 to i8* @@ -37,14 +41,11 @@ define signext i32 @memcmp4(i32* nocapture readonly %buffer1, i32* nocapture rea define signext i32 @memcmp2(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { ; CHECK-LABEL: memcmp2: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: lhbrx 3, 0, 3 ; CHECK-NEXT: lhbrx 4, 0, 4 -; CHECK-NEXT: li 5, 1 -; CHECK-NEXT: li 12, -1 -; CHECK-NEXT: cmplw 3, 4 -; CHECK-NEXT: isel 3, 12, 5, 0 -; CHECK-NEXT: isel 3, 0, 3, 2 +; CHECK-NEXT: subf 3, 4, 3 +; CHECK-NEXT: extsw 3, 3 ; CHECK-NEXT: blr %t0 = bitcast i32* %buffer1 to i8* %t1 = bitcast i32* %buffer2 to i8* @@ -54,14 +55,11 @@ define signext i32 @memcmp2(i32* nocapture readonly %buffer1, i32* nocapture rea define signext i32 @memcmp1(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { ; CHECK-LABEL: memcmp1: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: lbz 3, 0(3) ; CHECK-NEXT: lbz 4, 0(4) -; CHECK-NEXT: li 5, 1 -; CHECK-NEXT: li 12, -1 -; CHECK-NEXT: cmplw 3, 4 -; CHECK-NEXT: isel 3, 12, 5, 0 -; CHECK-NEXT: isel 3, 0, 3, 2 +; CHECK-NEXT: subf 3, 4, 3 +; CHECK-NEXT: extsw 3, 3 ; CHECK-NEXT: blr %t0 = bitcast i32* %buffer1 to i8* %t1 = bitcast i32* %buffer2 to i8* diff --git a/test/CodeGen/PowerPC/memcmpIR.ll b/test/CodeGen/PowerPC/memcmpIR.ll index 55f48ad19a636..9888519d8b612 100644 --- a/test/CodeGen/PowerPC/memcmpIR.ll +++ b/test/CodeGen/PowerPC/memcmpIR.ll @@ -59,20 +59,22 @@ define signext i32 @test2(i32* nocapture readonly %buffer1, i32* nocapture reado ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i32, i32* ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD1]]) ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD2]]) - ; CHECK-NEXT: [[CMP1:%[0-9]+]] = icmp ne i32 [[BSWAP1]], [[BSWAP2]] + ; CHECK-NEXT: [[CMP1:%[0-9]+]] = icmp ugt i32 [[BSWAP1]], [[BSWAP2]] ; CHECK-NEXT: [[CMP2:%[0-9]+]] = icmp ult i32 [[BSWAP1]], [[BSWAP2]] - ; CHECK-NEXT: [[SELECT1:%[0-9]+]] = select i1 [[CMP2]], i32 -1, i32 1 - ; CHECK-NEXT: [[SELECT2:%[0-9]+]] = select i1 [[CMP1]], i32 [[SELECT1]], i32 0 - ; CHECK-NEXT: ret i32 [[SELECT2]] + ; CHECK-NEXT: [[Z1:%[0-9]+]] = zext i1 [[CMP1]] to i32 + ; CHECK-NEXT: [[Z2:%[0-9]+]] = zext i1 [[CMP2]] to i32 + ; CHECK-NEXT: [[SUB:%[0-9]+]] = sub i32 [[Z1]], [[Z2]] + ; CHECK-NEXT: ret i32 [[SUB]] ; CHECK-BE-LABEL: @test2( ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i32, i32* ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i32, i32* - ; CHECK-BE-NEXT: [[CMP1:%[0-9]+]] = icmp ne i32 [[LOAD1]], [[LOAD2]] + ; CHECK-BE-NEXT: [[CMP1:%[0-9]+]] = icmp ugt i32 [[LOAD1]], [[LOAD2]] ; CHECK-BE-NEXT: [[CMP2:%[0-9]+]] = icmp ult i32 [[LOAD1]], [[LOAD2]] - ; CHECK-BE-NEXT: [[SELECT1:%[0-9]+]] = select i1 [[CMP2]], i32 -1, i32 1 - ; CHECK-BE-NEXT: [[SELECT2:%[0-9]+]] = select i1 [[CMP1]], i32 [[SELECT1]], i32 0 - ; CHECK-BE-NEXT: ret i32 [[SELECT2]] + ; CHECK-BE-NEXT: [[Z1:%[0-9]+]] = zext i1 [[CMP1]] to i32 + ; CHECK-BE-NEXT: [[Z2:%[0-9]+]] = zext i1 [[CMP2]] to i32 + ; CHECK-BE-NEXT: [[SUB:%[0-9]+]] = sub i32 [[Z1]], [[Z2]] + ; CHECK-BE-NEXT: ret i32 [[SUB]] entry: %0 = bitcast i32* %buffer1 to i8* diff --git a/test/CodeGen/PowerPC/mtvsrdd.ll b/test/CodeGen/PowerPC/mtvsrdd.ll index 1d6a3553b2a1f..a4a3d829f2d3f 100644 --- a/test/CodeGen/PowerPC/mtvsrdd.ll +++ b/test/CodeGen/PowerPC/mtvsrdd.ll @@ -1,5 +1,5 @@ -; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \ -; RUN: < %s | FileCheck %s +; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ +; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s ; This test case checks r0 is used as constant 0 in instruction mtvsrdd. diff --git a/test/CodeGen/PowerPC/mul-neg-power-2.ll b/test/CodeGen/PowerPC/mul-neg-power-2.ll index 5290b0532a966..81e8d6c376915 100644 --- a/test/CodeGen/PowerPC/mul-neg-power-2.ll +++ b/test/CodeGen/PowerPC/mul-neg-power-2.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep mul +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep mul define i32 @test1(i32 %a) { %tmp.1 = mul i32 %a, -2 ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/mul-with-overflow.ll b/test/CodeGen/PowerPC/mul-with-overflow.ll index 85b07fc3298c7..1c0dbc5a19277 100644 --- a/test/CodeGen/PowerPC/mul-with-overflow.ll +++ b/test/CodeGen/PowerPC/mul-with-overflow.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b) define zeroext i1 @a(i32 %x) nounwind { diff --git a/test/CodeGen/PowerPC/mulhs.ll b/test/CodeGen/PowerPC/mulhs.ll index 8e303d3c7753c..b52384f680458 100644 --- a/test/CodeGen/PowerPC/mulhs.ll +++ b/test/CodeGen/PowerPC/mulhs.ll @@ -1,5 +1,5 @@ ; All of these ands and shifts should be folded into rlwimi's -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -o %t +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t ; RUN: not grep mulhwu %t ; RUN: not grep srawi %t ; RUN: not grep add %t diff --git a/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll b/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll index 57345df4d2f1a..9bbec5b241883 100644 --- a/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll +++ b/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -no-integrated-as +; RUN: llc -verify-machineinstrs < %s -no-integrated-as ; ModuleID = 'mult-alt-generic.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" -target triple = "powerpc" +target triple = "powerpc--" @mout0 = common global i32 0, align 4 @min1 = common global i32 0, align 4 diff --git a/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll b/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll index aefcaf1254e38..1fa9c0d3c1302 100644 --- a/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll +++ b/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -no-integrated-as +; RUN: llc -verify-machineinstrs < %s -no-integrated-as ; ModuleID = 'mult-alt-generic.c' target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" -target triple = "powerpc64" +target triple = "powerpc64--" @mout0 = common global i32 0, align 4 @min1 = common global i32 0, align 4 diff --git a/test/CodeGen/PowerPC/neg.ll b/test/CodeGen/PowerPC/neg.ll index 3828c23c9ad9a..37d2897d01647 100644 --- a/test/CodeGen/PowerPC/neg.ll +++ b/test/CodeGen/PowerPC/neg.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep neg +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep neg define i32 @test(i32 %X) { %Y = sub i32 0, %X ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/negate-i1.ll b/test/CodeGen/PowerPC/negate-i1.ll index c6a7867fe9dbc..a56048d67a873 100644 --- a/test/CodeGen/PowerPC/negate-i1.ll +++ b/test/CodeGen/PowerPC/negate-i1.ll @@ -4,7 +4,7 @@ define i32 @select_i32_neg1_or_0(i1 %a) { ; CHECK-LABEL: select_i32_neg1_or_0: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: clrldi 3, 3, 63 ; CHECK-NEXT: neg 3, 3 ; CHECK-NEXT: blr @@ -15,7 +15,7 @@ define i32 @select_i32_neg1_or_0(i1 %a) { define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) { ; CHECK-LABEL: select_i32_neg1_or_0_zeroext: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: neg 3, 3 ; CHECK-NEXT: blr ; diff --git a/test/CodeGen/PowerPC/no-pref-jumps.ll b/test/CodeGen/PowerPC/no-pref-jumps.ll index 71f79409820a6..1c22d8b790369 100644 --- a/test/CodeGen/PowerPC/no-pref-jumps.ll +++ b/test/CodeGen/PowerPC/no-pref-jumps.ll @@ -1,3 +1,4 @@ +; XFAIL: * ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -11,9 +12,13 @@ entry: br i1 %or.cond, label %if.then, label %if.else ; CHECK-LABEL: @foo -; CHECK: cmpwi -; CHECK: cmpwi -; CHECK: cror +; CHECK: li +; CHECK: li +; CHECK: sub +; CHECK: sub +; CHECK: rldicl +; CHECK: rldicl +; CHECK: or. ; CHECK: blr if.then: ; preds = %entry diff --git a/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir index bab2ff22a4cbd..ed6ceec8d4082 100644 --- a/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir +++ b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir @@ -3,11 +3,11 @@ --- | target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" - + @d = global i32 15, align 4 @b = global i32* @d, align 8 @a = common global i32 0, align 4 - + ; Function Attrs: nounwind define signext i32 @main() #0 { entry: @@ -31,7 +31,7 @@ store i32 %or.1, i32* %0, align 4 ret i32 %or.1 } - + attributes #0 = { nounwind "target-cpu"="ppc64" } ... @@ -40,7 +40,7 @@ name: main alignment: 2 exposesReturnsTwice: false tracksRegLiveness: true -registers: +registers: - { id: 0, class: g8rc_and_g8rc_nox0 } - { id: 1, class: g8rc_and_g8rc_nox0 } - { id: 2, class: gprc } @@ -52,7 +52,7 @@ registers: - { id: 8, class: gprc } - { id: 9, class: gprc } - { id: 10, class: g8rc } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -76,9 +76,9 @@ body: | %3 = LI 0 %4 = RLWIMI %3, killed %2, 0, 0, 31 ; CHECK-LABEL: name: main - ; CHECK: %[[REG1:[0-9]+]] = LI 0 - ; CHECK: %[[REG2:[0-9]+]] = COPY %[[REG1]] - ; CHECK: %[[REG2]] = RLWIMI %[[REG2]], killed %2, 0, 0, 31 + ; CHECK: %[[REG1:[0-9]+]]:gprc = LI 0 + ; CHECK: %[[REG2:[0-9]+]]:gprc = COPY %[[REG1]] + ; CHECK: %[[REG2]]:gprc = RLWIMI %[[REG2]], killed %2, 0, 0, 31 %8 = RLWIMI %3, %4, 0, 0, 31 STW %4, 0, %1 :: (store 4 into %ir.0) %10 = EXTSW_32_64 %8 diff --git a/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll b/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll index 2aeb0e1f71f91..c9c9f6a8958fb 100644 --- a/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll +++ b/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll @@ -1,4 +1,5 @@ ; RUN: llc -verify-machineinstrs -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64le-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s ; CHECK-LABEL: fn1 define signext i32 @fn1(i32 %baz) { @@ -6,12 +7,12 @@ define signext i32 @fn1(i32 %baz) { %2 = zext i32 %1 to i64 %3 = shl i64 %2, 48 %4 = ashr exact i64 %3, 48 -; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead>; +; CHECK: ANDIo8 killed {{[^,]+}}, 65520, implicit-def dead %cr0; ; CHECK: CMPLDI ; CHECK: BCC -; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def>; -; CHECK: COPY %CR0 +; CHECK: ANDIo8 {{[^,]+}}, 65520, implicit-def %cr0; +; CHECK: COPY %cr0 ; CHECK: BCC %5 = icmp eq i64 %4, 0 br i1 %5, label %foo, label %bar @@ -25,9 +26,9 @@ bar: ; CHECK-LABEL: fn2 define signext i32 @fn2(i64 %a, i64 %b) { -; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %CR0<imp-def>; -; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0 -; CHECK: BCC 12, [[CREG]]<kill> +; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, implicit-def %cr0; +; CHECK: [[CREG:[^, ]+]]:crrc = COPY killed %cr0 +; CHECK: BCC 12, killed [[CREG]] %1 = or i64 %b, %a %2 = icmp sgt i64 %1, -1 br i1 %2, label %foo, label %bar @@ -41,9 +42,9 @@ bar: ; CHECK-LABEL: fn3 define signext i32 @fn3(i32 %a) { -; CHECK: ANDIo {{[^, ]+}}, 10, %CR0<imp-def>; -; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0 -; CHECK: BCC 76, [[CREG]]<kill> +; CHECK: ANDIo killed {{[%0-9]+}}, 10, implicit-def %cr0; +; CHECK: [[CREG:[^, ]+]]:crrc = COPY %cr0 +; CHECK: BCC 76, killed [[CREG]] %1 = and i32 %a, 10 %2 = icmp ne i32 %1, 0 br i1 %2, label %foo, label %bar @@ -54,3 +55,83 @@ foo: bar: ret i32 0 } + +; This test case confirms that a record-form instruction is +; generated even if the branch has a static branch hint. + +; CHECK-LABEL: fn4 +define i64 @fn4(i64 %a, i64 %b) { +; CHECK: ADD8o +; CHECK-NOT: CMP +; CHECK: BCC 71 + +entry: + %add = add nsw i64 %b, %a + %cmp = icmp eq i64 %add, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: + tail call void @exit(i32 signext 0) #3 + unreachable + +if.end: + ret i64 %add +} + +declare void @exit(i32 signext) + +; Since %v1 and %v2 are zero-extended 32-bit values, %1 is also zero-extended. +; In this case, we want to use ORo instead of OR + CMPLWI. + +; CHECK-LABEL: fn5 +define zeroext i32 @fn5(i32* %p1, i32* %p2) { +; CHECK: ORo +; CHECK-NOT: CMP +; CHECK: BCC + %v1 = load i32, i32* %p1 + %v2 = load i32, i32* %p2 + %1 = or i32 %v1, %v2 + %2 = icmp eq i32 %1, 0 + br i1 %2, label %foo, label %bar + +foo: + ret i32 1 + +bar: + ret i32 0 +} + +; This test confirms record-form instructions are emitted for comparison +; against a non-zero value. + +; CHECK-LABEL: fn6 +define i8* @fn6(i8* readonly %p) { +; CHECK: LBZU +; CHECK: EXTSBo +; CHECK-NOT: CMP +; CHECK: BCC +; CHECK: LBZU +; CHECK: EXTSBo +; CHECK-NOT: CMP +; CHECK: BCC + +entry: + %incdec.ptr = getelementptr inbounds i8, i8* %p, i64 -1 + %0 = load i8, i8* %incdec.ptr + %cmp = icmp sgt i8 %0, -1 + br i1 %cmp, label %out, label %if.end + +if.end: + %incdec.ptr2 = getelementptr inbounds i8, i8* %p, i64 -2 + %1 = load i8, i8* %incdec.ptr2 + %cmp4 = icmp sgt i8 %1, -1 + br i1 %cmp4, label %out, label %cleanup + +out: + %p.addr.0 = phi i8* [ %incdec.ptr, %entry ], [ %incdec.ptr2, %if.end ] + br label %cleanup + +cleanup: + %retval.0 = phi i8* [ %p.addr.0, %out ], [ null, %if.end ] + ret i8* %retval.0 +} diff --git a/test/CodeGen/PowerPC/opt-li-add-to-addi.ll b/test/CodeGen/PowerPC/opt-li-add-to-addi.ll new file mode 100644 index 0000000000000..43d8445b7cfaf --- /dev/null +++ b/test/CodeGen/PowerPC/opt-li-add-to-addi.ll @@ -0,0 +1,60 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s + +define i64 @testOptimizeLiAddToAddi(i64 %a) { +; CHECK-LABEL: testOptimizeLiAddToAddi: +; CHECK: addi 3, 30, 2444 +; CHECK: bl callv +; CHECK: addi 3, 30, 234 +; CHECK: bl call +; CHECK: blr +entry: + %cmp = icmp sgt i64 %a, 33 + br i1 %cmp, label %if.then, label %if.end + +if.then: + tail call void bitcast (void (...)* @callv to void ()*)() + br label %if.end + +if.end: + %add.0 = phi i64 [ 234, %if.then ], [ 2444, %entry ] + %add2 = add nsw i64 %add.0, %a + %call = tail call i64 @call(i64 %add2) + ret i64 %call +} + +define i64 @testThreePhiIncomings(i64 %a) { +; CHECK-LABEL: testThreePhiIncomings: +; CHECK: bl callv +; CHECK: addi 3, 30, 234 +; CHECK: addi 3, 30, 2444 +; CHECK: bl callv +; CHECK: addi 3, 30, 345 +; CHECK: bl call +; CHECK: blr +entry: + %cmp = icmp slt i64 %a, 33 + br i1 %cmp, label %if.then, label %if.else + +if.then: + tail call void bitcast (void (...)* @callv to void ()*)() + br label %if.end4 + +if.else: + %cmp1 = icmp slt i64 %a, 55 + br i1 %cmp1, label %if.then2, label %if.end4 + +if.then2: + tail call void bitcast (void (...)* @callv to void ()*)() + br label %if.end4 + +if.end4: + %add.0 = phi i64 [ 234, %if.then ], [ 345, %if.then2 ], [ 2444, %if.else ] + %add5 = add nsw i64 %add.0, %a + %call = tail call i64 @call(i64 %add5) + ret i64 %call +} + +declare void @callv(...) + +declare i64 @call(i64) diff --git a/test/CodeGen/PowerPC/optcmp.ll b/test/CodeGen/PowerPC/optcmp.ll index a1921452d6206..acb5b4e6f67ce 100644 --- a/test/CodeGen/PowerPC/optcmp.ll +++ b/test/CodeGen/PowerPC/optcmp.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 | FileCheck %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -127,7 +127,7 @@ entry: ret i64 %conv1 ; CHECK: @foo2l -; CHECK: sld. 4, 3, 4 +; CHECK: sld 4, 3, 4 ; CHECK: std 4, 0(5) } diff --git a/test/CodeGen/PowerPC/ori_imm32.ll b/test/CodeGen/PowerPC/ori_imm32.ll new file mode 100644 index 0000000000000..5444a5bc7e65e --- /dev/null +++ b/test/CodeGen/PowerPC/ori_imm32.ll @@ -0,0 +1,96 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s + +define i64 @ori_test_a(i64 %a) { +entry: +; CHECK-LABEL: @ori_test_a +; CHECK-DAG: ori 3, 3, 65535 +; CHECK-DAG: oris 3, 3, 65535 +; CHECK-NEXT: blr + %or = or i64 %a, 4294967295 + ret i64 %or +} + +define i64 @ori_test_b(i64 %a) { +entry: +; CHECK-LABEL: @ori_test_b +; CHECK: or 3, 3, {{[0-9]+}} +; CHECK-NEXT: blr + %or = or i64 %a, 4294967296 + ret i64 %or +} + +define i64 @ori_test_c(i64 %a) { +entry: +; CHECK-LABEL: @ori_test_c +; CHECK: ori 3, 3, 65535 +; CHECK-NEXT: blr + %or = or i64 %a, 65535 + ret i64 %or +} + +define i64 @ori_test_d(i64 %a) { +entry: +; CHECK-LABEL: @ori_test_d +; CHECK: oris 3, 3, 1 +; CHECK-NEXT: blr + %or = or i64 %a, 65536 + ret i64 %or +} + +define zeroext i32 @ori_test_e(i32 zeroext %a) { +entry: +; CHECK-LABEL: @ori_test_e +; CHECK-DAG: ori 3, 3, 65535 +; CHECK-DAG: oris 3, 3, 255 +; CHECK-NEXT: blr + %or = or i32 %a, 16777215 + ret i32 %or +} + +define i64 @xori_test_a(i64 %a) { +entry: +; CHECK-LABEL: @xori_test_a +; CHECK-DAG: xori 3, 3, 65535 +; CHECK-DAG: xoris 3, 3, 65535 +; CHECK-NEXT: blr + %xor = xor i64 %a, 4294967295 + ret i64 %xor +} + +define i64 @xori_test_b(i64 %a) { +entry: +; CHECK-LABEL: @xori_test_b +; CHECK: xor 3, 3, {{[0-9]+}} +; CHECK-NEXT: blr + %xor = xor i64 %a, 4294967296 + ret i64 %xor +} + +define i64 @xori_test_c(i64 %a) { +entry: +; CHECK-LABEL: @xori_test_c +; CHECK: xori 3, 3, 65535 +; CHECK-NEXT: blr + %xor = xor i64 %a, 65535 + ret i64 %xor +} + +define i64 @xori_test_d(i64 %a) { +entry: +; CHECK-LABEL: @xori_test_d +; CHECK: xoris 3, 3, 1 +; CHECK-NEXT: blr + %xor = xor i64 %a, 65536 + ret i64 %xor +} + +define zeroext i32 @xori_test_e(i32 zeroext %a) { +entry: +; CHECK-LABEL: @xori_test_e +; CHECK-DAG: xori 3, 3, 65535 +; CHECK-DAG: xoris 3, 3, 255 +; CHECK-NEXT: blr + %xor = xor i32 %a, 16777215 + ret i32 %xor +} diff --git a/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll index f399b2584d0b1..3c705bb3e6c1b 100644 --- a/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll +++ b/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll @@ -328,7 +328,6 @@ entry: ; CHECK-LABEL: @getuc0 ; CHECK: mfvsrd 3, 34 ; CHECK: rldicl 3, 3, 8, 56 -; CHECK: clrldi 3, 3, 56 ; CHECK-LE-LABEL: @getuc0 ; CHECK-LE: mfvsrd 3, ; CHECK-LE: clrldi 3, 3, 56 @@ -342,11 +341,9 @@ entry: ; CHECK-LABEL: @getuc1 ; CHECK: mfvsrd 3, 34 ; CHECK: rldicl 3, 3, 16, 56 -; CHECK: clrldi 3, 3, 56 ; CHECK-LE-LABEL: @getuc1 ; CHECK-LE: mfvsrd 3, ; CHECK-LE: rldicl 3, 3, 56, 56 -; CHECK-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -357,11 +354,9 @@ entry: ; CHECK-LABEL: @getuc2 ; CHECK: mfvsrd 3, 34 ; CHECK: rldicl 3, 3, 24, 56 -; CHECK: clrldi 3, 3, 56 ; CHECK-LE-LABEL: @getuc2 ; CHECK-LE: mfvsrd 3, ; CHECK-LE: rldicl 3, 3, 48, 56 -; CHECK-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -372,11 +367,9 @@ entry: ; CHECK-LABEL: @getuc3 ; CHECK: mfvsrd 3, 34 ; CHECK: rldicl 3, 3, 32, 56 -; CHECK: clrldi 3, 3, 56 ; CHECK-LE-LABEL: @getuc3 ; CHECK-LE: mfvsrd 3, ; CHECK-LE: rldicl 3, 3, 40, 56 -; CHECK-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -387,11 +380,9 @@ entry: ; CHECK-LABEL: @getuc4 ; CHECK: mfvsrd 3, 34 ; CHECK: rldicl 3, 3, 40, 56 -; CHECK: clrldi 3, 3, 56 ; CHECK-LE-LABEL: @getuc4 ; CHECK-LE: mfvsrd 3, ; CHECK-LE: rldicl 3, 3, 32, 56 -; CHECK-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -402,11 +393,9 @@ entry: ; CHECK-LABEL: @getuc5 ; CHECK: mfvsrd 3, 34 ; CHECK: rldicl 3, 3, 48, 56 -; CHECK: clrldi 3, 3, 56 ; CHECK-LE-LABEL: @getuc5 ; CHECK-LE: mfvsrd 3, ; CHECK-LE: rldicl 3, 3, 24, 56 -; CHECK-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -417,11 +406,9 @@ entry: ; CHECK-LABEL: @getuc6 ; CHECK: mfvsrd 3, 34 ; CHECK: rldicl 3, 3, 56, 56 -; CHECK: clrldi 3, 3, 56 ; CHECK-LE-LABEL: @getuc6 ; CHECK-LE: mfvsrd 3, ; CHECK-LE: rldicl 3, 3, 16, 56 -; CHECK-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -435,7 +422,6 @@ entry: ; CHECK-LE-LABEL: @getuc7 ; CHECK-LE: mfvsrd 3, ; CHECK-LE: rldicl 3, 3, 8, 56 -; CHECK-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -446,7 +432,6 @@ entry: ; CHECK-LABEL: @getuc8 ; CHECK: mfvsrd 3, ; CHECK: rldicl 3, 3, 8, 56 -; CHECK: clrldi 3, 3, 56 ; CHECK-LE-LABEL: @getuc8 ; CHECK-LE: mfvsrd 3, 34 ; CHECK-LE: clrldi 3, 3, 56 @@ -460,11 +445,9 @@ entry: ; CHECK-LABEL: @getuc9 ; CHECK: mfvsrd 3, ; CHECK: rldicl 3, 3, 16, 56 -; CHECK: clrldi 3, 3, 56 ; CHECK-LE-LABEL: @getuc9 ; CHECK-LE: mfvsrd 3, 34 ; CHECK-LE: rldicl 3, 3, 56, 56 -; CHECK-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -475,11 +458,9 @@ entry: ; CHECK-LABEL: @getuc10 ; CHECK: mfvsrd 3, ; CHECK: rldicl 3, 3, 24, 56 -; CHECK: clrldi 3, 3, 56 ; CHECK-LE-LABEL: @getuc10 ; CHECK-LE: mfvsrd 3, 34 ; CHECK-LE: rldicl 3, 3, 48, 56 -; CHECK-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -490,11 +471,9 @@ entry: ; CHECK-LABEL: @getuc11 ; CHECK: mfvsrd 3, ; CHECK: rldicl 3, 3, 32, 56 -; CHECK: clrldi 3, 3, 56 ; CHECK-LE-LABEL: @getuc11 ; CHECK-LE: mfvsrd 3, 34 ; CHECK-LE: rldicl 3, 3, 40, 56 -; CHECK-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -505,11 +484,9 @@ entry: ; CHECK-LABEL: @getuc12 ; CHECK: mfvsrd 3, ; CHECK: rldicl 3, 3, 40, 56 -; CHECK: clrldi 3, 3, 56 ; CHECK-LE-LABEL: @getuc12 ; CHECK-LE: mfvsrd 3, 34 ; CHECK-LE: rldicl 3, 3, 32, 56 -; CHECK-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -520,11 +497,9 @@ entry: ; CHECK-LABEL: @getuc13 ; CHECK: mfvsrd 3, ; CHECK: rldicl 3, 3, 48, 56 -; CHECK: clrldi 3, 3, 56 ; CHECK-LE-LABEL: @getuc13 ; CHECK-LE: mfvsrd 3, 34 ; CHECK-LE: rldicl 3, 3, 24, 56 -; CHECK-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -535,11 +510,9 @@ entry: ; CHECK-LABEL: @getuc14 ; CHECK: mfvsrd 3, ; CHECK: rldicl 3, 3, 56, 56 -; CHECK: clrldi 3, 3, 56 ; CHECK-LE-LABEL: @getuc14 ; CHECK-LE: mfvsrd 3, 34 ; CHECK-LE: rldicl 3, 3, 16, 56 -; CHECK-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -553,7 +526,6 @@ entry: ; CHECK-LE-LABEL: @getuc15 ; CHECK-LE: mfvsrd 3, 34 ; CHECK-LE: rldicl 3, 3, 8, 56 -; CHECK-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -739,7 +711,6 @@ entry: ; CHECK-LABEL: @getus0 ; CHECK: mfvsrd 3, 34 ; CHECK: rldicl 3, 3, 16, 48 -; CHECK: clrldi 3, 3, 48 ; CHECK-LE-LABEL: @getus0 ; CHECK-LE: mfvsrd 3, ; CHECK-LE: clrldi 3, 3, 48 @@ -753,11 +724,9 @@ entry: ; CHECK-LABEL: @getus1 ; CHECK: mfvsrd 3, 34 ; CHECK: rldicl 3, 3, 32, 48 -; CHECK: clrldi 3, 3, 48 ; CHECK-LE-LABEL: @getus1 ; CHECK-LE: mfvsrd 3, ; CHECK-LE: rldicl 3, 3, 48, 48 -; CHECK-LE: clrldi 3, 3, 48 } ; Function Attrs: norecurse nounwind readnone @@ -768,11 +737,9 @@ entry: ; CHECK-LABEL: @getus2 ; CHECK: mfvsrd 3, 34 ; CHECK: rldicl 3, 3, 48, 48 -; CHECK: clrldi 3, 3, 48 ; CHECK-LE-LABEL: @getus2 ; CHECK-LE: mfvsrd 3, ; CHECK-LE: rldicl 3, 3, 32, 48 -; CHECK-LE: clrldi 3, 3, 48 } ; Function Attrs: norecurse nounwind readnone @@ -786,7 +753,6 @@ entry: ; CHECK-LE-LABEL: @getus3 ; CHECK-LE: mfvsrd 3, ; CHECK-LE: rldicl 3, 3, 16, 48 -; CHECK-LE: clrldi 3, 3, 48 } ; Function Attrs: norecurse nounwind readnone @@ -797,7 +763,6 @@ entry: ; CHECK-LABEL: @getus4 ; CHECK: mfvsrd 3, ; CHECK: rldicl 3, 3, 16, 48 -; CHECK: clrldi 3, 3, 48 ; CHECK-LE-LABEL: @getus4 ; CHECK-LE: mfvsrd 3, 34 ; CHECK-LE: clrldi 3, 3, 48 @@ -811,11 +776,9 @@ entry: ; CHECK-LABEL: @getus5 ; CHECK: mfvsrd 3, ; CHECK: rldicl 3, 3, 32, 48 -; CHECK: clrldi 3, 3, 48 ; CHECK-LE-LABEL: @getus5 ; CHECK-LE: mfvsrd 3, 34 ; CHECK-LE: rldicl 3, 3, 48, 48 -; CHECK-LE: clrldi 3, 3, 48 } ; Function Attrs: norecurse nounwind readnone @@ -826,11 +789,9 @@ entry: ; CHECK-LABEL: @getus6 ; CHECK: mfvsrd 3, ; CHECK: rldicl 3, 3, 48, 48 -; CHECK: clrldi 3, 3, 48 ; CHECK-LE-LABEL: @getus6 ; CHECK-LE: mfvsrd 3, 34 ; CHECK-LE: rldicl 3, 3, 32, 48 -; CHECK-LE: clrldi 3, 3, 48 } ; Function Attrs: norecurse nounwind readnone @@ -844,7 +805,6 @@ entry: ; CHECK-LE-LABEL: @getus7 ; CHECK-LE: mfvsrd 3, 34 ; CHECK-LE: rldicl 3, 3, 16, 48 -; CHECK-LE: clrldi 3, 3, 48 } ; Function Attrs: norecurse nounwind readnone @@ -973,11 +933,9 @@ entry: ; CHECK-LABEL: @getui0 ; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 ; CHECK: mfvsrwz 3, [[SHL]] -; CHECK: clrldi 3, 3, 32 ; CHECK-LE-LABEL: @getui0 ; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34 ; CHECK-LE: mfvsrwz 3, [[SHL]] -; CHECK-LE: clrldi 3, 3, 32 } ; Function Attrs: norecurse nounwind readnone @@ -987,11 +945,9 @@ entry: ret i32 %vecext ; CHECK-LABEL: @getui1 ; CHECK: mfvsrwz 3, 34 -; CHECK: clrldi 3, 3, 32 ; CHECK-LE-LABEL: @getui1 ; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 ; CHECK-LE: mfvsrwz 3, [[SHL]] -; CHECK-LE: clrldi 3, 3, 32 } ; Function Attrs: norecurse nounwind readnone @@ -1002,10 +958,8 @@ entry: ; CHECK-LABEL: @getui2 ; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 ; CHECK: mfvsrwz 3, [[SHL]] -; CHECK: clrldi 3, 3, 32 ; CHECK-LE-LABEL: @getui2 ; CHECK-LE: mfvsrwz 3, 34 -; CHECK-LE: clrldi 3, 3, 32 } ; Function Attrs: norecurse nounwind readnone @@ -1016,11 +970,9 @@ entry: ; CHECK-LABEL: @getui3 ; CHECK: xxswapd [[SHL:[0-9]+]], 34 ; CHECK: mfvsrwz 3, [[SHL]] -; CHECK: clrldi 3, 3, 32 ; CHECK-LE-LABEL: @getui3 ; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 ; CHECK-LE: mfvsrwz 3, [[SHL]] -; CHECK-LE: clrldi 3, 3, 32 } ; Function Attrs: norecurse nounwind readnone diff --git a/test/CodeGen/PowerPC/p9-vinsert-vextract.ll b/test/CodeGen/PowerPC/p9-vinsert-vextract.ll new file mode 100644 index 0000000000000..c8c7d797c0054 --- /dev/null +++ b/test/CodeGen/PowerPC/p9-vinsert-vextract.ll @@ -0,0 +1,1122 @@ +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE +; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE + +; The following testcases take one halfword element from the second vector and +; inserts it at various locations in the first vector +define <8 x i16> @shuffle_vector_halfword_0_8(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_0_8 +; CHECK: vsldoi 3, 3, 3, 8 +; CHECK: vinserth 2, 3, 14 +; CHECK-BE-LABEL: shuffle_vector_halfword_0_8 +; CHECK-BE: vsldoi 3, 3, 3, 10 +; CHECK-BE: vinserth 2, 3, 0 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_1_15(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_1_15 +; CHECK: vsldoi 3, 3, 3, 10 +; CHECK: vinserth 2, 3, 12 +; CHECK-BE-LABEL: shuffle_vector_halfword_1_15 +; CHECK-BE: vsldoi 3, 3, 3, 8 +; CHECK-BE: vinserth 2, 3, 2 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 15, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_2_9(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_2_9 +; CHECK: vsldoi 3, 3, 3, 6 +; CHECK: vinserth 2, 3, 10 +; CHECK-BE-LABEL: shuffle_vector_halfword_2_9 +; CHECK-BE: vsldoi 3, 3, 3, 12 +; CHECK-BE: vinserth 2, 3, 4 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 9, i32 3, i32 4, i32 5, i32 6, i32 7> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_3_13(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_3_13 +; CHECK: vsldoi 3, 3, 3, 14 +; CHECK: vinserth 2, 3, 8 +; CHECK-BE-LABEL: shuffle_vector_halfword_3_13 +; CHECK-BE: vsldoi 3, 3, 3, 4 +; CHECK-BE: vinserth 2, 3, 6 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_4_10(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_4_10 +; CHECK: vsldoi 3, 3, 3, 4 +; CHECK: vinserth 2, 3, 6 +; CHECK-BE-LABEL: shuffle_vector_halfword_4_10 +; CHECK-BE: vsldoi 3, 3, 3, 14 +; CHECK-BE: vinserth 2, 3, 8 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 5, i32 6, i32 7> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_5_14(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_5_14 +; CHECK: vsldoi 3, 3, 3, 12 +; CHECK: vinserth 2, 3, 4 +; CHECK-BE-LABEL: shuffle_vector_halfword_5_14 +; CHECK-BE: vsldoi 3, 3, 3, 6 +; CHECK-BE: vinserth 2, 3, 10 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 14, i32 6, i32 7> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_6_11(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_6_11 +; CHECK: vsldoi 3, 3, 3, 2 +; CHECK: vinserth 2, 3, 2 +; CHECK-BE-LABEL: shuffle_vector_halfword_6_11 +; CHECK-BE: vinserth 2, 3, 12 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 11, i32 7> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_7_12(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_7_12 +; CHECK: vinserth 2, 3, 0 +; CHECK-BE-LABEL: shuffle_vector_halfword_7_12 +; CHECK-BE: vsldoi 3, 3, 3, 2 +; CHECK-BE: vinserth 2, 3, 14 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 12> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_8_1(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_8_1 +; CHECK: vsldoi 2, 2, 2, 6 +; CHECK: vinserth 3, 2, 14 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_halfword_8_1 +; CHECK-BE: vsldoi 2, 2, 2, 12 +; CHECK-BE: vinserth 3, 2, 0 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <8 x i16> %vecins +} + +; The following testcases take one halfword element from the first vector and +; inserts it at various locations in the second vector +define <8 x i16> @shuffle_vector_halfword_9_7(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_9_7 +; CHECK: vsldoi 2, 2, 2, 10 +; CHECK: vinserth 3, 2, 12 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_halfword_9_7 +; CHECK-BE: vsldoi 2, 2, 2, 8 +; CHECK-BE: vinserth 3, 2, 2 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_10_4(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_10_4 +; CHECK: vinserth 3, 2, 10 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_halfword_10_4 +; CHECK-BE: vsldoi 2, 2, 2, 2 +; CHECK-BE: vinserth 3, 2, 4 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 4, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_11_2(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_11_2 +; CHECK: vsldoi 2, 2, 2, 4 +; CHECK: vinserth 3, 2, 8 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_halfword_11_2 +; CHECK-BE: vsldoi 2, 2, 2, 14 +; CHECK-BE: vinserth 3, 2, 6 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 2, i32 12, i32 13, i32 14, i32 15> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_12_6(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_12_6 +; CHECK: vsldoi 2, 2, 2, 12 +; CHECK: vinserth 3, 2, 6 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_halfword_12_6 +; CHECK-BE: vsldoi 2, 2, 2, 6 +; CHECK-BE: vinserth 3, 2, 8 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 6, i32 13, i32 14, i32 15> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_13_3(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_13_3 +; CHECK: vsldoi 2, 2, 2, 2 +; CHECK: vinserth 3, 2, 4 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_halfword_13_3 +; CHECK-BE: vinserth 3, 2, 10 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 3, i32 14, i32 15> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_14_5(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_14_5 +; CHECK: vsldoi 2, 2, 2, 14 +; CHECK: vinserth 3, 2, 2 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_halfword_14_5 +; CHECK-BE: vsldoi 2, 2, 2, 4 +; CHECK-BE: vinserth 3, 2, 12 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 5, i32 15> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_15_0(<8 x i16> %a, <8 x i16> %b) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_15_0 +; CHECK: vsldoi 2, 2, 2, 8 +; CHECK: vinserth 3, 2, 0 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_halfword_15_0 +; CHECK-BE: vsldoi 2, 2, 2, 10 +; CHECK-BE: vinserth 3, 2, 14 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0> + ret <8 x i16> %vecins +} + +; The following testcases use the same vector in both arguments of the +; shufflevector. If halfword element 3 in BE mode(or 4 in LE mode) is the one +; we're attempting to insert, then we can use the vector insert instruction +define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_0_4 +; CHECK: vinserth 2, 2, 14 +; CHECK-BE-LABEL: shuffle_vector_halfword_0_4 +; CHECK-BE-NOT: vinserth + %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_1_3 +; CHECK-NOT: vinserth +; CHECK-BE-LABEL: shuffle_vector_halfword_1_3 +; CHECK-BE: vinserth 2, 2, 2 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_2_3 +; CHECK-NOT: vinserth +; CHECK-BE-LABEL: shuffle_vector_halfword_2_3 +; CHECK-BE: vinserth 2, 2, 4 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_3_4 +; CHECK: vinserth 2, 2, 8 +; CHECK-BE-LABEL: shuffle_vector_halfword_3_4 +; CHECK-BE-NOT: vinserth + %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_4_3 +; CHECK-NOT: vinserth +; CHECK-BE-LABEL: shuffle_vector_halfword_4_3 +; CHECK-BE: vinserth 2, 2, 8 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_5_3 +; CHECK-NOT: vinserth +; CHECK-BE-LABEL: shuffle_vector_halfword_5_3 +; CHECK-BE: vinserth 2, 2, 10 + %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_6_4 +; CHECK: vinserth 2, 2, 2 +; CHECK-BE-LABEL: shuffle_vector_halfword_6_4 +; CHECK-BE-NOT: vinserth + %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7> + ret <8 x i16> %vecins +} + +define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) { +entry: +; CHECK-LABEL: shuffle_vector_halfword_7_4 +; CHECK: vinserth 2, 2, 0 +; CHECK-BE-LABEL: shuffle_vector_halfword_7_4 +; CHECK-BE-NOT: vinserth + %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4> + ret <8 x i16> %vecins +} + +; The following testcases take one byte element from the second vector and +; inserts it at various locations in the first vector +define <16 x i8> @shuffle_vector_byte_0_16(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_0_16 +; CHECK: vsldoi 3, 3, 3, 8 +; CHECK: vinsertb 2, 3, 15 +; CHECK-BE-LABEL: shuffle_vector_byte_0_16 +; CHECK-BE: vsldoi 3, 3, 3, 9 +; CHECK-BE: vinsertb 2, 3, 0 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_1_25(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_1_25 +; CHECK: vsldoi 3, 3, 3, 15 +; CHECK: vinsertb 2, 3, 14 +; CHECK-BE-LABEL: shuffle_vector_byte_1_25 +; CHECK-BE: vsldoi 3, 3, 3, 2 +; CHECK-BE: vinsertb 2, 3, 1 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 25, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_2_18(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_2_18 +; CHECK: vsldoi 3, 3, 3, 6 +; CHECK: vinsertb 2, 3, 13 +; CHECK-BE-LABEL: shuffle_vector_byte_2_18 +; CHECK-BE: vsldoi 3, 3, 3, 11 +; CHECK-BE: vinsertb 2, 3, 2 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 18, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_3_27(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_3_27 +; CHECK: vsldoi 3, 3, 3, 13 +; CHECK: vinsertb 2, 3, 12 +; CHECK-BE-LABEL: shuffle_vector_byte_3_27 +; CHECK-BE: vsldoi 3, 3, 3, 4 +; CHECK-BE: vinsertb 2, 3, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 27, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_4_20(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_4_20 +; CHECK: vsldoi 3, 3, 3, 4 +; CHECK: vinsertb 2, 3, 11 +; CHECK-BE-LABEL: shuffle_vector_byte_4_20 +; CHECK-BE: vsldoi 3, 3, 3, 13 +; CHECK-BE: vinsertb 2, 3, 4 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_5_29(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_5_29 +; CHECK: vsldoi 3, 3, 3, 11 +; CHECK: vinsertb 2, 3, 10 +; CHECK-BE-LABEL: shuffle_vector_byte_5_29 +; CHECK-BE: vsldoi 3, 3, 3, 6 +; CHECK-BE: vinsertb 2, 3, 5 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 29, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_6_22(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_6_22 +; CHECK: vsldoi 3, 3, 3, 2 +; CHECK: vinsertb 2, 3, 9 +; CHECK-BE-LABEL: shuffle_vector_byte_6_22 +; CHECK-BE: vsldoi 3, 3, 3, 15 +; CHECK-BE: vinsertb 2, 3, 6 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 22, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_7_31(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_7_31 +; CHECK: vsldoi 3, 3, 3, 9 +; CHECK: vinsertb 2, 3, 8 +; CHECK-BE-LABEL: shuffle_vector_byte_7_31 +; CHECK-BE: vsldoi 3, 3, 3, 8 +; CHECK-BE: vinsertb 2, 3, 7 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_8_24(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_8_24 +; CHECK: vinsertb 2, 3, 7 +; CHECK-BE-LABEL: shuffle_vector_byte_8_24 +; CHECK-BE: vsldoi 3, 3, 3, 1 +; CHECK-BE: vinsertb 2, 3, 8 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_9_17(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_9_17 +; CHECK: vsldoi 3, 3, 3, 7 +; CHECK: vinsertb 2, 3, 6 +; CHECK-BE-LABEL: shuffle_vector_byte_9_17 +; CHECK-BE: vsldoi 3, 3, 3, 10 +; CHECK-BE: vinsertb 2, 3, 9 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 17, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_10_26(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_10_26 +; CHECK: vsldoi 3, 3, 3, 14 +; CHECK: vinsertb 2, 3, 5 +; CHECK-BE-LABEL: shuffle_vector_byte_10_26 +; CHECK-BE: vsldoi 3, 3, 3, 3 +; CHECK-BE: vinsertb 2, 3, 10 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 26, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_11_19(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_11_19 +; CHECK: vsldoi 3, 3, 3, 5 +; CHECK: vinsertb 2, 3, 4 +; CHECK-BE-LABEL: shuffle_vector_byte_11_19 +; CHECK-BE: vsldoi 3, 3, 3, 12 +; CHECK-BE: vinsertb 2, 3, 11 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 19, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_12_28(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_12_28 +; CHECK: vsldoi 3, 3, 3, 12 +; CHECK: vinsertb 2, 3, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_12_28 +; CHECK-BE: vsldoi 3, 3, 3, 5 +; CHECK-BE: vinsertb 2, 3, 12 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 28, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_13_21(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_13_21 +; CHECK: vsldoi 3, 3, 3, 3 +; CHECK: vinsertb 2, 3, 2 +; CHECK-BE-LABEL: shuffle_vector_byte_13_21 +; CHECK-BE: vsldoi 3, 3, 3, 14 +; CHECK-BE: vinsertb 2, 3, 13 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 21, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_14_30(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_14_30 +; CHECK: vsldoi 3, 3, 3, 10 +; CHECK: vinsertb 2, 3, 1 +; CHECK-BE-LABEL: shuffle_vector_byte_14_30 +; CHECK-BE: vsldoi 3, 3, 3, 7 +; CHECK-BE: vinsertb 2, 3, 14 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 30, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_15_23(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_15_23 +; CHECK: vsldoi 3, 3, 3, 1 +; CHECK: vinsertb 2, 3, 0 +; CHECK-BE-LABEL: shuffle_vector_byte_15_23 +; CHECK-BE: vinsertb 2, 3, 15 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 23> + ret <16 x i8> %vecins +} + +; The following testcases take one byte element from the first vector and +; inserts it at various locations in the second vector +define <16 x i8> @shuffle_vector_byte_16_8(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_16_8 +; CHECK: vinsertb 3, 2, 15 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_16_8 +; CHECK-BE: vsldoi 2, 2, 2, 1 +; CHECK-BE: vinsertb 3, 2, 0 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_17_1(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_17_1 +; CHECK: vsldoi 2, 2, 2, 7 +; CHECK: vinsertb 3, 2, 14 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_17_1 +; CHECK-BE: vsldoi 2, 2, 2, 10 +; CHECK-BE: vinsertb 3, 2, 1 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_18_10(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_18_10 +; CHECK: vsldoi 2, 2, 2, 14 +; CHECK: vinsertb 3, 2, 13 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_18_10 +; CHECK-BE: vsldoi 2, 2, 2, 3 +; CHECK-BE: vinsertb 3, 2, 2 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 10, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_19_3(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_19_3 +; CHECK: vsldoi 2, 2, 2, 5 +; CHECK: vinsertb 3, 2, 12 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_19_3 +; CHECK-BE: vsldoi 2, 2, 2, 12 +; CHECK-BE: vinsertb 3, 2, 3 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_20_12(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_20_12 +; CHECK: vsldoi 2, 2, 2, 12 +; CHECK: vinsertb 3, 2, 11 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_20_12 +; CHECK-BE: vsldoi 2, 2, 2, 5 +; CHECK-BE: vinsertb 3, 2, 4 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 12, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_21_5(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_21_5 +; CHECK: vsldoi 2, 2, 2, 3 +; CHECK: vinsertb 3, 2, 10 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_21_5 +; CHECK-BE: vsldoi 2, 2, 2, 14 +; CHECK-BE: vinsertb 3, 2, 5 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 5, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_22_14(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_22_14 +; CHECK: vsldoi 2, 2, 2, 10 +; CHECK: vinsertb 3, 2, 9 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_22_14 +; CHECK-BE: vsldoi 2, 2, 2, 7 +; CHECK-BE: vinsertb 3, 2, 6 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 14, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_23_7(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_23_7 +; CHECK: vsldoi 2, 2, 2, 1 +; CHECK: vinsertb 3, 2, 8 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_23_7 +; CHECK-BE: vinsertb 3, 2, 7 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_24_0(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_24_0 +; CHECK: vsldoi 2, 2, 2, 8 +; CHECK: vinsertb 3, 2, 7 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_24_0 +; CHECK-BE: vsldoi 2, 2, 2, 9 +; CHECK-BE: vinsertb 3, 2, 8 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_25_9(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_25_9 +; CHECK: vsldoi 2, 2, 2, 15 +; CHECK: vinsertb 3, 2, 6 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_25_9 +; CHECK-BE: vsldoi 2, 2, 2, 2 +; CHECK-BE: vinsertb 3, 2, 9 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 9, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_26_2(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_26_2 +; CHECK: vsldoi 2, 2, 2, 6 +; CHECK: vinsertb 3, 2, 5 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_26_2 +; CHECK-BE: vsldoi 2, 2, 2, 11 +; CHECK-BE: vinsertb 3, 2, 10 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 2, i32 27, i32 28, i32 29, i32 30, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_27_11(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_27_11 +; CHECK: vsldoi 2, 2, 2, 13 +; CHECK: vinsertb 3, 2, 4 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_27_11 +; CHECK-BE: vsldoi 2, 2, 2, 4 +; CHECK-BE: vinsertb 3, 2, 11 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 11, i32 28, i32 29, i32 30, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_28_4(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_28_4 +; CHECK: vsldoi 2, 2, 2, 4 +; CHECK: vinsertb 3, 2, 3 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_28_4 +; CHECK-BE: vsldoi 2, 2, 2, 13 +; CHECK-BE: vinsertb 3, 2, 12 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 4, i32 29, i32 30, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_29_13(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_29_13 +; CHECK: vsldoi 2, 2, 2, 11 +; CHECK: vinsertb 3, 2, 2 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_29_13 +; CHECK-BE: vsldoi 2, 2, 2, 6 +; CHECK-BE: vinsertb 3, 2, 13 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 13, i32 30, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_30_6(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_30_6 +; CHECK: vsldoi 2, 2, 2, 2 +; CHECK: vinsertb 3, 2, 1 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_30_6 +; CHECK-BE: vsldoi 2, 2, 2, 15 +; CHECK-BE: vinsertb 3, 2, 14 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 6, i32 31> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_31_15(<16 x i8> %a, <16 x i8> %b) { +entry: +; CHECK-LABEL: shuffle_vector_byte_31_15 +; CHECK: vsldoi 2, 2, 2, 9 +; CHECK: vinsertb 3, 2, 0 +; CHECK: vmr 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_31_15 +; CHECK-BE: vsldoi 2, 2, 2, 8 +; CHECK-BE: vinsertb 3, 2, 15 +; CHECK-BE: vmr 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 15> + ret <16 x i8> %vecins +} + +; The following testcases use the same vector in both arguments of the +; shufflevector. If byte element 7 in BE mode(or 8 in LE mode) is the one +; we're attempting to insert, then we can use the vector insert instruction +define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_0_7 +; CHECK-NOT: vinsertb +; CHECK-BE-LABEL: shuffle_vector_byte_0_7 +; CHECK-BE: vinsertb 2, 2, 0 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_1_8 +; CHECK: vinsertb 2, 2, 14 +; CHECK-BE-LABEL: shuffle_vector_byte_1_8 +; CHECK-BE-NOT: vinsertb + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_2_8 +; CHECK: vinsertb 2, 2, 13 +; CHECK-BE-LABEL: shuffle_vector_byte_2_8 +; CHECK-BE-NOT: vinsertb + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_3_7 +; CHECK-NOT: vinsertb +; CHECK-BE-LABEL: shuffle_vector_byte_3_7 +; CHECK-BE: vinsertb 2, 2, 3 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_4_7 +; CHECK-NOT: vinsertb +; CHECK-BE-LABEL: shuffle_vector_byte_4_7 +; CHECK-BE: vinsertb 2, 2, 4 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_5_8 +; CHECK: vinsertb 2, 2, 10 +; CHECK-BE-LABEL: shuffle_vector_byte_5_8 +; CHECK-BE-NOT: vinsertb + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_6_8 +; CHECK: vinsertb 2, 2, 9 +; CHECK-BE-LABEL: shuffle_vector_byte_6_8 +; CHECK-BE-NOT: vinsertb + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_7_8 +; CHECK: vinsertb 2, 2, 8 +; CHECK-BE-LABEL: shuffle_vector_byte_7_8 +; CHECK-BE-NOT: vinsertb + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_8_7 +; CHECK-NOT: vinsertb +; CHECK-BE-LABEL: shuffle_vector_byte_8_7 +; CHECK-BE: vinsertb 2, 2, 8 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_9_7 +; CHECK-NOT: vinsertb +; CHECK-BE-LABEL: shuffle_vector_byte_9_7 +; CHECK-BE: vinsertb 2, 2, 9 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_10_7 +; CHECK-NOT: vinsertb +; CHECK-BE-LABEL: shuffle_vector_byte_10_7 +; CHECK-BE: vinsertb 2, 2, 10 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_11_8 +; CHECK: vinsertb 2, 2, 4 +; CHECK-BE-LABEL: shuffle_vector_byte_11_8 +; CHECK-BE-NOT: vinsertb + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_12_8 +; CHECK: vinsertb 2, 2, 3 +; CHECK-BE-LABEL: shuffle_vector_byte_12_8 +; CHECK-BE-NOT: vinsertb + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_13_7 +; CHECK-NOT: vinsertb +; CHECK-BE-LABEL: shuffle_vector_byte_13_7 +; CHECK-BE: vinsertb 2, 2, 13 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_14_7 +; CHECK-NOT: vinsertb +; CHECK-BE-LABEL: shuffle_vector_byte_14_7 +; CHECK-BE: vinsertb 2, 2, 14 + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15> + ret <16 x i8> %vecins +} + +define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) { +entry: +; CHECK-LABEL: shuffle_vector_byte_15_8 +; CHECK: vinsertb 2, 2, 0 +; CHECK-BE-LABEL: shuffle_vector_byte_15_8 +; CHECK-BE-NOT: vinsertb + %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8> + ret <16 x i8> %vecins +} + +; The following tests try to insert one halfword element into the vector. We +; should always be using the 'vinserth' instruction. +define <8 x i16> @insert_halfword_0(<8 x i16> %a, i16 %b) { +entry: +; CHECK-LABEL: insert_halfword_0 +; CHECK: vinserth 2, 3, 14 +; CHECK-BE-LABEL: insert_halfword_0 +; CHECK-BE: vinserth 2, 3, 0 + %vecins = insertelement <8 x i16> %a, i16 %b, i32 0 + ret <8 x i16> %vecins +} + +define <8 x i16> @insert_halfword_1(<8 x i16> %a, i16 %b) { +entry: +; CHECK-LABEL: insert_halfword_1 +; CHECK: vinserth 2, 3, 12 +; CHECK-BE-LABEL: insert_halfword_1 +; CHECK-BE: vinserth 2, 3, 2 + %vecins = insertelement <8 x i16> %a, i16 %b, i32 1 + ret <8 x i16> %vecins +} + +define <8 x i16> @insert_halfword_2(<8 x i16> %a, i16 %b) { +entry: +; CHECK-LABEL: insert_halfword_2 +; CHECK: vinserth 2, 3, 10 +; CHECK-BE-LABEL: insert_halfword_2 +; CHECK-BE: vinserth 2, 3, 4 + %vecins = insertelement <8 x i16> %a, i16 %b, i32 2 + ret <8 x i16> %vecins +} + +define <8 x i16> @insert_halfword_3(<8 x i16> %a, i16 %b) { +entry: +; CHECK-LABEL: insert_halfword_3 +; CHECK: vinserth 2, 3, 8 +; CHECK-BE-LABEL: insert_halfword_3 +; CHECK-BE: vinserth 2, 3, 6 + %vecins = insertelement <8 x i16> %a, i16 %b, i32 3 + ret <8 x i16> %vecins +} + +define <8 x i16> @insert_halfword_4(<8 x i16> %a, i16 %b) { +entry: +; CHECK-LABEL: insert_halfword_4 +; CHECK: vinserth 2, 3, 6 +; CHECK-BE-LABEL: insert_halfword_4 +; CHECK-BE: vinserth 2, 3, 8 + %vecins = insertelement <8 x i16> %a, i16 %b, i32 4 + ret <8 x i16> %vecins +} + +define <8 x i16> @insert_halfword_5(<8 x i16> %a, i16 %b) { +entry: +; CHECK-LABEL: insert_halfword_5 +; CHECK: vinserth 2, 3, 4 +; CHECK-BE-LABEL: insert_halfword_5 +; CHECK-BE: vinserth 2, 3, 10 + %vecins = insertelement <8 x i16> %a, i16 %b, i32 5 + ret <8 x i16> %vecins +} + +define <8 x i16> @insert_halfword_6(<8 x i16> %a, i16 %b) { +entry: +; CHECK-LABEL: insert_halfword_6 +; CHECK: vinserth 2, 3, 2 +; CHECK-BE-LABEL: insert_halfword_6 +; CHECK-BE: vinserth 2, 3, 12 + %vecins = insertelement <8 x i16> %a, i16 %b, i32 6 + ret <8 x i16> %vecins +} + +define <8 x i16> @insert_halfword_7(<8 x i16> %a, i16 %b) { +entry: +; CHECK-LABEL: insert_halfword_7 +; CHECK: vinserth 2, 3, 0 +; CHECK-BE-LABEL: insert_halfword_7 +; CHECK-BE: vinserth 2, 3, 14 + %vecins = insertelement <8 x i16> %a, i16 %b, i32 7 + ret <8 x i16> %vecins +} + +; The following tests try to insert one byte element into the vector. We +; should always be using the 'vinsertb' instruction. +define <16 x i8> @insert_byte_0(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_0 +; CHECK: vinsertb 2, 3, 15 +; CHECK-BE-LABEL: insert_byte_0 +; CHECK-BE: vinsertb 2, 3, 0 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 0 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_1(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_1 +; CHECK: vinsertb 2, 3, 14 +; CHECK-BE-LABEL: insert_byte_1 +; CHECK-BE: vinsertb 2, 3, 1 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 1 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_2(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_2 +; CHECK: vinsertb 2, 3, 13 +; CHECK-BE-LABEL: insert_byte_2 +; CHECK-BE: vinsertb 2, 3, 2 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 2 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_3(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_3 +; CHECK: vinsertb 2, 3, 12 +; CHECK-BE-LABEL: insert_byte_3 +; CHECK-BE: vinsertb 2, 3, 3 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 3 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_4(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_4 +; CHECK: vinsertb 2, 3, 11 +; CHECK-BE-LABEL: insert_byte_4 +; CHECK-BE: vinsertb 2, 3, 4 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 4 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_5(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_5 +; CHECK: vinsertb 2, 3, 10 +; CHECK-BE-LABEL: insert_byte_5 +; CHECK-BE: vinsertb 2, 3, 5 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 5 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_6(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_6 +; CHECK: vinsertb 2, 3, 9 +; CHECK-BE-LABEL: insert_byte_6 +; CHECK-BE: vinsertb 2, 3, 6 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 6 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_7(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_7 +; CHECK: vinsertb 2, 3, 8 +; CHECK-BE-LABEL: insert_byte_7 +; CHECK-BE: vinsertb 2, 3, 7 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 7 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_8(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_8 +; CHECK: vinsertb 2, 3, 7 +; CHECK-BE-LABEL: insert_byte_8 +; CHECK-BE: vinsertb 2, 3, 8 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 8 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_9(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_9 +; CHECK: vinsertb 2, 3, 6 +; CHECK-BE-LABEL: insert_byte_9 +; CHECK-BE: vinsertb 2, 3, 9 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 9 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_10(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_10 +; CHECK: vinsertb 2, 3, 5 +; CHECK-BE-LABEL: insert_byte_10 +; CHECK-BE: vinsertb 2, 3, 10 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 10 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_11(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_11 +; CHECK: vinsertb 2, 3, 4 +; CHECK-BE-LABEL: insert_byte_11 +; CHECK-BE: vinsertb 2, 3, 11 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 11 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_12(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_12 +; CHECK: vinsertb 2, 3, 3 +; CHECK-BE-LABEL: insert_byte_12 +; CHECK-BE: vinsertb 2, 3, 12 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 12 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_13(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_13 +; CHECK: vinsertb 2, 3, 2 +; CHECK-BE-LABEL: insert_byte_13 +; CHECK-BE: vinsertb 2, 3, 13 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 13 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_14(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_14 +; CHECK: vinsertb 2, 3, 1 +; CHECK-BE-LABEL: insert_byte_14 +; CHECK-BE: vinsertb 2, 3, 14 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 14 + ret <16 x i8> %vecins +} + +define <16 x i8> @insert_byte_15(<16 x i8> %a, i8 %b) { +entry: +; CHECK-LABEL: insert_byte_15 +; CHECK: vinsertb 2, 3, 0 +; CHECK-BE-LABEL: insert_byte_15 +; CHECK-BE: vinsertb 2, 3, 15 + %vecins = insertelement <16 x i8> %a, i8 %b, i32 15 + ret <16 x i8> %vecins +} diff --git a/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll b/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll index fe34bcb85637b..0e50b3a68cece 100644 --- a/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll +++ b/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll @@ -439,6 +439,69 @@ entry: ret float %conv } +; Verify we generate optimal code for unsigned vector int elem extract followed +; by conversion to double + +define double @conv2dlbTestui0(<4 x i32> %a) { +entry: +; CHECK-LABEL: conv2dlbTestui0 +; CHECK: xxextractuw [[SW:[0-9]+]], 34, 12 +; CHECK: xscvuxddp 1, [[SW]] +; CHECK-BE-LABEL: conv2dlbTestui0 +; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 0 +; CHECK-BE: xscvuxddp 1, [[CP]] + %0 = extractelement <4 x i32> %a, i32 0 + %1 = uitofp i32 %0 to double + ret double %1 +} + +define double @conv2dlbTestui1(<4 x i32> %a) { +entry: +; CHECK-LABEL: conv2dlbTestui1 +; CHECK: xxextractuw [[SW:[0-9]+]], 34, 8 +; CHECK: xscvuxddp 1, [[SW]] +; CHECK-BE-LABEL: conv2dlbTestui1 +; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 4 +; CHECK-BE: xscvuxddp 1, [[CP]] + %0 = extractelement <4 x i32> %a, i32 1 + %1 = uitofp i32 %0 to double + ret double %1 +} + +define double @conv2dlbTestui2(<4 x i32> %a) { +entry: +; CHECK-LABEL: conv2dlbTestui2 +; CHECK: xxextractuw [[SW:[0-9]+]], 34, 4 +; CHECK: xscvuxddp 1, [[SW]] +; CHECK-BE-LABEL: conv2dlbTestui2 +; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 8 +; CHECK-BE: xscvuxddp 1, [[CP]] + %0 = extractelement <4 x i32> %a, i32 2 + %1 = uitofp i32 %0 to double + ret double %1 +} + +define double @conv2dlbTestui3(<4 x i32> %a) { +entry: +; CHECK-LABEL: conv2dlbTestui3 +; CHECK: xxextractuw [[SW:[0-9]+]], 34, 0 +; CHECK: xscvuxddp 1, [[SW]] +; CHECK-BE-LABEL: conv2dlbTestui3 +; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 12 +; CHECK-BE: xscvuxddp 1, [[CP]] + %0 = extractelement <4 x i32> %a, i32 3 + %1 = uitofp i32 %0 to double + ret double %1 +} + +; verify we don't crash for variable elem extract +define double @conv2dlbTestuiVar(<4 x i32> %a, i32 zeroext %elem) { +entry: + %vecext = extractelement <4 x i32> %a, i32 %elem + %conv = uitofp i32 %vecext to double + ret double %conv +} + define <4 x float> @_Z10testInsEltILj0EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) { entry: ; CHECK-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_ @@ -971,10 +1034,10 @@ entry: define <4 x float> @insertVarF(<4 x float> %a, float %f, i32 %el) { entry: ; CHECK-LABEL: insertVarF -; CHECK: stxsspx 1, +; CHECK: stfsx 1, ; CHECK: lxv ; CHECK-BE-LABEL: insertVarF -; CHECK-BE: stxsspx 1, +; CHECK-BE: stfsx 1, ; CHECK-BE: lxv %vecins = insertelement <4 x float> %a, float %f, i32 %el ret <4 x float> %vecins diff --git a/test/CodeGen/PowerPC/popcnt.ll b/test/CodeGen/PowerPC/popcnt.ll index 614a0786f7eab..9c71c94f51015 100644 --- a/test/CodeGen/PowerPC/popcnt.ll +++ b/test/CodeGen/PowerPC/popcnt.ll @@ -1,8 +1,8 @@ -; RUN: llc -verify-machineinstrs -march=ppc64 -mattr=+popcntd < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -march=ppc64 -mattr=+slow-popcntd < %s | FileCheck %s --check-prefix=SLOWPC -; RUN: llc -verify-machineinstrs -march=ppc64 -mcpu=pwr7 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -march=ppc64 -mcpu=a2q < %s | FileCheck %s --check-prefix=SLOWPC -; RUN: llc -verify-machineinstrs -march=ppc64 -mcpu=a2q -mattr=+popcntd < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=ppc64-- -mattr=+popcntd < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=ppc64-- -mattr=+slow-popcntd < %s | FileCheck %s --check-prefix=SLOWPC +; RUN: llc -verify-machineinstrs -mtriple=ppc64-- -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=ppc64-- -mcpu=a2q < %s | FileCheck %s --check-prefix=SLOWPC +; RUN: llc -verify-machineinstrs -mtriple=ppc64-- -mcpu=a2q -mattr=+popcntd < %s | FileCheck %s define i8 @cnt8(i8 %x) nounwind readnone { %cnt = tail call i8 @llvm.ctpop.i8(i8 %x) diff --git a/test/CodeGen/PowerPC/ppc-crbits-onoff.ll b/test/CodeGen/PowerPC/ppc-crbits-onoff.ll index c403b5ac2e5aa..c5546254fe38f 100644 --- a/test/CodeGen/PowerPC/ppc-crbits-onoff.ll +++ b/test/CodeGen/PowerPC/ppc-crbits-onoff.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll b/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll index 10edefb2e21d3..2bf4b0722f969 100644 --- a/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll +++ b/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll @@ -591,7 +591,9 @@ if.end: ; Another infinite loop test this time with two nested infinite loop. ; CHECK-LABEL: infiniteloop3 -; CHECK: # %end +; CHECK: Lfunc_begin[[FUNCNUM:[0-9]+]] +; CHECK: bclr +; CHECK: Lfunc_end[[FUNCNUM]] define void @infiniteloop3() { entry: br i1 undef, label %loop2a, label %body diff --git a/test/CodeGen/PowerPC/ppc-vaarg-agg.ll b/test/CodeGen/PowerPC/ppc-vaarg-agg.ll index d5ea044599eee..3468a91a1b631 100644 --- a/test/CodeGen/PowerPC/ppc-vaarg-agg.ll +++ b/test/CodeGen/PowerPC/ppc-vaarg-agg.ll @@ -1,6 +1,6 @@ +; RUN: llc < %s | FileCheck %s target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" target triple = "powerpc-montavista-linux-gnuspe" -; RUN: llc < %s -march=ppc32 | FileCheck %s %struct.__va_list_tag.0.9.18.23.32.41.48.55.62.67.72.77.82.87.90.93.96.101.105 = type { i8, i8, i16, i8*, i8* } diff --git a/test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll b/test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll index c8435a97b7966..740bc787ec9ab 100644 --- a/test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll +++ b/test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll @@ -18,4 +18,4 @@ declare i32 @printf(i8* nocapture readonly, ...) #0 attributes #0 = { "use-soft-float"="true" } -
\ No newline at end of file + diff --git a/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll b/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll index 635a0e7fc1fe2..71836b4929924 100644 --- a/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll +++ b/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=ppc32 | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=ppc32 -mtriple=powerpc-darwin9 | FileCheck %s -check-prefix=CHECK-D +; RUN: llc -verify-machineinstrs < %s -mcpu=ppc32 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mcpu=ppc32 -mtriple=powerpc-darwin9 | FileCheck %s -check-prefix=CHECK-D target triple = "powerpc-unknown-linux-gnu" declare void @printf(i8*, ...) diff --git a/test/CodeGen/PowerPC/ppc32-nest.ll b/test/CodeGen/PowerPC/ppc32-nest.ll index 221e8be295158..b933edcf61631 100644 --- a/test/CodeGen/PowerPC/ppc32-nest.ll +++ b/test/CodeGen/PowerPC/ppc32-nest.ll @@ -7,7 +7,7 @@ target triple = "powerpc-unknown-linux-gnu" define i8* @nest_receiver(i8* nest %arg) nounwind { ; CHECK-LABEL: nest_receiver: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: mr 3, 11 ; CHECK-NEXT: blr diff --git a/test/CodeGen/PowerPC/ppc440-fp-basic.ll b/test/CodeGen/PowerPC/ppc440-fp-basic.ll index 724c56bb5dc3c..646722958f562 100644 --- a/test/CodeGen/PowerPC/ppc440-fp-basic.ll +++ b/test/CodeGen/PowerPC/ppc440-fp-basic.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=440 -fp-contract=fast | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=440 -fp-contract=fast | FileCheck %s %0 = type { double, double } diff --git a/test/CodeGen/PowerPC/ppc440-msync.ll b/test/CodeGen/PowerPC/ppc440-msync.ll index 97ca032db5b74..fd1c5c62d5671 100644 --- a/test/CodeGen/PowerPC/ppc440-msync.ll +++ b/test/CodeGen/PowerPC/ppc440-msync.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2 | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=440 | FileCheck %s -check-prefix=BE-CHK +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=a2 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=440 | FileCheck %s -check-prefix=BE-CHK define i32 @has_a_fence(i32 %a, i32 %b) nounwind { entry: diff --git a/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll b/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll new file mode 100644 index 0000000000000..5f7363641bd5a --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll @@ -0,0 +1,358 @@ +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-PWR8 -implicit-check-not vabsdu + +; Function Attrs: nounwind readnone +define <4 x i32> @simple_absv_32(<4 x i32> %a) local_unnamed_addr { +entry: + %sub.i = sub <4 x i32> zeroinitializer, %a + %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %a, <4 x i32> %sub.i) + ret <4 x i32> %0 +; CHECK-LABEL: simple_absv_32 +; CHECK: vxor [[ZERO:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK-NEXT: vabsduw 2, 2, [[ZERO]] +; CHECK-NEXT: blr +; CHECK-PWR8-LABEL: simple_absv_32 +; CHECK-PWR8: xxlxor +; CHECK-PWR8: vsubuwm +; CHECK-PWR8: vmaxsw +; CHECK-PWR8: blr +} + +; Function Attrs: nounwind readnone +define <4 x i32> @simple_absv_32_swap(<4 x i32> %a) local_unnamed_addr { +entry: + %sub.i = sub <4 x i32> zeroinitializer, %a + %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub.i, <4 x i32> %a) + ret <4 x i32> %0 +; CHECK-LABEL: simple_absv_32_swap +; CHECK: vxor [[ZERO:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK-NEXT: vabsduw 2, 2, [[ZERO]] +; CHECK-NEXT: blr +; CHECK-PWR8-LABEL: simple_absv_32_swap +; CHECK-PWR8: xxlxor +; CHECK-PWR8: vsubuwm +; CHECK-PWR8: vmaxsw +; CHECK-PWR8: blr +} + +define <8 x i16> @simple_absv_16(<8 x i16> %a) local_unnamed_addr { +entry: + %sub.i = sub <8 x i16> zeroinitializer, %a + %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %a, <8 x i16> %sub.i) + ret <8 x i16> %0 +; CHECK-LABEL: simple_absv_16 +; CHECK: vxor [[ZERO:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK-NEXT: vabsduh 2, 2, [[ZERO]] +; CHECK-NEXT: blr +; CHECK-PWR8-LABEL: simple_absv_16 +; CHECK-PWR8: xxlxor +; CHECK-PWR8: vsubuhm +; CHECK-PWR8: vmaxsh +; CHECK-PWR8: blr +} + +; Function Attrs: nounwind readnone +define <16 x i8> @simple_absv_8(<16 x i8> %a) local_unnamed_addr { +entry: + %sub.i = sub <16 x i8> zeroinitializer, %a + %0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %a, <16 x i8> %sub.i) + ret <16 x i8> %0 +; CHECK-LABEL: simple_absv_8 +; CHECK: vxor [[ZERO:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} +; CHECK-NEXT: vabsdub 2, 2, [[ZERO]] +; CHECK-NEXT: blr +; CHECK-PWR8-LABEL: simple_absv_8 +; CHECK-PWR8: xxlxor +; CHECK-PWR8: vsububm +; CHECK-PWR8: vmaxsb +; CHECK-PWR8: blr +} + +; The select pattern can only be detected for v4i32. +; Function Attrs: norecurse nounwind readnone +define <4 x i32> @sub_absv_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr { +entry: + %0 = sub nsw <4 x i32> %a, %b + %1 = icmp sgt <4 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1> + %2 = sub <4 x i32> zeroinitializer, %0 + %3 = select <4 x i1> %1, <4 x i32> %0, <4 x i32> %2 + ret <4 x i32> %3 +; CHECK-LABEL: sub_absv_32 +; CHECK: vabsduw 2, 2, 3 +; CHECK-NEXT: blr +; CHECK-PWR8-LABEL: sub_absv_32 +; CHECK-PWR8: vsubuwm +; CHECK-PWR8: xxlxor +; CHECK-PWR8: blr +} + +; FIXME: This does not produce the ISD::ABS that we are looking for. +; We should fix the missing canonicalization. +; We do manage to find the word version of ABS but not the halfword. +; Threfore, we end up doing more work than is required with a pair of abs for word +; instead of just one for the halfword. +; Function Attrs: norecurse nounwind readnone +define <8 x i16> @sub_absv_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr { +entry: + %0 = sext <8 x i16> %a to <8 x i32> + %1 = sext <8 x i16> %b to <8 x i32> + %2 = sub nsw <8 x i32> %0, %1 + %3 = icmp sgt <8 x i32> %2, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> + %4 = sub nsw <8 x i32> zeroinitializer, %2 + %5 = select <8 x i1> %3, <8 x i32> %2, <8 x i32> %4 + %6 = trunc <8 x i32> %5 to <8 x i16> + ret <8 x i16> %6 +; CHECK-LABEL: sub_absv_16 +; CHECK-NOT: vabsduh +; CHECK: vabsduw +; CHECK-NOT: vabsduh +; CHECK: vabsduw +; CHECK-NOT: vabsduh +; CHECK: blr +; CHECK-PWR8-LABEL: sub_absv_16 +; CHECK-PWR8: vsubuwm +; CHECK-PWR8: xxlxor +; CHECK-PWR8: blr +} + +; FIXME: This does not produce ISD::ABS. This does not even vectorize correctly! +; This function should look like sub_absv_32 and sub_absv_16 except that the type is v16i8. +; Function Attrs: norecurse nounwind readnone +define <16 x i8> @sub_absv_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr { +entry: + %vecext = extractelement <16 x i8> %a, i32 0 + %conv = zext i8 %vecext to i32 + %vecext1 = extractelement <16 x i8> %b, i32 0 + %conv2 = zext i8 %vecext1 to i32 + %sub = sub nsw i32 %conv, %conv2 + %ispos = icmp sgt i32 %sub, -1 + %neg = sub nsw i32 0, %sub + %0 = select i1 %ispos, i32 %sub, i32 %neg + %conv3 = trunc i32 %0 to i8 + %vecins = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %conv3, i32 0 + %vecext4 = extractelement <16 x i8> %a, i32 1 + %conv5 = zext i8 %vecext4 to i32 + %vecext6 = extractelement <16 x i8> %b, i32 1 + %conv7 = zext i8 %vecext6 to i32 + %sub8 = sub nsw i32 %conv5, %conv7 + %ispos171 = icmp sgt i32 %sub8, -1 + %neg172 = sub nsw i32 0, %sub8 + %1 = select i1 %ispos171, i32 %sub8, i32 %neg172 + %conv10 = trunc i32 %1 to i8 + %vecins11 = insertelement <16 x i8> %vecins, i8 %conv10, i32 1 + %vecext12 = extractelement <16 x i8> %a, i32 2 + %conv13 = zext i8 %vecext12 to i32 + %vecext14 = extractelement <16 x i8> %b, i32 2 + %conv15 = zext i8 %vecext14 to i32 + %sub16 = sub nsw i32 %conv13, %conv15 + %ispos173 = icmp sgt i32 %sub16, -1 + %neg174 = sub nsw i32 0, %sub16 + %2 = select i1 %ispos173, i32 %sub16, i32 %neg174 + %conv18 = trunc i32 %2 to i8 + %vecins19 = insertelement <16 x i8> %vecins11, i8 %conv18, i32 2 + %vecext20 = extractelement <16 x i8> %a, i32 3 + %conv21 = zext i8 %vecext20 to i32 + %vecext22 = extractelement <16 x i8> %b, i32 3 + %conv23 = zext i8 %vecext22 to i32 + %sub24 = sub nsw i32 %conv21, %conv23 + %ispos175 = icmp sgt i32 %sub24, -1 + %neg176 = sub nsw i32 0, %sub24 + %3 = select i1 %ispos175, i32 %sub24, i32 %neg176 + %conv26 = trunc i32 %3 to i8 + %vecins27 = insertelement <16 x i8> %vecins19, i8 %conv26, i32 3 + %vecext28 = extractelement <16 x i8> %a, i32 4 + %conv29 = zext i8 %vecext28 to i32 + %vecext30 = extractelement <16 x i8> %b, i32 4 + %conv31 = zext i8 %vecext30 to i32 + %sub32 = sub nsw i32 %conv29, %conv31 + %ispos177 = icmp sgt i32 %sub32, -1 + %neg178 = sub nsw i32 0, %sub32 + %4 = select i1 %ispos177, i32 %sub32, i32 %neg178 + %conv34 = trunc i32 %4 to i8 + %vecins35 = insertelement <16 x i8> %vecins27, i8 %conv34, i32 4 + %vecext36 = extractelement <16 x i8> %a, i32 5 + %conv37 = zext i8 %vecext36 to i32 + %vecext38 = extractelement <16 x i8> %b, i32 5 + %conv39 = zext i8 %vecext38 to i32 + %sub40 = sub nsw i32 %conv37, %conv39 + %ispos179 = icmp sgt i32 %sub40, -1 + %neg180 = sub nsw i32 0, %sub40 + %5 = select i1 %ispos179, i32 %sub40, i32 %neg180 + %conv42 = trunc i32 %5 to i8 + %vecins43 = insertelement <16 x i8> %vecins35, i8 %conv42, i32 5 + %vecext44 = extractelement <16 x i8> %a, i32 6 + %conv45 = zext i8 %vecext44 to i32 + %vecext46 = extractelement <16 x i8> %b, i32 6 + %conv47 = zext i8 %vecext46 to i32 + %sub48 = sub nsw i32 %conv45, %conv47 + %ispos181 = icmp sgt i32 %sub48, -1 + %neg182 = sub nsw i32 0, %sub48 + %6 = select i1 %ispos181, i32 %sub48, i32 %neg182 + %conv50 = trunc i32 %6 to i8 + %vecins51 = insertelement <16 x i8> %vecins43, i8 %conv50, i32 6 + %vecext52 = extractelement <16 x i8> %a, i32 7 + %conv53 = zext i8 %vecext52 to i32 + %vecext54 = extractelement <16 x i8> %b, i32 7 + %conv55 = zext i8 %vecext54 to i32 + %sub56 = sub nsw i32 %conv53, %conv55 + %ispos183 = icmp sgt i32 %sub56, -1 + %neg184 = sub nsw i32 0, %sub56 + %7 = select i1 %ispos183, i32 %sub56, i32 %neg184 + %conv58 = trunc i32 %7 to i8 + %vecins59 = insertelement <16 x i8> %vecins51, i8 %conv58, i32 7 + %vecext60 = extractelement <16 x i8> %a, i32 8 + %conv61 = zext i8 %vecext60 to i32 + %vecext62 = extractelement <16 x i8> %b, i32 8 + %conv63 = zext i8 %vecext62 to i32 + %sub64 = sub nsw i32 %conv61, %conv63 + %ispos185 = icmp sgt i32 %sub64, -1 + %neg186 = sub nsw i32 0, %sub64 + %8 = select i1 %ispos185, i32 %sub64, i32 %neg186 + %conv66 = trunc i32 %8 to i8 + %vecins67 = insertelement <16 x i8> %vecins59, i8 %conv66, i32 8 + %vecext68 = extractelement <16 x i8> %a, i32 9 + %conv69 = zext i8 %vecext68 to i32 + %vecext70 = extractelement <16 x i8> %b, i32 9 + %conv71 = zext i8 %vecext70 to i32 + %sub72 = sub nsw i32 %conv69, %conv71 + %ispos187 = icmp sgt i32 %sub72, -1 + %neg188 = sub nsw i32 0, %sub72 + %9 = select i1 %ispos187, i32 %sub72, i32 %neg188 + %conv74 = trunc i32 %9 to i8 + %vecins75 = insertelement <16 x i8> %vecins67, i8 %conv74, i32 9 + %vecext76 = extractelement <16 x i8> %a, i32 10 + %conv77 = zext i8 %vecext76 to i32 + %vecext78 = extractelement <16 x i8> %b, i32 10 + %conv79 = zext i8 %vecext78 to i32 + %sub80 = sub nsw i32 %conv77, %conv79 + %ispos189 = icmp sgt i32 %sub80, -1 + %neg190 = sub nsw i32 0, %sub80 + %10 = select i1 %ispos189, i32 %sub80, i32 %neg190 + %conv82 = trunc i32 %10 to i8 + %vecins83 = insertelement <16 x i8> %vecins75, i8 %conv82, i32 10 + %vecext84 = extractelement <16 x i8> %a, i32 11 + %conv85 = zext i8 %vecext84 to i32 + %vecext86 = extractelement <16 x i8> %b, i32 11 + %conv87 = zext i8 %vecext86 to i32 + %sub88 = sub nsw i32 %conv85, %conv87 + %ispos191 = icmp sgt i32 %sub88, -1 + %neg192 = sub nsw i32 0, %sub88 + %11 = select i1 %ispos191, i32 %sub88, i32 %neg192 + %conv90 = trunc i32 %11 to i8 + %vecins91 = insertelement <16 x i8> %vecins83, i8 %conv90, i32 11 + %vecext92 = extractelement <16 x i8> %a, i32 12 + %conv93 = zext i8 %vecext92 to i32 + %vecext94 = extractelement <16 x i8> %b, i32 12 + %conv95 = zext i8 %vecext94 to i32 + %sub96 = sub nsw i32 %conv93, %conv95 + %ispos193 = icmp sgt i32 %sub96, -1 + %neg194 = sub nsw i32 0, %sub96 + %12 = select i1 %ispos193, i32 %sub96, i32 %neg194 + %conv98 = trunc i32 %12 to i8 + %vecins99 = insertelement <16 x i8> %vecins91, i8 %conv98, i32 12 + %vecext100 = extractelement <16 x i8> %a, i32 13 + %conv101 = zext i8 %vecext100 to i32 + %vecext102 = extractelement <16 x i8> %b, i32 13 + %conv103 = zext i8 %vecext102 to i32 + %sub104 = sub nsw i32 %conv101, %conv103 + %ispos195 = icmp sgt i32 %sub104, -1 + %neg196 = sub nsw i32 0, %sub104 + %13 = select i1 %ispos195, i32 %sub104, i32 %neg196 + %conv106 = trunc i32 %13 to i8 + %vecins107 = insertelement <16 x i8> %vecins99, i8 %conv106, i32 13 + %vecext108 = extractelement <16 x i8> %a, i32 14 + %conv109 = zext i8 %vecext108 to i32 + %vecext110 = extractelement <16 x i8> %b, i32 14 + %conv111 = zext i8 %vecext110 to i32 + %sub112 = sub nsw i32 %conv109, %conv111 + %ispos197 = icmp sgt i32 %sub112, -1 + %neg198 = sub nsw i32 0, %sub112 + %14 = select i1 %ispos197, i32 %sub112, i32 %neg198 + %conv114 = trunc i32 %14 to i8 + %vecins115 = insertelement <16 x i8> %vecins107, i8 %conv114, i32 14 + %vecext116 = extractelement <16 x i8> %a, i32 15 + %conv117 = zext i8 %vecext116 to i32 + %vecext118 = extractelement <16 x i8> %b, i32 15 + %conv119 = zext i8 %vecext118 to i32 + %sub120 = sub nsw i32 %conv117, %conv119 + %ispos199 = icmp sgt i32 %sub120, -1 + %neg200 = sub nsw i32 0, %sub120 + %15 = select i1 %ispos199, i32 %sub120, i32 %neg200 + %conv122 = trunc i32 %15 to i8 + %vecins123 = insertelement <16 x i8> %vecins115, i8 %conv122, i32 15 + ret <16 x i8> %vecins123 +; CHECK-LABEL: sub_absv_8 +; CHECK-NOT: vabsdub +; CHECK: subf +; CHECK-NOT: vabsdub +; CHECK: xor +; CHECK-NOT: vabsdub +; CHECK: blr +; CHECK-PWR8-LABEL: sub_absv_8 +; CHECK-PWR8: subf +; CHECK-PWR8: xor +; CHECK-PWR8: blr +} + +; Function Attrs: nounwind readnone +define <4 x i32> @sub_absv_vec_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr { +entry: + %sub = sub <4 x i32> %a, %b + %sub.i = sub <4 x i32> zeroinitializer, %sub + %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub, <4 x i32> %sub.i) + ret <4 x i32> %0 +; CHECK-LABEL: sub_absv_vec_32 +; CHECK: vabsduw 2, 2, 3 +; CHECK-NEXT: blr +; CHECK-PWR8-LABEL: sub_absv_vec_32 +; CHECK-PWR8: xxlxor +; CHECK-PWR8: vsubuwm +; CHECK-PWR8: vmaxsw +; CHECK-PWR8: blr +} + +; Function Attrs: nounwind readnone +define <8 x i16> @sub_absv_vec_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr { +entry: + %sub = sub <8 x i16> %a, %b + %sub.i = sub <8 x i16> zeroinitializer, %sub + %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %sub, <8 x i16> %sub.i) + ret <8 x i16> %0 +; CHECK-LABEL: sub_absv_vec_16 +; CHECK: vabsduh 2, 2, 3 +; CHECK-NEXT: blr +; CHECK-PWR8-LABEL: sub_absv_vec_16 +; CHECK-PWR8: xxlxor +; CHECK-PWR8: vsubuhm +; CHECK-PWR8: vmaxsh +; CHECK-PWR8: blr +} + +; Function Attrs: nounwind readnone +define <16 x i8> @sub_absv_vec_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr { +entry: + %sub = sub <16 x i8> %a, %b + %sub.i = sub <16 x i8> zeroinitializer, %sub + %0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %sub, <16 x i8> %sub.i) + ret <16 x i8> %0 +; CHECK-LABEL: sub_absv_vec_8 +; CHECK: vabsdub 2, 2, 3 +; CHECK-NEXT: blr +; CHECK-PWR8-LABEL: sub_absv_vec_8 +; CHECK-PWR8: xxlxor +; CHECK-PWR8: vsububm +; CHECK-PWR8: vmaxsb +; CHECK-PWR8: blr +} + + +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) + +; Function Attrs: nounwind readnone +declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) + +; Function Attrs: nounwind readnone +declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) + diff --git a/test/CodeGen/PowerPC/ppc64-altivec-abi.ll b/test/CodeGen/PowerPC/ppc64-altivec-abi.ll index 74182b0542042..c0ab39d899e53 100644 --- a/test/CodeGen/PowerPC/ppc64-altivec-abi.ll +++ b/test/CodeGen/PowerPC/ppc64-altivec-abi.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mattr=+altivec | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mattr=+altivec | FileCheck %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/ppc64-blnop.ll b/test/CodeGen/PowerPC/ppc64-blnop.ll index 2fe23f91c83d9..3b3d9add183e2 100644 --- a/test/CodeGen/PowerPC/ppc64-blnop.ll +++ b/test/CodeGen/PowerPC/ppc64-blnop.ll @@ -5,6 +5,8 @@ ; RUN: llc < %s -function-sections -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS ; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s ; RUN: llc < %s -function-sections -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS +; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -code-model=small -mcpu=pwr8 | FileCheck %s -check-prefix=SCM %class.T = type { [2 x i8] } @@ -74,7 +76,11 @@ define void @wo_hcaller(%class.T* %this, i8* %c) { ; CHECK-LABEL: wo_hcaller: ; CHECK: bl wo_hcallee -; CHECK-NEXT: nop +; CHECK-NOT: nop + +; SCM-LABEL: wo_hcaller: +; SCM: bl wo_hcallee +; SCM-NEXT: nop } define weak_odr protected void @wo_pcallee(%class.T* %this, i8* %c) { ret void } @@ -84,7 +90,11 @@ define void @wo_pcaller(%class.T* %this, i8* %c) { ; CHECK-LABEL: wo_pcaller: ; CHECK: bl wo_pcallee -; CHECK-NEXT: nop +; CHECK-NOT: nop + +; SCM-LABEL: wo_pcaller: +; SCM: bl wo_pcallee +; SCM-NEXT: nop } define weak_odr void @wo_callee(%class.T* %this, i8* %c) { ret void } @@ -104,7 +114,11 @@ define void @w_pcaller(i8* %ptr) { ; CHECK-LABEL: w_pcaller: ; CHECK: bl w_pcallee -; CHECK-NEXT: nop +; CHECK-NOT: nop + +; SCM-LABEL: w_pcaller: +; SCM: bl w_pcallee +; SCM-NEXT: nop } define weak hidden void @w_hcallee(i8* %ptr) { ret void } @@ -114,7 +128,11 @@ define void @w_hcaller(i8* %ptr) { ; CHECK-LABEL: w_hcaller: ; CHECK: bl w_hcallee -; CHECK-NEXT: nop +; CHECK-NOT: nop + +; SCM-LABEL: w_hcaller: +; SCM: bl w_hcallee +; SCM-NEXT: nop } define weak void @w_callee(i8* %ptr) { ret void } diff --git a/test/CodeGen/PowerPC/ppc64-byval-align.ll b/test/CodeGen/PowerPC/ppc64-byval-align.ll index 88756086fea59..69f4759eac789 100644 --- a/test/CodeGen/PowerPC/ppc64-byval-align.ll +++ b/test/CodeGen/PowerPC/ppc64-byval-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -O1 < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s +; RUN: llc -verify-machineinstrs -O1 < %s -mcpu=pwr7 | FileCheck %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/ppc64-calls.ll b/test/CodeGen/PowerPC/ppc64-calls.ll index 907c945c5d6b6..245056f7add9b 100644 --- a/test/CodeGen/PowerPC/ppc64-calls.ll +++ b/test/CodeGen/PowerPC/ppc64-calls.ll @@ -1,4 +1,6 @@ -; RUN: llc -relocation-model=static -verify-machineinstrs < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s +; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mcpu=pwr7 | FileCheck %s +; RUN: llc -relocation-model=static -verify-machineinstrs < %s -code-model=small -mcpu=pwr7 | FileCheck %s -check-prefix=SCM + target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -21,13 +23,22 @@ define void @test_direct() nounwind readnone { ret void } -; Calls to weak function requires a TOC restore 'nop' because they -; may be overridden in a different module. +; Calls to weak function requires a TOC restore 'nop' with the small codemodel +; because the definition that gets choosen at link time may come from a +; different section even though we have seen a weak definition in the same +; section at compile time. +; With large and medium codemodels no TOC restore is needed, since we know +; whichever definition is choosen it resides within the same DSO boundaries and +; therefore shares the same TOC. define void @test_weak() nounwind readnone { -; CHECK-LABEL: test_weak: tail call void @foo_weak() nounwind -; CHECK: bl foo -; CHECK-NEXT: nop +; CHECK-LABEL: test_weak: +; CHECK: b foo_weak +; CHECK-NOT: nop + +; SCM-LABEL: test_weak: +; SCM: bl foo_weak +; SCM-NEXT: nop ret void } diff --git a/test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll b/test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll index 7ca5332865caa..9d7526c54d5ba 100644 --- a/test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll +++ b/test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll @@ -4,7 +4,7 @@ ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-ppc-prefetching=true -ppc-loop-prefetch-cache-line=64 | FileCheck %s -check-prefix=CHECK-DCBT ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -enable-ppc-prefetching=true | FileCheck %s ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -enable-ppc-prefetching=true -ppc-loop-prefetch-cache-line=64 | FileCheck %s -check-prefix=CHECK-DCBT -; RUN: llc < %s -march=ppc64 -mcpu=a2 -enable-ppc-prefetching=true | FileCheck %s -check-prefix=CHECK-DCBT +; RUN: llc < %s -mtriple=ppc64-- -mcpu=a2 -enable-ppc-prefetching=true | FileCheck %s -check-prefix=CHECK-DCBT ; Function Attrs: nounwind define signext i32 @check_cache_line() local_unnamed_addr { diff --git a/test/CodeGen/PowerPC/ppc64-i128-abi.ll b/test/CodeGen/PowerPC/ppc64-i128-abi.ll index 6d19d7f0d6292..f5319b24d457e 100644 --- a/test/CodeGen/PowerPC/ppc64-i128-abi.ll +++ b/test/CodeGen/PowerPC/ppc64-i128-abi.ll @@ -20,8 +20,8 @@ ; RUN: FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr < %s | FileCheck %s \ -; RUN: -check-prefix=CHECK-P9 --implicit-check-not xxswapd +; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ +; RUN: FileCheck %s -check-prefix=CHECK-P9 --implicit-check-not xxswapd ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \ diff --git a/test/CodeGen/PowerPC/ppc64-nest.ll b/test/CodeGen/PowerPC/ppc64-nest.ll index 14872632e8140..cd2366cfa4504 100644 --- a/test/CodeGen/PowerPC/ppc64-nest.ll +++ b/test/CodeGen/PowerPC/ppc64-nest.ll @@ -7,7 +7,7 @@ target triple = "powerpc64-unknown-linux-gnu" define i8* @nest_receiver(i8* nest %arg) nounwind { ; CHECK-LABEL: nest_receiver: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: mr 3, 11 ; CHECK-NEXT: blr diff --git a/test/CodeGen/PowerPC/ppc64-pre-inc-no-extra-phi.ll b/test/CodeGen/PowerPC/ppc64-pre-inc-no-extra-phi.ll new file mode 100644 index 0000000000000..032bad6f63d67 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-pre-inc-no-extra-phi.ll @@ -0,0 +1,30 @@ +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s + +@perm = common local_unnamed_addr global [100 x i64] zeroinitializer, align 8 + +define void @sort_basket() local_unnamed_addr { +entry: + br label %while.cond + +while.cond: + %l.0 = phi i64 [ 0, %entry ], [ %inc, %while.cond ] + %arrayidx = getelementptr inbounds [100 x i64], [100 x i64]* @perm, i64 0, i64 %l.0 + %0 = load i64, i64* %arrayidx, align 8 + %cmp = icmp sgt i64 %0, 0 + %inc = add nuw nsw i64 %l.0, 1 + br i1 %cmp, label %while.cond, label %while.end + +while.end: + store i64 0, i64* %arrayidx, align 8 + ret void +; CHECK-LABEL: sort_basket +; CHECK: addi {{[0-9]+}}, {{[0-9]+}}, -8 +; CHECK-NOT: addi {{[0-9]+}}, {{[0-9]+}}, 8 +; CHECK: ldu {{[0-9]+}}, 8({{[0-9]+}}) +; CHECK-NOT: addi {{[0-9]+}}, {{[0-9]+}}, 8 +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/ppc64-sibcall.ll b/test/CodeGen/PowerPC/ppc64-sibcall.ll index 59e545601475f..3c08ecb5119fb 100644 --- a/test/CodeGen/PowerPC/ppc64-sibcall.ll +++ b/test/CodeGen/PowerPC/ppc64-sibcall.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-SCO ; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO-HASQPX ; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO-HASQPX +; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -code-model=small | FileCheck %s -check-prefix=SCM ; No combination of "powerpc64le-unknown-linux-gnu" + "CHECK-SCO", because ; only Power8 (and later) fully support LE. @@ -142,7 +143,10 @@ define void @wo_hcaller(%class.T* %this, i8* %c) { ret void ; CHECK-SCO-LABEL: wo_hcaller: -; CHECK-SCO: bl wo_hcallee +; CHECK-SCO: b wo_hcallee + +; SCM-LABEL: wo_hcaller: +; SCM: bl wo_hcallee } define weak_odr protected void @wo_pcallee(%class.T* %this, i8* %c) { ret void } @@ -151,7 +155,10 @@ define void @wo_pcaller(%class.T* %this, i8* %c) { ret void ; CHECK-SCO-LABEL: wo_pcaller: -; CHECK-SCO: bl wo_pcallee +; CHECK-SCO: b wo_pcallee + +; SCM-LABEL: wo_pcaller: +; SCM: bl wo_pcallee } define weak_odr void @wo_callee(%class.T* %this, i8* %c) { ret void } @@ -160,7 +167,10 @@ define void @wo_caller(%class.T* %this, i8* %c) { ret void ; CHECK-SCO-LABEL: wo_caller: -; CHECK-SCO: bl wo_callee +; CHECK-SCO: b wo_callee + +; SCM-LABEL: wo_caller: +; SCM: bl wo_callee } define weak protected void @w_pcallee(i8* %ptr) { ret void } @@ -169,7 +179,10 @@ define void @w_pcaller(i8* %ptr) { ret void ; CHECK-SCO-LABEL: w_pcaller: -; CHECK-SCO: bl w_pcallee +; CHECK-SCO: b w_pcallee + +; SCM-LABEL: w_pcaller: +; SCM: bl w_pcallee } define weak hidden void @w_hcallee(i8* %ptr) { ret void } @@ -178,7 +191,10 @@ define void @w_hcaller(i8* %ptr) { ret void ; CHECK-SCO-LABEL: w_hcaller: -; CHECK-SCO: bl w_hcallee +; CHECK-SCO: b w_hcallee + +; SCM-LABEL: w_hcaller: +; SCM: bl w_hcallee } define weak void @w_callee(i8* %ptr) { ret void } @@ -187,7 +203,10 @@ define void @w_caller(i8* %ptr) { ret void ; CHECK-SCO-LABEL: w_caller: -; CHECK-SCO: bl w_callee +; CHECK-SCO: b w_callee + +; SCM-LABEL: w_caller: +; SCM: bl w_callee } %struct.byvalTest = type { [8 x i8] } diff --git a/test/CodeGen/PowerPC/ppc64le-aggregates.ll b/test/CodeGen/PowerPC/ppc64le-aggregates.ll index 6fcbdda4e34f0..91119786b1f54 100644 --- a/test/CodeGen/PowerPC/ppc64le-aggregates.ll +++ b/test/CodeGen/PowerPC/ppc64le-aggregates.ll @@ -1,8 +1,8 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64le -mcpu=pwr8 \ +; RUN: llc -verify-machineinstrs < %s -mcpu=pwr8 \ ; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -march=ppc64le -mattr=+altivec \ +; RUN: llc -verify-machineinstrs < %s -mattr=+altivec \ ; RUN: -mattr=-vsx | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -march=ppc64le -mcpu=pwr9 \ +; RUN: llc -verify-machineinstrs < %s -mcpu=pwr9 \ ; RUN: -mattr=-direct-move -mattr=+altivec | FileCheck %s ; Currently VSX support is disabled for this test because we generate lxsdx diff --git a/test/CodeGen/PowerPC/ppc64le-calls.ll b/test/CodeGen/PowerPC/ppc64le-calls.ll index 133dde687df91..3eab2dba5644e 100644 --- a/test/CodeGen/PowerPC/ppc64le-calls.ll +++ b/test/CodeGen/PowerPC/ppc64le-calls.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs -march=ppc64le -mcpu=pwr8 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -march=ppc64le < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; The second run of the test case is to ensure the behaviour is the same ; without specifying -mcpu=pwr8 as that is now the baseline for ppc64le. diff --git a/test/CodeGen/PowerPC/ppc64le-localentry-large.ll b/test/CodeGen/PowerPC/ppc64le-localentry-large.ll index 17f92185f04c7..ec51f91a3059a 100644 --- a/test/CodeGen/PowerPC/ppc64le-localentry-large.ll +++ b/test/CodeGen/PowerPC/ppc64le-localentry-large.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -march=ppc64le -code-model=large < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -code-model=large < %s | FileCheck %s target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/ppc64le-localentry.ll b/test/CodeGen/PowerPC/ppc64le-localentry.ll index 8f7b0ff111726..e894a545a1bf7 100644 --- a/test/CodeGen/PowerPC/ppc64le-localentry.ll +++ b/test/CodeGen/PowerPC/ppc64le-localentry.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -march=ppc64le -mcpu=pwr8 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -march=ppc64le -mcpu=pwr8 -O0 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -march=ppc64le < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -march=ppc64le -O0 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -O0 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 < %s | FileCheck %s ; The second run of the test case is to ensure the behaviour is the same ; without specifying -mcpu=pwr8 as that is now the baseline for ppc64le. diff --git a/test/CodeGen/PowerPC/ppc64le-smallarg.ll b/test/CodeGen/PowerPC/ppc64le-smallarg.ll index 3a425406d043f..0143067182485 100644 --- a/test/CodeGen/PowerPC/ppc64le-smallarg.ll +++ b/test/CodeGen/PowerPC/ppc64le-smallarg.ll @@ -43,7 +43,7 @@ entry: } ; CHECK: @callee2 ; CHECK: addi [[TOCREG:[0-9]+]], 1, 136 -; CHECK: lxsspx {{[0-9]+}}, {{[0-9]+}}, [[TOCREG]] +; CHECK: lfsx {{[0-9]+}}, {{[0-9]+}}, [[TOCREG]] ; CHECK: blr define void @caller2() { @@ -54,7 +54,7 @@ entry: } ; CHECK: @caller2 ; CHECK: addi [[TOCOFF:[0-9]+]], {{[0-9]+}}, 136 -; CHECK: stxsspx {{[0-9]+}}, 0, [[TOCOFF]] +; CHECK: stfsx {{[0-9]+}}, 0, [[TOCOFF]] ; CHECK: bl test2 declare float @test2(float, float, float, float, float, float, float, float, float, float, float, float, float, float) diff --git a/test/CodeGen/PowerPC/ppcf128-2.ll b/test/CodeGen/PowerPC/ppcf128-2.ll index 04c97e8349f1a..66eb4548c170e 100644 --- a/test/CodeGen/PowerPC/ppcf128-2.ll +++ b/test/CodeGen/PowerPC/ppcf128-2.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- define i64 @__fixtfdi(ppc_fp128 %a) nounwind { entry: diff --git a/test/CodeGen/PowerPC/ppcf128-3.ll b/test/CodeGen/PowerPC/ppcf128-3.ll index e06df4bf23999..b9a35e0149238 100644 --- a/test/CodeGen/PowerPC/ppcf128-3.ll +++ b/test/CodeGen/PowerPC/ppcf128-3.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- %struct.stp_sequence = type { double, double } define i32 @stp_sequence_set_short_data(%struct.stp_sequence* %sequence, i32 %count, i16* %data) { diff --git a/test/CodeGen/PowerPC/ppcf128-4.ll b/test/CodeGen/PowerPC/ppcf128-4.ll index 13c08ce7f9f4d..67fcf46147fe3 100644 --- a/test/CodeGen/PowerPC/ppcf128-4.ll +++ b/test/CodeGen/PowerPC/ppcf128-4.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- define ppc_fp128 @__floatditf(i64 %u) nounwind { entry: diff --git a/test/CodeGen/PowerPC/pr17168.ll b/test/CodeGen/PowerPC/pr17168.ll index e29a058370201..7cfe2681a5ce5 100644 --- a/test/CodeGen/PowerPC/pr17168.ll +++ b/test/CodeGen/PowerPC/pr17168.ll @@ -57,7 +57,7 @@ attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!7} !llvm.module.flags = !{!261, !262} -!0 = !DIGlobalVariableExpression(var: !1) +!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) !1 = !DIGlobalVariable(name: "grid_points", scope: null, file: !2, line: 28, type: !3, isLocal: true, isDefinition: true) !2 = !DIFile(filename: "./header.h", directory: "/home/hfinkel/src/NPB2.3-omp-C/BT") !3 = !DICompositeType(tag: DW_TAG_array_type, baseType: !4, size: 96, align: 32, elements: !5) @@ -68,255 +68,255 @@ attributes #1 = { nounwind readnone } !8 = !DIFile(filename: "bt.c", directory: "/home/hfinkel/src/NPB2.3-omp-C/BT") !9 = !{} !10 = !{!0, !11, !14, !20, !22, !24, !26, !28, !30, !32, !34, !36, !38, !40, !42, !44, !46, !48, !50, !52, !54, !56, !58, !60, !62, !64, !66, !68, !70, !72, !74, !76, !78, !80, !82, !84, !86, !88, !93, !97, !99, !101, !103, !105, !107, !109, !114, !116, !118, !120, !122, !124, !126, !128, !130, !132, !134, !136, !138, !140, !142, !144, !146, !148, !150, !152, !154, !156, !158, !160, !162, !164, !166, !168, !170, !172, !174, !176, !178, !180, !182, !184, !186, !188, !190, !192, !194, !196, !198, !200, !202, !204, !206, !208, !210, !212, !214, !216, !218, !220, !222, !224, !226, !228, !230, !232, !236, !241, !243, !247, !249, !253, !255, !257, !259} -!11 = !DIGlobalVariableExpression(var: !12) +!11 = !DIGlobalVariableExpression(var: !12, expr: !DIExpression()) !12 = !DIGlobalVariable(name: "dt", scope: null, file: !2, line: 35, type: !13, isLocal: true, isDefinition: true) !13 = !DIBasicType(name: "double", size: 64, align: 64, encoding: DW_ATE_float) -!14 = !DIGlobalVariableExpression(var: !15) +!14 = !DIGlobalVariableExpression(var: !15, expr: !DIExpression()) !15 = !DIGlobalVariable(name: "rhs", scope: null, file: !2, line: 68, type: !16, isLocal: true, isDefinition: true) !16 = !DICompositeType(tag: DW_TAG_array_type, baseType: !13, size: 1385839040, align: 64, elements: !17) !17 = !{!18, !18, !18, !19} !18 = !DISubrange(count: 163) !19 = !DISubrange(count: 5) -!20 = !DIGlobalVariableExpression(var: !21) +!20 = !DIGlobalVariableExpression(var: !21, expr: !DIExpression()) !21 = !DIGlobalVariable(name: "zzcon5", scope: null, file: !2, line: 42, type: !13, isLocal: true, isDefinition: true) -!22 = !DIGlobalVariableExpression(var: !23) +!22 = !DIGlobalVariableExpression(var: !23, expr: !DIExpression()) !23 = !DIGlobalVariable(name: "zzcon4", scope: null, file: !2, line: 42, type: !13, isLocal: true, isDefinition: true) -!24 = !DIGlobalVariableExpression(var: !25) +!24 = !DIGlobalVariableExpression(var: !25, expr: !DIExpression()) !25 = !DIGlobalVariable(name: "zzcon3", scope: null, file: !2, line: 42, type: !13, isLocal: true, isDefinition: true) -!26 = !DIGlobalVariableExpression(var: !27) +!26 = !DIGlobalVariableExpression(var: !27, expr: !DIExpression()) !27 = !DIGlobalVariable(name: "dz5tz1", scope: null, file: !2, line: 43, type: !13, isLocal: true, isDefinition: true) -!28 = !DIGlobalVariableExpression(var: !29) +!28 = !DIGlobalVariableExpression(var: !29, expr: !DIExpression()) !29 = !DIGlobalVariable(name: "dz4tz1", scope: null, file: !2, line: 43, type: !13, isLocal: true, isDefinition: true) -!30 = !DIGlobalVariableExpression(var: !31) +!30 = !DIGlobalVariableExpression(var: !31, expr: !DIExpression()) !31 = !DIGlobalVariable(name: "dz3tz1", scope: null, file: !2, line: 43, type: !13, isLocal: true, isDefinition: true) -!32 = !DIGlobalVariableExpression(var: !33) +!32 = !DIGlobalVariableExpression(var: !33, expr: !DIExpression()) !33 = !DIGlobalVariable(name: "zzcon2", scope: null, file: !2, line: 42, type: !13, isLocal: true, isDefinition: true) -!34 = !DIGlobalVariableExpression(var: !35) +!34 = !DIGlobalVariableExpression(var: !35, expr: !DIExpression()) !35 = !DIGlobalVariable(name: "dz2tz1", scope: null, file: !2, line: 43, type: !13, isLocal: true, isDefinition: true) -!36 = !DIGlobalVariableExpression(var: !37) +!36 = !DIGlobalVariableExpression(var: !37, expr: !DIExpression()) !37 = !DIGlobalVariable(name: "tz2", scope: null, file: !2, line: 31, type: !13, isLocal: true, isDefinition: true) -!38 = !DIGlobalVariableExpression(var: !39) +!38 = !DIGlobalVariableExpression(var: !39, expr: !DIExpression()) !39 = !DIGlobalVariable(name: "dz1tz1", scope: null, file: !2, line: 43, type: !13, isLocal: true, isDefinition: true) -!40 = !DIGlobalVariableExpression(var: !41) +!40 = !DIGlobalVariableExpression(var: !41, expr: !DIExpression()) !41 = !DIGlobalVariable(name: "yycon5", scope: null, file: !2, line: 40, type: !13, isLocal: true, isDefinition: true) -!42 = !DIGlobalVariableExpression(var: !43) +!42 = !DIGlobalVariableExpression(var: !43, expr: !DIExpression()) !43 = !DIGlobalVariable(name: "yycon4", scope: null, file: !2, line: 40, type: !13, isLocal: true, isDefinition: true) -!44 = !DIGlobalVariableExpression(var: !45) +!44 = !DIGlobalVariableExpression(var: !45, expr: !DIExpression()) !45 = !DIGlobalVariable(name: "yycon3", scope: null, file: !2, line: 40, type: !13, isLocal: true, isDefinition: true) -!46 = !DIGlobalVariableExpression(var: !47) +!46 = !DIGlobalVariableExpression(var: !47, expr: !DIExpression()) !47 = !DIGlobalVariable(name: "dy5ty1", scope: null, file: !2, line: 41, type: !13, isLocal: true, isDefinition: true) -!48 = !DIGlobalVariableExpression(var: !49) +!48 = !DIGlobalVariableExpression(var: !49, expr: !DIExpression()) !49 = !DIGlobalVariable(name: "dy4ty1", scope: null, file: !2, line: 41, type: !13, isLocal: true, isDefinition: true) -!50 = !DIGlobalVariableExpression(var: !51) +!50 = !DIGlobalVariableExpression(var: !51, expr: !DIExpression()) !51 = !DIGlobalVariable(name: "dy3ty1", scope: null, file: !2, line: 41, type: !13, isLocal: true, isDefinition: true) -!52 = !DIGlobalVariableExpression(var: !53) +!52 = !DIGlobalVariableExpression(var: !53, expr: !DIExpression()) !53 = !DIGlobalVariable(name: "yycon2", scope: null, file: !2, line: 40, type: !13, isLocal: true, isDefinition: true) -!54 = !DIGlobalVariableExpression(var: !55) +!54 = !DIGlobalVariableExpression(var: !55, expr: !DIExpression()) !55 = !DIGlobalVariable(name: "dy2ty1", scope: null, file: !2, line: 41, type: !13, isLocal: true, isDefinition: true) -!56 = !DIGlobalVariableExpression(var: !57) +!56 = !DIGlobalVariableExpression(var: !57, expr: !DIExpression()) !57 = !DIGlobalVariable(name: "ty2", scope: null, file: !2, line: 31, type: !13, isLocal: true, isDefinition: true) -!58 = !DIGlobalVariableExpression(var: !59) +!58 = !DIGlobalVariableExpression(var: !59, expr: !DIExpression()) !59 = !DIGlobalVariable(name: "dy1ty1", scope: null, file: !2, line: 41, type: !13, isLocal: true, isDefinition: true) -!60 = !DIGlobalVariableExpression(var: !61) +!60 = !DIGlobalVariableExpression(var: !61, expr: !DIExpression()) !61 = !DIGlobalVariable(name: "dssp", scope: null, file: !2, line: 35, type: !13, isLocal: true, isDefinition: true) -!62 = !DIGlobalVariableExpression(var: !63) +!62 = !DIGlobalVariableExpression(var: !63, expr: !DIExpression()) !63 = !DIGlobalVariable(name: "c1", scope: null, file: !2, line: 45, type: !13, isLocal: true, isDefinition: true) -!64 = !DIGlobalVariableExpression(var: !65) +!64 = !DIGlobalVariableExpression(var: !65, expr: !DIExpression()) !65 = !DIGlobalVariable(name: "xxcon5", scope: null, file: !2, line: 38, type: !13, isLocal: true, isDefinition: true) -!66 = !DIGlobalVariableExpression(var: !67) +!66 = !DIGlobalVariableExpression(var: !67, expr: !DIExpression()) !67 = !DIGlobalVariable(name: "xxcon4", scope: null, file: !2, line: 38, type: !13, isLocal: true, isDefinition: true) -!68 = !DIGlobalVariableExpression(var: !69) +!68 = !DIGlobalVariableExpression(var: !69, expr: !DIExpression()) !69 = !DIGlobalVariable(name: "xxcon3", scope: null, file: !2, line: 38, type: !13, isLocal: true, isDefinition: true) -!70 = !DIGlobalVariableExpression(var: !71) +!70 = !DIGlobalVariableExpression(var: !71, expr: !DIExpression()) !71 = !DIGlobalVariable(name: "dx5tx1", scope: null, file: !2, line: 39, type: !13, isLocal: true, isDefinition: true) -!72 = !DIGlobalVariableExpression(var: !73) +!72 = !DIGlobalVariableExpression(var: !73, expr: !DIExpression()) !73 = !DIGlobalVariable(name: "dx4tx1", scope: null, file: !2, line: 39, type: !13, isLocal: true, isDefinition: true) -!74 = !DIGlobalVariableExpression(var: !75) +!74 = !DIGlobalVariableExpression(var: !75, expr: !DIExpression()) !75 = !DIGlobalVariable(name: "dx3tx1", scope: null, file: !2, line: 39, type: !13, isLocal: true, isDefinition: true) -!76 = !DIGlobalVariableExpression(var: !77) +!76 = !DIGlobalVariableExpression(var: !77, expr: !DIExpression()) !77 = !DIGlobalVariable(name: "c2", scope: null, file: !2, line: 45, type: !13, isLocal: true, isDefinition: true) -!78 = !DIGlobalVariableExpression(var: !79) +!78 = !DIGlobalVariableExpression(var: !79, expr: !DIExpression()) !79 = !DIGlobalVariable(name: "con43", scope: null, file: !2, line: 48, type: !13, isLocal: true, isDefinition: true) -!80 = !DIGlobalVariableExpression(var: !81) +!80 = !DIGlobalVariableExpression(var: !81, expr: !DIExpression()) !81 = !DIGlobalVariable(name: "xxcon2", scope: null, file: !2, line: 38, type: !13, isLocal: true, isDefinition: true) -!82 = !DIGlobalVariableExpression(var: !83) +!82 = !DIGlobalVariableExpression(var: !83, expr: !DIExpression()) !83 = !DIGlobalVariable(name: "dx2tx1", scope: null, file: !2, line: 39, type: !13, isLocal: true, isDefinition: true) -!84 = !DIGlobalVariableExpression(var: !85) +!84 = !DIGlobalVariableExpression(var: !85, expr: !DIExpression()) !85 = !DIGlobalVariable(name: "tx2", scope: null, file: !2, line: 31, type: !13, isLocal: true, isDefinition: true) -!86 = !DIGlobalVariableExpression(var: !87) +!86 = !DIGlobalVariableExpression(var: !87, expr: !DIExpression()) !87 = !DIGlobalVariable(name: "dx1tx1", scope: null, file: !2, line: 39, type: !13, isLocal: true, isDefinition: true) -!88 = !DIGlobalVariableExpression(var: !89) +!88 = !DIGlobalVariableExpression(var: !89, expr: !DIExpression()) !89 = !DIGlobalVariable(name: "forcing", scope: null, file: !2, line: 66, type: !90, isLocal: true, isDefinition: true) !90 = !DICompositeType(tag: DW_TAG_array_type, baseType: !13, size: 1663006848, align: 64, elements: !91) !91 = !{!18, !18, !18, !92} !92 = !DISubrange(count: 6) -!93 = !DIGlobalVariableExpression(var: !94) +!93 = !DIGlobalVariableExpression(var: !94, expr: !DIExpression()) !94 = !DIGlobalVariable(name: "qs", scope: null, file: !2, line: 63, type: !95, isLocal: true, isDefinition: true) !95 = !DICompositeType(tag: DW_TAG_array_type, baseType: !13, size: 277167808, align: 64, elements: !96) !96 = !{!18, !18, !18} -!97 = !DIGlobalVariableExpression(var: !98) +!97 = !DIGlobalVariableExpression(var: !98, expr: !DIExpression()) !98 = !DIGlobalVariable(name: "square", scope: null, file: !2, line: 65, type: !95, isLocal: true, isDefinition: true) -!99 = !DIGlobalVariableExpression(var: !100) +!99 = !DIGlobalVariableExpression(var: !100, expr: !DIExpression()) !100 = !DIGlobalVariable(name: "ws", scope: null, file: !2, line: 62, type: !95, isLocal: true, isDefinition: true) -!101 = !DIGlobalVariableExpression(var: !102) +!101 = !DIGlobalVariableExpression(var: !102, expr: !DIExpression()) !102 = !DIGlobalVariable(name: "vs", scope: null, file: !2, line: 61, type: !95, isLocal: true, isDefinition: true) -!103 = !DIGlobalVariableExpression(var: !104) +!103 = !DIGlobalVariableExpression(var: !104, expr: !DIExpression()) !104 = !DIGlobalVariable(name: "us", scope: null, file: !2, line: 60, type: !95, isLocal: true, isDefinition: true) -!105 = !DIGlobalVariableExpression(var: !106) +!105 = !DIGlobalVariableExpression(var: !106, expr: !DIExpression()) !106 = !DIGlobalVariable(name: "rho_i", scope: null, file: !2, line: 64, type: !95, isLocal: true, isDefinition: true) -!107 = !DIGlobalVariableExpression(var: !108) +!107 = !DIGlobalVariableExpression(var: !108, expr: !DIExpression()) !108 = !DIGlobalVariable(name: "u", scope: null, file: !2, line: 67, type: !16, isLocal: true, isDefinition: true) -!109 = !DIGlobalVariableExpression(var: !110) +!109 = !DIGlobalVariableExpression(var: !110, expr: !DIExpression()) !110 = !DIGlobalVariable(name: "ce", scope: null, file: !2, line: 36, type: !111, isLocal: true, isDefinition: true) !111 = !DICompositeType(tag: DW_TAG_array_type, baseType: !13, size: 4160, align: 64, elements: !112) !112 = !{!19, !113} !113 = !DISubrange(count: 13) -!114 = !DIGlobalVariableExpression(var: !115) +!114 = !DIGlobalVariableExpression(var: !115, expr: !DIExpression()) !115 = !DIGlobalVariable(name: "dnzm1", scope: null, file: !2, line: 44, type: !13, isLocal: true, isDefinition: true) -!116 = !DIGlobalVariableExpression(var: !117) +!116 = !DIGlobalVariableExpression(var: !117, expr: !DIExpression()) !117 = !DIGlobalVariable(name: "dnym1", scope: null, file: !2, line: 44, type: !13, isLocal: true, isDefinition: true) -!118 = !DIGlobalVariableExpression(var: !119) +!118 = !DIGlobalVariableExpression(var: !119, expr: !DIExpression()) !119 = !DIGlobalVariable(name: "dnxm1", scope: null, file: !2, line: 44, type: !13, isLocal: true, isDefinition: true) -!120 = !DIGlobalVariableExpression(var: !121) +!120 = !DIGlobalVariableExpression(var: !121, expr: !DIExpression()) !121 = !DIGlobalVariable(name: "zzcon1", scope: null, file: !2, line: 42, type: !13, isLocal: true, isDefinition: true) -!122 = !DIGlobalVariableExpression(var: !123) +!122 = !DIGlobalVariableExpression(var: !123, expr: !DIExpression()) !123 = !DIGlobalVariable(name: "yycon1", scope: null, file: !2, line: 40, type: !13, isLocal: true, isDefinition: true) -!124 = !DIGlobalVariableExpression(var: !125) +!124 = !DIGlobalVariableExpression(var: !125, expr: !DIExpression()) !125 = !DIGlobalVariable(name: "xxcon1", scope: null, file: !2, line: 38, type: !13, isLocal: true, isDefinition: true) -!126 = !DIGlobalVariableExpression(var: !127) +!126 = !DIGlobalVariableExpression(var: !127, expr: !DIExpression()) !127 = !DIGlobalVariable(name: "con16", scope: null, file: !2, line: 48, type: !13, isLocal: true, isDefinition: true) -!128 = !DIGlobalVariableExpression(var: !129) +!128 = !DIGlobalVariableExpression(var: !129, expr: !DIExpression()) !129 = !DIGlobalVariable(name: "c2iv", scope: null, file: !2, line: 48, type: !13, isLocal: true, isDefinition: true) -!130 = !DIGlobalVariableExpression(var: !131) +!130 = !DIGlobalVariableExpression(var: !131, expr: !DIExpression()) !131 = !DIGlobalVariable(name: "c3c4tz3", scope: null, file: !2, line: 48, type: !13, isLocal: true, isDefinition: true) -!132 = !DIGlobalVariableExpression(var: !133) +!132 = !DIGlobalVariableExpression(var: !133, expr: !DIExpression()) !133 = !DIGlobalVariable(name: "c3c4ty3", scope: null, file: !2, line: 48, type: !13, isLocal: true, isDefinition: true) -!134 = !DIGlobalVariableExpression(var: !135) +!134 = !DIGlobalVariableExpression(var: !135, expr: !DIExpression()) !135 = !DIGlobalVariable(name: "c3c4tx3", scope: null, file: !2, line: 48, type: !13, isLocal: true, isDefinition: true) -!136 = !DIGlobalVariableExpression(var: !137) +!136 = !DIGlobalVariableExpression(var: !137, expr: !DIExpression()) !137 = !DIGlobalVariable(name: "comz6", scope: null, file: !2, line: 47, type: !13, isLocal: true, isDefinition: true) -!138 = !DIGlobalVariableExpression(var: !139) +!138 = !DIGlobalVariableExpression(var: !139, expr: !DIExpression()) !139 = !DIGlobalVariable(name: "comz5", scope: null, file: !2, line: 47, type: !13, isLocal: true, isDefinition: true) -!140 = !DIGlobalVariableExpression(var: !141) +!140 = !DIGlobalVariableExpression(var: !141, expr: !DIExpression()) !141 = !DIGlobalVariable(name: "comz4", scope: null, file: !2, line: 47, type: !13, isLocal: true, isDefinition: true) -!142 = !DIGlobalVariableExpression(var: !143) +!142 = !DIGlobalVariableExpression(var: !143, expr: !DIExpression()) !143 = !DIGlobalVariable(name: "comz1", scope: null, file: !2, line: 47, type: !13, isLocal: true, isDefinition: true) -!144 = !DIGlobalVariableExpression(var: !145) +!144 = !DIGlobalVariableExpression(var: !145, expr: !DIExpression()) !145 = !DIGlobalVariable(name: "dtdssp", scope: null, file: !2, line: 45, type: !13, isLocal: true, isDefinition: true) -!146 = !DIGlobalVariableExpression(var: !147) +!146 = !DIGlobalVariableExpression(var: !147, expr: !DIExpression()) !147 = !DIGlobalVariable(name: "c2dttz1", scope: null, file: !2, line: 47, type: !13, isLocal: true, isDefinition: true) -!148 = !DIGlobalVariableExpression(var: !149) +!148 = !DIGlobalVariableExpression(var: !149, expr: !DIExpression()) !149 = !DIGlobalVariable(name: "c2dtty1", scope: null, file: !2, line: 47, type: !13, isLocal: true, isDefinition: true) -!150 = !DIGlobalVariableExpression(var: !151) +!150 = !DIGlobalVariableExpression(var: !151, expr: !DIExpression()) !151 = !DIGlobalVariable(name: "c2dttx1", scope: null, file: !2, line: 47, type: !13, isLocal: true, isDefinition: true) -!152 = !DIGlobalVariableExpression(var: !153) +!152 = !DIGlobalVariableExpression(var: !153, expr: !DIExpression()) !153 = !DIGlobalVariable(name: "dttz2", scope: null, file: !2, line: 46, type: !13, isLocal: true, isDefinition: true) -!154 = !DIGlobalVariableExpression(var: !155) +!154 = !DIGlobalVariableExpression(var: !155, expr: !DIExpression()) !155 = !DIGlobalVariable(name: "dttz1", scope: null, file: !2, line: 46, type: !13, isLocal: true, isDefinition: true) -!156 = !DIGlobalVariableExpression(var: !157) +!156 = !DIGlobalVariableExpression(var: !157, expr: !DIExpression()) !157 = !DIGlobalVariable(name: "dtty2", scope: null, file: !2, line: 46, type: !13, isLocal: true, isDefinition: true) -!158 = !DIGlobalVariableExpression(var: !159) +!158 = !DIGlobalVariableExpression(var: !159, expr: !DIExpression()) !159 = !DIGlobalVariable(name: "dtty1", scope: null, file: !2, line: 46, type: !13, isLocal: true, isDefinition: true) -!160 = !DIGlobalVariableExpression(var: !161) +!160 = !DIGlobalVariableExpression(var: !161, expr: !DIExpression()) !161 = !DIGlobalVariable(name: "dttx2", scope: null, file: !2, line: 46, type: !13, isLocal: true, isDefinition: true) -!162 = !DIGlobalVariableExpression(var: !163) +!162 = !DIGlobalVariableExpression(var: !163, expr: !DIExpression()) !163 = !DIGlobalVariable(name: "dttx1", scope: null, file: !2, line: 46, type: !13, isLocal: true, isDefinition: true) -!164 = !DIGlobalVariableExpression(var: !165) +!164 = !DIGlobalVariableExpression(var: !165, expr: !DIExpression()) !165 = !DIGlobalVariable(name: "c5dssp", scope: null, file: !2, line: 45, type: !13, isLocal: true, isDefinition: true) -!166 = !DIGlobalVariableExpression(var: !167) +!166 = !DIGlobalVariableExpression(var: !167, expr: !DIExpression()) !167 = !DIGlobalVariable(name: "c4dssp", scope: null, file: !2, line: 45, type: !13, isLocal: true, isDefinition: true) -!168 = !DIGlobalVariableExpression(var: !169) +!168 = !DIGlobalVariableExpression(var: !169, expr: !DIExpression()) !169 = !DIGlobalVariable(name: "dzmax", scope: null, file: !2, line: 37, type: !13, isLocal: true, isDefinition: true) -!170 = !DIGlobalVariableExpression(var: !171) +!170 = !DIGlobalVariableExpression(var: !171, expr: !DIExpression()) !171 = !DIGlobalVariable(name: "dymax", scope: null, file: !2, line: 37, type: !13, isLocal: true, isDefinition: true) -!172 = !DIGlobalVariableExpression(var: !173) +!172 = !DIGlobalVariableExpression(var: !173, expr: !DIExpression()) !173 = !DIGlobalVariable(name: "dxmax", scope: null, file: !2, line: 37, type: !13, isLocal: true, isDefinition: true) -!174 = !DIGlobalVariableExpression(var: !175) +!174 = !DIGlobalVariableExpression(var: !175, expr: !DIExpression()) !175 = !DIGlobalVariable(name: "dz5", scope: null, file: !2, line: 34, type: !13, isLocal: true, isDefinition: true) -!176 = !DIGlobalVariableExpression(var: !177) +!176 = !DIGlobalVariableExpression(var: !177, expr: !DIExpression()) !177 = !DIGlobalVariable(name: "dz4", scope: null, file: !2, line: 34, type: !13, isLocal: true, isDefinition: true) -!178 = !DIGlobalVariableExpression(var: !179) +!178 = !DIGlobalVariableExpression(var: !179, expr: !DIExpression()) !179 = !DIGlobalVariable(name: "dz3", scope: null, file: !2, line: 34, type: !13, isLocal: true, isDefinition: true) -!180 = !DIGlobalVariableExpression(var: !181) +!180 = !DIGlobalVariableExpression(var: !181, expr: !DIExpression()) !181 = !DIGlobalVariable(name: "dz2", scope: null, file: !2, line: 34, type: !13, isLocal: true, isDefinition: true) -!182 = !DIGlobalVariableExpression(var: !183) +!182 = !DIGlobalVariableExpression(var: !183, expr: !DIExpression()) !183 = !DIGlobalVariable(name: "dz1", scope: null, file: !2, line: 34, type: !13, isLocal: true, isDefinition: true) -!184 = !DIGlobalVariableExpression(var: !185) +!184 = !DIGlobalVariableExpression(var: !185, expr: !DIExpression()) !185 = !DIGlobalVariable(name: "dy5", scope: null, file: !2, line: 33, type: !13, isLocal: true, isDefinition: true) -!186 = !DIGlobalVariableExpression(var: !187) +!186 = !DIGlobalVariableExpression(var: !187, expr: !DIExpression()) !187 = !DIGlobalVariable(name: "dy4", scope: null, file: !2, line: 33, type: !13, isLocal: true, isDefinition: true) -!188 = !DIGlobalVariableExpression(var: !189) +!188 = !DIGlobalVariableExpression(var: !189, expr: !DIExpression()) !189 = !DIGlobalVariable(name: "dy3", scope: null, file: !2, line: 33, type: !13, isLocal: true, isDefinition: true) -!190 = !DIGlobalVariableExpression(var: !191) +!190 = !DIGlobalVariableExpression(var: !191, expr: !DIExpression()) !191 = !DIGlobalVariable(name: "dy2", scope: null, file: !2, line: 33, type: !13, isLocal: true, isDefinition: true) -!192 = !DIGlobalVariableExpression(var: !193) +!192 = !DIGlobalVariableExpression(var: !193, expr: !DIExpression()) !193 = !DIGlobalVariable(name: "dy1", scope: null, file: !2, line: 33, type: !13, isLocal: true, isDefinition: true) -!194 = !DIGlobalVariableExpression(var: !195) +!194 = !DIGlobalVariableExpression(var: !195, expr: !DIExpression()) !195 = !DIGlobalVariable(name: "dx5", scope: null, file: !2, line: 32, type: !13, isLocal: true, isDefinition: true) -!196 = !DIGlobalVariableExpression(var: !197) +!196 = !DIGlobalVariableExpression(var: !197, expr: !DIExpression()) !197 = !DIGlobalVariable(name: "dx4", scope: null, file: !2, line: 32, type: !13, isLocal: true, isDefinition: true) -!198 = !DIGlobalVariableExpression(var: !199) +!198 = !DIGlobalVariableExpression(var: !199, expr: !DIExpression()) !199 = !DIGlobalVariable(name: "dx3", scope: null, file: !2, line: 32, type: !13, isLocal: true, isDefinition: true) -!200 = !DIGlobalVariableExpression(var: !201) +!200 = !DIGlobalVariableExpression(var: !201, expr: !DIExpression()) !201 = !DIGlobalVariable(name: "dx2", scope: null, file: !2, line: 32, type: !13, isLocal: true, isDefinition: true) -!202 = !DIGlobalVariableExpression(var: !203) +!202 = !DIGlobalVariableExpression(var: !203, expr: !DIExpression()) !203 = !DIGlobalVariable(name: "dx1", scope: null, file: !2, line: 32, type: !13, isLocal: true, isDefinition: true) -!204 = !DIGlobalVariableExpression(var: !205) +!204 = !DIGlobalVariableExpression(var: !205, expr: !DIExpression()) !205 = !DIGlobalVariable(name: "tz3", scope: null, file: !2, line: 31, type: !13, isLocal: true, isDefinition: true) -!206 = !DIGlobalVariableExpression(var: !207) +!206 = !DIGlobalVariableExpression(var: !207, expr: !DIExpression()) !207 = !DIGlobalVariable(name: "tz1", scope: null, file: !2, line: 31, type: !13, isLocal: true, isDefinition: true) -!208 = !DIGlobalVariableExpression(var: !209) +!208 = !DIGlobalVariableExpression(var: !209, expr: !DIExpression()) !209 = !DIGlobalVariable(name: "ty3", scope: null, file: !2, line: 31, type: !13, isLocal: true, isDefinition: true) -!210 = !DIGlobalVariableExpression(var: !211) +!210 = !DIGlobalVariableExpression(var: !211, expr: !DIExpression()) !211 = !DIGlobalVariable(name: "ty1", scope: null, file: !2, line: 31, type: !13, isLocal: true, isDefinition: true) -!212 = !DIGlobalVariableExpression(var: !213) +!212 = !DIGlobalVariableExpression(var: !213, expr: !DIExpression()) !213 = !DIGlobalVariable(name: "tx3", scope: null, file: !2, line: 31, type: !13, isLocal: true, isDefinition: true) -!214 = !DIGlobalVariableExpression(var: !215) +!214 = !DIGlobalVariableExpression(var: !215, expr: !DIExpression()) !215 = !DIGlobalVariable(name: "tx1", scope: null, file: !2, line: 31, type: !13, isLocal: true, isDefinition: true) -!216 = !DIGlobalVariableExpression(var: !217) +!216 = !DIGlobalVariableExpression(var: !217, expr: !DIExpression()) !217 = !DIGlobalVariable(name: "conz1", scope: null, file: !2, line: 45, type: !13, isLocal: true, isDefinition: true) -!218 = !DIGlobalVariableExpression(var: !219) +!218 = !DIGlobalVariableExpression(var: !219, expr: !DIExpression()) !219 = !DIGlobalVariable(name: "c1345", scope: null, file: !2, line: 44, type: !13, isLocal: true, isDefinition: true) -!220 = !DIGlobalVariableExpression(var: !221) +!220 = !DIGlobalVariableExpression(var: !221, expr: !DIExpression()) !221 = !DIGlobalVariable(name: "c3c4", scope: null, file: !2, line: 44, type: !13, isLocal: true, isDefinition: true) -!222 = !DIGlobalVariableExpression(var: !223) +!222 = !DIGlobalVariableExpression(var: !223, expr: !DIExpression()) !223 = !DIGlobalVariable(name: "c1c5", scope: null, file: !2, line: 44, type: !13, isLocal: true, isDefinition: true) -!224 = !DIGlobalVariableExpression(var: !225) +!224 = !DIGlobalVariableExpression(var: !225, expr: !DIExpression()) !225 = !DIGlobalVariable(name: "c1c2", scope: null, file: !2, line: 44, type: !13, isLocal: true, isDefinition: true) -!226 = !DIGlobalVariableExpression(var: !227) +!226 = !DIGlobalVariableExpression(var: !227, expr: !DIExpression()) !227 = !DIGlobalVariable(name: "c5", scope: null, file: !2, line: 45, type: !13, isLocal: true, isDefinition: true) -!228 = !DIGlobalVariableExpression(var: !229) +!228 = !DIGlobalVariableExpression(var: !229, expr: !DIExpression()) !229 = !DIGlobalVariable(name: "c4", scope: null, file: !2, line: 45, type: !13, isLocal: true, isDefinition: true) -!230 = !DIGlobalVariableExpression(var: !231) +!230 = !DIGlobalVariableExpression(var: !231, expr: !DIExpression()) !231 = !DIGlobalVariable(name: "c3", scope: null, file: !2, line: 45, type: !13, isLocal: true, isDefinition: true) -!232 = !DIGlobalVariableExpression(var: !233) +!232 = !DIGlobalVariableExpression(var: !233, expr: !DIExpression()) !233 = !DIGlobalVariable(name: "lhs", scope: null, file: !2, line: 69, type: !234, isLocal: true, isDefinition: true) !234 = !DICompositeType(tag: DW_TAG_array_type, baseType: !13, size: 20787585600, align: 64, elements: !235) !235 = !{!18, !18, !18, !6, !19, !19} -!236 = !DIGlobalVariableExpression(var: !237) +!236 = !DIGlobalVariableExpression(var: !237, expr: !DIExpression()) !237 = !DIGlobalVariable(name: "q", scope: null, file: !2, line: 73, type: !238, isLocal: true, isDefinition: true) !238 = !DICompositeType(tag: DW_TAG_array_type, baseType: !13, size: 10368, align: 64, elements: !239) !239 = !{!240} !240 = !DISubrange(count: 162) -!241 = !DIGlobalVariableExpression(var: !242) +!241 = !DIGlobalVariableExpression(var: !242, expr: !DIExpression()) !242 = !DIGlobalVariable(name: "cuf", scope: null, file: !2, line: 72, type: !238, isLocal: true, isDefinition: true) -!243 = !DIGlobalVariableExpression(var: !244) +!243 = !DIGlobalVariableExpression(var: !244, expr: !DIExpression()) !244 = !DIGlobalVariable(name: "buf", scope: null, file: !2, line: 75, type: !245, isLocal: true, isDefinition: true) !245 = !DICompositeType(tag: DW_TAG_array_type, baseType: !13, size: 51840, align: 64, elements: !246) !246 = !{!240, !19} -!247 = !DIGlobalVariableExpression(var: !248) +!247 = !DIGlobalVariableExpression(var: !248, expr: !DIExpression()) !248 = !DIGlobalVariable(name: "ue", scope: null, file: !2, line: 74, type: !245, isLocal: true, isDefinition: true) -!249 = !DIGlobalVariableExpression(var: !250) +!249 = !DIGlobalVariableExpression(var: !250, expr: !DIExpression()) !250 = !DIGlobalVariable(name: "njac", scope: null, file: !2, line: 86, type: !251, isLocal: true, isDefinition: true) !251 = !DICompositeType(tag: DW_TAG_array_type, baseType: !13, size: 6886684800, align: 64, elements: !252) !252 = !{!18, !18, !240, !19, !19} -!253 = !DIGlobalVariableExpression(var: !254) +!253 = !DIGlobalVariableExpression(var: !254, expr: !DIExpression()) !254 = !DIGlobalVariable(name: "fjac", scope: null, file: !2, line: 84, type: !251, isLocal: true, isDefinition: true) -!255 = !DIGlobalVariableExpression(var: !256) +!255 = !DIGlobalVariableExpression(var: !256, expr: !DIExpression()) !256 = !DIGlobalVariable(name: "tmp3", scope: null, file: !2, line: 88, type: !13, isLocal: true, isDefinition: true) -!257 = !DIGlobalVariableExpression(var: !258) +!257 = !DIGlobalVariableExpression(var: !258, expr: !DIExpression()) !258 = !DIGlobalVariable(name: "tmp2", scope: null, file: !2, line: 88, type: !13, isLocal: true, isDefinition: true) -!259 = !DIGlobalVariableExpression(var: !260) +!259 = !DIGlobalVariableExpression(var: !260, expr: !DIExpression()) !260 = !DIGlobalVariable(name: "tmp1", scope: null, file: !2, line: 88, type: !13, isLocal: true, isDefinition: true) !261 = !{i32 2, !"Dwarf Version", i32 4} !262 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/PowerPC/pr18663-2.ll b/test/CodeGen/PowerPC/pr18663-2.ll index 1bd76115605cd..40d6036a99f6e 100644 --- a/test/CodeGen/PowerPC/pr18663-2.ll +++ b/test/CodeGen/PowerPC/pr18663-2.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mtriple=powerpc64-unknown-linux-gnu -; RUN: llc -verify-machineinstrs < %s -march=ppc64le -mtriple=powerpc64le-unknown-linux-gnu +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu %"class.std::__1::locale::id.1580.4307.4610.8491" = type { %"struct.std::__1::once_flag.1579.4306.4609.8490", i32 } %"struct.std::__1::once_flag.1579.4306.4609.8490" = type { i64 } diff --git a/test/CodeGen/PowerPC/pr18663.ll b/test/CodeGen/PowerPC/pr18663.ll index bbfbca9a65bb0..331870e456f33 100644 --- a/test/CodeGen/PowerPC/pr18663.ll +++ b/test/CodeGen/PowerPC/pr18663.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mtriple=powerpc64-unknown-linux-gnu -; RUN: llc -verify-machineinstrs < %s -march=ppc64le -mtriple=powerpc64le-unknown-linux-gnu +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu %class.Point.1 = type { %class.Tensor.0 } %class.Tensor.0 = type { [3 x double] } diff --git a/test/CodeGen/PowerPC/pr24546.ll b/test/CodeGen/PowerPC/pr24546.ll index c914dd0dd225e..19da0db593a27 100644 --- a/test/CodeGen/PowerPC/pr24546.ll +++ b/test/CodeGen/PowerPC/pr24546.ll @@ -79,7 +79,7 @@ attributes #3 = { nounwind } !21 = !{!22} !22 = !DILocalVariable(name: "power", arg: 1, scope: !18, file: !1, line: 1, type: !9) !23 = !{!24} -!24 = !DIGlobalVariableExpression(var: !DIGlobalVariable(name: "powers", scope: !18, file: !1, line: 3, type: !25, isLocal: true, isDefinition: true)) +!24 = !DIGlobalVariableExpression(var: !DIGlobalVariable(name: "powers", scope: !18, file: !1, line: 3, type: !25, isLocal: true, isDefinition: true), expr: !DIExpression()) !25 = !DICompositeType(tag: DW_TAG_array_type, baseType: !26, size: 1472, align: 64, elements: !27) !26 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !4) !27 = !{!28} diff --git a/test/CodeGen/PowerPC/pr25157-peephole.ll b/test/CodeGen/PowerPC/pr25157-peephole.ll index aacd64e401f5f..02301ea402819 100644 --- a/test/CodeGen/PowerPC/pr25157-peephole.ll +++ b/test/CodeGen/PowerPC/pr25157-peephole.ll @@ -57,7 +57,7 @@ L.LB38_2452: } ; CHECK-LABEL: @aercalc_ -; CHECK: lxsspx +; CHECK: lfsx ; CHECK: xxspltd ; CHECK: stxvd2x ; CHECK-NOT: xxswapd diff --git a/test/CodeGen/PowerPC/pr25157.ll b/test/CodeGen/PowerPC/pr25157.ll index ee9a0034f2cb8..27f50b0f8e6a5 100644 --- a/test/CodeGen/PowerPC/pr25157.ll +++ b/test/CodeGen/PowerPC/pr25157.ll @@ -57,6 +57,6 @@ L.LB38_2452: } ; CHECK-LABEL: @aercalc_ -; CHECK: lxsspx +; CHECK: lfsx ; CHECK-P9-LABEL: @aercalc_ ; CHECK-P9: lfs diff --git a/test/CodeGen/PowerPC/pr32140.ll b/test/CodeGen/PowerPC/pr32140.ll index 827a90404e4b1..3feb9bd9c9e19 100644 --- a/test/CodeGen/PowerPC/pr32140.ll +++ b/test/CodeGen/PowerPC/pr32140.ll @@ -9,7 +9,7 @@ define void @bswapStorei64Toi32() { ; CHECK-LABEL: bswapStorei64Toi32: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: lwa 3, 0(3) ; CHECK-NEXT: rldicl 3, 3, 32, 32 ; CHECK-NEXT: stwbrx 3, 0, 4 @@ -25,7 +25,7 @@ entry: define void @bswapStorei32Toi16() { ; CHECK-LABEL: bswapStorei32Toi16: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: lha 3, 0(3) ; CHECK-NEXT: srwi 3, 3, 16 ; CHECK-NEXT: sthbrx 3, 0, 4 @@ -41,7 +41,7 @@ entry: define void @bswapStorei64Toi16() { ; CHECK-LABEL: bswapStorei64Toi16: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: lha 3, 0(3) ; CHECK-NEXT: rldicl 3, 3, 16, 48 ; CHECK-NEXT: sthbrx 3, 0, 4 diff --git a/test/CodeGen/PowerPC/pr33093.ll b/test/CodeGen/PowerPC/pr33093.ll index 5212973f8317c..af0350e17fd92 100644 --- a/test/CodeGen/PowerPC/pr33093.ll +++ b/test/CodeGen/PowerPC/pr33093.ll @@ -4,7 +4,7 @@ define zeroext i32 @ReverseBits(i32 zeroext %n) { ; CHECK-LABEL: ReverseBits: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 5, 21845 ; CHECK-NEXT: slwi 6, 3, 1 @@ -68,7 +68,7 @@ entry: define i64 @ReverseBits64(i64 %n) { ; CHECK-LABEL: ReverseBits64: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 5, 21845 ; CHECK-NEXT: lis 6, -13108 @@ -91,38 +91,38 @@ define i64 @ReverseBits64(i64 %n) { ; CHECK-NEXT: and 4, 8, 4 ; CHECK-NEXT: lis 7, 3855 ; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: oris 12, 5, 52428 -; CHECK-NEXT: oris 9, 6, 13107 +; CHECK-NEXT: oris 9, 5, 52428 +; CHECK-NEXT: oris 10, 6, 13107 ; CHECK-NEXT: lis 6, -3856 ; CHECK-NEXT: ori 7, 7, 3855 ; CHECK-NEXT: sldi 8, 3, 2 -; CHECK-NEXT: ori 4, 12, 52428 +; CHECK-NEXT: ori 4, 9, 52428 ; CHECK-NEXT: rldicl 3, 3, 62, 2 -; CHECK-NEXT: ori 5, 9, 13107 +; CHECK-NEXT: ori 5, 10, 13107 ; CHECK-NEXT: ori 6, 6, 61680 ; CHECK-NEXT: and 3, 3, 5 ; CHECK-NEXT: sldi 5, 6, 32 ; CHECK-NEXT: and 4, 8, 4 ; CHECK-NEXT: sldi 6, 7, 32 ; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: oris 10, 5, 61680 -; CHECK-NEXT: oris 11, 6, 3855 +; CHECK-NEXT: oris 11, 5, 61680 +; CHECK-NEXT: oris 12, 6, 3855 ; CHECK-NEXT: sldi 6, 3, 4 -; CHECK-NEXT: ori 4, 10, 61680 +; CHECK-NEXT: ori 4, 11, 61680 ; CHECK-NEXT: rldicl 3, 3, 60, 4 -; CHECK-NEXT: ori 5, 11, 3855 +; CHECK-NEXT: ori 5, 12, 3855 ; CHECK-NEXT: and 4, 6, 4 ; CHECK-NEXT: and 3, 3, 5 ; CHECK-NEXT: or 3, 3, 4 +; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31 ; CHECK-NEXT: rldicl 4, 3, 32, 32 -; CHECK-NEXT: rlwinm 6, 3, 24, 0, 31 -; CHECK-NEXT: rlwinm 5, 4, 24, 0, 31 -; CHECK-NEXT: rlwimi 6, 3, 8, 8, 15 -; CHECK-NEXT: rlwimi 5, 4, 8, 8, 15 -; CHECK-NEXT: rlwimi 6, 3, 8, 24, 31 -; CHECK-NEXT: rlwimi 5, 4, 8, 24, 31 -; CHECK-NEXT: sldi 12, 5, 32 -; CHECK-NEXT: or 3, 12, 6 +; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31 +; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15 +; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15 +; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31 +; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31 +; CHECK-NEXT: sldi 3, 5, 32 +; CHECK-NEXT: or 3, 3, 6 ; CHECK-NEXT: blr entry: %shr = lshr i64 %n, 1 diff --git a/test/CodeGen/PowerPC/pr3711_widen_bit.ll b/test/CodeGen/PowerPC/pr3711_widen_bit.ll index da210b85d1af2..fc81efeeed99c 100644 --- a/test/CodeGen/PowerPC/pr3711_widen_bit.ll +++ b/test/CodeGen/PowerPC/pr3711_widen_bit.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 ; Test that causes a abort in expanding a bit convert due to a missing support ; for widening. diff --git a/test/CodeGen/PowerPC/preemption.ll b/test/CodeGen/PowerPC/preemption.ll new file mode 100644 index 0000000000000..5652f6d730a14 --- /dev/null +++ b/test/CodeGen/PowerPC/preemption.ll @@ -0,0 +1,301 @@ +; RUN: llc -mtriple powerpc64le-unkown-gnu-linux < %s | FileCheck %s +; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=static \ +; RUN: < %s | FileCheck --check-prefix=STATIC %s +; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=pic \ +; RUN: < %s | FileCheck %s + +; globals + +@strong_default = global i32 55 +define i32* @get_strong_default() #0 { + ret i32* @strong_default + +; STATIC-LABEL: @get_strong_default +; STATIC: addis 3, 2, strong_default@toc@ha +; STATIC: addi 3, 3, strong_default@toc@l +; STATIC: blr + +; CHECK-LABEL: @get_strong_default +; CHECK: addis 3, 2, .LC0@toc@ha +; CHECK: ld 3, .LC0@toc@l(3) +; CHECK: blr +} + +@weak_default = weak global i32 55 +define i32* @get_weak_default() #0 { + ret i32* @weak_default + +; STATIC-LABEL: @get_weak_default +; STATIC: addis 3, 2, weak_default@toc@ha +; STATIC: addi 3, 3, weak_default@toc@l +; STATIC: blr + +; CHECK-LABEL: @get_weak_default +; CHECK: addis 3, 2, .LC1@toc@ha +; CHECK: ld 3, .LC1@toc@l(3) +; CHECK: blr +} + +@external_default_global = external global i32 +define i32* @get_external_default_global() { + ret i32* @external_default_global + +; STATIC-LABEL: @get_external_default_global +; STATIC: addis 3, 2, .LC0@toc@ha +; STATIC: ld 3, .LC0@toc@l(3) +; STATIC: blr + +; CHECK-LABEL: @get_external_default_global +; CHECK: addis 3, 2, .LC2@toc@ha +; CHECK: ld 3, .LC2@toc@l(3) +; CHECK: blr +} + + +@strong_local_global = dso_local global i32 55 +define i32* @get_strong_local_global() { + ret i32* @strong_local_global + +; STATIC-LABEL: @get_strong_local_global +; STATIC: addis 3, 2, strong_local_global@toc@ha +; STATIC: addi 3, 3, strong_local_global@toc@l +; STATIC: blr + +; CHECK-LABEL: @get_strong_local_global +; CHECK: addis 3, 2, strong_local_global@toc@ha +; CHECK: addi 3, 3, strong_local_global@toc@l +; CHECK: blr +} + +@weak_local_global = weak dso_local global i32 42 +define i32* @get_weak_local_global() { + ret i32* @weak_local_global + +; STATIC-LABEL: @get_weak_local_global +; STATIC: addis 3, 2, weak_local_global@toc@ha +; STATIC: addi 3, 3, weak_local_global@toc@l +; STATIC: blr + +; CHECK-LABEL: @get_weak_local_global +; CHECK: addis 3, 2, weak_local_global@toc@ha +; CHECK: addi 3, 3, weak_local_global@toc@l +; CHECK: blr +} + +@external_local_global = external dso_local global i32 +define i32* @get_external_local_global() { + ret i32* @external_local_global +; STATIC-LABEL: @get_external_local_global +; STATIC: addis 3, 2, external_local_global@toc@ha +; STATIC: addi 3, 3, external_local_global@toc@l +; STATIC: blr + +; CHECK-LABEL: @get_external_local_global +; CHECK: addis 3, 2, external_local_global@toc@ha +; CHECK: addi 3, 3, external_local_global@toc@l +; CHECK: blr +} + +@strong_preemptable_global = dso_preemptable global i32 42 +define i32* @get_strong_preemptable_global() { + ret i32* @strong_preemptable_global + +; STATIC-LABEL: @get_strong_preemptable_global +; STATIC: addis 3, 2, strong_preemptable_global@toc@ha +; STATIC: addi 3, 3, strong_preemptable_global@toc@l +; STATIC: blr + +; CHECK-LABEL: @get_strong_preemptable_global +; CHECK: addis 3, 2, .LC3@toc@ha +; CHECK: ld 3, .LC3@toc@l(3) +; CHECK: blr +} + +@weak_preemptable_global = weak dso_preemptable global i32 42 +define i32* @get_weak_preemptable_global() { + ret i32* @weak_preemptable_global + +; STATIC-LABEL: @get_weak_preemptable_global +; STATIC: addis 3, 2, weak_preemptable_global@toc@ha +; STATIC: addi 3, 3, weak_preemptable_global@toc@l +; STATIC: blr + +; CHECK-LABEL: @get_weak_preemptable_global +; CHECK: addis 3, 2, .LC4@toc@ha +; CHECK: ld 3, .LC4@toc@l(3) +; CHECK: blr +} + +@external_preemptable_global = external dso_preemptable global i32 +define i32* @get_external_preemptable_global() { + ret i32* @external_preemptable_global + +; STATIC-LABEL: @get_external_preemptable_global +; STATIC: addis 3, 2, .LC1@toc@ha +; STATIC: ld 3, .LC1@toc@l(3) +; STATIC: blr + +; CHECK-LABEL: @get_external_preemptable_global +; CHECK: addis 3, 2, .LC5@toc@ha +; CHECK: ld 3, .LC5@toc@l(3) +; CHECK: blr +} + +; functions +define signext i32 @strong_default_function(i32 %i) { + ret i32 %i +} +define signext i32 @strong_default_function_caller(i32 %i) { + %call = notail call signext i32 @strong_default_function(i32 signext %i) + ret i32 %call + +; STATIC-LABEL: @strong_default_function_caller +; STATIC: bl strong_default_function +; STATIC-NOT: nop +; STATIC: blr + +; CHECK-LABEL: @strong_default_function_caller +; CHECK: bl strong_default_function +; CHECK-NEXT: nop +; CHECK: blr +} + +define weak signext i32 @weak_default_function(i32 %i) { + ret i32 %i +} +define signext i32 @weak_default_function_caller(i32 %i) { + %call = notail call signext i32 @weak_default_function(i32 signext %i) + ret i32 %call + +; STATIC-LABEL: @weak_default_function_caller +; STATIC: bl weak_default_function +; STATIC-NOT: nop +; STATIC: blr + +; CHECK-LABEL: @weak_default_function_caller +; CHECK: bl weak_default_function +; CHECK-NEXT: nop +; CHECK: blr +} + + +declare i32 @external_default_function(i32 %i) +define i32 @external_default_function_caller(i32 %i) { + %call = notail call signext i32 @external_default_function(i32 signext %i) + ret i32 %call + +; STATIC-LABEL: @external_default_function_caller +; STATIC: bl external_default_function +; STATIC-NEXT: nop +; STATIC: blr + +; CHECK-LABEL: @external_default_function_caller +; CHECK: bl external_default_function +; CHECK-NEXT: nop +; CHECK: blr +} + +define dso_local signext i32 @strong_local_function(i32 %i) { + ret i32 %i +} +define signext i32 @strong_local_function_caller(i32 %i) { + %call = notail call signext i32 @strong_local_function(i32 signext %i) + ret i32 %call + +; STATIC-LABEL: @strong_local_function_caller +; STATIC: bl strong_local_function +; STATIC-NOT: nop +; STATIC: blr + +; CHECK-LABEL: @strong_local_function_caller +; CHECK: bl strong_local_function +; CHECK-NOT: nop +; CHECK: blr +} + +define weak dso_local signext i32 @weak_local_function(i32 %i) { + ret i32 %i +} +define signext i32 @weak_local_function_caller(i32 %i) { + %call = notail call signext i32 @weak_local_function(i32 signext %i) + ret i32 %call + +; STATIC-LABEL: @weak_local_function_caller +; STATIC: bl weak_local_function +; STATIC-NOT: nop +; STATIC: blr + +; CHECK-LABEL: @weak_local_function_caller +; CHECK: bl weak_local_function +; CHECK-NOT: nop +; CHECK: blr +} + +declare dso_local i32 @external_local_function(i32 %i) +define i32 @external_local_function_caller(i32 %i) { + %call = notail call signext i32 @external_local_function(i32 signext %i) + ret i32 %call + +; STATIC-LABEL: @external_local_function_caller +; STATIC: bl external_local_function +; STATIC-NOT: nop +; STATIC: blr + +; CHECK-LABEL: @external_local_function_caller +; CHECK: bl external_local_function +; CHECK-NOT: nop +; CHECK: blr +} + +define dso_preemptable signext i32 @strong_preemptable_function(i32 %i) { + ret i32 %i +} +define signext i32 @strong_preemptable_function_caller(i32 %i) { + %call = notail call signext i32 @strong_preemptable_function(i32 signext %i) + ret i32 %call + +; STATIC-LABEL: @strong_preemptable_function_caller +; STATIC: bl strong_preemptable_function +; STATIC-NOT: nop +; STATIC: blr + +; CHECK-LABEL: @strong_preemptable_function_caller +; CHECK: bl strong_preemptable_function +; CHECK-NEXT: nop +; CHECK: blr +} + +define weak dso_preemptable signext i32 @weak_preemptable_function(i32 %i) { + ret i32 %i +} +define signext i32 @weak_preemptable_function_caller(i32 %i) { + %call = notail call signext i32 @weak_preemptable_function(i32 signext %i) + ret i32 %call + +; STATIC-LABEL: @weak_preemptable_function_caller +; STATIC: bl weak_preemptable_function +; STATIC-NOT: nop +; STATIC: blr + +; CHECK-LABEL: @weak_preemptable_function_caller +; CHECK: bl weak_preemptable_function +; CHECK-NEXT: nop +; CHECK: blr +} + +declare dso_preemptable i32 @external_preemptable_function(i32 %i) +define i32 @external_preemptable_function_caller(i32 %i) { + %call = notail call signext i32 @external_preemptable_function(i32 signext %i) + ret i32 %call + +; STATIC-LABEL: @external_preemptable_function_caller +; STATIC: bl external_preemptable_function +; STATIC-NEXT: nop +; STATIC: blr + +; CHECK-LABEL: @external_preemptable_function_caller +; CHECK: bl external_preemptable_function +; CHECK-NEXT: nop +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/pwr3-6x.ll b/test/CodeGen/PowerPC/pwr3-6x.ll index 9461d2b667c19..e74418ed693e8 100644 --- a/test/CodeGen/PowerPC/pwr3-6x.ll +++ b/test/CodeGen/PowerPC/pwr3-6x.ll @@ -1,10 +1,10 @@ ; Test basic support for some older processors. -;RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=pwr3 | FileCheck %s -;RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=pwr4 | FileCheck %s -;RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=pwr5 | FileCheck %s -;RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=pwr5x | FileCheck %s -;RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=pwr6x | FileCheck %s +;RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=pwr3 | FileCheck %s +;RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=pwr4 | FileCheck %s +;RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=pwr5 | FileCheck %s +;RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=pwr5x | FileCheck %s +;RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=pwr6x | FileCheck %s define void @foo() { entry: diff --git a/test/CodeGen/PowerPC/qpx-bv-sint.ll b/test/CodeGen/PowerPC/qpx-bv-sint.ll index b4accea5b6c87..36555b029abe1 100644 --- a/test/CodeGen/PowerPC/qpx-bv-sint.ll +++ b/test/CodeGen/PowerPC/qpx-bv-sint.ll @@ -1,6 +1,6 @@ +; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-bgq-linux" -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2q | FileCheck %s define void @s452(i32 %inp1) nounwind { entry: diff --git a/test/CodeGen/PowerPC/qpx-func-clobber.ll b/test/CodeGen/PowerPC/qpx-func-clobber.ll index 061e36ce491a6..ccbbd162a0cdb 100644 --- a/test/CodeGen/PowerPC/qpx-func-clobber.ll +++ b/test/CodeGen/PowerPC/qpx-func-clobber.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2q | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s target triple = "powerpc64-bgq-linux" declare <4 x double> @foo(<4 x double> %p) diff --git a/test/CodeGen/PowerPC/qpx-load.ll b/test/CodeGen/PowerPC/qpx-load.ll index 9b65aa45f8994..514f0934b6cfc 100644 --- a/test/CodeGen/PowerPC/qpx-load.ll +++ b/test/CodeGen/PowerPC/qpx-load.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2q | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s target triple = "powerpc64-bgq-linux" define <4 x double> @foo(<4 x double>* %p) { diff --git a/test/CodeGen/PowerPC/qpx-s-load.ll b/test/CodeGen/PowerPC/qpx-s-load.ll index 30c5f0b100ebe..57d7e3b0ded3c 100644 --- a/test/CodeGen/PowerPC/qpx-s-load.ll +++ b/test/CodeGen/PowerPC/qpx-s-load.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2q | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s target triple = "powerpc64-bgq-linux" define <4 x float> @foo(<4 x float>* %p) { diff --git a/test/CodeGen/PowerPC/qpx-s-sel.ll b/test/CodeGen/PowerPC/qpx-s-sel.ll index 541eefafa7886..83b444b044cd9 100644 --- a/test/CodeGen/PowerPC/qpx-s-sel.ll +++ b/test/CodeGen/PowerPC/qpx-s-sel.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2q | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s target triple = "powerpc64-bgq-linux" @R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16 diff --git a/test/CodeGen/PowerPC/qpx-s-store.ll b/test/CodeGen/PowerPC/qpx-s-store.ll index 1c51ecc52fa5d..81cff7b6457f1 100644 --- a/test/CodeGen/PowerPC/qpx-s-store.ll +++ b/test/CodeGen/PowerPC/qpx-s-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2q | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s target triple = "powerpc64-bgq-linux" define void @foo(<4 x float> %v, <4 x float>* %p) { diff --git a/test/CodeGen/PowerPC/qpx-sel.ll b/test/CodeGen/PowerPC/qpx-sel.ll index 4278d357760ad..b027d602eb493 100644 --- a/test/CodeGen/PowerPC/qpx-sel.ll +++ b/test/CodeGen/PowerPC/qpx-sel.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2q | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s target triple = "powerpc64-bgq-linux" @R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16 diff --git a/test/CodeGen/PowerPC/qpx-store.ll b/test/CodeGen/PowerPC/qpx-store.ll index 61dcbec726d67..2b96576ce4493 100644 --- a/test/CodeGen/PowerPC/qpx-store.ll +++ b/test/CodeGen/PowerPC/qpx-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2q | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s target triple = "powerpc64-bgq-linux" define void @foo(<4 x double> %v, <4 x double>* %p) { diff --git a/test/CodeGen/PowerPC/quadint-return.ll b/test/CodeGen/PowerPC/quadint-return.ll index 8b407849718ea..b8d982cd36651 100644 --- a/test/CodeGen/PowerPC/quadint-return.ll +++ b/test/CodeGen/PowerPC/quadint-return.ll @@ -14,6 +14,6 @@ entry: ; CHECK: ********** Function: foo ; CHECK: ********** FAST REGISTER ALLOCATION ********** -; CHECK: %X3<def> = COPY %vreg -; CHECK-NEXT: %X4<def> = COPY %vreg +; CHECK: %x3 = COPY %{{[0-9]+}} +; CHECK-NEXT: %x4 = COPY %{{[0-9]+}} ; CHECK-NEXT: BLR diff --git a/test/CodeGen/PowerPC/reg-coalesce-simple.ll b/test/CodeGen/PowerPC/reg-coalesce-simple.ll index c9e97cd28991b..06af1c6245a82 100644 --- a/test/CodeGen/PowerPC/reg-coalesce-simple.ll +++ b/test/CodeGen/PowerPC/reg-coalesce-simple.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep or +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep or %struct.foo = type { i32, i32, [0 x i8] } diff --git a/test/CodeGen/PowerPC/reg-names.ll b/test/CodeGen/PowerPC/reg-names.ll index 0ad11312513b2..70c3b6087d489 100644 --- a/test/CodeGen/PowerPC/reg-names.ll +++ b/test/CodeGen/PowerPC/reg-names.ll @@ -1,5 +1,6 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names < %s | FileCheck -check-prefix=CHECK-FN %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -ppc-reg-with-percent-prefix < %s | FileCheck -check-prefix=CHECK-PN %s define i64 @test1(i64 %a, i64 %b) { ; CHECK-LABEL: @test1 @@ -10,8 +11,10 @@ entry: ; CHECK: mr 3, 4 ; CHECK-FN: mr r3, r4 +; CHECK-PN: mr %r3, %r4 ; CHECK: blr ; CHECK-FN: blr +; CHECK-PN: blr } diff --git a/test/CodeGen/PowerPC/remove-redundant-moves.ll b/test/CodeGen/PowerPC/remove-redundant-moves.ll index 6b845cbf380ac..40e39c64deadb 100644 --- a/test/CodeGen/PowerPC/remove-redundant-moves.ll +++ b/test/CodeGen/PowerPC/remove-redundant-moves.ll @@ -105,3 +105,131 @@ entry: %1 = uitofp i64 %0 to float ret float %1 } + +define float @conv2fltTesti0(<4 x i32> %a) { +entry: +; CHECK-LABEL: conv2fltTesti0 +; CHECK: xxspltw [[SW:[0-9]+]], 34, 3 +; CHECK: xvcvsxwsp [[SW]], [[SW]] +; CHECK: xscvspdpn 1, [[SW]] +; CHECK-BE-LABEL: conv2fltTesti0 +; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 0 +; CHECK-BE: xvcvsxwsp [[CP]], [[CP]] +; CHECK-BE: xscvspdpn 1, [[CP]] + %vecext = extractelement <4 x i32> %a, i32 0 + %conv = sitofp i32 %vecext to float + ret float %conv +} + +define float @conv2fltTesti1(<4 x i32> %a) { +entry: +; CHECK-LABEL: conv2fltTesti1 +; CHECK: xxspltw [[SW:[0-9]+]], 34, 2 +; CHECK: xvcvsxwsp [[SW]], [[SW]] +; CHECK: xscvspdpn 1, [[SW]] +; CHECK-BE-LABEL: conv2fltTesti1 +; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 1 +; CHECK-BE: xvcvsxwsp [[CP]], [[CP]] +; CHECK-BE: xscvspdpn 1, [[CP]] + %vecext = extractelement <4 x i32> %a, i32 1 + %conv = sitofp i32 %vecext to float + ret float %conv +} + +define float @conv2fltTesti2(<4 x i32> %a) { +entry: +; CHECK-LABEL: conv2fltTesti2 +; CHECK: xxspltw [[SW:[0-9]+]], 34, 1 +; CHECK: xvcvsxwsp [[SW]], [[SW]] +; CHECK: xscvspdpn 1, [[SW]] +; CHECK-BE-LABEL: conv2fltTesti2 +; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 2 +; CHECK-BE: xvcvsxwsp [[CP]], [[CP]] +; CHECK-BE: xscvspdpn 1, [[CP]] + %vecext = extractelement <4 x i32> %a, i32 2 + %conv = sitofp i32 %vecext to float + ret float %conv +} + +define float @conv2fltTesti3(<4 x i32> %a) { +entry: +; CHECK-LABEL: conv2fltTesti3 +; CHECK: xxspltw [[SW:[0-9]+]], 34, 0 +; CHECK: xvcvsxwsp [[SW]], [[SW]] +; CHECK: xscvspdpn 1, [[SW]] +; CHECK-BE-LABEL: conv2fltTesti3 +; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 3 +; CHECK-BE: xvcvsxwsp [[CP]], [[CP]] +; CHECK-BE: xscvspdpn 1, [[CP]] + %vecext = extractelement <4 x i32> %a, i32 3 + %conv = sitofp i32 %vecext to float + ret float %conv +} + +; verify we don't crash for variable elem extract +define float @conv2fltTestiVar(<4 x i32> %a, i32 zeroext %elem) { +entry: + %vecext = extractelement <4 x i32> %a, i32 %elem + %conv = sitofp i32 %vecext to float + ret float %conv +} + +define double @conv2dblTesti0(<4 x i32> %a) { +entry: +; CHECK-LABEL: conv2dblTesti0 +; CHECK: xxspltw [[SW:[0-9]+]], 34, 3 +; CHECK: xvcvsxwdp 1, [[SW]] +; CHECK-BE-LABEL: conv2dblTesti0 +; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 0 +; CHECK-BE: xvcvsxwdp 1, [[CP]] + %vecext = extractelement <4 x i32> %a, i32 0 + %conv = sitofp i32 %vecext to double + ret double %conv +} + +define double @conv2dblTesti1(<4 x i32> %a) { +entry: +; CHECK-LABEL: conv2dblTesti1 +; CHECK: xxspltw [[SW:[0-9]+]], 34, 2 +; CHECK: xvcvsxwdp 1, [[SW]] +; CHECK-BE-LABEL: conv2dblTesti1 +; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 1 +; CHECK-BE: xvcvsxwdp 1, [[CP]] + %vecext = extractelement <4 x i32> %a, i32 1 + %conv = sitofp i32 %vecext to double + ret double %conv +} + +define double @conv2dblTesti2(<4 x i32> %a) { +entry: +; CHECK-LABEL: conv2dblTesti2 +; CHECK: xxspltw [[SW:[0-9]+]], 34, 1 +; CHECK: xvcvsxwdp 1, [[SW]] +; CHECK-BE-LABEL: conv2dblTesti2 +; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 2 +; CHECK-BE: xvcvsxwdp 1, [[CP]] + %vecext = extractelement <4 x i32> %a, i32 2 + %conv = sitofp i32 %vecext to double + ret double %conv +} + +define double @conv2dblTesti3(<4 x i32> %a) { +entry: +; CHECK-LABEL: conv2dblTesti3 +; CHECK: xxspltw [[SW:[0-9]+]], 34, 0 +; CHECK: xvcvsxwdp 1, [[SW]] +; CHECK-BE-LABEL: conv2dblTesti3 +; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 3 +; CHECK-BE: xvcvsxwdp 1, [[CP]] + %vecext = extractelement <4 x i32> %a, i32 3 + %conv = sitofp i32 %vecext to double + ret double %conv +} + +; verify we don't crash for variable elem extract +define double @conv2dblTestiVar(<4 x i32> %a, i32 zeroext %elem) { +entry: + %vecext = extractelement <4 x i32> %a, i32 %elem + %conv = sitofp i32 %vecext to double + ret double %conv +} diff --git a/test/CodeGen/PowerPC/remove-redundant-toc-saves.ll b/test/CodeGen/PowerPC/remove-redundant-toc-saves.ll new file mode 100644 index 0000000000000..8b9729544b850 --- /dev/null +++ b/test/CodeGen/PowerPC/remove-redundant-toc-saves.ll @@ -0,0 +1,123 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +define signext i32 @test1(i32 signext %i, i32 (i32)* nocapture %Func, i32 (i32)* nocapture %Func2) { +entry: +; CHECK-LABEL: test1: +; CHECK: std 2, 24(1) +; CHECK-NOT: std 2, 24(1) + %call = tail call signext i32 %Func(i32 signext %i) + %call1 = tail call signext i32 %Func2(i32 signext %i) + %add2 = add nsw i32 %call1, %call + ret i32 %add2 +} + +define signext i32 @test2(i32 signext %i, i32 signext %j, i32 (i32)* nocapture %Func, i32 (i32)* nocapture %Func2) { +entry: +; CHECK-LABEL: test2: +; CHECK: std 2, 24(1) +; CHECK-NOT: std 2, 24(1) + %call = tail call signext i32 %Func(i32 signext %i) + %tobool = icmp eq i32 %j, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + %call1 = tail call signext i32 %Func(i32 signext %i) + %add2 = add nsw i32 %call1, %call + %call3 = tail call signext i32 %Func2(i32 signext %i) + %add4 = add nsw i32 %add2, %call3 + br label %if.end + +if.end: ; preds = %entry, %if.then + %Sum.0 = phi i32 [ %add4, %if.then ], [ %call, %entry ] + %call5 = tail call signext i32 %Func(i32 signext %i) + %add6 = add nsw i32 %call5, %Sum.0 + ret i32 %add6 +} + +; Check for multiple TOC saves with if then else where neither dominates the other. +define signext i32 @test3(i32 signext %i, i32 (i32)* nocapture %Func, i32 (i32)* nocapture %Func2) { +; CHECK-LABEL: test3: +; CHECK: std 2, 24(1) +; CHECK: std 2, 24(1) +; CHECK-NOT: std 2, 24(1) +entry: + %tobool = icmp eq i32 %i, 0 + br i1 %tobool, label %if.else, label %if.then + +if.then: ; preds = %entry + %call = tail call signext i32 %Func(i32 signext %i) + br label %if.end + +if.else: ; preds = %entry + %call1 = tail call signext i32 %Func2(i32 signext 0) + br label %if.end + +if.end: ; preds = %if.else, %if.then + %Sum.0 = phi i32 [ %call, %if.then ], [ %call1, %if.else ] + %call3 = tail call signext i32 %Func(i32 signext %i) + %add4 = add nsw i32 %call3, %Sum.0 + ret i32 %add4 +} + +define signext i32 @test4(i32 signext %i, i32 (i32)* nocapture %Func, i32 (i32)* nocapture %Func2) { +; CHECK-LABEL: test4: +; CHECK: std 2, 24(1) +; CHECK-NOT: std 2, 24(1) + +entry: + %call = tail call signext i32 %Func(i32 signext %i) + %tobool = icmp eq i32 %i, 0 + br i1 %tobool, label %if.else, label %if.then + +if.then: ; preds = %entry + %call1 = tail call signext i32 %Func(i32 signext %i) + br label %if.end + +if.else: ; preds = %entry + %call3 = tail call signext i32 %Func2(i32 signext 0) + br label %if.end + +if.end: ; preds = %if.else, %if.then + %call1.pn = phi i32 [ %call1, %if.then ], [ %call3, %if.else ] + %Sum.0 = add nsw i32 %call1.pn, %call + ret i32 %Sum.0 +} + +; Check for multiple TOC saves with if then where neither is redundant. +define signext i32 @test5(i32 signext %i, i32 (i32)* nocapture %Func, i32 (i32)* nocapture readnone %Func2) { +entry: +; CHECK-LABEL: test5: +; CHECK: std 2, 24(1) +; CHECK: std 2, 24(1) + + %tobool = icmp eq i32 %i, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + %call = tail call signext i32 %Func(i32 signext %i) + br label %if.end + +if.end: ; preds = %entry, %if.then + %Sum.0 = phi i32 [ %call, %if.then ], [ 0, %entry ] + %call1 = tail call signext i32 %Func(i32 signext %i) + %add2 = add nsw i32 %call1, %Sum.0 + ret i32 %add2 +} + +; Check for multiple TOC saves if there are dynamic allocations on the stack. +define signext i32 @test6(i32 signext %i, i32 (i32)* nocapture %Func, i32 (i32)* nocapture %Func2) { +entry: +; CHECK-LABEL: test6: +; CHECK: std 2, 24(1) +; CHECK: std 2, 24(1) + + %conv = sext i32 %i to i64 + %0 = alloca i8, i64 %conv, align 16 + %1 = bitcast i8* %0 to i32* + %call = tail call signext i32 %Func(i32 signext %i) + call void @useAlloca(i32* nonnull %1, i32 signext %call) + %call1 = call signext i32 %Func2(i32 signext %i) + %add2 = add nsw i32 %call1, %call + ret i32 %add2 +} + +declare void @useAlloca(i32*, i32 signext) diff --git a/test/CodeGen/PowerPC/restore-r30.ll b/test/CodeGen/PowerPC/restore-r30.ll index 216d5a709340d..8dba2be693075 100644 --- a/test/CodeGen/PowerPC/restore-r30.ll +++ b/test/CodeGen/PowerPC/restore-r30.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=ppc32 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -relocation-model=pic < %s | FileCheck %s ; The load restoring r30 at the end of the function was placed out of order ; relative to its uses as the PIC base pointer. @@ -11,7 +11,7 @@ ; CHECK-NOT: 30, target datalayout = "E-m:e-p:32:32-i64:64-n32" -target triple = "powerpc" +target triple = "powerpc--" define double @fred(i64 %a) #0 { entry: diff --git a/test/CodeGen/PowerPC/retaddr.ll b/test/CodeGen/PowerPC/retaddr.ll index d8b6a18d31625..3794f6e12af78 100644 --- a/test/CodeGen/PowerPC/retaddr.ll +++ b/test/CodeGen/PowerPC/retaddr.ll @@ -1,8 +1,6 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep mflr -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep lwz -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | grep "ld r., 16(r1)" - -target triple = "powerpc-apple-darwin8" +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 | grep mflr +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 | grep lwz +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin8 | grep "ld r., 16(r1)" define void @foo(i8** %X) nounwind { entry: diff --git a/test/CodeGen/PowerPC/return-val-i128.ll b/test/CodeGen/PowerPC/return-val-i128.ll index 3cd95d2a7e1bc..11e5fdc10fadb 100644 --- a/test/CodeGen/PowerPC/return-val-i128.ll +++ b/test/CodeGen/PowerPC/return-val-i128.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- define i128 @__fixsfdi(float %a) { entry: diff --git a/test/CodeGen/PowerPC/rlwimi-commute.ll b/test/CodeGen/PowerPC/rlwimi-commute.ll index 34351d884755c..e06c339584ee6 100644 --- a/test/CodeGen/PowerPC/rlwimi-commute.ll +++ b/test/CodeGen/PowerPC/rlwimi-commute.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep rlwimi -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep "or " +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rlwimi +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep "or " ; Make sure there is no register-register copies here. diff --git a/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll b/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll index 9c55b4301c1eb..9897d2b9a571a 100644 --- a/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll +++ b/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin | FileCheck %s ; Formerly dropped the RHS of %tmp6 when constructing rlwimi. ; 7346117 diff --git a/test/CodeGen/PowerPC/rlwimi.ll b/test/CodeGen/PowerPC/rlwimi.ll index ba795ea93c520..e701236b840b2 100644 --- a/test/CodeGen/PowerPC/rlwimi.ll +++ b/test/CodeGen/PowerPC/rlwimi.ll @@ -1,6 +1,6 @@ ; All of these ands and shifts should be folded into rlwimi's -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep and -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep rlwimi | count 8 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep and +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rlwimi | count 8 define i32 @test1(i32 %x, i32 %y) { entry: diff --git a/test/CodeGen/PowerPC/rlwimi2.ll b/test/CodeGen/PowerPC/rlwimi2.ll index 5fe963a700733..4474ddf759df4 100644 --- a/test/CodeGen/PowerPC/rlwimi2.ll +++ b/test/CodeGen/PowerPC/rlwimi2.ll @@ -1,5 +1,5 @@ ; All of these ands and shifts should be folded into rlwimi's -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -o %t +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t ; RUN: grep rlwimi %t | count 4 ; RUN: not grep srwi %t ; RUN: not grep slwi %t diff --git a/test/CodeGen/PowerPC/rlwimi3.ll b/test/CodeGen/PowerPC/rlwimi3.ll index da4ae45964344..eb3ab79535613 100644 --- a/test/CodeGen/PowerPC/rlwimi3.ll +++ b/test/CodeGen/PowerPC/rlwimi3.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -stats 2>&1 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -stats 2>&1 | \ ; RUN: grep "Number of machine instrs printed" | grep 12 define i16 @Trans16Bit(i32 %srcA, i32 %srcB, i32 %alpha) { diff --git a/test/CodeGen/PowerPC/rlwinm.ll b/test/CodeGen/PowerPC/rlwinm.ll index 7755f8295743e..2f3b3bf003cf6 100644 --- a/test/CodeGen/PowerPC/rlwinm.ll +++ b/test/CodeGen/PowerPC/rlwinm.ll @@ -1,5 +1,5 @@ ; All of these ands and shifts should be folded into rlwimi's -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -o %t +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t ; RUN: not grep and %t ; RUN: not grep srawi %t ; RUN: not grep srwi %t diff --git a/test/CodeGen/PowerPC/rlwinm2.ll b/test/CodeGen/PowerPC/rlwinm2.ll index 4faea96416339..87b5cddaeb930 100644 --- a/test/CodeGen/PowerPC/rlwinm2.ll +++ b/test/CodeGen/PowerPC/rlwinm2.ll @@ -1,5 +1,5 @@ ; All of these ands and shifts should be folded into rlw[i]nm instructions -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -o %t +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t ; RUN: not grep and %t ; RUN: not grep srawi %t ; RUN: not grep srwi %t diff --git a/test/CodeGen/PowerPC/rotl-2.ll b/test/CodeGen/PowerPC/rotl-2.ll index 6247b939453aa..43d34f6f8c73f 100644 --- a/test/CodeGen/PowerPC/rotl-2.ll +++ b/test/CodeGen/PowerPC/rotl-2.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep rotlwi | count 2 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep clrlwi | count 2 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep rotlw | count 4 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep or +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rotlwi | count 2 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep clrlwi | count 2 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rotlw | count 4 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep or define i32 @rotl32(i32 %A, i8 %Amt) nounwind { %shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1] diff --git a/test/CodeGen/PowerPC/rotl-64.ll b/test/CodeGen/PowerPC/rotl-64.ll index 6942f3c63ae5b..f8e8378371cc2 100644 --- a/test/CodeGen/PowerPC/rotl-64.ll +++ b/test/CodeGen/PowerPC/rotl-64.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | grep rotld -; RUN: llc -verify-machineinstrs < %s -march=ppc64 | grep rotldi +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- | grep rotld +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- | grep rotldi ; PR1613 define i64 @t1(i64 %A) { diff --git a/test/CodeGen/PowerPC/rotl.ll b/test/CodeGen/PowerPC/rotl.ll index 35780de887cbd..5204d28a144d8 100644 --- a/test/CodeGen/PowerPC/rotl.ll +++ b/test/CodeGen/PowerPC/rotl.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep rotrw: | count 1 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep rotlw: | count 1 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep rotlwi: | count 1 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep rotrwi: | count 1 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rotrw: | count 1 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rotlw: | count 1 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rotlwi: | count 1 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rotrwi: | count 1 define i32 @rotlw(i32 %x, i32 %sh) { entry: diff --git a/test/CodeGen/PowerPC/s000-alias-misched.ll b/test/CodeGen/PowerPC/s000-alias-misched.ll index 2e213ea82f821..5c15145af2378 100644 --- a/test/CodeGen/PowerPC/s000-alias-misched.ll +++ b/test/CodeGen/PowerPC/s000-alias-misched.ll @@ -1,7 +1,7 @@ +; RUN: llc -verify-machineinstrs < %s -enable-misched -mcpu=a2 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -enable-misched -enable-aa-sched-mi -mcpu=a2 | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-bgq-linux" -; RUN: llc -verify-machineinstrs < %s -enable-misched -march=ppc64 -mcpu=a2 | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -enable-misched -enable-aa-sched-mi -march=ppc64 -mcpu=a2 | FileCheck %s @aa = external global [256 x [256 x double]], align 32 @bb = external global [256 x [256 x double]], align 32 diff --git a/test/CodeGen/PowerPC/save-bp.ll b/test/CodeGen/PowerPC/save-bp.ll index 1c7e19a1d5cb3..2e403cb80f4af 100644 --- a/test/CodeGen/PowerPC/save-bp.ll +++ b/test/CodeGen/PowerPC/save-bp.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=ppc64 -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC64 -; RUN: llc -march=ppc32 -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32 -; RUN: llc -march=ppc32 -ppc-always-use-base-pointer -relocation-model pic < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32PIC +; RUN: llc -mtriple=ppc64-- -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC64 +; RUN: llc -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32 +; RUN: llc -ppc-always-use-base-pointer -relocation-model pic < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32PIC ; CHECK-LABEL: fred: diff --git a/test/CodeGen/PowerPC/save-cr-ppc32svr4.ll b/test/CodeGen/PowerPC/save-cr-ppc32svr4.ll index 9fabca1860505..c5f4bf369fecb 100644 --- a/test/CodeGen/PowerPC/save-cr-ppc32svr4.ll +++ b/test/CodeGen/PowerPC/save-cr-ppc32svr4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=ppc32 -relocation-model pic < %s | FileCheck %s +; RUN: llc -relocation-model pic < %s | FileCheck %s ; ; Make sure that the CR register is saved correctly on PPC32/SVR4. diff --git a/test/CodeGen/PowerPC/save-crbp-ppc32svr4.ll b/test/CodeGen/PowerPC/save-crbp-ppc32svr4.ll index b7b3c1ada9653..a42ae66ac374b 100644 --- a/test/CodeGen/PowerPC/save-crbp-ppc32svr4.ll +++ b/test/CodeGen/PowerPC/save-crbp-ppc32svr4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=ppc32 -relocation-model pic < %s | FileCheck %s +; RUN: llc -relocation-model pic < %s | FileCheck %s ; CHECK-LABEL: fred ; CHECK: stwux 1, 1, 0 diff --git a/test/CodeGen/PowerPC/select-addrRegRegOnly.ll b/test/CodeGen/PowerPC/select-addrRegRegOnly.ll index f880d1faf9d90..46b23ff04f2be 100644 --- a/test/CodeGen/PowerPC/select-addrRegRegOnly.ll +++ b/test/CodeGen/PowerPC/select-addrRegRegOnly.ll @@ -4,9 +4,9 @@ ; Function Attrs: norecurse nounwind readonly define float @testSingleAccess(i32* nocapture readonly %arr) local_unnamed_addr #0 { ; CHECK-LABEL: testSingleAccess: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi 3, 3, 8 -; CHECK-NEXT: lxsiwax 0, 0, 3 +; CHECK-NEXT: lfiwax 0, 0, 3 ; CHECK-NEXT: xscvsxdsp 1, 0 ; CHECK-NEXT: blr entry: @@ -19,7 +19,7 @@ entry: ; Function Attrs: norecurse nounwind readonly define float @testMultipleAccess(i32* nocapture readonly %arr) local_unnamed_addr #0 { ; CHECK-LABEL: testMultipleAccess: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lwz 4, 8(3) ; CHECK-NEXT: lwz 12, 12(3) ; CHECK-NEXT: add 3, 12, 4 diff --git a/test/CodeGen/PowerPC/select-cc.ll b/test/CodeGen/PowerPC/select-cc.ll index 104f4335c3181..7b2421735d896 100644 --- a/test/CodeGen/PowerPC/select-cc.ll +++ b/test/CodeGen/PowerPC/select-cc.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- ; PR3011 define <2 x double> @vector_select(<2 x double> %x, <2 x double> %y) nounwind { diff --git a/test/CodeGen/PowerPC/select-i1-vs-i1.ll b/test/CodeGen/PowerPC/select-i1-vs-i1.ll index b7beb8165fdf1..e8e6f99cb229a 100644 --- a/test/CodeGen/PowerPC/select-i1-vs-i1.ll +++ b/test/CodeGen/PowerPC/select-i1-vs-i1.ll @@ -1,5 +1,6 @@ -; RUN: llc -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -ppc-reduce-cr-logicals -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -ppc-reduce-cr-logicals -verify-machineinstrs \ +; RUN: -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -475,12 +476,13 @@ entry: ret float %cond ; CHECK-LABEL: @testfloatslt -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: fmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: fmr 1, 5 ; CHECK: blr } @@ -494,12 +496,13 @@ entry: ret float %cond ; CHECK-LABEL: @testfloatult -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: fmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: fmr 1, 5 ; CHECK: blr } @@ -513,10 +516,10 @@ entry: ret float %cond ; CHECK-LABEL: @testfloatsle -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 12, 2, .LBB[[BB]] ; CHECK: fmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: fmr 1, 5 @@ -532,10 +535,10 @@ entry: ret float %cond ; CHECK-LABEL: @testfloatule -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 4, 2, .LBB[[BB]] ; CHECK: fmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: fmr 1, 5 @@ -570,10 +573,10 @@ entry: ret float %cond ; CHECK-LABEL: @testfloatsge -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 4, 2, .LBB[[BB]] ; CHECK: fmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: fmr 1, 5 @@ -589,10 +592,10 @@ entry: ret float %cond ; CHECK-LABEL: @testfloatuge -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 12, 2, .LBB[[BB]] ; CHECK: fmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: fmr 1, 5 @@ -608,12 +611,13 @@ entry: ret float %cond ; CHECK-LABEL: @testfloatsgt -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: fmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: fmr 1, 5 ; CHECK: blr } @@ -627,12 +631,13 @@ entry: ret float %cond ; CHECK-LABEL: @testfloatugt -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: fmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: fmr 1, 5 ; CHECK: blr } @@ -665,12 +670,13 @@ entry: ret double %cond ; CHECK-LABEL: @testdoubleslt -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: fmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: fmr 1, 5 ; CHECK: blr } @@ -684,12 +690,13 @@ entry: ret double %cond ; CHECK-LABEL: @testdoubleult -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: fmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: fmr 1, 5 ; CHECK: blr } @@ -703,10 +710,10 @@ entry: ret double %cond ; CHECK-LABEL: @testdoublesle -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 12, 2, .LBB[[BB]] ; CHECK: fmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: fmr 1, 5 @@ -722,10 +729,10 @@ entry: ret double %cond ; CHECK-LABEL: @testdoubleule -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 4, 2, .LBB[[BB]] ; CHECK: fmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: fmr 1, 5 @@ -760,10 +767,10 @@ entry: ret double %cond ; CHECK-LABEL: @testdoublesge -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 4, 2, .LBB[[BB]] ; CHECK: fmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: fmr 1, 5 @@ -779,10 +786,10 @@ entry: ret double %cond ; CHECK-LABEL: @testdoubleuge -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 12, 2, .LBB[[BB]] ; CHECK: fmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: fmr 1, 5 @@ -798,12 +805,13 @@ entry: ret double %cond ; CHECK-LABEL: @testdoublesgt -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: fmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: fmr 1, 5 ; CHECK: blr } @@ -817,12 +825,13 @@ entry: ret double %cond ; CHECK-LABEL: @testdoubleugt -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: fmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: fmr 1, 5 ; CHECK: blr } @@ -856,9 +865,10 @@ entry: ; CHECK-LABEL: @testv4floatslt ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: bclr 12, 2, 0 +; CHECK: .LBB[[BB]]: ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -872,10 +882,11 @@ entry: ret <4 x float> %cond ; CHECK-LABEL: @testv4floatult -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bclr 4, 2, 0 +; CHECK: .LBB[[BB]]: ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -889,10 +900,10 @@ entry: ret <4 x float> %cond ; CHECK-LABEL: @testv4floatsle -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bclr 4, 2, 0 +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bclr 12, 2, 0 ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -907,9 +918,9 @@ entry: ; CHECK-LABEL: @testv4floatule ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bclr 12, 2, 0 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: bclr 4, 2, 0 ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -943,9 +954,9 @@ entry: ; CHECK-LABEL: @testv4floatsge ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bclr 12, 2, 0 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: bclr 4, 2, 0 ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -960,9 +971,9 @@ entry: ; CHECK-LABEL: @testv4floatuge ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bclr 4, 2, 0 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: bclr 12, 2, 0 ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -976,10 +987,10 @@ entry: ret <4 x float> %cond ; CHECK-LABEL: @testv4floatsgt -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bclr 4, 2, 0 ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -993,10 +1004,11 @@ entry: ret <4 x float> %cond ; CHECK-LABEL: @testv4floatugt -; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 -; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] +; CHECK: fcmpu {{[0-9]+}}, 1, 2 +; CHECK: bclr 12, 2, 0 +; CHECK: .LBB[[BB]] ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1059,9 +1071,10 @@ entry: ; CHECK-LABEL: @testv2doubleslt ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: bc 4, 2, .LBB[[BB]] +; CHECK: .LBB[[BB]]: ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1076,9 +1089,10 @@ entry: ; CHECK-LABEL: @testv2doubleult ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: bc 12, 2, .LBB[[BB]] +; CHECK: .LBB[[BB]]: ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1093,9 +1107,9 @@ entry: ; CHECK-LABEL: @testv2doublesle ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bclr 4, 2, 0 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: bclr 12, 2, 0 ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1110,9 +1124,9 @@ entry: ; CHECK-LABEL: @testv2doubleule ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bclr 12, 2, 0 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: bclr 4, 2, 0 ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1146,9 +1160,9 @@ entry: ; CHECK-LABEL: @testv2doublesge ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bclr 12, 2, 0 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: bclr 4, 2, 0 ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1163,9 +1177,9 @@ entry: ; CHECK-LABEL: @testv2doubleuge ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bclr 4, 2, 0 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: bclr 12, 2, 0 ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1180,9 +1194,10 @@ entry: ; CHECK-LABEL: @testv2doublesgt ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: bc 12, 2, .LBB[[BB]] +; CHECK: .LBB[[BB]] ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1197,9 +1212,10 @@ entry: ; CHECK-LABEL: @testv2doubleugt ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bclr 12, [[REG1]], 0 +; CHECK: bc 4, 2, .LBB[[BB]] +; CHECK: .LBB[[BB]] ; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1231,11 +1247,12 @@ entry: ; CHECK-LABEL: @testqv4doubleslt ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: qvfmr 1, 5 ; CHECK: blr } @@ -1250,11 +1267,12 @@ entry: ; CHECK-LABEL: @testqv4doubleult ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: qvfmr 1, 5 ; CHECK: blr } @@ -1269,9 +1287,9 @@ entry: ; CHECK-LABEL: @testqv4doublesle ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 12, 2, .LBB[[BB]] ; CHECK: qvfmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: qvfmr 1, 5 @@ -1288,9 +1306,9 @@ entry: ; CHECK-LABEL: @testqv4doubleule ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 4, 2, .LBB[[BB]] ; CHECK: qvfmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: qvfmr 1, 5 @@ -1326,9 +1344,9 @@ entry: ; CHECK-LABEL: @testqv4doublesge ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 4, 2, .LBB[[BB]] ; CHECK: qvfmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: qvfmr 1, 5 @@ -1345,9 +1363,9 @@ entry: ; CHECK-LABEL: @testqv4doubleuge ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 12, 2, .LBB[[BB]] ; CHECK: qvfmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: qvfmr 1, 5 @@ -1364,11 +1382,12 @@ entry: ; CHECK-LABEL: @testqv4doublesgt ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: qvfmr 1, 5 ; CHECK: blr } @@ -1383,11 +1402,12 @@ entry: ; CHECK-LABEL: @testqv4doubleugt ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: qvfmr 1, 5 ; CHECK: blr } @@ -1421,11 +1441,12 @@ entry: ; CHECK-LABEL: @testqv4floatslt ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: qvfmr 1, 5 ; CHECK: blr } @@ -1440,11 +1461,12 @@ entry: ; CHECK-LABEL: @testqv4floatult ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: qvfmr 1, 5 ; CHECK: blr } @@ -1459,9 +1481,9 @@ entry: ; CHECK-LABEL: @testqv4floatsle ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 12, 2, .LBB[[BB]] ; CHECK: qvfmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: qvfmr 1, 5 @@ -1478,9 +1500,9 @@ entry: ; CHECK-LABEL: @testqv4floatule ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 4, 2, .LBB[[BB]] ; CHECK: qvfmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: qvfmr 1, 5 @@ -1516,9 +1538,9 @@ entry: ; CHECK-LABEL: @testqv4floatsge ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 4, 2, .LBB[[BB]] ; CHECK: qvfmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: qvfmr 1, 5 @@ -1535,9 +1557,9 @@ entry: ; CHECK-LABEL: @testqv4floatuge ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 12, 2, .LBB[[BB]] ; CHECK: qvfmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: qvfmr 1, 5 @@ -1554,11 +1576,12 @@ entry: ; CHECK-LABEL: @testqv4floatsgt ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: qvfmr 1, 5 ; CHECK: blr } @@ -1573,11 +1596,12 @@ entry: ; CHECK-LABEL: @testqv4floatugt ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: qvfmr 1, 5 ; CHECK: blr } @@ -1611,11 +1635,12 @@ entry: ; CHECK-LABEL: @testqv4i1slt ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: qvfmr 1, 5 ; CHECK: blr } @@ -1630,11 +1655,12 @@ entry: ; CHECK-LABEL: @testqv4i1ult ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: qvfmr 1, 5 ; CHECK: blr } @@ -1649,9 +1675,9 @@ entry: ; CHECK-LABEL: @testqv4i1sle ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 12, 2, .LBB[[BB]] ; CHECK: qvfmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: qvfmr 1, 5 @@ -1668,9 +1694,9 @@ entry: ; CHECK-LABEL: @testqv4i1ule ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 4, 2, .LBB[[BB]] ; CHECK: qvfmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: qvfmr 1, 5 @@ -1706,9 +1732,9 @@ entry: ; CHECK-LABEL: @testqv4i1sge ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 4, 2, .LBB[[BB]] ; CHECK: qvfmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: qvfmr 1, 5 @@ -1725,9 +1751,9 @@ entry: ; CHECK-LABEL: @testqv4i1uge ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 12, 2, .LBB[[BB]] ; CHECK: qvfmr 5, 6 ; CHECK: .LBB[[BB]]: ; CHECK: qvfmr 1, 5 @@ -1744,11 +1770,12 @@ entry: ; CHECK-LABEL: @testqv4i1sgt ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: qvfmr 1, 5 ; CHECK: blr } @@ -1763,11 +1790,12 @@ entry: ; CHECK-LABEL: @testqv4i1ugt ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 +; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 -; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]] +; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] +; CHECK: .LBB[[BB1]]: ; CHECK: qvfmr 5, 6 -; CHECK: .LBB[[BB]]: +; CHECK: .LBB[[BB2]]: ; CHECK: qvfmr 1, 5 ; CHECK: blr } diff --git a/test/CodeGen/PowerPC/select_const.ll b/test/CodeGen/PowerPC/select_const.ll index 29548123be888..178d9187e3b46 100644 --- a/test/CodeGen/PowerPC/select_const.ll +++ b/test/CodeGen/PowerPC/select_const.ll @@ -9,7 +9,7 @@ define i32 @select_0_or_1(i1 %cond) { ; ALL-LABEL: select_0_or_1: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: not 3, 3 ; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: blr @@ -19,7 +19,7 @@ define i32 @select_0_or_1(i1 %cond) { define i32 @select_0_or_1_zeroext(i1 zeroext %cond) { ; ALL-LABEL: select_0_or_1_zeroext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: xori 3, 3, 1 ; ALL-NEXT: blr %sel = select i1 %cond, i32 0, i32 1 @@ -28,7 +28,7 @@ define i32 @select_0_or_1_zeroext(i1 zeroext %cond) { define i32 @select_0_or_1_signext(i1 signext %cond) { ; ALL-LABEL: select_0_or_1_signext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: not 3, 3 ; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: blr @@ -40,7 +40,7 @@ define i32 @select_0_or_1_signext(i1 signext %cond) { define i32 @select_1_or_0(i1 %cond) { ; ALL-LABEL: select_1_or_0: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: blr %sel = select i1 %cond, i32 1, i32 0 @@ -49,7 +49,7 @@ define i32 @select_1_or_0(i1 %cond) { define i32 @select_1_or_0_zeroext(i1 zeroext %cond) { ; ALL-LABEL: select_1_or_0_zeroext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: blr %sel = select i1 %cond, i32 1, i32 0 ret i32 %sel @@ -57,7 +57,7 @@ define i32 @select_1_or_0_zeroext(i1 zeroext %cond) { define i32 @select_1_or_0_signext(i1 signext %cond) { ; ALL-LABEL: select_1_or_0_signext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: blr %sel = select i1 %cond, i32 1, i32 0 @@ -68,7 +68,7 @@ define i32 @select_1_or_0_signext(i1 signext %cond) { define i32 @select_0_or_neg1(i1 %cond) { ; ISEL-LABEL: select_0_or_neg1: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -77,7 +77,7 @@ define i32 @select_0_or_neg1(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_0_or_neg1: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 @@ -93,7 +93,7 @@ define i32 @select_0_or_neg1(i1 %cond) { define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) { ; ISEL-LABEL: select_0_or_neg1_zeroext: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -102,7 +102,7 @@ define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_0_or_neg1_zeroext: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 @@ -118,7 +118,7 @@ define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) { define i32 @select_0_or_neg1_signext(i1 signext %cond) { ; ISEL-LABEL: select_0_or_neg1_signext: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -127,7 +127,7 @@ define i32 @select_0_or_neg1_signext(i1 signext %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_0_or_neg1_signext: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 @@ -145,7 +145,7 @@ define i32 @select_0_or_neg1_signext(i1 signext %cond) { define i32 @select_neg1_or_0(i1 %cond) { ; ISEL-LABEL: select_neg1_or_0: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -154,13 +154,13 @@ define i32 @select_neg1_or_0(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_neg1_or_0: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 ; NO_ISEL-NEXT: ori 3, 3, 65535 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i32 -1, i32 0 @@ -169,7 +169,7 @@ define i32 @select_neg1_or_0(i1 %cond) { define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) { ; ISEL-LABEL: select_neg1_or_0_zeroext: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -178,13 +178,13 @@ define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_neg1_or_0_zeroext: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 ; NO_ISEL-NEXT: ori 3, 3, 65535 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i32 -1, i32 0 @@ -193,7 +193,7 @@ define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) { define i32 @select_neg1_or_0_signext(i1 signext %cond) { ; ISEL-LABEL: select_neg1_or_0_signext: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -202,13 +202,13 @@ define i32 @select_neg1_or_0_signext(i1 signext %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_neg1_or_0_signext: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 ; NO_ISEL-NEXT: ori 3, 3, 65535 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i32 -1, i32 0 @@ -219,7 +219,7 @@ define i32 @select_neg1_or_0_signext(i1 signext %cond) { define i32 @select_Cplus1_C(i1 %cond) { ; ALL-LABEL: select_Cplus1_C: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: addi 3, 3, 41 ; ALL-NEXT: blr @@ -229,7 +229,7 @@ define i32 @select_Cplus1_C(i1 %cond) { define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) { ; ALL-LABEL: select_Cplus1_C_zeroext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: addi 3, 3, 41 ; ALL-NEXT: blr %sel = select i1 %cond, i32 42, i32 41 @@ -238,7 +238,7 @@ define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) { define i32 @select_Cplus1_C_signext(i1 signext %cond) { ; ALL-LABEL: select_Cplus1_C_signext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: subfic 3, 3, 41 ; ALL-NEXT: blr %sel = select i1 %cond, i32 42, i32 41 @@ -249,7 +249,7 @@ define i32 @select_Cplus1_C_signext(i1 signext %cond) { define i32 @select_C_Cplus1(i1 %cond) { ; ALL-LABEL: select_C_Cplus1: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: subfic 3, 3, 42 ; ALL-NEXT: blr @@ -259,7 +259,7 @@ define i32 @select_C_Cplus1(i1 %cond) { define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) { ; ALL-LABEL: select_C_Cplus1_zeroext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: subfic 3, 3, 42 ; ALL-NEXT: blr %sel = select i1 %cond, i32 41, i32 42 @@ -268,7 +268,7 @@ define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) { define i32 @select_C_Cplus1_signext(i1 signext %cond) { ; ALL-LABEL: select_C_Cplus1_signext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: addi 3, 3, 42 ; ALL-NEXT: blr %sel = select i1 %cond, i32 41, i32 42 @@ -280,7 +280,7 @@ define i32 @select_C_Cplus1_signext(i1 signext %cond) { define i32 @select_C1_C2(i1 %cond) { ; ISEL-LABEL: select_C1_C2: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: li 4, 421 ; ISEL-NEXT: li 3, 42 @@ -288,7 +288,7 @@ define i32 @select_C1_C2(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_C1_C2: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: li 4, 421 ; NO_ISEL-NEXT: li 3, 42 @@ -303,7 +303,7 @@ define i32 @select_C1_C2(i1 %cond) { define i32 @select_C1_C2_zeroext(i1 zeroext %cond) { ; ISEL-LABEL: select_C1_C2_zeroext: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: li 4, 421 ; ISEL-NEXT: li 3, 42 @@ -311,7 +311,7 @@ define i32 @select_C1_C2_zeroext(i1 zeroext %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_C1_C2_zeroext: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: li 4, 421 ; NO_ISEL-NEXT: li 3, 42 @@ -326,7 +326,7 @@ define i32 @select_C1_C2_zeroext(i1 zeroext %cond) { define i32 @select_C1_C2_signext(i1 signext %cond) { ; ISEL-LABEL: select_C1_C2_signext: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: li 4, 421 ; ISEL-NEXT: li 3, 42 @@ -334,7 +334,7 @@ define i32 @select_C1_C2_signext(i1 signext %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_C1_C2_signext: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: li 4, 421 ; NO_ISEL-NEXT: li 3, 42 @@ -351,7 +351,7 @@ define i32 @select_C1_C2_signext(i1 signext %cond) { define i8 @sel_constants_add_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_add_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: li 4, 1 ; ISEL-NEXT: li 3, 28 @@ -359,7 +359,7 @@ define i8 @sel_constants_add_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_add_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: li 4, 1 ; NO_ISEL-NEXT: li 3, 28 @@ -375,7 +375,7 @@ define i8 @sel_constants_add_constant(i1 %cond) { define i8 @sel_constants_sub_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_sub_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -385,14 +385,14 @@ define i8 @sel_constants_sub_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_sub_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 ; NO_ISEL-NEXT: li 4, 18 ; NO_ISEL-NEXT: ori 3, 3, 65527 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i8 -4, i8 23 @@ -402,7 +402,7 @@ define i8 @sel_constants_sub_constant(i1 %cond) { define i8 @sel_constants_mul_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_mul_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: lis 4, 16383 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: ori 3, 4, 65531 @@ -412,14 +412,14 @@ define i8 @sel_constants_mul_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_mul_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: lis 4, 16383 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: ori 3, 4, 65531 ; NO_ISEL-NEXT: li 4, 115 ; NO_ISEL-NEXT: sldi 3, 3, 2 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i8 -4, i8 23 @@ -429,14 +429,14 @@ define i8 @sel_constants_mul_constant(i1 %cond) { define i8 @sel_constants_sdiv_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_sdiv_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: li 3, 4 ; ISEL-NEXT: isel 3, 0, 3, 1 ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_sdiv_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: li 3, 4 ; NO_ISEL-NEXT: bc 12, 1, .LBB24_1 @@ -451,7 +451,7 @@ define i8 @sel_constants_sdiv_constant(i1 %cond) { define i8 @sel_constants_udiv_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_udiv_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: li 4, 50 ; ISEL-NEXT: li 3, 4 @@ -459,7 +459,7 @@ define i8 @sel_constants_udiv_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_udiv_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: li 4, 50 ; NO_ISEL-NEXT: li 3, 4 @@ -475,7 +475,7 @@ define i8 @sel_constants_udiv_constant(i1 %cond) { define i8 @sel_constants_srem_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_srem_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: lis 4, 16383 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: ori 3, 4, 65535 @@ -485,14 +485,14 @@ define i8 @sel_constants_srem_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_srem_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: lis 4, 16383 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: ori 3, 4, 65535 ; NO_ISEL-NEXT: li 4, 3 ; NO_ISEL-NEXT: sldi 3, 3, 2 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i8 -4, i8 23 @@ -502,7 +502,7 @@ define i8 @sel_constants_srem_constant(i1 %cond) { define i8 @sel_constants_urem_constant(i1 %cond) { ; ALL-LABEL: sel_constants_urem_constant: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: rlwinm 3, 3, 0, 31, 31 ; ALL-NEXT: subfic 3, 3, 3 ; ALL-NEXT: blr @@ -513,7 +513,7 @@ define i8 @sel_constants_urem_constant(i1 %cond) { define i8 @sel_constants_and_constant(i1 %cond) { ; ALL-LABEL: sel_constants_and_constant: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: rlwinm 3, 3, 0, 31, 31 ; ALL-NEXT: subfic 3, 3, 5 ; ALL-NEXT: blr @@ -524,7 +524,7 @@ define i8 @sel_constants_and_constant(i1 %cond) { define i8 @sel_constants_or_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_or_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -534,14 +534,14 @@ define i8 @sel_constants_or_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_or_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 ; NO_ISEL-NEXT: li 4, 23 ; NO_ISEL-NEXT: ori 3, 3, 65533 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i8 -4, i8 23 @@ -551,7 +551,7 @@ define i8 @sel_constants_or_constant(i1 %cond) { define i8 @sel_constants_xor_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_xor_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -561,14 +561,14 @@ define i8 @sel_constants_xor_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_xor_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 ; NO_ISEL-NEXT: li 4, 18 ; NO_ISEL-NEXT: ori 3, 3, 65529 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i8 -4, i8 23 @@ -578,7 +578,7 @@ define i8 @sel_constants_xor_constant(i1 %cond) { define i8 @sel_constants_shl_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_shl_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: lis 5, 511 ; ISEL-NEXT: lis 4, 2047 ; ISEL-NEXT: andi. 3, 3, 1 @@ -590,7 +590,7 @@ define i8 @sel_constants_shl_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_shl_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: lis 5, 511 ; NO_ISEL-NEXT: lis 4, 2047 ; NO_ISEL-NEXT: andi. 3, 3, 1 @@ -610,7 +610,7 @@ define i8 @sel_constants_shl_constant(i1 %cond) { define i8 @sel_constants_lshr_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_lshr_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: li 4, 7 ; ISEL-NEXT: li 3, 0 @@ -618,7 +618,7 @@ define i8 @sel_constants_lshr_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_lshr_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: li 4, 7 ; NO_ISEL-NEXT: li 3, 0 @@ -634,7 +634,7 @@ define i8 @sel_constants_lshr_constant(i1 %cond) { define i8 @sel_constants_ashr_constant(i1 %cond) { ; ALL-LABEL: sel_constants_ashr_constant: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: neg 3, 3 ; ALL-NEXT: blr @@ -645,7 +645,7 @@ define i8 @sel_constants_ashr_constant(i1 %cond) { define double @sel_constants_fadd_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_fadd_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: addis 4, 2, .LCPI34_0@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI34_1@toc@ha @@ -656,14 +656,14 @@ define double @sel_constants_fadd_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fadd_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: addis 4, 2, .LCPI34_0@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI34_1@toc@ha ; NO_ISEL-NEXT: addi 4, 4, .LCPI34_0@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI34_1@toc@l ; NO_ISEL-NEXT: bc 12, 1, .LBB34_2 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB34_2 ; NO_ISEL-NEXT: .LBB34_2: @@ -676,7 +676,7 @@ define double @sel_constants_fadd_constant(i1 %cond) { define double @sel_constants_fsub_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_fsub_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: addis 4, 2, .LCPI35_0@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI35_1@toc@ha @@ -687,14 +687,14 @@ define double @sel_constants_fsub_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fsub_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: addis 4, 2, .LCPI35_0@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI35_1@toc@ha ; NO_ISEL-NEXT: addi 4, 4, .LCPI35_0@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI35_1@toc@l ; NO_ISEL-NEXT: bc 12, 1, .LBB35_2 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB35_2 ; NO_ISEL-NEXT: .LBB35_2: @@ -707,7 +707,7 @@ define double @sel_constants_fsub_constant(i1 %cond) { define double @sel_constants_fmul_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_fmul_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: addis 4, 2, .LCPI36_0@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI36_1@toc@ha @@ -718,14 +718,14 @@ define double @sel_constants_fmul_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fmul_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: addis 4, 2, .LCPI36_0@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI36_1@toc@ha ; NO_ISEL-NEXT: addi 4, 4, .LCPI36_0@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI36_1@toc@l ; NO_ISEL-NEXT: bc 12, 1, .LBB36_2 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB36_2 ; NO_ISEL-NEXT: .LBB36_2: @@ -738,7 +738,7 @@ define double @sel_constants_fmul_constant(i1 %cond) { define double @sel_constants_fdiv_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_fdiv_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: addis 4, 2, .LCPI37_0@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI37_1@toc@ha @@ -749,14 +749,14 @@ define double @sel_constants_fdiv_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fdiv_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: addis 4, 2, .LCPI37_0@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI37_1@toc@ha ; NO_ISEL-NEXT: addi 4, 4, .LCPI37_0@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI37_1@toc@l ; NO_ISEL-NEXT: bc 12, 1, .LBB37_2 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB37_2 ; NO_ISEL-NEXT: .LBB37_2: @@ -769,10 +769,10 @@ define double @sel_constants_fdiv_constant(i1 %cond) { define double @sel_constants_frem_constant(i1 %cond) { ; ALL-LABEL: sel_constants_frem_constant: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: andi. 3, 3, 1 ; ALL-NEXT: bc 12, 1, .LBB38_2 -; ALL-NEXT: # BB#1: +; ALL-NEXT: # %bb.1: ; ALL-NEXT: addis 3, 2, .LCPI38_0@toc@ha ; ALL-NEXT: addi 3, 3, .LCPI38_0@toc@l ; ALL-NEXT: lxsdx 1, 0, 3 @@ -780,7 +780,7 @@ define double @sel_constants_frem_constant(i1 %cond) { ; ALL-NEXT: .LBB38_2: ; ALL-NEXT: addis 3, 2, .LCPI38_1@toc@ha ; ALL-NEXT: addi 3, 3, .LCPI38_1@toc@l -; ALL-NEXT: lxsspx 1, 0, 3 +; ALL-NEXT: lfsx 1, 0, 3 ; ALL-NEXT: blr %sel = select i1 %cond, double -4.0, double 23.3 %bo = frem double %sel, 5.1 diff --git a/test/CodeGen/PowerPC/select_lt0.ll b/test/CodeGen/PowerPC/select_lt0.ll index 20d372a4cfd43..9164ee0c4e273 100644 --- a/test/CodeGen/PowerPC/select_lt0.ll +++ b/test/CodeGen/PowerPC/select_lt0.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep cmp +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep cmp define i32 @seli32_1(i32 %a) { entry: diff --git a/test/CodeGen/PowerPC/selectiondag-sextload.ll b/test/CodeGen/PowerPC/selectiondag-sextload.ll new file mode 100644 index 0000000000000..de33faf000acb --- /dev/null +++ b/test/CodeGen/PowerPC/selectiondag-sextload.ll @@ -0,0 +1,26 @@ +; RUN: llc --mtriple=powerpc64le-linux-gnu < %s | FileCheck %s + +; It tests in function DAGCombiner::visitSIGN_EXTEND_INREG +; signext will not be combined with extload, and causes extra zext. + +declare void @g(i32 signext) + +define void @foo(i8* %p) { +entry: + br label %while.body + +while.body: + %0 = load i8, i8* %p, align 1 + %conv = zext i8 %0 to i32 + %cmp = icmp sgt i8 %0, 0 + br i1 %cmp, label %if.then, label %while.body +; CHECK: lbz +; CHECK: extsb. +; CHECK-NOT: rlwinm +; CHECK: ble + +if.then: + tail call void @g(i32 signext %conv) + br label %while.body +} + diff --git a/test/CodeGen/PowerPC/setcc-logic.ll b/test/CodeGen/PowerPC/setcc-logic.ll index 8a6f4975ec97b..3b9b5228fa4b7 100644 --- a/test/CodeGen/PowerPC/setcc-logic.ll +++ b/test/CodeGen/PowerPC/setcc-logic.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown | FileCheck %s +; RUN: llc < %s -ppc-gpr-icmps=all -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -ppc-convert-rr-to-ri=true | FileCheck %s define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) { ; CHECK-LABEL: all_bits_clear: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: srwi 3, 3, 5 @@ -16,7 +16,7 @@ define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) { define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q) { ; CHECK-LABEL: all_sign_bits_clear: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: nor 3, 3, 3 ; CHECK-NEXT: srwi 3, 3, 31 @@ -29,7 +29,7 @@ define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q) { define zeroext i1 @all_bits_set(i32 %P, i32 %Q) { ; CHECK-LABEL: all_bits_set: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: li 5, -1 ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: xor 3, 3, 5 @@ -44,7 +44,7 @@ define zeroext i1 @all_bits_set(i32 %P, i32 %Q) { define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) { ; CHECK-LABEL: all_sign_bits_set: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: srwi 3, 3, 31 ; CHECK-NEXT: blr @@ -56,7 +56,7 @@ define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) { define zeroext i1 @any_bits_set(i32 %P, i32 %Q) { ; CHECK-LABEL: any_bits_set: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: srwi 3, 3, 5 @@ -70,7 +70,7 @@ define zeroext i1 @any_bits_set(i32 %P, i32 %Q) { define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) { ; CHECK-LABEL: any_sign_bits_set: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: srwi 3, 3, 31 ; CHECK-NEXT: blr @@ -82,7 +82,7 @@ define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) { define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) { ; CHECK-LABEL: any_bits_clear: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: li 5, -1 ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: xor 3, 3, 5 @@ -98,7 +98,7 @@ define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) { define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) { ; CHECK-LABEL: any_sign_bits_clear: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: nor 3, 3, 3 ; CHECK-NEXT: srwi 3, 3, 31 @@ -112,10 +112,10 @@ define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) { ; PR3351 - (P == 0) & (Q == 0) -> (P|Q) == 0 define i32 @all_bits_clear_branch(i32* %P, i32* %Q) { ; CHECK-LABEL: all_bits_clear_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or. 3, 3, 4 ; CHECK-NEXT: bne 0, .LBB8_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB8_2: # %return @@ -136,11 +136,11 @@ return: define i32 @all_sign_bits_clear_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: all_sign_bits_clear_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: cmpwi 0, 3, 0 ; CHECK-NEXT: blt 0, .LBB9_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB9_2: # %return @@ -161,11 +161,11 @@ return: define i32 @all_bits_set_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: all_bits_set_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: bne 0, .LBB10_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB10_2: # %return @@ -186,11 +186,11 @@ return: define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: all_sign_bits_set_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: bgt 0, .LBB11_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB11_2: # %return @@ -212,10 +212,10 @@ return: ; PR3351 - (P != 0) | (Q != 0) -> (P|Q) != 0 define i32 @any_bits_set_branch(i32* %P, i32* %Q) { ; CHECK-LABEL: any_bits_set_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or. 3, 3, 4 ; CHECK-NEXT: beq 0, .LBB12_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB12_2: # %return @@ -236,11 +236,11 @@ return: define i32 @any_sign_bits_set_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: any_sign_bits_set_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: bgt 0, .LBB13_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB13_2: # %return @@ -261,11 +261,11 @@ return: define i32 @any_bits_clear_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: any_bits_clear_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: beq 0, .LBB14_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB14_2: # %return @@ -286,11 +286,11 @@ return: define i32 @any_sign_bits_clear_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: any_sign_bits_clear_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: cmpwi 0, 3, 0 ; CHECK-NEXT: blt 0, .LBB15_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB15_2: # %return @@ -311,7 +311,7 @@ return: define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: all_bits_clear_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xxlxor 36, 36, 36 ; CHECK-NEXT: xxlor 34, 34, 35 ; CHECK-NEXT: vcmpequw 2, 2, 4 @@ -324,7 +324,7 @@ define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: all_sign_bits_clear_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisb 4, -1 ; CHECK-NEXT: xxlor 34, 34, 35 ; CHECK-NEXT: vcmpgtsw 2, 2, 4 @@ -337,7 +337,7 @@ define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: all_bits_set_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisb 4, -1 ; CHECK-NEXT: xxland 34, 34, 35 ; CHECK-NEXT: vcmpequw 2, 2, 4 @@ -350,7 +350,7 @@ define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: all_sign_bits_set_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xxlxor 36, 36, 36 ; CHECK-NEXT: xxland 34, 34, 35 ; CHECK-NEXT: vcmpgtsw 2, 4, 2 @@ -363,7 +363,7 @@ define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: any_bits_set_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xxlxor 36, 36, 36 ; CHECK-NEXT: xxlor 34, 34, 35 ; CHECK-NEXT: vcmpequw 2, 2, 4 @@ -377,7 +377,7 @@ define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: any_sign_bits_set_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xxlxor 36, 36, 36 ; CHECK-NEXT: xxlor 34, 34, 35 ; CHECK-NEXT: vcmpgtsw 2, 4, 2 @@ -390,7 +390,7 @@ define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: any_bits_clear_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisb 4, -1 ; CHECK-NEXT: xxland 34, 34, 35 ; CHECK-NEXT: vcmpequw 2, 2, 4 @@ -404,7 +404,7 @@ define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: any_sign_bits_clear_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisb 4, -1 ; CHECK-NEXT: xxland 34, 34, 35 ; CHECK-NEXT: vcmpgtsw 2, 2, 4 @@ -417,12 +417,12 @@ define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) { ; CHECK-LABEL: ne_neg1_and_ne_zero: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: addi 3, 3, 1 -; CHECK-NEXT: li 4, 0 -; CHECK-NEXT: li 12, 1 -; CHECK-NEXT: cmpldi 3, 1 -; CHECK-NEXT: isel 3, 12, 4, 1 +; CHECK-NEXT: li 4, 1 +; CHECK-NEXT: subfic 3, 3, 1 +; CHECK-NEXT: subfe 3, 4, 4 +; CHECK-NEXT: neg 3, 3 ; CHECK-NEXT: blr %cmp1 = icmp ne i64 %x, -1 %cmp2 = icmp ne i64 %x, 0 @@ -434,7 +434,7 @@ define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) { define zeroext i1 @and_eq(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) { ; CHECK-LABEL: and_eq: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xor 5, 5, 6 ; CHECK-NEXT: xor 3, 3, 4 ; CHECK-NEXT: or 3, 3, 5 @@ -449,7 +449,7 @@ define zeroext i1 @and_eq(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 z define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK-LABEL: or_ne: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xor 5, 5, 6 ; CHECK-NEXT: xor 3, 3, 4 ; CHECK-NEXT: or 3, 3, 5 @@ -467,7 +467,7 @@ define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) { define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { ; CHECK-LABEL: and_eq_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: vcmpequw 19, 4, 5 ; CHECK-NEXT: xxland 34, 34, 51 diff --git a/test/CodeGen/PowerPC/setcc-to-sub.ll b/test/CodeGen/PowerPC/setcc-to-sub.ll index 752ebe0c9d8b5..a143d73c7c0ca 100644 --- a/test/CodeGen/PowerPC/setcc-to-sub.ll +++ b/test/CodeGen/PowerPC/setcc-to-sub.ll @@ -8,7 +8,7 @@ ; Function Attrs: norecurse nounwind readonly define zeroext i1 @test1(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { ; CHECK-LABEL: test1: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 @@ -30,7 +30,7 @@ entry: ; Function Attrs: norecurse nounwind readonly define zeroext i1 @test2(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { ; CHECK-LABEL: test2: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 @@ -53,7 +53,7 @@ entry: ; Function Attrs: norecurse nounwind readonly define zeroext i1 @test3(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { ; CHECK-LABEL: test3: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 @@ -75,7 +75,7 @@ entry: ; Function Attrs: norecurse nounwind readonly define zeroext i1 @test4(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { ; CHECK-LABEL: test4: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 diff --git a/test/CodeGen/PowerPC/setcc_no_zext.ll b/test/CodeGen/PowerPC/setcc_no_zext.ll index d3501fc88b674..14d64071c7028 100644 --- a/test/CodeGen/PowerPC/setcc_no_zext.ll +++ b/test/CodeGen/PowerPC/setcc_no_zext.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep rlwinm +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep rlwinm ; FIXME: This optimization has temporarily regressed with crbits enabled by ; default at the default CodeOpt level. diff --git a/test/CodeGen/PowerPC/seteq-0.ll b/test/CodeGen/PowerPC/seteq-0.ll index 4863ca266cc75..721b6613c8ccc 100644 --- a/test/CodeGen/PowerPC/seteq-0.ll +++ b/test/CodeGen/PowerPC/seteq-0.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 | FileCheck %s define i32 @eq0(i32 %a) { %tmp.1 = icmp eq i32 %a, 0 ; <i1> [#uses=1] diff --git a/test/CodeGen/PowerPC/shift_mask.ll b/test/CodeGen/PowerPC/shift_mask.ll index e9ca9b0bdf022..59382c6153119 100644 --- a/test/CodeGen/PowerPC/shift_mask.ll +++ b/test/CodeGen/PowerPC/shift_mask.ll @@ -4,7 +4,7 @@ target triple = "powerpc64le-linux-gnu" define i8 @test000(i8 %a, i8 %b) { ; CHECK-LABEL: test000: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31 ; CHECK-NEXT: slw 3, 3, 4 ; CHECK-NEXT: blr @@ -15,7 +15,7 @@ define i8 @test000(i8 %a, i8 %b) { define i16 @test001(i16 %a, i16 %b) { ; CHECK-LABEL: test001: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 ; CHECK-NEXT: slw 3, 3, 4 ; CHECK-NEXT: blr @@ -26,7 +26,7 @@ define i16 @test001(i16 %a, i16 %b) { define i32 @test002(i32 %a, i32 %b) { ; CHECK-LABEL: test002: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31 ; CHECK-NEXT: slw 3, 3, 4 ; CHECK-NEXT: blr @@ -37,7 +37,7 @@ define i32 @test002(i32 %a, i32 %b) { define i64 @test003(i64 %a, i64 %b) { ; CHECK-LABEL: test003: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31 ; CHECK-NEXT: sld 3, 3, 4 ; CHECK-NEXT: blr @@ -48,7 +48,7 @@ define i64 @test003(i64 %a, i64 %b) { define <16 x i8> @test010(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: test010: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vslb 2, 2, 3 ; CHECK-NEXT: blr %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> @@ -58,7 +58,7 @@ define <16 x i8> @test010(<16 x i8> %a, <16 x i8> %b) { define <8 x i16> @test011(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: test011: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vslh 2, 2, 3 ; CHECK-NEXT: blr %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> @@ -68,7 +68,7 @@ define <8 x i16> @test011(<8 x i16> %a, <8 x i16> %b) { define <4 x i32> @test012(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: test012: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vslw 2, 2, 3 ; CHECK-NEXT: blr %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31> @@ -78,7 +78,7 @@ define <4 x i32> @test012(<4 x i32> %a, <4 x i32> %b) { define <2 x i64> @test013(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: test013: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsld 2, 2, 3 ; CHECK-NEXT: blr %rem = and <2 x i64> %b, <i64 63, i64 63> @@ -88,7 +88,7 @@ define <2 x i64> @test013(<2 x i64> %a, <2 x i64> %b) { define i8 @test100(i8 %a, i8 %b) { ; CHECK-LABEL: test100: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 3, 3, 0, 24, 31 ; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31 ; CHECK-NEXT: srw 3, 3, 4 @@ -100,7 +100,7 @@ define i8 @test100(i8 %a, i8 %b) { define i16 @test101(i16 %a, i16 %b) { ; CHECK-LABEL: test101: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 3, 3, 0, 16, 31 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 ; CHECK-NEXT: srw 3, 3, 4 @@ -112,7 +112,7 @@ define i16 @test101(i16 %a, i16 %b) { define i32 @test102(i32 %a, i32 %b) { ; CHECK-LABEL: test102: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31 ; CHECK-NEXT: srw 3, 3, 4 ; CHECK-NEXT: blr @@ -123,7 +123,7 @@ define i32 @test102(i32 %a, i32 %b) { define i64 @test103(i64 %a, i64 %b) { ; CHECK-LABEL: test103: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31 ; CHECK-NEXT: srd 3, 3, 4 ; CHECK-NEXT: blr @@ -134,7 +134,7 @@ define i64 @test103(i64 %a, i64 %b) { define <16 x i8> @test110(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: test110: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsrb 2, 2, 3 ; CHECK-NEXT: blr %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> @@ -144,7 +144,7 @@ define <16 x i8> @test110(<16 x i8> %a, <16 x i8> %b) { define <8 x i16> @test111(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: test111: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsrh 2, 2, 3 ; CHECK-NEXT: blr %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> @@ -154,7 +154,7 @@ define <8 x i16> @test111(<8 x i16> %a, <8 x i16> %b) { define <4 x i32> @test112(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: test112: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsrw 2, 2, 3 ; CHECK-NEXT: blr %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31> @@ -164,7 +164,7 @@ define <4 x i32> @test112(<4 x i32> %a, <4 x i32> %b) { define <2 x i64> @test113(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: test113: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsrd 2, 2, 3 ; CHECK-NEXT: blr %rem = and <2 x i64> %b, <i64 63, i64 63> @@ -174,7 +174,7 @@ define <2 x i64> @test113(<2 x i64> %a, <2 x i64> %b) { define i8 @test200(i8 %a, i8 %b) { ; CHECK-LABEL: test200: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: extsb 3, 3 ; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31 ; CHECK-NEXT: sraw 3, 3, 4 @@ -186,7 +186,7 @@ define i8 @test200(i8 %a, i8 %b) { define i16 @test201(i16 %a, i16 %b) { ; CHECK-LABEL: test201: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: extsh 3, 3 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 ; CHECK-NEXT: sraw 3, 3, 4 @@ -198,7 +198,7 @@ define i16 @test201(i16 %a, i16 %b) { define i32 @test202(i32 %a, i32 %b) { ; CHECK-LABEL: test202: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31 ; CHECK-NEXT: sraw 3, 3, 4 ; CHECK-NEXT: blr @@ -209,7 +209,7 @@ define i32 @test202(i32 %a, i32 %b) { define i64 @test203(i64 %a, i64 %b) { ; CHECK-LABEL: test203: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31 ; CHECK-NEXT: srad 3, 3, 4 ; CHECK-NEXT: blr @@ -220,7 +220,7 @@ define i64 @test203(i64 %a, i64 %b) { define <16 x i8> @test210(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: test210: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsrab 2, 2, 3 ; CHECK-NEXT: blr %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> @@ -230,7 +230,7 @@ define <16 x i8> @test210(<16 x i8> %a, <16 x i8> %b) { define <8 x i16> @test211(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: test211: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsrah 2, 2, 3 ; CHECK-NEXT: blr %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> @@ -240,7 +240,7 @@ define <8 x i16> @test211(<8 x i16> %a, <8 x i16> %b) { define <4 x i32> @test212(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: test212: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsraw 2, 2, 3 ; CHECK-NEXT: blr %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31> @@ -250,7 +250,7 @@ define <4 x i32> @test212(<4 x i32> %a, <4 x i32> %b) { define <2 x i64> @test213(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: test213: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsrad 2, 2, 3 ; CHECK-NEXT: blr %rem = and <2 x i64> %b, <i64 63, i64 63> diff --git a/test/CodeGen/PowerPC/shl_elim.ll b/test/CodeGen/PowerPC/shl_elim.ll index 2570317795767..8d360f7143fb1 100644 --- a/test/CodeGen/PowerPC/shl_elim.ll +++ b/test/CodeGen/PowerPC/shl_elim.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep slwi +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep slwi define i32 @test1(i64 %a) { %tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1] diff --git a/test/CodeGen/PowerPC/shl_sext.ll b/test/CodeGen/PowerPC/shl_sext.ll index 62fb935808c27..cf83944fef8d6 100644 --- a/test/CodeGen/PowerPC/shl_sext.ll +++ b/test/CodeGen/PowerPC/shl_sext.ll @@ -1,5 +1,5 @@ ; This test should not contain a sign extend -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep extsb +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep extsb define i32 @test(i32 %mode.0.i.0) { %tmp.79 = trunc i32 %mode.0.i.0 to i8 ; <i8> [#uses=1] diff --git a/test/CodeGen/PowerPC/sign_ext_inreg1.ll b/test/CodeGen/PowerPC/sign_ext_inreg1.ll index fc037ace1ec45..ffb53802c8ff9 100644 --- a/test/CodeGen/PowerPC/sign_ext_inreg1.ll +++ b/test/CodeGen/PowerPC/sign_ext_inreg1.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep srwi -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep rlwimi +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep srwi +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep rlwimi define i32 @baz(i64 %a) { %tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1] diff --git a/test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll b/test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll new file mode 100644 index 0000000000000..3988d9c8d5a98 --- /dev/null +++ b/test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll @@ -0,0 +1,51 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 \ +; RUN: -ppc-convert-rr-to-ri -verify-machineinstrs | FileCheck %s +define void @test(i32 zeroext %parts) { +; CHECK-LABEL: test: +; CHECK: # %bb.0: # %cond.end.i +; CHECK-NEXT: cmplwi 0, 3, 1 +; CHECK-NEXT: bnelr+ 0 +; CHECK-NEXT: # %bb.1: # %test2.exit.us.unr-lcssa +; CHECK-NEXT: ld 3, 0(3) +; CHECK-NEXT: std 3, 0(3) +entry: + br label %cond.end.i + +cond.end.i: ; preds = %entry + %cmp18.i = icmp eq i32 %parts, 1 + br i1 %cmp18.i, label %while.body.lr.ph.i.us.preheader, label %test3.exit.split + +while.body.lr.ph.i.us.preheader: ; preds = %cond.end.i + %0 = icmp eq i32 %parts, 1 + br label %for.body.i62.us.preheader + +for.body.i62.us.preheader: ; preds = %while.body.lr.ph.i.us.preheader + br i1 %0, label %test2.exit.us.unr-lcssa, label %for.body.i62.us.preheader.new + +for.body.i62.us.preheader.new: ; preds = %for.body.i62.us.preheader + br label %for.body.i62.us + +for.body.i62.us: ; preds = %if.end.i.us.1, %for.body.i62.us.preheader.new + %niter = phi i64 [ undef, %for.body.i62.us.preheader.new ], [ %niter.nsub.1, %if.end.i.us.1 ] + %cmp8.i.us.1 = icmp uge i64 undef, 0 + br label %if.end.i.us.1 + +test2.exit.us.unr-lcssa: ; preds = %if.end.i.us.1, %for.body.i62.us.preheader + %c.addr.036.i.us.unr = phi i64 [ 0, %for.body.i62.us.preheader ], [ %c.addr.1.i.us.1, %if.end.i.us.1 ] + %1 = load i64, i64* undef, align 8 + %tobool.i61.us.epil = icmp eq i64 %c.addr.036.i.us.unr, 0 + %add.neg.i.us.epil.pn = select i1 %tobool.i61.us.epil, i64 %1, i64 0 + %storemerge269 = sub i64 %add.neg.i.us.epil.pn, 0 + store i64 %storemerge269, i64* undef, align 8 + unreachable + +test3.exit.split: ; preds = %cond.end.i + ret void + +if.end.i.us.1: ; preds = %for.body.i62.us + %c.addr.1.i.us.1 = zext i1 %cmp8.i.us.1 to i64 + %niter.nsub.1 = add i64 %niter, -2 + %niter.ncmp.1 = icmp eq i64 %niter.nsub.1, 0 + br i1 %niter.ncmp.1, label %test2.exit.us.unr-lcssa, label %for.body.i62.us +} diff --git a/test/CodeGen/PowerPC/sjlj.ll b/test/CodeGen/PowerPC/sjlj.ll index f86f5345f8760..68b53417f01ec 100644 --- a/test/CodeGen/PowerPC/sjlj.ll +++ b/test/CodeGen/PowerPC/sjlj.ll @@ -60,7 +60,7 @@ return: ; preds = %if.end, %if.then ; FIXME: We should be saving VRSAVE on Darwin, but we're not! -; CHECK: @main +; CHECK-LABEL: main: ; CHECK: std ; Make sure that we're not saving VRSAVE on non-Darwin: ; CHECK-NOT: mfspr @@ -77,7 +77,7 @@ return: ; preds = %if.end, %if.then ; CHECK: bcl 20, 31, .LBB1_3 ; CHECK: li 3, 1 ; CHECK: #EH_SjLj_Setup .LBB1_3 -; CHECK: b .LBB1_1 +; CHECK: # %bb.1: ; CHECK: .LBB1_3: ; CHECK: mflr [[REGL:[0-9]+]] @@ -87,12 +87,12 @@ return: ; preds = %if.end, %if.then ; CHECK: .LBB1_5: -; CHECK: lfd -; CHECK: lxvd2x +; CHECK-DAG: lfd +; CHECK-DAG: lxvd2x ; CHECK: ld ; CHECK: blr -; CHECK-NOAV: @main +; CHECK-NOAV-LABEL: main: ; CHECK-NOAV-NOT: stxvd2x ; CHECK-NOAV: bcl ; CHECK-NOAV: mflr @@ -131,7 +131,7 @@ return: ; preds = %if.end, %if.then %3 = load i32, i32* %retval ret i32 %3 -; CHECK: @main2 +; CHECK-LABEL: main2: ; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha ; CHECK-DAG: std 31, env_sigill@toc@l([[REG]]) diff --git a/test/CodeGen/PowerPC/small-arguments.ll b/test/CodeGen/PowerPC/small-arguments.ll index 07f93d5630849..d35ef3d514c52 100644 --- a/test/CodeGen/PowerPC/small-arguments.ll +++ b/test/CodeGen/PowerPC/small-arguments.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep "extsh\|rlwinm" +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep "extsh\|rlwinm" declare signext i16 @foo() diff --git a/test/CodeGen/PowerPC/splat-larger-types-as-v16i8.ll b/test/CodeGen/PowerPC/splat-larger-types-as-v16i8.ll new file mode 100644 index 0000000000000..2ae61f1bb57c6 --- /dev/null +++ b/test/CodeGen/PowerPC/splat-larger-types-as-v16i8.ll @@ -0,0 +1,20 @@ +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s +define <8 x i16> @test1() { +entry: + ret <8 x i16> <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257> +; CHECK-LABEL: test1 +; CHECK: xxspltib 34, 1 +} +define <8 x i16> @testAB() { +entry: +; CHECK-LABEL: testAB +; CHECK: xxspltib 34, 171 + ret <8 x i16> <i16 43947, i16 43947, i16 43947, i16 43947, i16 43947, i16 43947, i16 43947, i16 43947> +} +define <4 x i32> @testAB32() { +entry: +; CHECK-LABEL: testAB32 +; CHECK: xxspltib 34, 171 + ret <4 x i32> <i32 2880154539, i32 2880154539, i32 2880154539, i32 2880154539> +} diff --git a/test/CodeGen/PowerPC/stfiwx.ll b/test/CodeGen/PowerPC/stfiwx.ll index 9b995e08256c9..bb53589c9de8b 100644 --- a/test/CodeGen/PowerPC/stfiwx.ll +++ b/test/CodeGen/PowerPC/stfiwx.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=stfiwx | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-stfiwx | FileCheck -check-prefix=CHECK-LS %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 -mattr=stfiwx | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin8 -mattr=-stfiwx | FileCheck -check-prefix=CHECK-LS %s define void @test1(float %a, i32* %b) nounwind { ; CHECK-LABEL: @test1 diff --git a/test/CodeGen/PowerPC/store-constant.ll b/test/CodeGen/PowerPC/store-constant.ll new file mode 100644 index 0000000000000..60b06f34882b4 --- /dev/null +++ b/test/CodeGen/PowerPC/store-constant.ll @@ -0,0 +1,191 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s + +@CVal = external local_unnamed_addr global i8, align 1 +@SVal = external local_unnamed_addr global i16, align 2 +@IVal = external local_unnamed_addr global i32, align 4 +@LVal = external local_unnamed_addr global i64, align 8 +@USVal = external local_unnamed_addr global i16, align 2 +@arr = external local_unnamed_addr global i64*, align 8 +@arri = external local_unnamed_addr global i32*, align 8 + +; Test the same constant can be used by different stores. + +%struct.S = type { i64, i8, i16, i32 } + +define void @foo(%struct.S* %p) { + %l4 = bitcast %struct.S* %p to i64* + store i64 0, i64* %l4, align 8 + %c = getelementptr %struct.S, %struct.S* %p, i64 0, i32 1 + store i8 0, i8* %c, align 8 + %s = getelementptr %struct.S, %struct.S* %p, i64 0, i32 2 + store i16 0, i16* %s, align 2 + %i = getelementptr %struct.S, %struct.S* %p, i64 0, i32 3 + store i32 0, i32* %i, align 4 + ret void + +; CHECK-LABEL: @foo +; CHECK: li 4, 0 +; CHECK: stb 4, 8(3) +; CHECK: std 4, 0(3) +; CHECK: sth 4, 10(3) +; CHECK: stw 4, 12(3) +} + +define void @bar(%struct.S* %p) { + %i = getelementptr %struct.S, %struct.S* %p, i64 0, i32 3 + store i32 2, i32* %i, align 4 + %s = getelementptr %struct.S, %struct.S* %p, i64 0, i32 2 + store i16 2, i16* %s, align 2 + %c = getelementptr %struct.S, %struct.S* %p, i64 0, i32 1 + store i8 2, i8* %c, align 8 + %l4 = bitcast %struct.S* %p to i64* + store i64 2, i64* %l4, align 8 + ret void + +; CHECK-LABEL: @bar +; CHECK: li 4, 2 +; CHECK: stw 4, 12(3) +; CHECK: sth 4, 10(3) +; CHECK: std 4, 0(3) +; CHECK: stb 4, 8(3) +} + +; Function Attrs: norecurse nounwind +define void @setSmallNeg() { +entry: + store i8 -7, i8* @CVal, align 1 + store i16 -7, i16* @SVal, align 2 + store i32 -7, i32* @IVal, align 4 + store i64 -7, i64* @LVal, align 8 + ret void +; CHECK-LABEL: setSmallNeg +; CHECK: li 7, -7 +; CHECK-DAG: stb 7, +; CHECK-DAG: sth 7, +; CHECK-DAG: stw 7, +; CHECK-DAG: std 7, +} + +; Function Attrs: norecurse nounwind +define void @setSmallPos() { +entry: + store i8 8, i8* @CVal, align 1 + store i16 8, i16* @SVal, align 2 + store i32 8, i32* @IVal, align 4 + store i64 8, i64* @LVal, align 8 + ret void +; CHECK-LABEL: setSmallPos +; CHECK: li 7, 8 +; CHECK-DAG: stb 7, +; CHECK-DAG: sth 7, +; CHECK-DAG: stw 7, +; CHECK-DAG: std 7, +} + +; Function Attrs: norecurse nounwind +define void @setMaxNeg() { +entry: + store i16 -32768, i16* @SVal, align 2 + store i32 -32768, i32* @IVal, align 4 + store i64 -32768, i64* @LVal, align 8 + ret void +; CHECK-LABEL: setMaxNeg +; CHECK: li 6, -32768 +; CHECK-DAG: sth 6, +; CHECK-DAG: stw 6, +; CHECK-DAG: std 6, +} + +; Function Attrs: norecurse nounwind +define void @setMaxPos() { +entry: + store i16 32767, i16* @SVal, align 2 + store i32 32767, i32* @IVal, align 4 + store i64 32767, i64* @LVal, align 8 + ret void +; CHECK-LABEL: setMaxPos +; CHECK: li 6, 32767 +; CHECK-DAG: sth 6, +; CHECK-DAG: stw 6, +; CHECK-DAG: std 6, +} + +; Function Attrs: norecurse nounwind +define void @setExcessiveNeg() { +entry: + store i32 -32769, i32* @IVal, align 4 + store i64 -32769, i64* @LVal, align 8 + ret void +; CHECK-LABEL: setExcessiveNeg +; CHECK: lis 5, -1 +; CHECK: ori 5, 5, 32767 +; CHECK-DAG: stw 5, +; CHECK-DAG: std 5, +} + +; Function Attrs: norecurse nounwind +define void @setExcessivePos() { +entry: + store i16 -32768, i16* @USVal, align 2 + store i32 32768, i32* @IVal, align 4 + store i64 32768, i64* @LVal, align 8 + ret void +; CHECK-LABEL: setExcessivePos +; CHECK: li 6, 0 +; CHECK: ori 6, 6, 32768 +; CHECK-DAG: sth 6, +; CHECK-DAG: stw 6, +; CHECK-DAG: std 6, +} + +define void @SetArr(i32 signext %Len) { +entry: + %cmp7 = icmp sgt i32 %Len, 0 + br i1 %cmp7, label %for.body.lr.ph, label %for.cond.cleanup + +for.body.lr.ph: ; preds = %entry + %0 = load i64*, i64** @arr, align 8 + %1 = load i32*, i32** @arri, align 8 + %wide.trip.count = zext i32 %Len to i64 + br label %for.body + +for.cond.cleanup: ; preds = %for.body, %entry + ret void + +for.body: ; preds = %for.body, %for.body.lr.ph + %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i64, i64* %0, i64 %indvars.iv + store i64 -7, i64* %arrayidx, align 8 + %arrayidx2 = getelementptr inbounds i32, i32* %1, i64 %indvars.iv + store i32 -7, i32* %arrayidx2, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count + br i1 %exitcond, label %for.cond.cleanup, label %for.body +; CHECK-LABEL: SetArr +; CHECK: li 5, -7 +; CHECK: stdu 5, 8(3) +; CHECK: stwu 5, 4(4) +} + +define void @setSameValDiffSizeCI() { +entry: + store i32 255, i32* @IVal, align 4 + store i8 -1, i8* @CVal, align 1 + ret void +; CHECK-LABEL: setSameValDiffSizeCI +; CHECK: li 5, 255 +; CHECK-DAG: stb 5, +; CHECK-DAG: stw 5, +} + +define void @setSameValDiffSizeSI() { +entry: + store i32 65535, i32* @IVal, align 4 + store i16 -1, i16* @SVal, align 2 + ret void +; CHECK-LABEL: setSameValDiffSizeSI +; CHECK: li 5, 0 +; CHECK: ori 5, 5, 65535 +; CHECK-DAG: sth 5, +; CHECK-DAG: stw 5, +} diff --git a/test/CodeGen/PowerPC/store-load-fwd.ll b/test/CodeGen/PowerPC/store-load-fwd.ll index 12e1dbe319f56..3d0b8096dc4d8 100644 --- a/test/CodeGen/PowerPC/store-load-fwd.ll +++ b/test/CodeGen/PowerPC/store-load-fwd.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | not grep lwz +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep lwz define i32 @test(i32* %P) { store i32 1, i32* %P diff --git a/test/CodeGen/PowerPC/subc.ll b/test/CodeGen/PowerPC/subc.ll index f09150a82d1c4..c9cb5761739bf 100644 --- a/test/CodeGen/PowerPC/subc.ll +++ b/test/CodeGen/PowerPC/subc.ll @@ -1,5 +1,5 @@ ; All of these should be codegen'd without loading immediates -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -o %t +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t ; RUN: grep subfc %t | count 1 ; RUN: grep subfe %t | count 1 ; RUN: grep subfze %t | count 1 diff --git a/test/CodeGen/PowerPC/subreg-postra-2.ll b/test/CodeGen/PowerPC/subreg-postra-2.ll index 338000cd8bae6..794c9c190d1c6 100644 --- a/test/CodeGen/PowerPC/subreg-postra-2.ll +++ b/test/CodeGen/PowerPC/subreg-postra-2.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gep-opt=0 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false -ppc-gep-opt=0 < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -38,10 +38,10 @@ while.end418: ; preds = %wait_on_buffer.exit ; CHECK: stdcx. ; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]] ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] -; CHECK-NO-ISEL: ori 4, 7, 0 +; CHECK-NO-ISEL: ori 7, 8, 0 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-NO-ISEL: [[TRUE]] -; CHECK-NO-ISEL-NEXT: addi 4, 3, 0 +; CHECK-NO-ISEL: addi 7, 3, 0 if.then420: ; preds = %while.end418 unreachable diff --git a/test/CodeGen/PowerPC/tail-dup-branch-to-fallthrough.ll b/test/CodeGen/PowerPC/tail-dup-branch-to-fallthrough.ll index 0b1014571613d..3ff4753200ef6 100644 --- a/test/CodeGen/PowerPC/tail-dup-branch-to-fallthrough.ll +++ b/test/CodeGen/PowerPC/tail-dup-branch-to-fallthrough.ll @@ -12,17 +12,17 @@ declare void @f4() ; Function Attrs: nounwind ; CHECK-LABEL: tail_dup_fallthrough_with_branch -; CHECK: # %entry +; CHECK: # %bb.{{[0-9]+}}: # %entry ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} -; CHECK: # %entry +; CHECK: # %bb.{{[0-9]+}}: # %entry ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} -; CHECK: # %sw.0 +; CHECK: # %bb.{{[0-9]+}}: # %sw.0 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} ; CHECK: # %sw.1 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} ; CHECK: # %sw.default ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} -; CHECK: # %if.then +; CHECK: # %bb.{{[0-9]+}}: # %if.then ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} ; CHECK: # %if.else ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} diff --git a/test/CodeGen/PowerPC/tail-dup-layout.ll b/test/CodeGen/PowerPC/tail-dup-layout.ll index 9665901e874fc..c9019983e933c 100644 --- a/test/CodeGen/PowerPC/tail-dup-layout.ll +++ b/test/CodeGen/PowerPC/tail-dup-layout.ll @@ -1,5 +1,7 @@ -; RUN: llc -O2 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-O2 %s -; RUN: llc -O3 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-O3 %s +; RUN: llc -O2 -ppc-reduce-cr-logicals -o - %s | FileCheck \ +; RUN: --check-prefix=CHECK --check-prefix=CHECK-O2 %s +; RUN: llc -O3 -ppc-reduce-cr-logicals -o - %s | FileCheck \ +; RUN: --check-prefix=CHECK --check-prefix=CHECK-O3 %s target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-grtev4-linux-gnu" @@ -276,9 +278,10 @@ exit: ;CHECK: add [[TAGPTRREG:[0-9]+]], 3, 4 ;CHECK: .[[LATCHLABEL:[._0-9A-Za-z]+]]: # %for.latch ;CHECK: addi -;CHECK: .[[CHECKLABEL:[._0-9A-Za-z]+]]: # %for.check +;CHECK-O2: .[[CHECKLABEL:[._0-9A-Za-z]+]]: # %for.check ;CHECK: lwz [[TAGREG:[0-9]+]], 0([[TAGPTRREG]]) -;CHECK: # %test1 +;CHECK-O3: .[[CHECKLABEL:[._0-9A-Za-z]+]]: # %for.check +;CHECK: # %bb.{{[0-9]+}}: # %test1 ;CHECK: andi. {{[0-9]+}}, [[TAGREG]], 1 ;CHECK-NEXT: bc 12, 1, .[[OPT1LABEL:[._0-9A-Za-z]+]] ;CHECK-NEXT: # %test2 @@ -366,12 +369,12 @@ exit: ; code is independent of the outlining code, which works by choosing the ; "unavoidable" blocks. ; CHECK-LABEL: avoidable_test: -; CHECK: # %entry +; CHECK: # %bb.{{[0-9]+}}: # %entry ; CHECK: andi. -; CHECK: # %test2 +; CHECK: # %bb.{{[0-9]+}}: # %test2 ; Make sure then2 falls through from test2 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} -; CHECK: # %then2 +; CHECK: # %bb.{{[0-9]+}}: # %then2 ; CHECK: rlwinm. {{[0-9]+}}, {{[0-9]+}}, 0, 29, 29 ; CHECK: # %else1 ; CHECK: bl a @@ -420,8 +423,8 @@ end1: ; The f;g->h;i trellis should be resolved as f->i;g->h. ; The h;i->j;ret trellis contains a triangle edge, and should be resolved as ; h->j->ret -; CHECK: # %entry -; CHECK: # %c10 +; CHECK: # %bb.{{[0-9]+}}: # %entry +; CHECK: # %bb.{{[0-9]+}}: # %c10 ; CHECK: # %e9 ; CHECK: # %g10 ; CHECK: # %h10 @@ -504,8 +507,8 @@ ret: ; checking, it's profitable to duplicate G into F. The weights here are not ; really important. They are there to help make the test stable. ; CHECK-LABEL: trellis_then_dup_test -; CHECK: # %entry -; CHECK: # %b +; CHECK: # %bb.{{[0-9]+}}: # %entry +; CHECK: # %bb.{{[0-9]+}}: # %b ; CHECK: # %d ; CHECK: # %g ; CHECK: # %ret1 @@ -568,8 +571,8 @@ ret: ; Verify that we did not mis-identify triangle trellises if it is not ; really a triangle. ; CHECK-LABEL: trellis_no_triangle -; CHECK: # %entry -; CHECK: # %b +; CHECK: # %bb.{{[0-9]+}}: # %entry +; CHECK: # %bb.{{[0-9]+}}: # %b ; CHECK: # %d ; CHECK: # %ret ; CHECK: # %c diff --git a/test/CodeGen/PowerPC/tailcall1.ll b/test/CodeGen/PowerPC/tailcall1.ll index dedb8702c78ef..1c71b359cdec9 100644 --- a/test/CodeGen/PowerPC/tailcall1.ll +++ b/test/CodeGen/PowerPC/tailcall1.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -tailcallopt | grep TC_RETURN +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -tailcallopt | grep TC_RETURN define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { entry: ret i32 %a3 diff --git a/test/CodeGen/PowerPC/testBitReverse.ll b/test/CodeGen/PowerPC/testBitReverse.ll index 6993d17ad8f34..22fefe4546833 100644 --- a/test/CodeGen/PowerPC/testBitReverse.ll +++ b/test/CodeGen/PowerPC/testBitReverse.ll @@ -4,7 +4,7 @@ declare i32 @llvm.bitreverse.i32(i32) define i32 @testBitReverseIntrinsicI32(i32 %arg) { ; CHECK-LABEL: testBitReverseIntrinsicI32: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 5, 21845 ; CHECK-NEXT: slwi 6, 3, 1 @@ -44,7 +44,7 @@ define i32 @testBitReverseIntrinsicI32(i32 %arg) { declare i64 @llvm.bitreverse.i64(i64) define i64 @testBitReverseIntrinsicI64(i64 %arg) { ; CHECK-LABEL: testBitReverseIntrinsicI64: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 5, 21845 ; CHECK-NEXT: lis 6, -13108 @@ -67,38 +67,38 @@ define i64 @testBitReverseIntrinsicI64(i64 %arg) { ; CHECK-NEXT: and 4, 8, 4 ; CHECK-NEXT: lis 7, 3855 ; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: oris 12, 5, 52428 -; CHECK-NEXT: oris 9, 6, 13107 +; CHECK-NEXT: oris 9, 5, 52428 +; CHECK-NEXT: oris 10, 6, 13107 ; CHECK-NEXT: lis 6, -3856 ; CHECK-NEXT: ori 7, 7, 3855 ; CHECK-NEXT: sldi 8, 3, 2 -; CHECK-NEXT: ori 4, 12, 52428 +; CHECK-NEXT: ori 4, 9, 52428 ; CHECK-NEXT: rldicl 3, 3, 62, 2 -; CHECK-NEXT: ori 5, 9, 13107 +; CHECK-NEXT: ori 5, 10, 13107 ; CHECK-NEXT: ori 6, 6, 61680 ; CHECK-NEXT: and 3, 3, 5 ; CHECK-NEXT: sldi 5, 6, 32 ; CHECK-NEXT: and 4, 8, 4 ; CHECK-NEXT: sldi 6, 7, 32 ; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: oris 10, 5, 61680 -; CHECK-NEXT: oris 11, 6, 3855 +; CHECK-NEXT: oris 11, 5, 61680 +; CHECK-NEXT: oris 12, 6, 3855 ; CHECK-NEXT: sldi 6, 3, 4 -; CHECK-NEXT: ori 4, 10, 61680 +; CHECK-NEXT: ori 4, 11, 61680 ; CHECK-NEXT: rldicl 3, 3, 60, 4 -; CHECK-NEXT: ori 5, 11, 3855 +; CHECK-NEXT: ori 5, 12, 3855 ; CHECK-NEXT: and 4, 6, 4 ; CHECK-NEXT: and 3, 3, 5 ; CHECK-NEXT: or 3, 3, 4 +; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31 ; CHECK-NEXT: rldicl 4, 3, 32, 32 -; CHECK-NEXT: rlwinm 6, 3, 24, 0, 31 -; CHECK-NEXT: rlwinm 5, 4, 24, 0, 31 -; CHECK-NEXT: rlwimi 6, 3, 8, 8, 15 -; CHECK-NEXT: rlwimi 5, 4, 8, 8, 15 -; CHECK-NEXT: rlwimi 6, 3, 8, 24, 31 -; CHECK-NEXT: rlwimi 5, 4, 8, 24, 31 -; CHECK-NEXT: sldi 12, 5, 32 -; CHECK-NEXT: or 3, 12, 6 +; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31 +; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15 +; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15 +; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31 +; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31 +; CHECK-NEXT: sldi 3, 5, 32 +; CHECK-NEXT: or 3, 3, 6 ; CHECK-NEXT: blr %res = call i64 @llvm.bitreverse.i64(i64 %arg) ret i64 %res diff --git a/test/CodeGen/PowerPC/testComparesi32gtu.ll b/test/CodeGen/PowerPC/testComparesi32gtu.ll new file mode 100644 index 0000000000000..4341b59390e70 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesi32gtu.ll @@ -0,0 +1,52 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +%struct.tree_common = type { i8, [3 x i8] } +declare signext i32 @fn2(...) local_unnamed_addr #1 + +; Function Attrs: nounwind +define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) { +; CHECK-LABEL: testCompare1: +; CHECK: # %bb.0: # %entry +; CHECK: lbz r3, 0(r3) +; CHECK-DAG: clrlwi r3, r3, 31 +; CHECK-DAG: clrldi r3, r3, 32 +; CHECK: lbz r4, 0(r4) +; CHECK-DAG: clrlwi r4, r4, 31 +; CHECK-DAG: clrldi r4, r4, 32 +; CHECK: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +entry: + %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4 + %bf.clear = and i8 %bf.load, 1 + %0 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %arg1, i64 0, i32 0 + %bf.load1 = load i8, i8* %0, align 4 + %bf.clear2 = and i8 %bf.load1, 1 + %cmp = icmp ugt i8 %bf.clear, %bf.clear2 + %conv = zext i1 %cmp to i32 + %call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2 + ret i32 undef +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: testCompare2: +; CHECK: # %bb.0: # %entry +; CHECK-DAG: rlwinm r3, r3, 0, 31, 31 +; CHECK-DAG: rlwinm r4, r4, 0, 31, 31 +; CHECK-DAG: clrldi r3, r3, 32 +; CHECK-DAG: clrldi r4, r4, 32 +; CHECK: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %and = and i32 %a, 1 + %and1 = and i32 %b, 1 + %cmp = icmp ugt i32 %and, %and1 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} diff --git a/test/CodeGen/PowerPC/testComparesi32leu.ll b/test/CodeGen/PowerPC/testComparesi32leu.ll new file mode 100644 index 0000000000000..3ba967b51dad0 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesi32leu.ll @@ -0,0 +1,26 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +define signext i32 @test(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31 +; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31 +; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r4, r4, 32 +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %0 = and i8 %a, 1 + %1 = and i8 %b, 1 + %cmp = icmp ule i8 %0, %1 + %conv3 = zext i1 %cmp to i32 + ret i32 %conv3 +} diff --git a/test/CodeGen/PowerPC/testComparesi32ltu.ll b/test/CodeGen/PowerPC/testComparesi32ltu.ll new file mode 100644 index 0000000000000..9623a63e9bc37 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesi32ltu.ll @@ -0,0 +1,52 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +%struct.tree_common = type { i8, [3 x i8] } +declare signext i32 @fn2(...) local_unnamed_addr #1 + +; Function Attrs: nounwind +define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) { +; CHECK-LABEL: testCompare1: +; CHECK: # %bb.0: # %entry +; CHECK: lbz r3, 0(r3) +; CHECK-DAG: clrlwi r3, r3, 31 +; CHECK-DAG: clrldi r3, r3, 32 +; CHECK: lbz r4, 0(r4) +; CHECK-DAG: clrlwi r4, r4, 31 +; CHECK-DAG: clrldi r4, r4, 32 +; CHECK: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +entry: + %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4 + %bf.clear = and i8 %bf.load, 1 + %0 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %arg1, i64 0, i32 0 + %bf.load1 = load i8, i8* %0, align 4 + %bf.clear2 = and i8 %bf.load1, 1 + %cmp = icmp ult i8 %bf.clear, %bf.clear2 + %conv = zext i1 %cmp to i32 + %call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2 + ret i32 undef +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: testCompare2: +; CHECK: # %bb.0: # %entry +; CHECK-DAG: rlwinm r3, r3, 0, 31, 31 +; CHECK-DAG: rlwinm r4, r4, 0, 31, 31 +; CHECK-DAG: clrldi r3, r3, 32 +; CHECK-DAG: clrldi r4, r4, 32 +; CHECK: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %and = and i32 %a, 1 + %and1 = and i32 %b, 1 + %cmp = icmp ult i32 %and, %and1 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} diff --git a/test/CodeGen/PowerPC/testComparesieqsc.ll b/test/CodeGen/PowerPC/testComparesieqsc.ll index 71ad5ed349692..aa0211ebb6507 100644 --- a/test/CodeGen/PowerPC/testComparesieqsc.ll +++ b/test/CodeGen/PowerPC/testComparesieqsc.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesieqsc.c' @@ -12,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsc(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ieqsc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -26,11 +26,11 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ieqsc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -41,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsc_z(i8 signext %a) { ; CHECK-LABEL: test_ieqsc_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -54,10 +54,10 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsc_sext_z(i8 signext %a) { ; CHECK-LABEL: test_ieqsc_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 @@ -68,7 +68,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ieqsc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -86,13 +86,13 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ieqsc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -105,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsc_z_store(i8 signext %a) { ; CHECK-LABEL: test_ieqsc_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -122,12 +122,12 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsc_sext_z_store(i8 signext %a) { ; CHECK-LABEL: test_ieqsc_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesieqsi.ll b/test/CodeGen/PowerPC/testComparesieqsi.ll index 16882dbd00453..0a6b7b9ca351a 100644 --- a/test/CodeGen/PowerPC/testComparesieqsi.ll +++ b/test/CodeGen/PowerPC/testComparesieqsi.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesieqsi.c' @@ -12,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsi(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ieqsi: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -26,11 +26,11 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsi_sext(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ieqsi_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -41,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsi_z(i32 signext %a) { ; CHECK-LABEL: test_ieqsi_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -54,10 +54,10 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsi_sext_z(i32 signext %a) { ; CHECK-LABEL: test_ieqsi_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 @@ -68,7 +68,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ieqsi_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -86,13 +86,13 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ieqsi_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -105,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsi_z_store(i32 signext %a) { ; CHECK-LABEL: test_ieqsi_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -122,12 +122,12 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsi_sext_z_store(i32 signext %a) { ; CHECK-LABEL: test_ieqsi_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesieqsll.ll b/test/CodeGen/PowerPC/testComparesieqsll.ll index 57c7365eff03a..1dae985c36c19 100644 --- a/test/CodeGen/PowerPC/testComparesieqsll.ll +++ b/test/CodeGen/PowerPC/testComparesieqsll.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesieqsll.c' @@ -12,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsll(i64 %a, i64 %b) { ; CHECK-LABEL: test_ieqsll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 @@ -26,7 +26,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_ieqsll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 @@ -40,7 +40,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsll_z(i64 %a) { ; CHECK-LABEL: test_ieqsll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr @@ -53,7 +53,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsll_sext_z(i64 %a) { ; CHECK-LABEL: test_ieqsll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr @@ -66,7 +66,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ieqsll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -84,7 +84,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ieqsll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -102,7 +102,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsll_z_store(i64 %a) { ; CHECK-LABEL: test_ieqsll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -119,7 +119,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_ieqsll_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesieqss.ll b/test/CodeGen/PowerPC/testComparesieqss.ll index 110c5a62804ed..93a92e1780727 100644 --- a/test/CodeGen/PowerPC/testComparesieqss.ll +++ b/test/CodeGen/PowerPC/testComparesieqss.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesieqss.c' @@ -12,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqss(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_ieqss: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -26,11 +26,11 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_ieqss_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -41,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqss_z(i16 signext %a) { ; CHECK-LABEL: test_ieqss_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -54,10 +54,10 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqss_sext_z(i16 signext %a) { ; CHECK-LABEL: test_ieqss_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 @@ -68,7 +68,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqss_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_ieqss_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -86,13 +86,13 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_ieqss_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -105,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqss_z_store(i16 signext %a) { ; CHECK-LABEL: test_ieqss_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -122,12 +122,12 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqss_sext_z_store(i16 signext %a) { ; CHECK-LABEL: test_ieqss_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesiequc.ll b/test/CodeGen/PowerPC/testComparesiequc.ll index e2c975f2c1918..592f7bc83bb8d 100644 --- a/test/CodeGen/PowerPC/testComparesiequc.ll +++ b/test/CodeGen/PowerPC/testComparesiequc.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesiequc.c' @@ -12,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_iequc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -26,11 +26,11 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_iequc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -41,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequc_z(i8 zeroext %a) { ; CHECK-LABEL: test_iequc_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -54,10 +54,10 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequc_sext_z(i8 zeroext %a) { ; CHECK-LABEL: test_iequc_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 @@ -68,7 +68,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_iequc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -86,13 +86,13 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_iequc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -105,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequc_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_iequc_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -122,12 +122,12 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequc_sext_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_iequc_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesiequi.ll b/test/CodeGen/PowerPC/testComparesiequi.ll index 789b176a77001..9a639dc54100c 100644 --- a/test/CodeGen/PowerPC/testComparesiequi.ll +++ b/test/CodeGen/PowerPC/testComparesiequi.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesiequi.c' @@ -12,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_iequi: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -26,11 +26,11 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_iequi_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -41,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequi_z(i32 zeroext %a) { ; CHECK-LABEL: test_iequi_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -54,10 +54,10 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequi_sext_z(i32 zeroext %a) { ; CHECK-LABEL: test_iequi_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 @@ -68,7 +68,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_iequi_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -86,13 +86,13 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_iequi_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -105,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequi_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_iequi_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -122,12 +122,12 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequi_sext_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_iequi_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesiequll.ll b/test/CodeGen/PowerPC/testComparesiequll.ll index c289290718455..f147478d5ea8a 100644 --- a/test/CodeGen/PowerPC/testComparesiequll.ll +++ b/test/CodeGen/PowerPC/testComparesiequll.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesiequll.c' @@ -12,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequll(i64 %a, i64 %b) { ; CHECK-LABEL: test_iequll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 @@ -26,7 +26,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_iequll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 @@ -40,7 +40,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequll_z(i64 %a) { ; CHECK-LABEL: test_iequll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr @@ -53,7 +53,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequll_sext_z(i64 %a) { ; CHECK-LABEL: test_iequll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr @@ -66,7 +66,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_iequll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -84,7 +84,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_iequll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -102,7 +102,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequll_z_store(i64 %a) { ; CHECK-LABEL: test_iequll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -119,7 +119,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_iequll_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesiequs.ll b/test/CodeGen/PowerPC/testComparesiequs.ll index b72943893e98e..195339ddb2e51 100644 --- a/test/CodeGen/PowerPC/testComparesiequs.ll +++ b/test/CodeGen/PowerPC/testComparesiequs.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesiequs.c' @@ -12,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_iequs: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -26,11 +26,11 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_iequs_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -41,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequs_z(i16 zeroext %a) { ; CHECK-LABEL: test_iequs_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -54,10 +54,10 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequs_sext_z(i16 zeroext %a) { ; CHECK-LABEL: test_iequs_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 @@ -68,7 +68,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_iequs_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -86,13 +86,13 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_iequs_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -105,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequs_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_iequs_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -122,12 +122,12 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequs_sext_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_iequs_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesigesc.ll b/test/CodeGen/PowerPC/testComparesigesc.ll new file mode 100644 index 0000000000000..69dd97fc9c449 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigesc.ll @@ -0,0 +1,68 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +@glob = common local_unnamed_addr global i8 0, align 1 + +define signext i32 @test_igesc(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_igesc: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_igesc_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_igesc_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_igesc_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_igesc_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesigesi.ll b/test/CodeGen/PowerPC/testComparesigesi.ll new file mode 100644 index 0000000000000..7efc8ae82450b --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigesi.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i32 0, align 4 + +define signext i32 @test_igesi(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igesi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igesi_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_igesi_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igesi_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igesi_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesigesll.ll b/test/CodeGen/PowerPC/testComparesigesll.ll new file mode 100644 index 0000000000000..30efe3da3e91d --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigesll.ll @@ -0,0 +1,128 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i64 0, align 8 + +define signext i32 @test_igesll(i64 %a, i64 %b) { +; CHECK-LABEL: test_igesll: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi r5, r3, 63 +; CHECK-NEXT: rldicl r6, r4, 1, 63 +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_igesll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_igesll_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi r5, r3, 63 +; CHECK-NEXT: rldicl r6, r4, 1, 63 +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define signext i32 @test_igesll_z(i64 %a) { +; CHECK-LABEL: test_igesll_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_igesll_sext_z(i64 %a) { +; CHECK-LABEL: test_igesll_sext_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: not r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_igesll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_igesll_store: +; CHECK: # %bb.0: # %entry +; CHECK: sradi r6, r3, 63 +; CHECK: subfc r3, r4, r3 +; CHECK: rldicl r3, r4, 1, 63 +; CHECK: adde r3, r6, r3 +; CHECK: std r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_igesll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_igesll_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi r6, r3, 63 +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: rldicl r3, r4, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: adde r3, r6, r3 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_igesll_z_store(i64 %a) { +; CHECK-LABEL: test_igesll_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_igesll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_igesll_sext_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: not r3, r3 +; CHECK-NEXT: std r3, +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesigess.ll b/test/CodeGen/PowerPC/testComparesigess.ll new file mode 100644 index 0000000000000..231a26c916db0 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigess.ll @@ -0,0 +1,68 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +@glob = common local_unnamed_addr global i16 0, align 2 + +define signext i32 @test_igess(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_igess: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_igess_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_igess_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_igess_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +define void @test_igess_sext_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_igess_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesigeuc.ll b/test/CodeGen/PowerPC/testComparesigeuc.ll new file mode 100644 index 0000000000000..907cda39a5af7 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigeuc.ll @@ -0,0 +1,112 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i8 0, align 1 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: test_igeuc: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeuc_sext(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeuc_sext +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr + +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeuc_z(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: @test_igeuc_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeuc_sext_z(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv2 = sext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: @test_igeuc_sext_z +; CHECK: li r3, -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK_LABEL: test_igeuc_store: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeuc_sext_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-TBD-LABEL: @test_igeuc_sext_store +; CHECK-TBD: subf [[REG1:r[0-9]+]], r3, r4 +; CHECK-TBD: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-TBD: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-TBD: stb [[REG3]] +; CHECK-TBD: blr +} + +; Function Attrs : norecurse nounwind +define void @test_igeuc_z_store(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-LABEL: @test_igeuc_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: stb [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeuc_sext_z_store(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-LABEL: @test_igeuc_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: stb [[REG1]] +; CHECK: blr +} diff --git a/test/CodeGen/PowerPC/testComparesigeui.ll b/test/CodeGen/PowerPC/testComparesigeui.ll new file mode 100644 index 0000000000000..ac55500432f1b --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigeui.ll @@ -0,0 +1,112 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +; CHECK-LABEL: test_igeui: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeui_sext(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeui_sext +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeui_z(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %sub = zext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeui_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeui_sext_z(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeui_sext_z +; CHECK: li r3, -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob + ret void +; CHECK_LABEL: test_igeuc_store: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeui_sext_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_igeui_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: stw [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeui_z_store(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %conv1 = zext i1 %cmp to i32 + store i32 %conv1, i32* @glob + ret void +; CHECK-LABEL: @test_igeui_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: stw [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeui_sext_z_store(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %conv1 = sext i1 %cmp to i32 + store i32 %conv1, i32* @glob + ret void +; CHECK-LABEL: @test_igeui_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: stw [[REG1]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesigeull.ll b/test/CodeGen/PowerPC/testComparesigeull.ll new file mode 100644 index 0000000000000..103eeb1c70593 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigeull.ll @@ -0,0 +1,111 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeull(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +; CHECK-LABEL: test_igeull: +; CHECK: subfc {{r[0-9]+}}, r4, r3 +; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4 +; CHECK-NEXT: addi r3, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeull_sext(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeull_sext +; CHECK: subfc [[REG1:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not r3, [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeull_z(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %sub = zext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeull_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeull_sext_z(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeull_sext_z +; CHECK: li r3, -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeull_store(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_igeull_store: +; CHECK: subfc {{r[0-9]+}}, r4, r3 +; CHECK: subfe [[REG1:r[0-9]+]], r4, r4 +; CHECK: addi {{r[0-9]+}}, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeull_sext_store(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_igeull_sext_store +; CHECK: subfc [[REG1:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: std [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeull_z_store(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_igeull_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: std [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeull_sext_z_store(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_igeull_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: std [[REG1]] +; CHECK: blr +} diff --git a/test/CodeGen/PowerPC/testComparesigeus.ll b/test/CodeGen/PowerPC/testComparesigeus.ll new file mode 100644 index 0000000000000..ab8790746d68f --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigeus.ll @@ -0,0 +1,112 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: test_igeus: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeus_sext(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeus_sext +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeus_z(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: @test_igeus_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeus_sext_z(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: @test_igeus_sext_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK_LABEL: test_igeus_store: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeus_sext_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: @test_igeus_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: sth [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeus_z_store(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: @test_igeus_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: sth [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeus_sext_z_store(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: @test_igeus_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: sth [[REG1]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesigtsc.ll b/test/CodeGen/PowerPC/testComparesigtsc.ll new file mode 100644 index 0000000000000..8009043c45d95 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigtsc.ll @@ -0,0 +1,116 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i8 0, align 1 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_igtsc: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i8 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsc_sext(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_igtsc_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i8 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; FIXME +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsc_z(i8 signext %a) { +; CHECK-LABEL: test_igtsc_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i8 %a, 0 + %conv1 = zext i1 %cmp to i32 + ret i32 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsc_sext_z(i8 signext %a) { +; CHECK-LABEL: test_igtsc_sext_z: +; CHECK: neg [[REG2:r[0-9]+]], r3 +; CHECK-NEXT: sradi r3, [[REG2]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i8 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_igtsc_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_igtsc_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp sgt i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtsc_sext_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_igtsc_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp sgt i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +; FIXME +; Function Attrs: norecurse nounwind +define void @test_igtsc_z_store(i8 signext %a) { +; CHECK-LABEL: test_igtsc_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: stb r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i8 %a, 0 + %conv2 = zext i1 %cmp to i8 + store i8 %conv2, i8* @glob, align 1 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtsc_sext_z_store(i8 signext %a) { +; CHECK-LABEL: test_igtsc_sext_z_store: +; CHECK: neg [[REG2:r[0-9]+]], r3 +; CHECK: sradi {{r[0-9]+}}, [[REG2]], 63 +entry: + %cmp = icmp sgt i8 %a, 0 + %conv2 = sext i1 %cmp to i8 + store i8 %conv2, i8* @glob, align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesigtsi.ll b/test/CodeGen/PowerPC/testComparesigtsi.ll new file mode 100644 index 0000000000000..77dfc3583f1ae --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigtsi.ll @@ -0,0 +1,116 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igtsi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i32 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsi_sext(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igtsi_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i32 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; FIXME +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsi_z(i32 signext %a) { +; CHECK-LABEL: test_igtsi_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i32 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsi_sext_z(i32 signext %a) { +; CHECK-LABEL: test_igtsi_sext_z: +; CHECK: neg [[REG2:r[0-9]+]], r3 +; CHECK-NEXT: sradi r3, [[REG2]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i32 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_igtsi_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igtsi_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp sgt i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtsi_sext_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igtsi_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp sgt i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} + +; FIXME +; Function Attrs: norecurse nounwind +define void @test_igtsi_z_store(i32 signext %a) { +; CHECK-LABEL: test_igtsi_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: stw r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i32 %a, 0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtsi_sext_z_store(i32 signext %a) { +; CHECK-LABEL: test_igtsi_sext_z_store: +; CHECK: neg [[REG:r[0-9]+]], r3 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp sgt i32 %a, 0 + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesigtsll.ll b/test/CodeGen/PowerPC/testComparesigtsll.ll new file mode 100644 index 0000000000000..75314d708f525 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigtsll.ll @@ -0,0 +1,134 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsll(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtsll: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori r3, [[REG4]], 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtsll_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NEXT: neg r3, [[REG5]] +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; FIXME +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsll_z(i64 %a) { +; CHECK-LABEL: test_igtsll_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi r4, r3, -1 +; CHECK-NEXT: nor r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtsll_sext_z(i64 %a) { +; CHECK-LABEL: test_igtsll_sext_z: +; CHECK: addi [[REG1:r[0-9]+]], r3, -1 +; CHECK-NEXT: nor [[REG2:r[0-9]+]], [[REG1]], r3 +; CHECK-NEXT: sradi r3, [[REG2]], 63 +entry: + %cmp = icmp sgt i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_igtsll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtsll_store: +; CHECK: # %bb.0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NOT: neg +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtsll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_igtsll_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; FIXME +; Function Attrs: norecurse nounwind +define void @test_igtsll_z_store(i64 %a) { +; CHECK-LABEL: test_igtsll_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addi r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: nor r3, r5, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtsll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_igtsll_sext_z_store: +; CHECK: addi [[REG1:r[0-9]+]], r3, -1 +; CHECK: nor [[REG2:r[0-9]+]], [[REG1]], r3 +; CHECK: sradi [[REG3:r[0-9]+]], [[REG2]], 63 +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesigtss.ll b/test/CodeGen/PowerPC/testComparesigtss.ll new file mode 100644 index 0000000000000..23ddbe30f7e45 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigtss.ll @@ -0,0 +1,117 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtss(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_igtss: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl r3, [[REG1]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i16 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtss_sext(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_igtss_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i16 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; FIXME +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtss_z(i16 signext %a) { +; CHECK-LABEL: test_igtss_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i16 %a, 0 + %conv1 = zext i1 %cmp to i32 + ret i32 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtss_sext_z(i16 signext %a) { +; CHECK-LABEL: test_igtss_sext_z: +; CHECK: # %bb.0: # %entry +; CHECK: neg [[REG2:r[0-9]+]], r3 +; CHECK-NEXT: sradi r3, [[REG2]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i16 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_igtss_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_igtss_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 1, 63 +entry: + %cmp = icmp sgt i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtss_sext_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_igtss_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp sgt i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +; FIXME +; Function Attrs: norecurse nounwind +define void @test_igtss_z_store(i16 signext %a) { +; CHECK-LABEL: test_igtss_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i16 %a, 0 + %conv2 = zext i1 %cmp to i16 + store i16 %conv2, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtss_sext_z_store(i16 signext %a) { +; CHECK-LABEL: test_igtss_sext_z_store: +; CHECK: neg [[REG2:r[0-9]+]], r3 +; CHECK: sradi {{r[0-9]+}}, [[REG2]], 63 +entry: + %cmp = icmp sgt i16 %a, 0 + %conv2 = sext i1 %cmp to i16 + store i16 %conv2, i16* @glob, align 2 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesigtuc.ll b/test/CodeGen/PowerPC/testComparesigtuc.ll new file mode 100644 index 0000000000000..540b82001c2cf --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigtuc.ll @@ -0,0 +1,114 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i8 0, align 1 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtuc(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_igtuc: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i8 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtuc_sext(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_igtuc_sext: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i8 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtuc_z(i8 zeroext %a) { +; CHECK-LABEL: test_igtuc_z: +; CHECK: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i8 %a, 0 + %conv1 = zext i1 %cmp to i32 + ret i32 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtuc_sext_z(i8 zeroext %a) { +; CHECK-LABEL: test_igtuc_sext_z: +; CHECK: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i8 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_igtuc_store(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_igtuc_store: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp ugt i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtuc_sext_store(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_igtuc_sext_store: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp ugt i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtuc_z_store(i8 zeroext %a) { +; CHECK-LABEL: test_igtuc_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: stb r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i8 %a, 0 + %conv2 = zext i1 %cmp to i8 + store i8 %conv2, i8* @glob, align 1 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtuc_sext_z_store(i8 zeroext %a) { +; CHECK-LABEL: test_igtuc_sext_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: neg r3, r3 +; CHECK: stb r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i8 %a, 0 + %conv2 = sext i1 %cmp to i8 + store i8 %conv2, i8* @glob, align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesigtui.ll b/test/CodeGen/PowerPC/testComparesigtui.ll new file mode 100644 index 0000000000000..6fef78c6b0b96 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigtui.ll @@ -0,0 +1,115 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtui(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_igtui: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i32 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtui_sext(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_igtui_sext: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i32 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtui_z(i32 zeroext %a) { +; CHECK-LABEL: test_igtui_z: +; CHECK: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i32 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtui_sext_z(i32 zeroext %a) { +; CHECK-LABEL: test_igtui_sext_z: +; CHECK: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i32 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_igtui_store(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_igtui_store: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp ugt i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtui_sext_store(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_igtui_sext_store: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp ugt i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtui_z_store(i32 zeroext %a) { +; CHECK-LABEL: test_igtui_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: stw r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i32 %a, 0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtui_sext_z_store(i32 zeroext %a) { +; CHECK-LABEL: test_igtui_sext_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: neg r3, r3 +; CHECK: stw r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i32 %a, 0 + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} + diff --git a/test/CodeGen/PowerPC/testComparesigtus.ll b/test/CodeGen/PowerPC/testComparesigtus.ll new file mode 100644 index 0000000000000..07e810115f977 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigtus.ll @@ -0,0 +1,117 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtus(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_igtus: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i16 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtus_sext(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_igtus_sext: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i16 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtus_z(i16 zeroext %a) { +; CHECK-LABEL: test_igtus_z: +; CHECK: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i16 %a, 0 + %conv1 = zext i1 %cmp to i32 + ret i32 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igtus_sext_z(i16 zeroext %a) { +; CHECK-LABEL: test_igtus_sext_z: +; CHECK: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i16 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_igtus_store(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_igtus_store: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +; CHECK: blr +entry: + %cmp = icmp ugt i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtus_sext_store(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_igtus_sext_store: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +; CHECK: blr +entry: + %cmp = icmp ugt i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtus_z_store(i16 zeroext %a) { +; CHECK-LABEL: test_igtus_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: sth r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i16 %a, 0 + %conv2 = zext i1 %cmp to i16 + store i16 %conv2, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_igtus_sext_z_store(i16 zeroext %a) { +; CHECK-LABEL: test_igtus_sext_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: neg r3, r3 +; CHECK: sth r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i16 %a, 0 + %conv2 = sext i1 %cmp to i16 + store i16 %conv2, i16* @glob, align 2 + ret void +} + diff --git a/test/CodeGen/PowerPC/testComparesilesc.ll b/test/CodeGen/PowerPC/testComparesilesc.ll new file mode 100644 index 0000000000000..422dc3adc5d64 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesilesc.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i8 0, align 1 + +define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_ilesc: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_ilesc_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_ilesc_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_ilesc_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_ilesc_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesilesi.ll b/test/CodeGen/PowerPC/testComparesilesi.ll new file mode 100644 index 0000000000000..72439bd9aa3a8 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesilesi.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i32 0, align 4 + +define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_ilesi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_ilesi_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_ilesi_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_ilesi_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_ilesi_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesilesll.ll b/test/CodeGen/PowerPC/testComparesilesll.ll new file mode 100644 index 0000000000000..21b67664c30d0 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesilesll.ll @@ -0,0 +1,130 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i64 0, align 8 + +define signext i32 @test_ilesll(i64 %a, i64 %b) { +; CHECK-LABEL: test_ilesll: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi r5, r4, 63 +; CHECK-NEXT: rldicl r6, r3, 1, 63 +; CHECK-NEXT: subfc r12, r3, r4 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_ilesll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_ilesll_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi r5, r4, 63 +; CHECK-NEXT: rldicl r6, r3, 1, 63 +; CHECK-NEXT: subfc r12, r3, r4 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define signext i32 @test_ilesll_z(i64 %a) { +; CHECK-LABEL: test_ilesll_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi r4, r3, -1 +; CHECK-NEXT: or r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_ilesll_sext_z(i64 %a) { +; CHECK-LABEL: test_ilesll_sext_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi r4, r3, -1 +; CHECK-NEXT: or r3, r4, r3 +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_ilesll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_ilesll_store: +; CHECK: # %bb.0: # %entry +; CHECK: sradi r6, r4, 63 +; CHECK: subfc r4, r3, r4 +; CHECK: rldicl r3, r3, 1, 63 +; CHECK: adde r3, r6, r3 +; CHECK: std r3, +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_ilesll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_ilesll_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sradi r6, r4, 63 +; CHECK-DAG: rldicl r3, r3, 1, 63 +; CHECK-DAG: subfc r4, r3, r4 +; CHECK: adde r3, r6, r3 +; CHECK: neg r3, r3 +; CHECK: std r3, +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_ilesll_z_store(i64 %a) { +; CHECK-LABEL: test_ilesll_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addi r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: or r3, r5, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_ilesll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_ilesll_sext_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addi r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: or r3, r5, r3 +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesiless.ll b/test/CodeGen/PowerPC/testComparesiless.ll new file mode 100644 index 0000000000000..c85ff6078e7de --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesiless.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i16 0, align 2 + +define signext i32 @test_iless(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iless: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iless_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_iless_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iless_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +define void @test_iless_sext_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iless_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesileuc.ll b/test/CodeGen/PowerPC/testComparesileuc.ll new file mode 100644 index 0000000000000..b387d4b867f7e --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesileuc.ll @@ -0,0 +1,117 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i8 0, align 1 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: test_ileuc: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileuc_sext(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileuc_sext +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileuc_z(i8 zeroext %a) { +entry: + %cmp = icmp eq i8 %a, 0 + %conv1 = zext i1 %cmp to i32 + ret i32 %conv1 +; CHECK-LABEL: test_ileuc_z: +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi r3, [[REG1]], 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileuc_sext_z(i8 zeroext %a) { +entry: + %cmp = icmp ule i8 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileuc_sext_z +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-LABEL: test_ileuc_store: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileuc_sext_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-LABEL: @test_ileuc_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: stb [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileuc_z_store(i8 zeroext %a) { +entry: + %cmp = icmp eq i8 %a, 0 + %conv2 = zext i1 %cmp to i8 + store i8 %conv2, i8* @glob + ret void +; CHECK-LABEL: test_ileuc_z_store: +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileuc_sext_z_store(i8 zeroext %a) { +entry: + %cmp = icmp eq i8 %a, 0 + %conv2 = sext i1 %cmp to i8 + store i8 %conv2, i8* @glob + ret void +; CHECK-LABEL: @test_ileuc_sext_z_store +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK: neg [[REG3:r[0-9]+]], [[REG2]] +; CHECK: stb [[REG3]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesileui.ll b/test/CodeGen/PowerPC/testComparesileui.ll new file mode 100644 index 0000000000000..fd80167e50aef --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesileui.ll @@ -0,0 +1,117 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %sub = zext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: test_ileui: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileui_sext(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileui_sext +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileui_z(i32 zeroext %a) { +entry: + %cmp = icmp eq i32 %a, 0 + %sub = zext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: test_ileui_z: +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi r3, [[REG1]], 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileui_sext_z(i32 zeroext %a) { +entry: + %cmp = icmp eq i32 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileui_sext_z +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %sub = zext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: test_ileui_store: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileui_sext_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_ileui_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: stw [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileui_z_store(i32 zeroext %a) { +entry: + %cmp = icmp eq i32 %a, 0 + %sub = zext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: test_ileui_z_store: +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileui_sext_z_store(i32 zeroext %a) { +entry: + %cmp = icmp eq i32 %a, 0 + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_ileui_sext_z_store +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK: neg [[REG3:r[0-9]+]], [[REG2]] +; CHECK: stw [[REG3]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesileull.ll b/test/CodeGen/PowerPC/testComparesileull.ll new file mode 100644 index 0000000000000..afcf0ce4bbdb0 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesileull.ll @@ -0,0 +1,115 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileull(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +; CHECK-LABEL: test_ileull: +; CHECK: subfc {{r[0-9]+}}, r3, r4 +; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3 +; CHECK-NEXT: addi r3, [[REG1]], 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileull_sext(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileull_sext +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not r3, [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileull_z(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +; CHECK-LABEL: test_ileull_z +; CHECK: cntlzd [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileull_sext_z(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileull_sext_z +; CHECK: addic [[REG1:r[0-9]+]], r3, -1 +; CHECK: subfe r3, [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileull_store(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_ileull_store: +; CHECK: subfc {{r[0-9]+}}, r3, r4 +; CHECK: subfe [[REG1:r[0-9]+]], r3, r3 +; CHECK: addi {{r[0-9]+}}, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileull_sext_store(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_ileull_sext_store +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: std [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileull_z_store(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_ileull_z_store: +; CHECK: cntlzd [[REG1:r[0-9]+]], r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileull_sext_z_store(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_ileull_sext_z_store +; CHECK: addic [[REG1:r[0-9]+]], r3, -1 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: std [[REG2]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesileus.ll b/test/CodeGen/PowerPC/testComparesileus.ll new file mode 100644 index 0000000000000..6e54c5a521005 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesileus.ll @@ -0,0 +1,117 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: test_ileus: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileus_sext(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileus_sext +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileus_z(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %conv1 = zext i1 %cmp to i32 + ret i32 %conv1 +; CHECK-LABEL: test_ileus_z: +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi r3, [[REG1]], 5 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileus_sext_z(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileus_sext_z +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: test_ileus_store: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileus_sext_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: @test_ileus_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: sth [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileus_z_store(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %conv2 = zext i1 %cmp to i16 + store i16 %conv2, i16* @glob + ret void +; CHECK-LABEL: test_ileus_z_store: +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileus_sext_z_store(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %conv2 = sext i1 %cmp to i16 + store i16 %conv2, i16* @glob + ret void +; CHECK-LABEL: @test_ileus_sext_z_store +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK: neg [[REG3:r[0-9]+]], [[REG2]] +; CHECK: sth [[REG3]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesiltsc.ll b/test/CodeGen/PowerPC/testComparesiltsc.ll new file mode 100644 index 0000000000000..08a023302bddf --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesiltsc.ll @@ -0,0 +1,83 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i8 0, align 1 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_iltsc: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i8 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_iltsc_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i8 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsc_sext_z(i8 signext %a) { +; CHECK-LABEL: test_iltsc_sext_z: +; CHECK: srawi r3, r3, 31 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i8 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_iltsc_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_iltsc_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp slt i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_iltsc_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp slt i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltsc_sext_z_store(i8 signext %a) { +; CHECK-LABEL: test_iltsc_sext_z_store: +; CHECK: srwi {{r[0-9]+}}, r3, 7 +entry: + %cmp = icmp slt i8 %a, 0 + %conv2 = sext i1 %cmp to i8 + store i8 %conv2, i8* @glob, align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesiltsi.ll b/test/CodeGen/PowerPC/testComparesiltsi.ll new file mode 100644 index 0000000000000..39f37387f534f --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesiltsi.ll @@ -0,0 +1,85 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsi(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_iltsi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i32 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsi_sext(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_iltsi_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i32 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsi_sext_z(i32 signext %a) { +; CHECK-LABEL: test_iltsi_sext_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: srawi r3, r3, 31 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i32 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_iltsi_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_iltsi_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp slt i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltsi_sext_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_iltsi_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp slt i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltsi_sext_z_store(i32 signext %a) { +; CHECK-LABEL: test_iltsi_sext_z_store: +; CHECK: srawi {{r[0-9]+}}, r3, 31 +; CHECK: blr +entry: + %cmp = icmp slt i32 %a, 0 + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesiltsll.ll b/test/CodeGen/PowerPC/testComparesiltsll.ll new file mode 100644 index 0000000000000..4152b8556df00 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesiltsll.ll @@ -0,0 +1,99 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsll(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltsll: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori r3, [[REG4]], 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltsll_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NEXT: neg r3, [[REG5]] +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltsll_sext_z(i64 %a) { +; CHECK-LABEL: test_iltsll_sext_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_iltsll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltsll_store: +; CHECK: # %bb.0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NOT: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltsll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_iltsll_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltsll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_iltsll_sext_z_store: +; CHECK: sradi r3, r3, 63 +entry: + %cmp = icmp slt i64 %a, 0 + %conv2 = sext i1 %cmp to i64 + store i64 %conv2, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesiltss.ll b/test/CodeGen/PowerPC/testComparesiltss.ll new file mode 100644 index 0000000000000..db5a60dfb66b4 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesiltss.ll @@ -0,0 +1,83 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltss(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iltss: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i16 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltss_sext(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iltss_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i16 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltss_sext_z(i16 signext %a) { +; CHECK-LABEL: test_iltss_sext_z: +; CHECK: srawi r3, r3, 31 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i16 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_iltss_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iltss_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp slt i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltss_sext_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iltss_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp slt i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltss_sext_z_store(i16 signext %a) { +; CHECK-LABEL: test_iltss_sext_z_store: +; CHECK: srwi {{r[0-9]+}}, r3, 15 +entry: + %cmp = icmp slt i16 %a, 0 + %sub = sext i1 %cmp to i16 + store i16 %sub, i16* @glob, align 2 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesiltuc.ll b/test/CodeGen/PowerPC/testComparesiltuc.ll new file mode 100644 index 0000000000000..19db29a50c99a --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesiltuc.ll @@ -0,0 +1,56 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i8 0, align 1 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltuc(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_iltuc: +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i8 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltuc_sext(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_iltuc_sext: +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i8 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_iltuc_store(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_iltuc_store: +; CHECK: sub [[REG:r[2-9]+]], r3, r4 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp ult i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltuc_sext_store(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_iltuc_sext_store: +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp ult i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesiltui.ll b/test/CodeGen/PowerPC/testComparesiltui.ll new file mode 100644 index 0000000000000..dd9a202cbc998 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesiltui.ll @@ -0,0 +1,56 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltui(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_iltui: +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i32 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltui_sext(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_iltui_sext: +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i32 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_iltui_store(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_iltui_store: +; CHECK: sub [[REG:r[2-9]+]], r3, r4 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp ult i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltui_sext_store(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_iltui_sext_store: +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp ult i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesiltus.ll b/test/CodeGen/PowerPC/testComparesiltus.ll new file mode 100644 index 0000000000000..1174572505983 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesiltus.ll @@ -0,0 +1,56 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltus(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_iltus: +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i16 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltus_sext(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_iltus_sext: +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i16 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_iltus_store(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_iltus_store: +; CHECK: sub [[REG:r[2-9]+]], r3, r4 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp ult i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltus_sext_store(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_iltus_sext_store: +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp ult i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesinesc.ll b/test/CodeGen/PowerPC/testComparesinesc.ll index e6ade339573b9..a498f64462224 100644 --- a/test/CodeGen/PowerPC/testComparesinesc.ll +++ b/test/CodeGen/PowerPC/testComparesinesc.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py diff --git a/test/CodeGen/PowerPC/testComparesinesi.ll b/test/CodeGen/PowerPC/testComparesinesi.ll index ad9431c09e331..b47f6c808495e 100644 --- a/test/CodeGen/PowerPC/testComparesinesi.ll +++ b/test/CodeGen/PowerPC/testComparesinesi.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py diff --git a/test/CodeGen/PowerPC/testComparesinesll.ll b/test/CodeGen/PowerPC/testComparesinesll.ll new file mode 100644 index 0000000000000..cccff24c504ff --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesinesll.ll @@ -0,0 +1,125 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i64 0, align 8 + +define signext i32 @test_inesll(i64 %a, i64 %b) { +; CHECK-LABEL: test_inesll: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_inesll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_inesll_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define signext i32 @test_inesll_z(i64 %a) { +; CHECK-LABEL: test_inesll_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_inesll_sext_z(i64 %a) { +; CHECK-LABEL: test_inesll_sext_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_inesll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_inesll_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_inesll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_inesll_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_inesll_z_store(i64 %a) { +; CHECK-LABEL: test_inesll_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_inesll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_inesll_sext_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesiness.ll b/test/CodeGen/PowerPC/testComparesiness.ll index 56b7a6ab39740..66c95cd0d91d0 100644 --- a/test/CodeGen/PowerPC/testComparesiness.ll +++ b/test/CodeGen/PowerPC/testComparesiness.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py diff --git a/test/CodeGen/PowerPC/testComparesineuc.ll b/test/CodeGen/PowerPC/testComparesineuc.ll index 1cba13f122923..c478041b19e0e 100644 --- a/test/CodeGen/PowerPC/testComparesineuc.ll +++ b/test/CodeGen/PowerPC/testComparesineuc.ll @@ -1,15 +1,15 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i8 0, align 1 define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_ineuc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -23,7 +23,7 @@ entry: define signext i32 @test_ineuc_sext(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_ineuc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -38,7 +38,7 @@ entry: define signext i32 @test_ineuc_z(i8 zeroext %a) { ; CHECK-LABEL: test_ineuc_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -51,7 +51,7 @@ entry: define signext i32 @test_ineuc_sext_z(i8 zeroext %a) { ; CHECK-LABEL: test_ineuc_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -65,7 +65,7 @@ entry: define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_ineuc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -83,7 +83,7 @@ entry: define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_ineuc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -102,7 +102,7 @@ entry: define void @test_ineuc_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_ineuc_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -119,7 +119,7 @@ entry: define void @test_ineuc_sext_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_ineuc_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 diff --git a/test/CodeGen/PowerPC/testComparesineui.ll b/test/CodeGen/PowerPC/testComparesineui.ll index 36899b7ea8e1d..ef126270f418b 100644 --- a/test/CodeGen/PowerPC/testComparesineui.ll +++ b/test/CodeGen/PowerPC/testComparesineui.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py diff --git a/test/CodeGen/PowerPC/testComparesineull.ll b/test/CodeGen/PowerPC/testComparesineull.ll new file mode 100644 index 0000000000000..ba388a45fadde --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesineull.ll @@ -0,0 +1,125 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i64 0, align 8 + +define signext i32 @test_ineull(i64 %a, i64 %b) { +; CHECK-LABEL: test_ineull: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_ineull_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_ineull_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define signext i32 @test_ineull_z(i64 %a) { +; CHECK-LABEL: test_ineull_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_ineull_sext_z(i64 %a) { +; CHECK-LABEL: test_ineull_sext_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_ineull_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_ineull_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_ineull_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_ineull_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_ineull_z_store(i64 %a) { +; CHECK-LABEL: test_ineull_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_ineull_sext_z_store(i64 %a) { +; CHECK-LABEL: test_ineull_sext_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesineus.ll b/test/CodeGen/PowerPC/testComparesineus.ll index d24d854f31c9c..a78671b640758 100644 --- a/test/CodeGen/PowerPC/testComparesineus.ll +++ b/test/CodeGen/PowerPC/testComparesineus.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @@ -10,7 +10,7 @@ define signext i32 @test_ineus(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_ineus: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -24,7 +24,7 @@ entry: define signext i32 @test_ineus_sext(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_ineus_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -39,7 +39,7 @@ entry: define signext i32 @test_ineus_z(i16 zeroext %a) { ; CHECK-LABEL: test_ineus_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -52,7 +52,7 @@ entry: define signext i32 @test_ineus_sext_z(i16 zeroext %a) { ; CHECK-LABEL: test_ineus_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -66,7 +66,7 @@ entry: define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_ineus_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -84,7 +84,7 @@ entry: define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_ineus_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -103,7 +103,7 @@ entry: define void @test_ineus_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_ineus_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -120,7 +120,7 @@ entry: define void @test_ineus_sext_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_ineus_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 diff --git a/test/CodeGen/PowerPC/testCompareslleqsc.ll b/test/CodeGen/PowerPC/testCompareslleqsc.ll index 56af12827931f..43fb358efef65 100644 --- a/test/CodeGen/PowerPC/testCompareslleqsc.ll +++ b/test/CodeGen/PowerPC/testCompareslleqsc.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testCompareslleqsc.c' @@ -12,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsc(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lleqsc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -26,11 +26,11 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsc_sext(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lleqsc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -41,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsc_z(i8 signext %a) { ; CHECK-LABEL: test_lleqsc_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -54,10 +54,10 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsc_sext_z(i8 signext %a) { ; CHECK-LABEL: test_lleqsc_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 @@ -68,7 +68,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lleqsc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -86,13 +86,13 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lleqsc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -105,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsc_z_store(i8 signext %a) { ; CHECK-LABEL: test_lleqsc_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -122,12 +122,12 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsc_sext_z_store(i8 signext %a) { ; CHECK-LABEL: test_lleqsc_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testCompareslleqsi.ll b/test/CodeGen/PowerPC/testCompareslleqsi.ll index 90cf2c85888e6..ae8dffb1e2215 100644 --- a/test/CodeGen/PowerPC/testCompareslleqsi.ll +++ b/test/CodeGen/PowerPC/testCompareslleqsi.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 @@ -11,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsi(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lleqsi: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -25,11 +25,11 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsi_sext(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lleqsi_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -40,7 +40,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsi_z(i32 signext %a) { ; CHECK-LABEL: test_lleqsi_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -53,10 +53,10 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsi_sext_z(i32 signext %a) { ; CHECK-LABEL: test_lleqsi_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 @@ -67,7 +67,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lleqsi_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -85,13 +85,13 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lleqsi_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -104,7 +104,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsi_z_store(i32 signext %a) { ; CHECK-LABEL: test_lleqsi_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -122,12 +122,12 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsi_sext_z_store(i32 signext %a) { ; CHECK-LABEL: test_lleqsi_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testCompareslleqsll.ll b/test/CodeGen/PowerPC/testCompareslleqsll.ll index 4797ddfbfe970..89ef960a6f9ec 100644 --- a/test/CodeGen/PowerPC/testCompareslleqsll.ll +++ b/test/CodeGen/PowerPC/testCompareslleqsll.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @@ -11,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsll(i64 %a, i64 %b) { ; CHECK-LABEL: test_lleqsll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 @@ -25,7 +25,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_lleqsll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 @@ -39,7 +39,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsll_z(i64 %a) { ; CHECK-LABEL: test_lleqsll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr @@ -52,7 +52,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsll_sext_z(i64 %a) { ; CHECK-LABEL: test_lleqsll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr @@ -65,7 +65,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_lleqsll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -83,7 +83,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_lleqsll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -101,7 +101,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsll_z_store(i64 %a) { ; CHECK-LABEL: test_lleqsll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -118,7 +118,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_lleqsll_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testCompareslleqss.ll b/test/CodeGen/PowerPC/testCompareslleqss.ll index df60a6ccc00ee..5d1945d73e309 100644 --- a/test/CodeGen/PowerPC/testCompareslleqss.ll +++ b/test/CodeGen/PowerPC/testCompareslleqss.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -11,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqss(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_lleqss: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -25,11 +25,11 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqss_sext(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_lleqss_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -40,7 +40,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqss_z(i16 signext %a) { ; CHECK-LABEL: test_lleqss_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -53,10 +53,10 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqss_sext_z(i16 signext %a) { ; CHECK-LABEL: test_lleqss_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 @@ -67,7 +67,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqss_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_lleqss_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -85,13 +85,13 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_lleqss_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -104,7 +104,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqss_z_store(i16 signext %a) { ; CHECK-LABEL: test_lleqss_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -121,12 +121,12 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqss_sext_z_store(i16 signext %a) { ; CHECK-LABEL: test_lleqss_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesllequc.ll b/test/CodeGen/PowerPC/testComparesllequc.ll index 248825761295b..0f5d4c6f2879a 100644 --- a/test/CodeGen/PowerPC/testComparesllequc.ll +++ b/test/CodeGen/PowerPC/testComparesllequc.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 @@ -11,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_llequc(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llequc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -25,11 +25,11 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequc_sext(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llequc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -40,7 +40,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequc_z(i8 zeroext %a) { ; CHECK-LABEL: test_llequc_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -53,10 +53,10 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequc_sext_z(i8 zeroext %a) { ; CHECK-LABEL: test_llequc_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 @@ -67,7 +67,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llequc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -85,13 +85,13 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llequc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -104,7 +104,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequc_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_llequc_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -121,12 +121,12 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequc_sext_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_llequc_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesllequi.ll b/test/CodeGen/PowerPC/testComparesllequi.ll index 2342d80d94ef6..350168e0e6ccc 100644 --- a/test/CodeGen/PowerPC/testComparesllequi.ll +++ b/test/CodeGen/PowerPC/testComparesllequi.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 @@ -11,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_llequi(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llequi: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -25,11 +25,11 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequi_sext(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llequi_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -40,7 +40,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequi_z(i32 zeroext %a) { ; CHECK-LABEL: test_llequi_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -53,10 +53,10 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequi_sext_z(i32 zeroext %a) { ; CHECK-LABEL: test_llequi_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 @@ -67,7 +67,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llequi_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -85,13 +85,13 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llequi_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -104,7 +104,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequi_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_llequi_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -121,12 +121,12 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequi_sext_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_llequi_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesllequll.ll b/test/CodeGen/PowerPC/testComparesllequll.ll index 4dc7be69d2c8d..7d1fe527e8a54 100644 --- a/test/CodeGen/PowerPC/testComparesllequll.ll +++ b/test/CodeGen/PowerPC/testComparesllequll.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @@ -11,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_llequll(i64 %a, i64 %b) { ; CHECK-LABEL: test_llequll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 @@ -25,7 +25,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_llequll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 @@ -39,7 +39,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequll_z(i64 %a) { ; CHECK-LABEL: test_llequll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr @@ -52,7 +52,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequll_sext_z(i64 %a) { ; CHECK-LABEL: test_llequll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr @@ -65,7 +65,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llequll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -83,7 +83,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llequll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -101,7 +101,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequll_z_store(i64 %a) { ; CHECK-LABEL: test_llequll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -118,7 +118,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_llequll_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesllequs.ll b/test/CodeGen/PowerPC/testComparesllequs.ll index e79a974c06f5b..cc215216dfc42 100644 --- a/test/CodeGen/PowerPC/testComparesllequs.ll +++ b/test/CodeGen/PowerPC/testComparesllequs.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -11,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_llequs(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llequs: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -25,11 +25,11 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequs_sext(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llequs_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -40,7 +40,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequs_z(i16 zeroext %a) { ; CHECK-LABEL: test_llequs_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -53,10 +53,10 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequs_sext_z(i16 zeroext %a) { ; CHECK-LABEL: test_llequs_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 @@ -67,7 +67,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llequs_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -85,13 +85,13 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llequs_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -104,7 +104,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequs_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_llequs_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -121,12 +121,12 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequs_sext_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_llequs_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesllgesc.ll b/test/CodeGen/PowerPC/testComparesllgesc.ll new file mode 100644 index 0000000000000..82f54cd6b1b91 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgesc.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i8 0, align 1 + +define i64 @test_llgesc(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_llgesc: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +} + +define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_llgesc_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +} + +define void @test_llgesc_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_llgesc_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_llgesc_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllgesi.ll b/test/CodeGen/PowerPC/testComparesllgesi.ll new file mode 100644 index 0000000000000..82c1fa11b8b64 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgesi.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i32 0, align 4 + +define i64 @test_llgesi(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_llgesi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_llgesi_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define void @test_llgesi_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_llgesi_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_llgesi_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllgesll.ll b/test/CodeGen/PowerPC/testComparesllgesll.ll new file mode 100644 index 0000000000000..6fb53977a55a1 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgesll.ll @@ -0,0 +1,128 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i64 0, align 8 + +define i64 @test_llgesll(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgesll: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi r5, r3, 63 +; CHECK-NEXT: rldicl r6, r4, 1, 63 +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llgesll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgesll_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi r5, r3, 63 +; CHECK-NEXT: rldicl r6, r4, 1, 63 +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llgesll_z(i64 %a) { +; CHECK-LABEL: test_llgesll_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llgesll_sext_z(i64 %a) { +; CHECK-LABEL: test_llgesll_sext_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: not r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define void @test_llgesll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgesll_store: +; CHECK: # %bb.0: # %entry +; CHECK: sradi r6, r3, 63 +; CHECK: subfc r3, r4, r3 +; CHECK: rldicl r3, r4, 1, 63 +; CHECK: adde r3, r6, r3 +; CHECK: std r3, +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llgesll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgesll_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi r6, r3, 63 +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: rldicl r3, r4, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: adde r3, r6, r3 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llgesll_z_store(i64 %a) { +; CHECK-LABEL: test_llgesll_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llgesll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llgesll_sext_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: not r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllgess.ll b/test/CodeGen/PowerPC/testComparesllgess.ll new file mode 100644 index 0000000000000..1206339a23b77 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgess.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i16 0, align 2 + +define i64 @test_llgess(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llgess: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +} + +define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llgess_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +} + +define void @test_llgess_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llgess_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llgess_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllgeuc.ll b/test/CodeGen/PowerPC/testComparesllgeuc.ll new file mode 100644 index 0000000000000..e56e09b37ac3c --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgeuc.ll @@ -0,0 +1,112 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i8 0, align 1 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeuc(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: test_llgeuc: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeuc_sext(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: @test_llgeuc_sext +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeuc_z(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeuc_z +; CHECK: li r3, 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeuc_sext_z(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeuc_sext_z +; CHECK: li r3, -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeuc_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK_LABEL: test_llgeuc_store: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeuc_sext_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-LABEL: @test_llgeuc_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: stb [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeuc_z_store(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv1 = zext i1 %cmp to i8 + store i8 %conv1, i8* @glob + ret void +; CHECK-LABEL: @test_llgeuc_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: stb [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeuc_sext_z_store(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv1 = sext i1 %cmp to i8 + store i8 %conv1, i8* @glob + ret void +; CHECK-LABEL: @test_llgeuc_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: stb [[REG1]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesllgeui.ll b/test/CodeGen/PowerPC/testComparesllgeui.ll new file mode 100644 index 0000000000000..9e971b140de4f --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgeui.ll @@ -0,0 +1,112 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llgeui: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeui_sext(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeui_sext +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeui_z(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeui_z +; CHECK: li r3, 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeui_sext_z(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeui_sext_z +; CHECK: li r3, -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob + ret void +; CHECK_LABEL: test_igeuc_store: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeui_sext_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_llgeui_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: stw [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeui_z_store(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %sub = zext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_llgeui_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: stw [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeui_sext_z_store(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_llgeui_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: stw [[REG1]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesllgeull.ll b/test/CodeGen/PowerPC/testComparesllgeull.ll new file mode 100644 index 0000000000000..be1db4f754018 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgeull.ll @@ -0,0 +1,110 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeull(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llgeull: +; CHECK: subfc {{r[0-9]+}}, r4, r3 +; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4 +; CHECK-NEXT: addi r3, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeull_sext(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeull_sext +; CHECK: subfc [[REG1:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeull_z(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeull_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeull_sext_z(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeull_sext_z +; CHECK: li r3, -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeull_store(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_llgeull_store: +; CHECK: subfc {{r[0-9]+}}, r4, r3 +; CHECK: subfe [[REG1:r[0-9]+]], r4, r4 +; CHECK: addi {{r[0-9]+}}, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeull_sext_store(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_llgeull_sext_store +; CHECK: subfc [[REG1:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: std [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeull_z_store(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_llgeull_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: std [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeull_sext_z_store(i64 %a) { +entry: + store i64 -1, i64* @glob + ret void +; CHECK-LABEL: @test_llgeull_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: std [[REG1]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesllgeus.ll b/test/CodeGen/PowerPC/testComparesllgeus.ll new file mode 100644 index 0000000000000..4520ca3ead597 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgeus.ll @@ -0,0 +1,112 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeus(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: test_llgeus: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeus_sext(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: @test_llgeus_sext +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeus_z(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeus_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeus_sext_z(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeus_sext_z +; CHECK: li r3, -1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK_LABEL: test_llgeus_store: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeus_sext_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: @test_llgeus_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: sth [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeus_z_store(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv1 = zext i1 %cmp to i16 + store i16 %conv1, i16* @glob + ret void +; CHECK-LABEL: @test_llgeus_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: sth [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeus_sext_z_store(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv1 = sext i1 %cmp to i16 + store i16 %conv1, i16* @glob + ret void +; CHECK-LABEL: @test_llgeus_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: sth [[REG1]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesllgtsll.ll b/test/CodeGen/PowerPC/testComparesllgtsll.ll new file mode 100644 index 0000000000000..0dc1374374f79 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgtsll.ll @@ -0,0 +1,134 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtsll(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtsll: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori r3, [[REG4]], 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtsll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtsll_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NEXT: neg r3, [[REG5]] +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; FIXME +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtsll_z(i64 %a) { +; CHECK-LABEL: test_llgtsll_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi r4, r3, -1 +; CHECK-NEXT: nor r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtsll_sext_z(i64 %a) { +; CHECK-LABEL: test_llgtsll_sext_z: +; CHECK: addi [[REG1:r[0-9]+]], r3, -1 +; CHECK-NEXT: nor [[REG2:r[0-9]+]], [[REG1]], r3 +; CHECK-NEXT: sradi r3, [[REG2]], 63 +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind +define void @test_llgtsll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtsll_store: +; CHECK: # %bb.0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NOT: neg +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtsll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llgtsll_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp sgt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; FIXME +; Function Attrs: norecurse nounwind +define void @test_llgtsll_z_store(i64 %a) { +; CHECK-LABEL: test_llgtsll_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addi r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: nor r3, r5, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtsll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llgtsll_sext_z_store: +; CHECK: addi [[REG1:r[0-9]+]], r3, -1 +; CHECK: nor [[REG2:r[0-9]+]], [[REG1]], r3 +; CHECK: sradi [[REG3:r[0-9]+]], [[REG2]], 63 +entry: + %cmp = icmp sgt i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllgtuc.ll b/test/CodeGen/PowerPC/testComparesllgtuc.ll new file mode 100644 index 0000000000000..ba70713d61e58 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgtuc.ll @@ -0,0 +1,114 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i8 0, align 1 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtuc(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_llgtuc: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i8 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtuc_sext(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_llgtuc_sext: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i8 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtuc_z(i8 zeroext %a) { +; CHECK-LABEL: test_llgtuc_z: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i8 %a, 0 + %conv2 = zext i1 %cmp to i64 + ret i64 %conv2 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtuc_sext_z(i8 zeroext %a) { +; CHECK-LABEL: test_llgtuc_sext_z: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i8 %a, 0 + %conv2 = sext i1 %cmp to i64 + ret i64 %conv2 +} + +; Function Attrs: norecurse nounwind +define void @test_llgtuc_store(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_llgtuc_store: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp ugt i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtuc_sext_store(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_llgtuc_sext_store: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp ugt i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtuc_z_store(i8 zeroext %a) { +; CHECK-LABEL: test_llgtuc_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: stb r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i8 %a, 0 + %conv2 = zext i1 %cmp to i8 + store i8 %conv2, i8* @glob, align 1 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtuc_sext_z_store(i8 zeroext %a) { +; CHECK-LABEL: test_llgtuc_sext_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: neg r3, r3 +; CHECK: stb r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i8 %a, 0 + %conv2 = sext i1 %cmp to i8 + store i8 %conv2, i8* @glob, align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllgtui.ll b/test/CodeGen/PowerPC/testComparesllgtui.ll new file mode 100644 index 0000000000000..d07e85972f2dc --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgtui.ll @@ -0,0 +1,114 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtui(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_llgtui: +; CHECK-NOT: clrldi +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +entry: + %cmp = icmp ugt i32 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtui_sext(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_llgtui_sext: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i32 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtui_z(i32 zeroext %a) { +; CHECK-LABEL: test_llgtui_z: +; CHECK: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i32 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtui_sext_z(i32 zeroext %a) { +; CHECK-LABEL: test_llgtui_sext_z: +; CHECK: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i32 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind +define void @test_llgtui_store(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_llgtui_store: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp ugt i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtui_sext_store(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_llgtui_sext_store: +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp ugt i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtui_z_store(i32 zeroext %a) { +; CHECK-LABEL: test_llgtui_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: stw r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i32 %a, 0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtui_sext_z_store(i32 zeroext %a) { +; CHECK-LABEL: test_llgtui_sext_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: neg r3, r3 +; CHECK: stw r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i32 %a, 0 + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllgtus.ll b/test/CodeGen/PowerPC/testComparesllgtus.ll new file mode 100644 index 0000000000000..3758e8e097cee --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgtus.ll @@ -0,0 +1,127 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_llgtus: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i16 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtus_sext(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_llgtus_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ugt i16 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtus_z(i16 zeroext %a) { +; CHECK-LABEL: test_llgtus_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i16 %a, 0 + %conv2 = zext i1 %cmp to i64 + ret i64 %conv2 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgtus_sext_z(i16 zeroext %a) { +; CHECK-LABEL: test_llgtus_sext_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i16 %a, 0 + %conv2 = sext i1 %cmp to i64 + ret i64 %conv2 +} + +; Function Attrs: norecurse nounwind +define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_llgtus_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp ugt i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtus_sext_store(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_llgtus_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r4, r3 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp ugt i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtus_z_store(i16 zeroext %a) { +; CHECK-LABEL: test_llgtus_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i16 %a, 0 + %conv2 = zext i1 %cmp to i16 + store i16 %conv2, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llgtus_sext_z_store(i16 zeroext %a) { +; CHECK-LABEL: test_llgtus_sext_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i16 %a, 0 + %conv2 = sext i1 %cmp to i16 + store i16 %conv2, i16* @glob, align 2 + ret void +} + diff --git a/test/CodeGen/PowerPC/testCompareslllesc.ll b/test/CodeGen/PowerPC/testCompareslllesc.ll new file mode 100644 index 0000000000000..f9352990f2c44 --- /dev/null +++ b/test/CodeGen/PowerPC/testCompareslllesc.ll @@ -0,0 +1,69 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i8 0, align 1 + +define i64 @test_lllesc(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_lllesc: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +} + +define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_lllesc_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +} + +define void @test_lllesc_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_lllesc_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_lllesc_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/testCompareslllesi.ll b/test/CodeGen/PowerPC/testCompareslllesi.ll new file mode 100644 index 0000000000000..42062692a080d --- /dev/null +++ b/test/CodeGen/PowerPC/testCompareslllesi.ll @@ -0,0 +1,69 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i32 0, align 4 + +define i64 @test_lllesi(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_lllesi: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_lllesi_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define void @test_lllesi_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_lllesi_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_lllesi_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/testCompareslllesll.ll b/test/CodeGen/PowerPC/testCompareslllesll.ll new file mode 100644 index 0000000000000..8db1ee19ebb06 --- /dev/null +++ b/test/CodeGen/PowerPC/testCompareslllesll.ll @@ -0,0 +1,138 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_lllesll(i64 %a, i64 %b) { +; CHECK-LABEL: test_lllesll: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi r5, r4, 63 +; CHECK-NEXT: rldicl r6, r3, 1, 63 +; CHECK-NEXT: subfc r12, r3, r4 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_lllesll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_lllesll_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi r5, r4, 63 +; CHECK-NEXT: rldicl r6, r3, 1, 63 +; CHECK-NEXT: subfc r12, r3, r4 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_lllesll_z(i64 %a) { +; CHECK-LABEL: test_lllesll_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi r4, r3, -1 +; CHECK-NEXT: or r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_lllesll_sext_z(i64 %a) { +; CHECK-LABEL: test_lllesll_sext_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi r4, r3, -1 +; CHECK-NEXT: or r3, r4, r3 +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind +define void @test_lllesll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_lllesll_store: +; CHECK: # %bb.0: # %entry +; CHECK: sradi r6, r4, 63 +; CHECK: subfc r4, r3, r4 +; CHECK: rldicl r3, r3, 1, 63 +; CHECK: adde r3, r6, r3 +; CHECK: std r3, +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_lllesll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_lllesll_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sradi r6, r4, 63 +; CHECK-DAG: rldicl r3, r3, 1, 63 +; CHECK-DAG: subfc r4, r3, r4 +; CHECK: adde r3, r6, r3 +; CHECK: neg r3, r3 +; CHECK: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_lllesll_z_store(i64 %a) { +; CHECK-LABEL: test_lllesll_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addi r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: or r3, r5, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_lllesll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_lllesll_sext_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addi r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: or r3, r5, r3 +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 1 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllless.ll b/test/CodeGen/PowerPC/testComparesllless.ll new file mode 100644 index 0000000000000..a6f3b5e3988b3 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllless.ll @@ -0,0 +1,69 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i16 0, align 2 + +define i64 @test_llless(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llless: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +} + +define i64 @test_llless_sext(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llless_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +} + +define void @test_llless_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llless_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +define void @test_llless_sext_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llless_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllleuc.ll b/test/CodeGen/PowerPC/testComparesllleuc.ll new file mode 100644 index 0000000000000..3e4beb73b6fba --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllleuc.ll @@ -0,0 +1,116 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i8 0, align 1 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleuc(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: test_llleuc: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleuc_sext(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: @test_llleuc_sext +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleuc_z(i8 zeroext %a) { +entry: + %cmp = icmp ule i8 %a, 0 + %conv2 = zext i1 %cmp to i64 + ret i64 %conv2 +; CHECK-LABEL: test_llleuc_z: +; CHECK: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleuc_sext_z(i8 zeroext %a) { +entry: + %cmp = icmp ule i8 %a, 0 + %conv2 = sext i1 %cmp to i64 + ret i64 %conv2 +; CHECK-LABEL: @test_llleuc_sext_z +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleuc_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-LABEL: test_llleuc_store: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleuc_sext_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-LABEL: @test_llleuc_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: stb [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleuc_z_store(i8 zeroext %a) { +entry: + %cmp = icmp ule i8 %a, 0 + %conv2 = zext i1 %cmp to i8 + store i8 %conv2, i8* @glob + ret void +; CHECK-LABEL: test_llleuc_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi {{r[0-9]}}, r3, 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleuc_sext_z_store(i8 zeroext %a) { +entry: + %cmp = icmp ule i8 %a, 0 + %conv2 = sext i1 %cmp to i8 + store i8 %conv2, i8* @glob + ret void +; CHECK-LABEL: @test_llleuc_sext_z_store +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK: neg [[REG3:r[0-9]+]], [[REG2]] +; CHECK: stb [[REG3]] +; CHECK: blr +} diff --git a/test/CodeGen/PowerPC/testComparesllleui.ll b/test/CodeGen/PowerPC/testComparesllleui.ll new file mode 100644 index 0000000000000..0dca0dcb56fae --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllleui.ll @@ -0,0 +1,117 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleui(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llleui: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleui_sext(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llleui_sext +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleui_z(i32 zeroext %a) { +entry: + %cmp = icmp ule i32 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llleui_z: +; CHECK: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleui_sext_z(i32 zeroext %a) { +entry: + %cmp = icmp ule i32 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llleui_sext_z +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleui_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob + ret void +; CHECK-LABEL: test_llleui_store: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleui_sext_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_llleui_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: stw [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleui_z_store(i32 zeroext %a) { +entry: + %cmp = icmp ule i32 %a, 0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob + ret void +; CHECK-LABEL: test_llleui_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleui_sext_z_store(i32 zeroext %a) { +entry: + %cmp = icmp ule i32 %a, 0 + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_llleui_sext_z_store +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK: neg [[REG3:r[0-9]+]], [[REG2]] +; CHECK: stw [[REG3]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesllleull.ll b/test/CodeGen/PowerPC/testComparesllleull.ll new file mode 100644 index 0000000000000..bd75f8c736bee --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllleull.ll @@ -0,0 +1,115 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleull(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llleull: +; CHECK: subfc {{r[0-9]+}}, r3, r4 +; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3 +; CHECK-NEXT: addi r3, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleull_sext(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llleull_sext +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleull_z(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llleull_z +; CHECK: cntlzd [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleull_sext_z(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llleull_sext_z +; CHECK: addic [[REG1:r[0-9]+]], r3, -1 +; CHECK: subfe r3, [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleull_store(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_llleull_store: +; CHECK: subfc {{r[0-9]+}}, r3, r4 +; CHECK: subfe [[REG1:r[0-9]+]], r3, r3 +; CHECK: addi r3, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleull_sext_store(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_llleull_sext_store +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: std [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleull_z_store(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_llleull_z_store: +; CHECK: cntlzd [[REG1:r[0-9]+]], r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleull_sext_z_store(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_llleull_sext_z_store +; CHECK: addic [[REG1:r[0-9]+]], r3, -1 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: std [[REG2]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesllleus.ll b/test/CodeGen/PowerPC/testComparesllleus.ll new file mode 100644 index 0000000000000..422a2b3f0f26c --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllleus.ll @@ -0,0 +1,117 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleus(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: test_llleus: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleus_sext(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: @test_llleus_sext +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleus_z(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %conv2 = zext i1 %cmp to i64 + ret i64 %conv2 +; CHECK-LABEL: test_llleus_z: +; CHECK: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleus_sext_z(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %conv2 = sext i1 %cmp to i64 + ret i64 %conv2 +; CHECK-LABEL: @test_llleus_sext_z +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleus_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: test_llleus_store: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleus_sext_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: @test_llleus_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: sth [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleus_z_store(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %conv2 = zext i1 %cmp to i16 + store i16 %conv2, i16* @glob + ret void +; CHECK-LABEL: test_llleus_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleus_sext_z_store(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %conv2 = sext i1 %cmp to i16 + store i16 %conv2, i16* @glob + ret void +; CHECK-LABEL: @test_llleus_sext_z_store +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK: neg [[REG3:r[0-9]+]], [[REG2]] +; CHECK: sth [[REG3]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesllltsll.ll b/test/CodeGen/PowerPC/testComparesllltsll.ll new file mode 100644 index 0000000000000..3e37daf046f02 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllltsll.ll @@ -0,0 +1,99 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltsll(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltsll: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori r3, [[REG4]], 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltsll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltsll_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NEXT: neg r3, [[REG5]] +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltsll_sext_z(i64 %a) { +; CHECK-LABEL: test_llltsll_sext_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i64 %a, 0 + %sub = sext i1 %cmp to i64 + ret i64 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_llltsll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltsll_store: +; CHECK: # %bb.0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK-NOT: neg +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltsll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llltsll_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 +; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 +; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 +; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] +; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 +; CHECK: neg {{r[0-9]+}}, [[REG5]] +entry: + %cmp = icmp slt i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltsll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llltsll_sext_z_store: +; CHECK: sradi r3, r3, 63 +entry: + %cmp = icmp slt i64 %a, 0 + %sub = sext i1 %cmp to i64 + store i64 %sub, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllltuc.ll b/test/CodeGen/PowerPC/testComparesllltuc.ll new file mode 100644 index 0000000000000..a8244e757b15d --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllltuc.ll @@ -0,0 +1,60 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i8 0, align 1 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_llltuc: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i8 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltuc_sext(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_llltuc_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i8 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +} + +; Function Attrs: norecurse nounwind +define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_llltuc_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[2-9]+]], r3, r4 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp ult i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test_llltuc_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp ult i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllltui.ll b/test/CodeGen/PowerPC/testComparesllltui.ll new file mode 100644 index 0000000000000..e785942b3c9ff --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllltui.ll @@ -0,0 +1,108 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_llltui: +; CHECK: # %bb.0: # %entry +; CHECK-NOT: clrldi +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i32 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltui_sext(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_llltui_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i32 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltui_z(i32 zeroext %a) { +; CHECK-LABEL: test_llltui_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: li r3, 0 +; CHECK-NEXT: blr +entry: + ret i64 0 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltui_sext_z(i32 zeroext %a) { +; CHECK-LABEL: test_llltui_sext_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: li r3, 0 +; CHECK-NEXT: blr +entry: + ret i64 0 +} + +; Function Attrs: norecurse nounwind +define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_llltui_store: +; CHECK: # %bb.0: # %entry +; CHECK-NOT: clrldi +; CHECK: sub [[REG:r[2-9]+]], r3, r4 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp ult i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltui_sext_store(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: test_llltui_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NOT: clrldi +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp ult i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltui_z_store(i32 zeroext %a) { +; CHECK-LABEL: test_llltui_z_store: +; CHECK: # %bb.0: # %entry +; CHECK: li [[REG:r[0-9]+]], 0 +; CHECK: stw [[REG]], 0(r3) +; CHECK-NEXT: blr +entry: + store i32 0, i32* @glob, align 4 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltui_sext_z_store(i32 zeroext %a) { +; CHECK-LABEL: test_llltui_sext_z_store: +; CHECK: # %bb.0: # %entry +; CHECK: li [[REG:r[0-9]+]], 0 +; CHECK: stw [[REG]], 0(r3) +; CHECK-NEXT: blr +entry: + store i32 0, i32* @glob, align 4 + ret void +} + diff --git a/test/CodeGen/PowerPC/testComparesllltus.ll b/test/CodeGen/PowerPC/testComparesllltus.ll new file mode 100644 index 0000000000000..e997d0aa8b82b --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllltus.ll @@ -0,0 +1,59 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_llltus: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i16 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltus_sext(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_llltus_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i16 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +} + +; Function Attrs: norecurse nounwind +define void @test_llltus_store(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_llltus_store: +; CHECK: sub [[REG:r[2-9]+]], r3, r4 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp ult i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltus_sext_store(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_llltus_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp ult i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllnesll.ll b/test/CodeGen/PowerPC/testComparesllnesll.ll new file mode 100644 index 0000000000000..cdd272f57bd41 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllnesll.ll @@ -0,0 +1,125 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i64 0, align 8 + +define i64 @test_llnesll(i64 %a, i64 %b) { +; CHECK-LABEL: test_llnesll: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llnesll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llnesll_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llnesll_z(i64 %a) { +; CHECK-LABEL: test_llnesll_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llnesll_sext_z(i64 %a) { +; CHECK-LABEL: test_llnesll_sext_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define void @test_llnesll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llnesll_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llnesll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llnesll_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llnesll_z_store(i64 %a) { +; CHECK-LABEL: test_llnesll_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llnesll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llnesll_sext_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllneull.ll b/test/CodeGen/PowerPC/testComparesllneull.ll new file mode 100644 index 0000000000000..7956881f495a0 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllneull.ll @@ -0,0 +1,125 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i64 0, align 8 + +define i64 @test_llneull(i64 %a, i64 %b) { +; CHECK-LABEL: test_llneull: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llneull_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_llneull_sext: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llneull_z(i64 %a) { +; CHECK-LABEL: test_llneull_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addic r4, r3, -1 +; CHECK-NEXT: subfe r3, r4, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llneull_sext_z(i64 %a) { +; CHECK-LABEL: test_llneull_sext_z: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define void @test_llneull_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llneull_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llneull_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_llneull_sext_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llneull_z_store(i64 %a) { +; CHECK-LABEL: test_llneull_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_llneull_sext_z_store(i64 %a) { +; CHECK-LABEL: test_llneull_sext_z_store: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: subfic r3, r3, 0 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: subfe r3, r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp ne i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/tls-cse.ll b/test/CodeGen/PowerPC/tls-cse.ll index 6529469c1fd97..c770209c6ca5c 100644 --- a/test/CodeGen/PowerPC/tls-cse.ll +++ b/test/CodeGen/PowerPC/tls-cse.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs -march=ppc64 -mcpu=pwr7 -O2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -march=ppc64 -mcpu=pwr7 -O2 -relocation-model=pic < %s | grep "__tls_get_addr" | count 1 +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -relocation-model=pic < %s | grep "__tls_get_addr" | count 1 ; This test was derived from LLVM's own ; PrettyStackTraceEntry::~PrettyStackTraceEntry(). It demonstrates an diff --git a/test/CodeGen/PowerPC/tls-pic.ll b/test/CodeGen/PowerPC/tls-pic.ll index e498cd3fcd694..db60ec7e22a7f 100644 --- a/test/CodeGen/PowerPC/tls-pic.ll +++ b/test/CodeGen/PowerPC/tls-pic.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -march=ppc64 -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0 %s -; RUN: llc -verify-machineinstrs -march=ppc64 -mcpu=pwr7 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1 %s -; RUN: llc -verify-machineinstrs -march=ppc32 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0-32 %s -; RUN: llc -verify-machineinstrs -march=ppc32 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1-32 %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0 %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1 %s +; RUN: llc -verify-machineinstrs -mtriple=ppc32-- -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0-32 %s +; RUN: llc -verify-machineinstrs -mtriple=ppc32-- -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1-32 %s target triple = "powerpc64-unknown-linux-gnu" ; Test correct assembly code generation for thread-local storage using diff --git a/test/CodeGen/PowerPC/tls-store2.ll b/test/CodeGen/PowerPC/tls-store2.ll index c13bec249ad40..d51c08891b4ea 100644 --- a/test/CodeGen/PowerPC/tls-store2.ll +++ b/test/CodeGen/PowerPC/tls-store2.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -march=ppc64 -mcpu=pwr7 -O2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -relocation-model=pic < %s | FileCheck %s target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/tls.ll b/test/CodeGen/PowerPC/tls.ll index 63f498c1662c5..72e731cdb9cbd 100644 --- a/test/CodeGen/PowerPC/tls.ll +++ b/test/CodeGen/PowerPC/tls.ll @@ -1,6 +1,6 @@ -; RUN: llc -relocation-model=static -verify-machineinstrs -O0 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT0 %s -; RUN: llc -relocation-model=static -verify-machineinstrs -O1 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT1 %s -; RUN: llc -verify-machineinstrs -O0 < %s -march=ppc32 -mcpu=ppc | FileCheck -check-prefix=OPT0-PPC32 %s +; RUN: llc -relocation-model=static -verify-machineinstrs -O0 < %s -mcpu=ppc64 | FileCheck -check-prefix=OPT0 %s +; RUN: llc -relocation-model=static -verify-machineinstrs -O1 < %s -mcpu=ppc64 | FileCheck -check-prefix=OPT1 %s +; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=ppc32-- -mcpu=ppc | FileCheck -check-prefix=OPT0-PPC32 %s target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/tls_get_addr_fence1.mir b/test/CodeGen/PowerPC/tls_get_addr_fence1.mir index fa8e73e321dda..d45a83d0723f0 100644 --- a/test/CodeGen/PowerPC/tls_get_addr_fence1.mir +++ b/test/CodeGen/PowerPC/tls_get_addr_fence1.mir @@ -4,9 +4,9 @@ --- | target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" - + @tls_var = external thread_local local_unnamed_addr global i32 - + define i32 @tls_func() local_unnamed_addr { entry: %0 = load i32, i32* @tls_var @@ -22,13 +22,13 @@ legalized: false regBankSelected: false selected: false tracksRegLiveness: true -registers: +registers: - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' } - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' } - { id: 2, class: g8rc, preferred-register: '' } -liveins: +liveins: - { reg: '%x2' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -45,9 +45,9 @@ frameInfo: hasMustTailInVarArgFunc: false savePoint: '' restorePoint: '' -fixedStack: -stack: -constants: +fixedStack: +stack: +constants: body: | bb.0.entry: liveins: %x2 @@ -57,7 +57,7 @@ body: | %x3 = COPY %2 BLR8 implicit %lr8, implicit %rm, implicit %x3 ; CHECK-LABEL: bb.0.entry - ; CHECK: %[[reg1:[0-9]+]] = ADDIStlsgdHA %x2, @tls_var + ; CHECK: %[[reg1:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStlsgdHA %x2, @tls_var ; CHECK: ADJCALLSTACKDOWN 0, 0 ; CHECK: %x3 = ADDItlsgdL %[[reg1]], @tls_var ; CHECK: %x3 = GETtlsADDR %x3, @tls_var diff --git a/test/CodeGen/PowerPC/trampoline.ll b/test/CodeGen/PowerPC/trampoline.ll index d0658a8a23f1a..f8e896690acc0 100644 --- a/test/CodeGen/PowerPC/trampoline.ll +++ b/test/CodeGen/PowerPC/trampoline.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 | grep "__trampoline_setup" +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep "__trampoline_setup" module asm "\09.lazy_reference .objc_class_name_NSImageRep" module asm "\09.objc_class_name_NSBitmapImageRep=0" diff --git a/test/CodeGen/PowerPC/unaligned.ll b/test/CodeGen/PowerPC/unaligned.ll index 2d1fd80e5c4fc..c9f65f243b1d0 100644 --- a/test/CodeGen/PowerPC/unaligned.ll +++ b/test/CodeGen/PowerPC/unaligned.ll @@ -89,7 +89,7 @@ entry: ; CHECK: @foo6 ; CHECK-DAG: ld ; CHECK-DAG: ld -; CHECK-DAG: stdx +; CHECK-DAG: std ; CHECK: stdx ; For VSX on P7, unaligned loads and stores are preferable to aligned diff --git a/test/CodeGen/PowerPC/unsafe-math.ll b/test/CodeGen/PowerPC/unsafe-math.ll index baa951dc164c2..edc970b4d1629 100644 --- a/test/CodeGen/PowerPC/unsafe-math.ll +++ b/test/CodeGen/PowerPC/unsafe-math.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 | grep fmul | count 2 -; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -march=ppc32 -enable-unsafe-fp-math | \ +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- | grep fmul | count 2 +; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- -enable-unsafe-fp-math | \ ; RUN: grep fmul | count 1 define double @foo(double %X) nounwind { diff --git a/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll b/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll index 98862cd049a5d..82c6c318abdc3 100644 --- a/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll +++ b/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-late-peephole=true < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ ; RUN: --check-prefix=CHECK-BE ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ @@ -70,9 +70,9 @@ entry: ; CHECK-LABEL: @getf ; CHECK-P7-LABEL: @getf ; CHECK-BE-LABEL: @getf -; CHECK: li [[IMMREG:[0-9]+]], 3 -; CHECK: xor [[TRUNCREG:[0-9]+]], [[IMMREG]], 5 -; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[TRUNCREG]] +; CHECK: xori [[TRUNCREG:[0-9]+]], 5, 3 +; CHECK: sldi [[SHIFTREG:[0-9]+]], [[TRUNCREG]], 2 +; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] ; CHECK: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] ; CHECK: xscvspdpn 1, ; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 2, 28, 29 diff --git a/test/CodeGen/PowerPC/vcmp-fold.ll b/test/CodeGen/PowerPC/vcmp-fold.ll index 607106ee4cff4..416fd6cadea03 100644 --- a/test/CodeGen/PowerPC/vcmp-fold.ll +++ b/test/CodeGen/PowerPC/vcmp-fold.ll @@ -1,6 +1,6 @@ ; This should fold the "vcmpbfp." and "vcmpbfp" instructions into a single ; "vcmpbfp.". -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | grep vcmpbfp | count 1 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | grep vcmpbfp | count 1 define void @test(<4 x float>* %x, <4 x float>* %y, i32* %P) { diff --git a/test/CodeGen/PowerPC/vec_abs.ll b/test/CodeGen/PowerPC/vec_abs.ll index 95965ef96b104..f7ff18f3ce179 100644 --- a/test/CodeGen/PowerPC/vec_abs.ll +++ b/test/CodeGen/PowerPC/vec_abs.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64le \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mattr=+altivec -mattr=+vsx | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64le \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s \ ; RUN: -check-prefix=CHECK-NOVSX diff --git a/test/CodeGen/PowerPC/vec_add_sub_quadword.ll b/test/CodeGen/PowerPC/vec_add_sub_quadword.ll index f42f7d1178319..8f3864ff26836 100644 --- a/test/CodeGen/PowerPC/vec_add_sub_quadword.ll +++ b/test/CodeGen/PowerPC/vec_add_sub_quadword.ll @@ -8,7 +8,7 @@ define <1 x i128> @out_of_bounds_insertelement(<1 x i128> %x, i128 %val) nounwin %result = add <1 x i128> %x, %tmpvec ret <1 x i128> %result ; CHECK-LABEL: @out_of_bounds_insertelement -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: blr } diff --git a/test/CodeGen/PowerPC/vec_auto_constant.ll b/test/CodeGen/PowerPC/vec_auto_constant.ll index 7055fbe26a575..ab5f1b836318b 100644 --- a/test/CodeGen/PowerPC/vec_auto_constant.ll +++ b/test/CodeGen/PowerPC/vec_auto_constant.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s ; Formerly produced .long, 7320806 (partial) ; CHECK: .byte 22 ; CHECK: .byte 21 diff --git a/test/CodeGen/PowerPC/vec_br_cmp.ll b/test/CodeGen/PowerPC/vec_br_cmp.ll index b058fd0864d95..fad927a22a960 100644 --- a/test/CodeGen/PowerPC/vec_br_cmp.ll +++ b/test/CodeGen/PowerPC/vec_br_cmp.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 -o %t +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 -o %t ; RUN: grep vcmpeqfp. %t ; RUN: not grep mfcr %t diff --git a/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll b/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll index a088d4b314a9a..b48836db32ed1 100644 --- a/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll +++ b/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mattr=+altivec -disable-ppc-ilp-pref | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin -mattr=+altivec -disable-ppc-ilp-pref | FileCheck %s ; Formerly this did byte loads and word stores. @a = external global <16 x i8> @b = external global <16 x i8> diff --git a/test/CodeGen/PowerPC/vec_call.ll b/test/CodeGen/PowerPC/vec_call.ll index 61a4c47d98f80..a7b156f5600cb 100644 --- a/test/CodeGen/PowerPC/vec_call.ll +++ b/test/CodeGen/PowerPC/vec_call.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 define <4 x i32> @test_arg(<4 x i32> %A, <4 x i32> %B) { %C = add <4 x i32> %A, %B ; <<4 x i32>> [#uses=1] diff --git a/test/CodeGen/PowerPC/vec_extract_p9.ll b/test/CodeGen/PowerPC/vec_extract_p9.ll index 241209a0e6b75..7e397f546848c 100644 --- a/test/CodeGen/PowerPC/vec_extract_p9.ll +++ b/test/CodeGen/PowerPC/vec_extract_p9.ll @@ -4,12 +4,12 @@ define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) { ; CHECK-LE-LABEL: test1: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextubrx 3, 5, 2 ; CHECK-LE-NEXT: clrldi 3, 3, 56 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test1: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextublx 3, 5, 2 ; CHECK-BE-NEXT: clrldi 3, 3, 56 ; CHECK-BE-NEXT: blr @@ -21,12 +21,12 @@ entry: define signext i8 @test2(<16 x i8> %a, i32 signext %index) { ; CHECK-LE-LABEL: test2: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextubrx 3, 5, 2 ; CHECK-LE-NEXT: extsb 3, 3 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test2: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextublx 3, 5, 2 ; CHECK-BE-NEXT: extsb 3, 3 ; CHECK-BE-NEXT: blr @@ -38,13 +38,13 @@ entry: define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) { ; CHECK-LE-LABEL: test3: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-LE-NEXT: vextuhrx 3, 3, 2 ; CHECK-LE-NEXT: clrldi 3, 3, 48 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test3: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-BE-NEXT: vextuhlx 3, 3, 2 ; CHECK-BE-NEXT: clrldi 3, 3, 48 @@ -57,13 +57,13 @@ entry: define signext i16 @test4(<8 x i16> %a, i32 signext %index) { ; CHECK-LE-LABEL: test4: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-LE-NEXT: vextuhrx 3, 3, 2 ; CHECK-LE-NEXT: extsh 3, 3 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test4: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-BE-NEXT: vextuhlx 3, 3, 2 ; CHECK-BE-NEXT: extsh 3, 3 @@ -76,12 +76,12 @@ entry: define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) { ; CHECK-LE-LABEL: test5: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test5: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: blr @@ -93,13 +93,13 @@ entry: define signext i32 @test6(<4 x i32> %a, i32 signext %index) { ; CHECK-LE-LABEL: test6: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: extsw 3, 3 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test6: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: extsw 3, 3 @@ -113,13 +113,13 @@ entry: ; Test with immediate index define zeroext i8 @test7(<16 x i8> %a) { ; CHECK-LE-LABEL: test7: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: li 3, 1 ; CHECK-LE-NEXT: vextubrx 3, 3, 2 ; CHECK-LE-NEXT: clrldi 3, 3, 56 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test7: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: li 3, 1 ; CHECK-BE-NEXT: vextublx 3, 3, 2 ; CHECK-BE-NEXT: clrldi 3, 3, 56 @@ -132,13 +132,13 @@ entry: define zeroext i16 @test8(<8 x i16> %a) { ; CHECK-LE-LABEL: test8: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: li 3, 2 ; CHECK-LE-NEXT: vextuhrx 3, 3, 2 ; CHECK-LE-NEXT: clrldi 3, 3, 48 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test8: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: li 3, 2 ; CHECK-BE-NEXT: vextuhlx 3, 3, 2 ; CHECK-BE-NEXT: clrldi 3, 3, 48 @@ -151,17 +151,17 @@ entry: define zeroext i32 @test9(<4 x i32> %a) { ; CHECK-LE-LABEL: test9: -; CHECK-LE: # BB#0: # %entry -; CHECK-LE-NEXT: li 3, 4 +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: li 3, 12 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test9: -; CHECK-BE: # BB#0: # %entry -; CHECK-BE-NEXT: li 3, 4 +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: li 3, 12 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: blr entry: - %vecext = extractelement <4 x i32> %a, i32 1 + %vecext = extractelement <4 x i32> %a, i32 3 ret i32 %vecext } diff --git a/test/CodeGen/PowerPC/vec_extract_p9_2.ll b/test/CodeGen/PowerPC/vec_extract_p9_2.ll new file mode 100644 index 0000000000000..f2ce7924ed90f --- /dev/null +++ b/test/CodeGen/PowerPC/vec_extract_p9_2.ll @@ -0,0 +1,248 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE + +define zeroext i8 @test_add1(<16 x i8> %a, i32 signext %index, i8 zeroext %c) { +; CHECK-LE-LABEL: test_add1: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: vextubrx 3, 5, 2 +; CHECK-LE-NEXT: add 3, 3, 6 +; CHECK-LE-NEXT: rlwinm 3, 3, 0, 24, 31 +; CHECK-LE-NEXT: blr +; CHECK-BE-LABEL: test_add1: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: vextublx 3, 5, 2 +; CHECK-BE-NEXT: add 3, 3, 6 +; CHECK-BE-NEXT: rlwinm 3, 3, 0, 24, 31 +; CHECK-BE-NEXT: blr +entry: + %vecext = extractelement <16 x i8> %a, i32 %index + %conv = zext i8 %vecext to i32 + %conv1 = zext i8 %c to i32 + %add = add nuw nsw i32 %conv, %conv1 + %conv2 = trunc i32 %add to i8 + ret i8 %conv2 +} + +define signext i8 @test_add2(<16 x i8> %a, i32 signext %index, i8 signext %c) { +; CHECK-LE-LABEL: test_add2: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: vextubrx 3, 5, 2 +; CHECK-LE-NEXT: add 3, 3, 6 +; CHECK-LE-NEXT: extsb 3, 3 +; CHECK-LE-NEXT: blr +; CHECK-BE-LABEL: test_add2: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: vextublx 3, 5, 2 +; CHECK-BE-NEXT: add 3, 3, 6 +; CHECK-BE-NEXT: extsb 3, 3 +; CHECK-BE-NEXT: blr +entry: + %vecext = extractelement <16 x i8> %a, i32 %index + %conv3 = zext i8 %vecext to i32 + %conv14 = zext i8 %c to i32 + %add = add nuw nsw i32 %conv3, %conv14 + %conv2 = trunc i32 %add to i8 + ret i8 %conv2 +} + +define zeroext i16 @test_add3(<8 x i16> %a, i32 signext %index, i16 zeroext %c) { +; CHECK-LE-LABEL: test_add3: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 +; CHECK-LE-NEXT: vextuhrx 3, 3, 2 +; CHECK-LE-NEXT: add 3, 3, 6 +; CHECK-LE-NEXT: rlwinm 3, 3, 0, 16, 31 +; CHECK-LE-NEXT: blr +; CHECK-BE-LABEL: test_add3: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 +; CHECK-BE-NEXT: vextuhlx 3, 3, 2 +; CHECK-BE-NEXT: add 3, 3, 6 +; CHECK-BE-NEXT: rlwinm 3, 3, 0, 16, 31 +; CHECK-BE-NEXT: blr +entry: + %vecext = extractelement <8 x i16> %a, i32 %index + %conv = zext i16 %vecext to i32 + %conv1 = zext i16 %c to i32 + %add = add nuw nsw i32 %conv, %conv1 + %conv2 = trunc i32 %add to i16 + ret i16 %conv2 +} + +define signext i16 @test_add4(<8 x i16> %a, i32 signext %index, i16 signext %c) { +; CHECK-LE-LABEL: test_add4: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 +; CHECK-LE-NEXT: vextuhrx 3, 3, 2 +; CHECK-LE-NEXT: add 3, 3, 6 +; CHECK-LE-NEXT: extsh 3, 3 +; CHECK-LE-NEXT: blr +; CHECK-BE-LABEL: test_add4: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 +; CHECK-BE-NEXT: vextuhlx 3, 3, 2 +; CHECK-BE-NEXT: add 3, 3, 6 +; CHECK-BE-NEXT: extsh 3, 3 +; CHECK-BE-NEXT: blr +entry: + %vecext = extractelement <8 x i16> %a, i32 %index + %conv5 = zext i16 %vecext to i32 + %conv16 = zext i16 %c to i32 + %add = add nuw nsw i32 %conv5, %conv16 + %conv2 = trunc i32 %add to i16 + ret i16 %conv2 +} + +define zeroext i32 @test_add5(<4 x i32> %a, i32 signext %index, i32 zeroext %c) { +; CHECK-LE-LABEL: test_add5: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 +; CHECK-LE-NEXT: vextuwrx 3, 3, 2 +; CHECK-LE-NEXT: add 3, 3, 6 +; CHECK-LE-NEXT: clrldi 3, 3, 32 +; CHECK-LE-NEXT: blr +; CHECK-BE-LABEL: test_add5: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 +; CHECK-BE-NEXT: vextuwlx 3, 3, 2 +; CHECK-BE-NEXT: add 3, 3, 6 +; CHECK-BE-NEXT: clrldi 3, 3, 32 +; CHECK-BE-NEXT: blr +entry: + %vecext = extractelement <4 x i32> %a, i32 %index + %add = add i32 %vecext, %c + ret i32 %add +} + +define signext i32 @test_add6(<4 x i32> %a, i32 signext %index, i32 signext %c) { +; CHECK-LE-LABEL: test_add6: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 +; CHECK-LE-NEXT: vextuwrx 3, 3, 2 +; CHECK-LE-NEXT: add 3, 3, 6 +; CHECK-LE-NEXT: extsw 3, 3 +; CHECK-LE-NEXT: blr +; CHECK-BE-LABEL: test_add6: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 +; CHECK-BE-NEXT: vextuwlx 3, 3, 2 +; CHECK-BE-NEXT: add 3, 3, 6 +; CHECK-BE-NEXT: extsw 3, 3 +; CHECK-BE-NEXT: blr +entry: + %vecext = extractelement <4 x i32> %a, i32 %index + %add = add nsw i32 %vecext, %c + ret i32 %add +} + +; When extracting word element 2 on LE, it's better to use mfvsrwz rather than vextuwrx +define zeroext i32 @test7(<4 x i32> %a) { +; CHECK-LE-LABEL: test7: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: mfvsrwz 3, 34 +; CHECK-LE-NEXT: blr +; CHECK-BE-LABEL: test7: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: li 3, 8 +; CHECK-BE-NEXT: vextuwlx 3, 3, 2 +; CHECK-BE-NEXT: blr +entry: + %vecext = extractelement <4 x i32> %a, i32 2 + ret i32 %vecext +} + +define zeroext i32 @testadd_7(<4 x i32> %a, i32 zeroext %c) { +; CHECK-LE-LABEL: testadd_7: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: mfvsrwz 3, 34 +; CHECK-LE-NEXT: add 3, 3, 5 +; CHECK-LE-NEXT: clrldi 3, 3, 32 +; CHECK-LE-NEXT: blr +; CHECK-BE-LABEL: testadd_7: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: li 3, 8 +; CHECK-BE-NEXT: vextuwlx 3, 3, 2 +; CHECK-BE-NEXT: add 3, 3, 5 +; CHECK-BE-NEXT: clrldi 3, 3, 32 +; CHECK-BE-NEXT: blr +entry: + %vecext = extractelement <4 x i32> %a, i32 2 + %add = add i32 %vecext, %c + ret i32 %add +} + +define signext i32 @test8(<4 x i32> %a) { +; CHECK-LE-LABEL: test8: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: mfvsrwz 3, 34 +; CHECK-LE-NEXT: extsw 3, 3 +; CHECK-LE-NEXT: blr +; CHECK-BE-LABEL: test8: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: li 3, 8 +; CHECK-BE-NEXT: vextuwlx 3, 3, 2 +; CHECK-BE-NEXT: extsw 3, 3 +; CHECK-BE-NEXT: blr +entry: + %vecext = extractelement <4 x i32> %a, i32 2 + ret i32 %vecext +} + +define signext i32 @testadd_8(<4 x i32> %a, i32 signext %c) { +; CHECK-LE-LABEL: testadd_8: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: mfvsrwz 3, 34 +; CHECK-LE-NEXT: add 3, 3, 5 +; CHECK-LE-NEXT: extsw 3, 3 +; CHECK-LE-NEXT: blr +; CHECK-BE-LABEL: testadd_8: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: li 3, 8 +; CHECK-BE-NEXT: vextuwlx 3, 3, 2 +; CHECK-BE-NEXT: add 3, 3, 5 +; CHECK-BE-NEXT: extsw 3, 3 +; CHECK-BE-NEXT: blr +entry: + %vecext = extractelement <4 x i32> %a, i32 2 + %add = add nsw i32 %vecext, %c + ret i32 %add +} + +; When extracting word element 1 on BE, it's better to use mfvsrwz rather than vextuwlx +define signext i32 @test9(<4 x i32> %a) { +; CHECK-LE-LABEL: test9: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: li 3, 4 +; CHECK-LE-NEXT: vextuwrx 3, 3, 2 +; CHECK-LE-NEXT: extsw 3, 3 +; CHECK-LE-NEXT: blr +; CHECK-BE-LABEL: test9: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: mfvsrwz 3, 34 +; CHECK-BE-NEXT: extsw 3, 3 +; CHECK-BE-NEXT: blr +entry: + %vecext = extractelement <4 x i32> %a, i32 1 + ret i32 %vecext +} + +define signext i32 @testadd_9(<4 x i32> %a, i32 signext %c) { +; CHECK-LE-LABEL: testadd_9: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: li 3, 4 +; CHECK-LE-NEXT: vextuwrx 3, 3, 2 +; CHECK-LE-NEXT: add 3, 3, 5 +; CHECK-LE-NEXT: extsw 3, 3 +; CHECK-LE-NEXT: blr +; CHECK-BE-LABEL: testadd_9: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: mfvsrwz 3, 34 +; CHECK-BE-NEXT: add 3, 3, 5 +; CHECK-BE-NEXT: extsw 3, 3 +; CHECK-BE-NEXT: blr +entry: + %vecext = extractelement <4 x i32> %a, i32 1 + %add = add nsw i32 %vecext, %c + ret i32 %add +} diff --git a/test/CodeGen/PowerPC/vec_fneg.ll b/test/CodeGen/PowerPC/vec_fneg.ll index 2d7fb1ec07c30..904445abcaef2 100644 --- a/test/CodeGen/PowerPC/vec_fneg.ll +++ b/test/CodeGen/PowerPC/vec_fneg.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | FileCheck %s -check-prefix=CHECK-NOVSX -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64le \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | FileCheck %s -check-prefix=CHECK-NOVSX +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mattr=+altivec -mattr=+vsx | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64le \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s \ ; RUN: -check-prefix=CHECK-NOVSX diff --git a/test/CodeGen/PowerPC/vec_insert.ll b/test/CodeGen/PowerPC/vec_insert.ll index e09c1bae7a3f0..c7de289010dd9 100644 --- a/test/CodeGen/PowerPC/vec_insert.ll +++ b/test/CodeGen/PowerPC/vec_insert.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | grep sth +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | grep sth define <8 x i16> @insert(<8 x i16> %foo, i16 %a) nounwind { entry: diff --git a/test/CodeGen/PowerPC/vec_int_ext.ll b/test/CodeGen/PowerPC/vec_int_ext.ll index d7bed503318eb..1c86e38d06046 100644 --- a/test/CodeGen/PowerPC/vec_int_ext.ll +++ b/test/CodeGen/PowerPC/vec_int_ext.ll @@ -4,11 +4,11 @@ define <4 x i32> @vextsb2wLE(<16 x i8> %a) { ; CHECK-LE-LABEL: vextsb2wLE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsb2w 2, 2 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: vextsb2wLE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsb2w 2, 2 ; CHECK-BE-NEXT: blr @@ -31,11 +31,11 @@ entry: define <2 x i64> @vextsb2dLE(<16 x i8> %a) { ; CHECK-LE-LABEL: vextsb2dLE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsb2d 2, 2 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: vextsb2dLE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsb2d 2, 2 ; CHECK-BE-NEXT: blr @@ -52,11 +52,11 @@ entry: define <4 x i32> @vextsh2wLE(<8 x i16> %a) { ; CHECK-LE-LABEL: vextsh2wLE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsh2w 2, 2 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: vextsh2wLE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsh2w 2, 2 ; CHECK-BE-NEXT: blr @@ -79,11 +79,11 @@ entry: define <2 x i64> @vextsh2dLE(<8 x i16> %a) { ; CHECK-LE-LABEL: vextsh2dLE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsh2d 2, 2 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: vextsh2dLE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsh2d 2, 2 ; CHECK-BE-NEXT: blr @@ -100,11 +100,11 @@ entry: define <2 x i64> @vextsw2dLE(<4 x i32> %a) { ; CHECK-LE-LABEL: vextsw2dLE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsw2d 2, 2 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: vextsw2dLE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: vmrgew ; CHECK-BE-NEXT: vextsw2d 2, 2 ; CHECK-BE-NEXT: blr @@ -121,11 +121,11 @@ entry: define <4 x i32> @vextsb2wBE(<16 x i8> %a) { ; CHECK-BE-LABEL: vextsb2wBE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextsb2w 2, 2 ; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsb2wBE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 13 ; CHECK-LE-NEXT: vextsb2w 2, 2 ; CHECK-LE-NEXT: blr @@ -147,11 +147,11 @@ entry: define <2 x i64> @vextsb2dBE(<16 x i8> %a) { ; CHECK-BE-LABEL: vextsb2dBE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextsb2d 2, 2 ; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsb2dBE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 9 ; CHECK-LE-NEXT: vextsb2d 2, 2 ; CHECK-LE-NEXT: blr @@ -167,11 +167,11 @@ entry: define <4 x i32> @vextsh2wBE(<8 x i16> %a) { ; CHECK-BE-LABEL: vextsh2wBE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextsh2w 2, 2 ; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsh2wBE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 14 ; CHECK-LE-NEXT: vextsh2w 2, 2 ; CHECK-LE-NEXT: blr @@ -193,11 +193,11 @@ entry: define <2 x i64> @vextsh2dBE(<8 x i16> %a) { ; CHECK-BE-LABEL: vextsh2dBE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextsh2d 2, 2 ; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsh2dBE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 10 ; CHECK-LE-NEXT: vextsh2d 2, 2 ; CHECK-LE-NEXT: blr @@ -213,11 +213,11 @@ entry: define <2 x i64> @vextsw2dBE(<4 x i32> %a) { ; CHECK-BE-LABEL: vextsw2dBE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextsw2d 2, 2 ; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsw2dBE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 12 ; CHECK-LE-NEXT: vextsw2d 2, 2 ; CHECK-LE-NEXT: blr @@ -233,11 +233,11 @@ entry: define <2 x i64> @vextDiffVectors(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LE-LABEL: vextDiffVectors: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NOT: vextsw2d ; CHECK-BE-LABEL: vextDiffVectors: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NOT: vextsw2d entry: %vecext = extractelement <4 x i32> %a, i32 0 @@ -252,11 +252,11 @@ entry: define <8 x i16> @testInvalidExtend(<16 x i8> %a) { entry: ; CHECK-LE-LABEL: testInvalidExtend: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NOT: vexts ; CHECK-BE-LABEL: testInvalidExtend: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NOT: vexts %vecext = extractelement <16 x i8> %a, i32 0 diff --git a/test/CodeGen/PowerPC/vec_misaligned.ll b/test/CodeGen/PowerPC/vec_misaligned.ll index fb501a0635e7a..8af4da03c2548 100644 --- a/test/CodeGen/PowerPC/vec_misaligned.ll +++ b/test/CodeGen/PowerPC/vec_misaligned.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mcpu=g5 | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mattr=-power8-vector | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mattr=-power8-vector | FileCheck %s -check-prefix=CHECK-LE diff --git a/test/CodeGen/PowerPC/vec_mul.ll b/test/CodeGen/PowerPC/vec_mul.ll index 825ead61ccbea..b1714b21334d3 100644 --- a/test/CodeGen/PowerPC/vec_mul.ll +++ b/test/CodeGen/PowerPC/vec_mul.ll @@ -1,8 +1,8 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=-vsx -mattr=-power8-altivec | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx -mcpu=pwr8 -mattr=-power8-altivec | FileCheck %s -check-prefix=CHECK-LE -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-VSX -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx -mcpu=pwr8 -mattr=-power8-altivec | FileCheck %s -check-prefix=CHECK-LE-VSX +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mattr=-power8-altivec | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr8 -mattr=-power8-altivec | FileCheck %s -check-prefix=CHECK-LE +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-VSX +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -mcpu=pwr8 -mattr=-power8-altivec | FileCheck %s -check-prefix=CHECK-LE-VSX define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) { %tmp = load <4 x i32>, <4 x i32>* %X ; <<4 x i32>> [#uses=1] diff --git a/test/CodeGen/PowerPC/vec_perf_shuffle.ll b/test/CodeGen/PowerPC/vec_perf_shuffle.ll index 3ff901386fbe8..05877a03563c3 100644 --- a/test/CodeGen/PowerPC/vec_perf_shuffle.ll +++ b/test/CodeGen/PowerPC/vec_perf_shuffle.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | not grep vperm +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | not grep vperm define <4 x float> @test_uu72(<4 x float>* %P1, <4 x float>* %P2) { %V1 = load <4 x float>, <4 x float>* %P1 ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/PowerPC/vec_revb.ll b/test/CodeGen/PowerPC/vec_revb.ll index c09164bae13eb..00c08a1204fe2 100644 --- a/test/CodeGen/PowerPC/vec_revb.ll +++ b/test/CodeGen/PowerPC/vec_revb.ll @@ -3,7 +3,7 @@ define <8 x i16> @testXXBRH(<8 x i16> %a) { ; CHECK-LABEL: testXXBRH: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxbrh 34, 34 ; CHECK-NEXT: blr @@ -16,7 +16,7 @@ entry: define <4 x i32> @testXXBRW(<4 x i32> %a) { ; CHECK-LABEL: testXXBRW: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxbrw 34, 34 ; CHECK-NEXT: blr @@ -29,7 +29,7 @@ entry: define <2 x double> @testXXBRD(<2 x double> %a) { ; CHECK-LABEL: testXXBRD: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxbrd 34, 34 ; CHECK-NEXT: blr @@ -42,7 +42,7 @@ entry: define <1 x i128> @testXXBRQ(<1 x i128> %a) { ; CHECK-LABEL: testXXBRQ: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxbrq 34, 34 ; CHECK-NEXT: blr diff --git a/test/CodeGen/PowerPC/vec_shift.ll b/test/CodeGen/PowerPC/vec_shift.ll index b3e9418da4caf..6cdd0f4daf0e7 100644 --- a/test/CodeGen/PowerPC/vec_shift.ll +++ b/test/CodeGen/PowerPC/vec_shift.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 ; PR3628 define void @update(<4 x i32> %val, <4 x i32>* %dst) nounwind { diff --git a/test/CodeGen/PowerPC/vec_shuffle.ll b/test/CodeGen/PowerPC/vec_shuffle.ll index 41a884dfc8c62..9f055c3542b54 100644 --- a/test/CodeGen/PowerPC/vec_shuffle.ll +++ b/test/CodeGen/PowerPC/vec_shuffle.ll @@ -1,6 +1,6 @@ ; RUN: opt -mtriple=powerpc-apple-darwin < %s -instcombine | \ -; RUN: llc -march=ppc32 -mcpu=g5 | not grep vperm -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 > %t +; RUN: llc -mtriple=ppc32-- -mcpu=g5 | not grep vperm +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 > %t ; RUN: grep vsldoi %t | count 2 ; RUN: grep vmrgh %t | count 7 ; RUN: grep vmrgl %t | count 6 diff --git a/test/CodeGen/PowerPC/vec_splat.ll b/test/CodeGen/PowerPC/vec_splat.ll index 986852d7c3584..7829f6fbede34 100644 --- a/test/CodeGen/PowerPC/vec_splat.ll +++ b/test/CodeGen/PowerPC/vec_splat.ll @@ -1,7 +1,7 @@ ; Test that vectors are scalarized/lowered correctly. -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g3 | \ +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g3 | \ ; RUN: grep stfs | count 4 -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 -o %t +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 -o %t ; RUN: grep vspltw %t | count 2 ; RUN: grep vsplti %t | count 3 ; RUN: grep vsplth %t | count 1 diff --git a/test/CodeGen/PowerPC/vec_splat_constant.ll b/test/CodeGen/PowerPC/vec_splat_constant.ll index 69d251564362d..1751d04b2b937 100644 --- a/test/CodeGen/PowerPC/vec_splat_constant.ll +++ b/test/CodeGen/PowerPC/vec_splat_constant.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s ; Formerly incorrectly inserted vsldoi (endian confusion) @baz = common global <16 x i8> zeroinitializer ; <<16 x i8>*> [#uses=1] diff --git a/test/CodeGen/PowerPC/vec_vrsave.ll b/test/CodeGen/PowerPC/vec_vrsave.ll index e54ee32c23880..4d48c332fb100 100644 --- a/test/CodeGen/PowerPC/vec_vrsave.ll +++ b/test/CodeGen/PowerPC/vec_vrsave.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 -o %t +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 -o %t ; RUN: grep vrlw %t ; RUN: not grep spr %t ; RUN: not grep vrsave %t diff --git a/test/CodeGen/PowerPC/vec_zero.ll b/test/CodeGen/PowerPC/vec_zero.ll index 81bb320299d47..fe198bc8a5563 100644 --- a/test/CodeGen/PowerPC/vec_zero.ll +++ b/test/CodeGen/PowerPC/vec_zero.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | grep vxor +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | grep vxor define void @foo(<4 x float>* %P) { %T = load <4 x float>, <4 x float>* %P ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/PowerPC/vector-identity-shuffle.ll b/test/CodeGen/PowerPC/vector-identity-shuffle.ll index 075f2eea17aaf..7af4b827e7d03 100644 --- a/test/CodeGen/PowerPC/vector-identity-shuffle.ll +++ b/test/CodeGen/PowerPC/vector-identity-shuffle.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | grep test: -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 | not grep vperm +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | grep test: +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | not grep vperm define void @test(<4 x float>* %tmp2.i) { %tmp2.i.upgrd.1 = load <4 x float>, <4 x float>* %tmp2.i ; <<4 x float>> [#uses=4] diff --git a/test/CodeGen/PowerPC/vector-merge-store-fp-constants.ll b/test/CodeGen/PowerPC/vector-merge-store-fp-constants.ll index 004df6c4f3a6f..489e67f7ef2bb 100644 --- a/test/CodeGen/PowerPC/vector-merge-store-fp-constants.ll +++ b/test/CodeGen/PowerPC/vector-merge-store-fp-constants.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -march=ppc64 -mtriple=ppc64-apple-darwin < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=ppc64-apple-darwin < %s | FileCheck %s ; CHECK-LABEL: {{^}}_merge_8_float_zero_stores: ; CHECK: li [[ZEROREG:r[0-9]+]], 0 diff --git a/test/CodeGen/PowerPC/vector.ll b/test/CodeGen/PowerPC/vector.ll index 1f97d39816d76..8b1f98065a57c 100644 --- a/test/CodeGen/PowerPC/vector.ll +++ b/test/CodeGen/PowerPC/vector.ll @@ -1,6 +1,6 @@ ; Test that vectors are scalarized/lowered correctly. -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g5 > %t -; RUN: llc -verify-machineinstrs < %s -march=ppc32 -mcpu=g3 >> %t +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 > %t +; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g3 >> %t %d8 = type <8 x double> %f1 = type <1 x float> diff --git a/test/CodeGen/PowerPC/vselect-constants.ll b/test/CodeGen/PowerPC/vselect-constants.ll new file mode 100644 index 0000000000000..5f23c3e40de6f --- /dev/null +++ b/test/CodeGen/PowerPC/vselect-constants.ll @@ -0,0 +1,196 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s + +; First, check the generic pattern for any 2 vector constants. Then, check special cases where +; the constants are all off-by-one. Finally, check the extra special cases where the constants +; include 0 or -1. +; Each minimal select test is repeated with a more typical pattern that includes a compare to +; generate the condition value. + +define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) { +; CHECK-LABEL: sel_C1_or_C2_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: vspltisw 3, -16 +; CHECK-NEXT: vspltisw 4, 15 +; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha +; CHECK-NEXT: addis 4, 2, .LCPI0_1@toc@ha +; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l +; CHECK-NEXT: addi 4, 4, .LCPI0_1@toc@l +; CHECK-NEXT: lvx 18, 0, 3 +; CHECK-NEXT: lvx 19, 0, 4 +; CHECK-NEXT: vsubuwm 3, 4, 3 +; CHECK-NEXT: vslw 2, 2, 3 +; CHECK-NEXT: vsraw 2, 2, 3 +; CHECK-NEXT: xxsel 34, 51, 50, 34 +; CHECK-NEXT: blr + %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1> + ret <4 x i32> %add +} + +define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: cmp_sel_C1_or_C2_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: vcmpequw 2, 2, 3 +; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha +; CHECK-NEXT: addis 4, 2, .LCPI1_1@toc@ha +; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l +; CHECK-NEXT: addi 4, 4, .LCPI1_1@toc@l +; CHECK-NEXT: lvx 19, 0, 3 +; CHECK-NEXT: lvx 4, 0, 4 +; CHECK-NEXT: xxsel 34, 36, 51, 34 +; CHECK-NEXT: blr + %cond = icmp eq <4 x i32> %x, %y + %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1> + ret <4 x i32> %add +} + +define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) { +; CHECK-LABEL: sel_Cplus1_or_C_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: vspltisw 3, 1 +; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha +; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l +; CHECK-NEXT: lvx 19, 0, 3 +; CHECK-NEXT: xxland 34, 34, 35 +; CHECK-NEXT: vadduwm 2, 2, 19 +; CHECK-NEXT: blr + %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1> + ret <4 x i32> %add +} + +define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: vcmpequw 2, 2, 3 +; CHECK-NEXT: addis 3, 2, .LCPI3_0@toc@ha +; CHECK-NEXT: addi 3, 3, .LCPI3_0@toc@l +; CHECK-NEXT: lvx 19, 0, 3 +; CHECK-NEXT: vsubuwm 2, 19, 2 +; CHECK-NEXT: blr + %cond = icmp eq <4 x i32> %x, %y + %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1> + ret <4 x i32> %add +} + +define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) { +; CHECK-LABEL: sel_Cminus1_or_C_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: vspltisw 3, -16 +; CHECK-NEXT: vspltisw 4, 15 +; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha +; CHECK-NEXT: addi 3, 3, .LCPI4_0@toc@l +; CHECK-NEXT: lvx 19, 0, 3 +; CHECK-NEXT: vsubuwm 3, 4, 3 +; CHECK-NEXT: vslw 2, 2, 3 +; CHECK-NEXT: vsraw 2, 2, 3 +; CHECK-NEXT: vadduwm 2, 2, 19 +; CHECK-NEXT: blr + %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1> + ret <4 x i32> %add +} + +define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: vcmpequw 2, 2, 3 +; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha +; CHECK-NEXT: addi 3, 3, .LCPI5_0@toc@l +; CHECK-NEXT: lvx 19, 0, 3 +; CHECK-NEXT: vadduwm 2, 2, 19 +; CHECK-NEXT: blr + %cond = icmp eq <4 x i32> %x, %y + %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1> + ret <4 x i32> %add +} + +define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) { +; CHECK-LABEL: sel_minus1_or_0_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: vspltisw 3, -16 +; CHECK-NEXT: vspltisw 4, 15 +; CHECK-NEXT: vsubuwm 3, 4, 3 +; CHECK-NEXT: vslw 2, 2, 3 +; CHECK-NEXT: vsraw 2, 2, 3 +; CHECK-NEXT: blr + %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0> + ret <4 x i32> %add +} + +define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: cmp_sel_minus1_or_0_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: vcmpequw 2, 2, 3 +; CHECK-NEXT: blr + %cond = icmp eq <4 x i32> %x, %y + %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0> + ret <4 x i32> %add +} + +define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) { +; CHECK-LABEL: sel_0_or_minus1_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: vspltisw 3, 1 +; CHECK-NEXT: vspltisb 4, -1 +; CHECK-NEXT: xxland 34, 34, 35 +; CHECK-NEXT: vadduwm 2, 2, 4 +; CHECK-NEXT: blr + %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> + ret <4 x i32> %add +} + +define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: cmp_sel_0_or_minus1_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: vcmpequw 2, 2, 3 +; CHECK-NEXT: xxlnor 34, 34, 34 +; CHECK-NEXT: blr + %cond = icmp eq <4 x i32> %x, %y + %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> + ret <4 x i32> %add +} + +define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) { +; CHECK-LABEL: sel_1_or_0_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: vspltisw 3, 1 +; CHECK-NEXT: xxland 34, 34, 35 +; CHECK-NEXT: blr + %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0> + ret <4 x i32> %add +} + +define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: cmp_sel_1_or_0_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: vcmpequw 2, 2, 3 +; CHECK-NEXT: vspltisw 19, 1 +; CHECK-NEXT: xxland 34, 34, 51 +; CHECK-NEXT: blr + %cond = icmp eq <4 x i32> %x, %y + %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0> + ret <4 x i32> %add +} + +define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) { +; CHECK-LABEL: sel_0_or_1_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: vspltisw 3, 1 +; CHECK-NEXT: xxlandc 34, 35, 34 +; CHECK-NEXT: blr + %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1> + ret <4 x i32> %add +} + +define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: cmp_sel_0_or_1_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: vcmpequw 2, 2, 3 +; CHECK-NEXT: vspltisw 19, 1 +; CHECK-NEXT: xxlnor 0, 34, 34 +; CHECK-NEXT: xxland 34, 0, 51 +; CHECK-NEXT: blr + %cond = icmp eq <4 x i32> %x, %y + %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1> + ret <4 x i32> %add +} + diff --git a/test/CodeGen/PowerPC/vsx-spill.ll b/test/CodeGen/PowerPC/vsx-spill.ll index 93ad98556267e..1b612b0d7f67d 100644 --- a/test/CodeGen/PowerPC/vsx-spill.ll +++ b/test/CodeGen/PowerPC/vsx-spill.ll @@ -23,8 +23,11 @@ entry: ; CHECK-REG: blr ; CHECK-FISL: @foo1 -; CHECK-FISL: lis 3, -1 -; CHECK-FISL: ori 3, 3, 65384 +; CHECK-FISL-NOT: lis +; CHECK-FISL-NOT: ori +; CHECK-FISL: li 3, -152 +; CHECK-FISL-NOT: lis +; CHECK-FISL-NOT: ori ; CHECK-FISL: stxsdx 1, 1, 3 ; CHECK-FISL: blr diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll index 26b59926c7f17..56b3261090c37 100644 --- a/test/CodeGen/PowerPC/vsx.ll +++ b/test/CodeGen/PowerPC/vsx.ll @@ -235,8 +235,11 @@ entry: ; CHECK-FISL-LABEL: @test14 ; CHECK-FISL: xxlor 0, 34, 35 ; CHECK-FISL: xxlnor 34, 34, 35 -; CHECK-FISL: lis 3, -1 -; CHECK-FISL: ori 3, 3, 65520 +; CHECK-FISL-NOT: lis +; CHECK-FISL-NOT: ori +; CHECK-FISL: li 3, -16 +; CHECK-FISL-NOT: lis +; CHECK-FISL-NOT: ori ; CHECK-FISL: stxvd2x 0, 1, 3 ; CHECK-FISL: blr @@ -260,8 +263,11 @@ entry: ; CHECK-FISL: xxlor 36, 0, 0 ; CHECK-FISL: xxlnor 0, 34, 35 ; CHECK-FISL: xxlor 34, 0, 0 -; CHECK-FISL: lis 3, -1 -; CHECK-FISL: ori 3, 3, 65520 +; CHECK-FISL-NOT: lis +; CHECK-FISL-NOT: ori +; CHECK-FISL: li 3, -16 +; CHECK-FISL-NOT: lis +; CHECK-FISL-NOT: ori ; CHECK-FISL: stxvd2x 36, 1, 3 ; CHECK-FISL: blr @@ -285,8 +291,11 @@ entry: ; CHECK-FISL: xxlor 36, 0, 0 ; CHECK-FISL: xxlnor 0, 34, 35 ; CHECK-FISL: xxlor 34, 0, 0 -; CHECK-FISL: lis 3, -1 -; CHECK-FISL: ori 3, 3, 65520 +; CHECK-FISL-NOT: lis +; CHECK-FISL-NOT: ori +; CHECK-FISL: li 3, -16 +; CHECK-FISL-NOT: lis +; CHECK-FISL-NOT: ori ; CHECK-FISL: stxvd2x 36, 1, 3 ; CHECK-FISL: blr @@ -330,8 +339,11 @@ entry: ; CHECK-FISL: xxlor 36, 0, 0 ; CHECK-FISL: xxlandc 0, 34, 35 ; CHECK-FISL: xxlor 34, 0, 0 -; CHECK-FISL: lis 3, -1 -; CHECK-FISL: ori 3, 3, 65520 +; CHECK-FISL-NOT: lis +; CHECK-FISL-NOT: ori +; CHECK-FISL: li 3, -16 +; CHECK-FISL-NOT: lis +; CHECK-FISL-NOT: ori ; CHECK-FISL: stxvd2x 36, 1, 3 ; CHECK-FISL: blr @@ -355,8 +367,11 @@ entry: ; CHECK-FISL: xxlor 36, 0, 0 ; CHECK-FISL: xxlandc 0, 34, 35 ; CHECK-FISL: xxlor 34, 0, 0 -; CHECK-FISL: lis 3, -1 -; CHECK-FISL: ori 3, 3, 65520 +; CHECK-FISL-NOT: lis +; CHECK-FISL-NOT: ori +; CHECK-FISL: li 3, -16 +; CHECK-FISL-NOT: lis +; CHECK-FISL-NOT: ori ; CHECK-FISL: stxvd2x 36, 1, 3 ; CHECK-FISL: blr diff --git a/test/CodeGen/PowerPC/vsxD-Form-spills.ll b/test/CodeGen/PowerPC/vsxD-Form-spills.ll new file mode 100644 index 0000000000000..92427f5ccdeae --- /dev/null +++ b/test/CodeGen/PowerPC/vsxD-Form-spills.ll @@ -0,0 +1,65 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-PWR9 %s + +define <4 x i32> @testSpill(<4 x i32> %a, <4 x i32> %b) { + +; CHECK-LABEL: testSpill: +; CHECK: li 11, 80 +; CHECK: li 12, 96 +; CHECK: li 3, 48 +; CHECK: li 10, 64 +; CHECK: stxvd2x 62, 1, 11 # 16-byte Folded Spill +; CHECK: stxvd2x 63, 1, 12 # 16-byte Folded Spill +; CHECK: stxvd2x 60, 1, 3 # 16-byte Folded Spill +; CHECK: stxvd2x 61, 1, 10 # 16-byte Folded Spill +; CHECK: li 9, 96 +; CHECK: li 10, 80 +; CHECK: li 11, 64 +; CHECK: li 12, 48 +; CHECK: lxvd2x 63, 1, 9 # 16-byte Folded Reload +; CHECK: lxvd2x 62, 1, 10 # 16-byte Folded Reload +; CHECK: lxvd2x 61, 1, 11 # 16-byte Folded Reload +; CHECK: lxvd2x 60, 1, 12 # 16-byte Folded Reload +; CHECK: mtlr 0 +; CHECK-NEXT: blr +; +; CHECK-PWR9-LABEL: testSpill: +; CHECK-PWR9: stxv 62, 80(1) # 16-byte Folded Spill +; CHECK-PWR9: stxv 63, 96(1) # 16-byte Folded Spill +; CHECK-PWR9: stxv 60, 48(1) # 16-byte Folded Spill +; CHECK-PWR9: stxv 61, 64(1) # 16-byte Folded Spill +; CHECK-PWR9: lxv 63, 96(1) # 16-byte Folded Reload +; CHECK-PWR9: lxv 62, 80(1) # 16-byte Folded Reload +; CHECK-PWR9: lxv 61, 64(1) # 16-byte Folded Reload +; CHECK-PWR9: lxv 60, 48(1) # 16-byte Folded Reload +; CHECK-PWR9: mtlr 0 +; CHECK-PWR9-NEXT: blr + +entry: + %0 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %a, <4 x i32> %b) + %tobool = icmp eq i32 %0, 0 + br i1 %tobool, label %if.else, label %if.then + +if.then: ; preds = %entry + %call = tail call <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b) + br label %if.end + +if.else: ; preds = %entry + %call1 = tail call <4 x i32> @test2(<4 x i32> %b, <4 x i32> %a) + br label %if.end + +if.end: ; preds = %if.else, %if.then + %c.0.in = phi <4 x i32> [ %call, %if.then ], [ %call1, %if.else ] + %call3 = tail call <4 x i32> @test1(<4 x i32> %b, <4 x i32> %a) + %call5 = tail call <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b) + %add4 = add <4 x i32> %a, <i32 0, i32 0, i32 2, i32 2> + %add6 = add <4 x i32> %add4, %c.0.in + %c.0 = add <4 x i32> %add6, %call3 + %add7 = add <4 x i32> %c.0, %call5 + ret <4 x i32> %add7 +} + +; Function Attrs: nounwind readnone +declare i32 @llvm.ppc.altivec.vcmpgtsw.p(i32, <4 x i32>, <4 x i32>) +declare <4 x i32> @test1(<4 x i32>, <4 x i32>) +declare <4 x i32> @test2(<4 x i32>, <4 x i32>) diff --git a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll index 98fe3a813cb7d..0a4db39977aa2 100644 --- a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll +++ b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll @@ -17,8 +17,8 @@ define <2 x double> @testi0(<2 x double>* %p1, double* %p2) { ; CHECK-LABEL: testi0 ; CHECK: lxvd2x 0, 0, 3 ; CHECK: lxsdx 1, 0, 4 -; CHECK: xxswapd 0, 0 -; CHECK: xxspltd 1, 1, 0 +; CHECK-DAG: xxspltd 1, 1, 0 +; CHECK-DAG: xxswapd 0, 0 ; CHECK: xxpermdi 34, 0, 1, 1 ; CHECK-P9-LABEL: testi0 @@ -37,8 +37,8 @@ define <2 x double> @testi1(<2 x double>* %p1, double* %p2) { ; CHECK-LABEL: testi1 ; CHECK: lxvd2x 0, 0, 3 ; CHECK: lxsdx 1, 0, 4 -; CHECK: xxswapd 0, 0 -; CHECK: xxspltd 1, 1, 0 +; CHECK-DAG: xxspltd 1, 1, 0 +; CHECK-DAG: xxswapd 0, 0 ; CHECK: xxmrgld 34, 1, 0 ; CHECK-P9-LABEL: testi1 diff --git a/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll b/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll index 7da2ea27c18ef..d8ea0dc992f22 100644 --- a/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll +++ b/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll @@ -20,7 +20,7 @@ entry: ret void ; CHECK-LABEL: @dblToInt ; CHECK: xscvdpsxws [[REGCONV1:[0-9]+]], -; CHECK: stxsiwx [[REGCONV1]], +; CHECK: stfiwx [[REGCONV1]], } ; Function Attrs: nounwind @@ -33,7 +33,7 @@ entry: ret void ; CHECK-LABEL: @fltToInt ; CHECK: xscvdpsxws [[REGCONV2:[0-9]+]], -; CHECK: stxsiwx [[REGCONV2]], +; CHECK: stfiwx [[REGCONV2]], } ; Function Attrs: nounwind @@ -45,7 +45,7 @@ entry: store volatile double %conv, double* %dd, align 8 ret void ; CHECK-LABEL: @intToDbl -; CHECK: lxsiwax [[REGLD1:[0-9]+]], +; CHECK: lfiwax [[REGLD1:[0-9]+]], ; CHECK: xscvsxddp {{[0-9]+}}, [[REGLD1]] } @@ -58,7 +58,7 @@ entry: store volatile float %conv, float* %ff, align 4 ret void ; CHECK-LABEL: @intToFlt -; CHECK: lxsiwax [[REGLD2:[0-9]+]], +; CHECK: lfiwax [[REGLD2:[0-9]+]], ; CHECK: xscvsxdsp {{[0-9]}}, [[REGLD2]] } @@ -72,7 +72,7 @@ entry: ret void ; CHECK-LABEL: @dblToUInt ; CHECK: xscvdpuxws [[REGCONV3:[0-9]+]], -; CHECK: stxsiwx [[REGCONV3]], +; CHECK: stfiwx [[REGCONV3]], } ; Function Attrs: nounwind @@ -85,7 +85,7 @@ entry: ret void ; CHECK-LABEL: @fltToUInt ; CHECK: xscvdpuxws [[REGCONV4:[0-9]+]], -; CHECK: stxsiwx [[REGCONV4]], +; CHECK: stfiwx [[REGCONV4]], } ; Function Attrs: nounwind @@ -97,7 +97,7 @@ entry: store volatile double %conv, double* %dd, align 8 ret void ; CHECK-LABEL: @uIntToDbl -; CHECK: lxsiwzx [[REGLD3:[0-9]+]], +; CHECK: lfiwzx [[REGLD3:[0-9]+]], ; CHECK: xscvuxddp {{[0-9]+}}, [[REGLD3]] } @@ -110,7 +110,7 @@ entry: store volatile float %conv, float* %ff, align 4 ret void ; CHECK-LABEL: @uIntToFlt -; CHECK: lxsiwzx [[REGLD4:[0-9]+]], +; CHECK: lfiwzx [[REGLD4:[0-9]+]], ; CHECK: xscvuxdsp {{[0-9]+}}, [[REGLD4]] } @@ -124,7 +124,7 @@ entry: ret void ; CHECK-LABEL: @dblToFloat ; CHECK: lxsdx [[REGLD5:[0-9]+]], -; CHECK: stxsspx [[REGLD5]], +; CHECK: stfsx [[REGLD5]], ; CHECK-P9-LABEL: @dblToFloat ; CHECK-P9: lfd [[REGLD5:[0-9]+]], ; CHECK-P9: stfs [[REGLD5]], @@ -139,7 +139,7 @@ entry: store volatile double %conv, double* %dd, align 8 ret void ; CHECK-LABEL: @floatToDbl -; CHECK: lxsspx [[REGLD5:[0-9]+]], +; CHECK: lfsx [[REGLD5:[0-9]+]], ; CHECK: stxsdx [[REGLD5]], ; CHECK-P9-LABEL: @floatToDbl ; CHECK-P9: lfs [[REGLD5:[0-9]+]], diff --git a/test/CodeGen/PowerPC/xray-attribute-instrumentation.ll b/test/CodeGen/PowerPC/xray-attribute-instrumentation.ll new file mode 100644 index 0000000000000..875c1775216bc --- /dev/null +++ b/test/CodeGen/PowerPC/xray-attribute-instrumentation.ll @@ -0,0 +1,44 @@ +; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -relocation-model=pic < %s | FileCheck %s + +define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always" { +; CHECK-LABEL: .Ltmp0: +; CHECK: b .Ltmp1 +; CHECK-NEXT: nop +; CHECK-NEXT: std 0, -8(1) +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: bl __xray_FunctionEntry +; CHECK-NEXT: nop +; CHECK-NEXT: mtlr 0 +; CHECK-LABEL: .Ltmp1: + ret i32 0 +; CHECK-LABEL: .Ltmp2: +; CHECK: blr +; CHECK-NEXT: nop +; CHECK-NEXT: std 0, -8(1) +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: bl __xray_FunctionExit +; CHECK-NEXT: nop +; CHECK-NEXT: mtlr 0 +} +; CHECK-LABEL: xray_instr_map,"awo",@progbits,foo,unique,1 +; CHECK: .Lxray_sleds_start0: +; CHECK-NEXT: .quad .Ltmp0 +; CHECK-NEXT: .quad foo +; CHECK-NEXT: .byte 0x00 +; CHECK-NEXT: .byte 0x01 +; CHECK-NEXT: .byte 0x00 +; CHECK-NEXT: .space 13 +; CHECK-NEXT: .quad .Ltmp2 +; CHECK-NEXT: .quad foo +; CHECK-NEXT: .byte 0x01 +; CHECK-NEXT: .byte 0x01 +; CHECK-NEXT: .byte 0x00 +; CHECK-NEXT: .space 13 +; CHECK-NEXT: .Lxray_sleds_end0: +; CHECK-LABEL: xray_fn_idx,"awo",@progbits,foo,unique,1 +; CHECK: .p2align 4 +; CHECK-NEXT: .quad .Lxray_sleds_start0 +; CHECK-NEXT: .quad .Lxray_sleds_end0 +; CHECK-NEXT: .text diff --git a/test/CodeGen/PowerPC/xray-conditional-return.ll b/test/CodeGen/PowerPC/xray-conditional-return.ll new file mode 100644 index 0000000000000..4454d3dc62af7 --- /dev/null +++ b/test/CodeGen/PowerPC/xray-conditional-return.ll @@ -0,0 +1,79 @@ +; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +define void @Foo(i32 signext %a, i32 signext %b) #0 { +; CHECK-LABEL: @Foo +; CHECK: cmpw [[CR:[0-9]+]] +; CHECK-NEXT: ble [[CR]], [[LABEL:\.[a-zA-Z0-9]+]] +; CHECK-NEXT: .p2align 3 +; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}: +; CHECK-NEXT: blr +; CHECK-NEXT: nop +; CHECK-NEXT: std 0 +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: bl __xray_FunctionExit +; CHECK-NEXT: nop +; CHECK-NEXT: mtlr 0 +; CHECK-NEXT: blr +; CHECK-NEXT: [[LABEL]]: +entry: + %cmp = icmp sgt i32 %a, %b + br i1 %cmp, label %return, label %if.end + +; CHECK: .p2align 3 +; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}: +; CHECK-NEXT: blr +; CHECK-NEXT: nop +; CHECK-NEXT: std 0 +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: bl __xray_FunctionExit +; CHECK-NEXT: nop +; CHECK-NEXT: mtlr 0 +; CHECK-NEXT: blr +if.end: + tail call void @Bar() + br label %return + +return: + ret void +} + +define void @Foo2(i32 signext %a, i32 signext %b) #0 { +; CHECK-LABEL: @Foo2 +; CHECK: cmpw [[CR:[0-9]+]] +; CHECK-NEXT: bge [[CR]], [[LABEL:\.[a-zA-Z0-9]+]] +; CHECK-NEXT: .p2align 3 +; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}: +; CHECK-NEXT: blr +; CHECK-NEXT: nop +; CHECK-NEXT: std 0 +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: bl __xray_FunctionExit +; CHECK-NEXT: nop +; CHECK-NEXT: mtlr 0 +; CHECK-NEXT: blr +; CHECK-NEXT: [[LABEL]]: +entry: + %cmp = icmp slt i32 %a, %b + br i1 %cmp, label %return, label %if.end + +; CHECK: .p2align 3 +; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}: +; CHECK-NEXT: blr +; CHECK-NEXT: nop +; CHECK-NEXT: std 0 +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: bl __xray_FunctionExit +; CHECK-NEXT: nop +; CHECK-NEXT: mtlr 0 +; CHECK-NEXT: blr +if.end: + tail call void @Bar() + br label %return + +return: + ret void +} + +declare void @Bar() + +attributes #0 = { "function-instrument"="xray-always" } diff --git a/test/CodeGen/PowerPC/xray-ret-is-terminator.ll b/test/CodeGen/PowerPC/xray-ret-is-terminator.ll new file mode 100644 index 0000000000000..7e63530912aa2 --- /dev/null +++ b/test/CodeGen/PowerPC/xray-ret-is-terminator.ll @@ -0,0 +1,32 @@ +; RUN: llc -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +define void @ILLBeBack() #0 { +; CHECK-LABEL @ILLBeBack +; CHECK: beq {{[0-9]+}}, [[LABEL:\.[a-zA-Z0-9_]+]] +; CHECK: bl __xray_FunctionExit +; CHECK: [[LABEL]]: +bb: + br i1 undef, label %bb1, label %bb8 + +bb1: + %tmp = tail call i64 asm sideeffect "", "=&r,=*m,b,r,*m,~{cc}"(i64* nonnull undef, i64* nonnull undef, i64 1, i64* nonnull undef) + %tmp2 = icmp eq i64 %tmp, 0 + br i1 %tmp2, label %bb3, label %bb8 + +bb3: + %tmp4 = tail call i64 asm sideeffect "", "=&r,=*m,b,r,r,*m,~{cc}"(i64* undef, i64* undef, i64 0, i64 undef, i64* undef) + %tmp5 = icmp eq i64 0, %tmp4 + br i1 %tmp5, label %bb6, label %bb3 + +bb6: + br i1 undef, label %bb7, label %bb8 + +bb7: + tail call void () undef() + ret void + +bb8: + ret void +} + +attributes #0 = { "function-instrument"="xray-always" } diff --git a/test/CodeGen/PowerPC/xray-tail-call-hidden.ll b/test/CodeGen/PowerPC/xray-tail-call-hidden.ll new file mode 100644 index 0000000000000..3b1cd5f5870d1 --- /dev/null +++ b/test/CodeGen/PowerPC/xray-tail-call-hidden.ll @@ -0,0 +1,26 @@ +; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +declare hidden i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" + +define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" { +; CHECK-LABEL: .Ltmp0: +; CHECK: b .Ltmp1 +; CHECK-NEXT: nop +; CHECK-NEXT: std 0, -8(1) +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: bl __xray_FunctionEntry +; CHECK-NEXT: nop +; CHECK-NEXT: mtlr 0 +; CHECK-LABEL: .Ltmp1: + %retval = tail call i32 @callee() + ret i32 %retval +; CHECK-LABEL: .Ltmp2: +; CHECK: b callee +; CHECK-NEXT: nop +; CHECK-NEXT: std 0, -8(1) +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: bl __xray_FunctionExit +; CHECK-NEXT: nop +; CHECK-NEXT: mtlr 0 +} + diff --git a/test/CodeGen/PowerPC/xray-tail-call-sled.ll b/test/CodeGen/PowerPC/xray-tail-call-sled.ll new file mode 100644 index 0000000000000..e8fe9dbaa45f6 --- /dev/null +++ b/test/CodeGen/PowerPC/xray-tail-call-sled.ll @@ -0,0 +1,44 @@ +; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" { +; CHECK-LABEL: .Ltmp0: +; CHECK: b .Ltmp1 +; CHECK-NEXT: nop +; CHECK-NEXT: std 0, -8(1) +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: bl __xray_FunctionEntry +; CHECK-NEXT: nop +; CHECK-NEXT: mtlr 0 +; CHECK-LABEL: .Ltmp1: + ret i32 0 +; CHECK-LABEL: .Ltmp2: +; CHECK: blr +; CHECK-NEXT: nop +; CHECK-NEXT: std 0, -8(1) +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: bl __xray_FunctionExit +; CHECK-NEXT: nop +; CHECK-NEXT: mtlr 0 +} + +define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" { +; CHECK-LABEL: .Ltmp3: +; CHECK: b .Ltmp4 +; CHECK-NEXT: nop +; CHECK-NEXT: std 0, -8(1) +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: bl __xray_FunctionEntry +; CHECK-NEXT: nop +; CHECK-NEXT: mtlr 0 +; CHECK-LABEL: .Ltmp4: + %retval = tail call i32 @callee() + ret i32 %retval +; CHECK-LABEL: .Ltmp5: +; CHECK: blr +; CHECK-NEXT: nop +; CHECK-NEXT: std 0, -8(1) +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: bl __xray_FunctionExit +; CHECK-NEXT: nop +; CHECK-NEXT: mtlr 0 +} diff --git a/test/CodeGen/PowerPC/zext-and-cmp.ll b/test/CodeGen/PowerPC/zext-and-cmp.ll new file mode 100644 index 0000000000000..b06a384d73b30 --- /dev/null +++ b/test/CodeGen/PowerPC/zext-and-cmp.ll @@ -0,0 +1,33 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +; Test that we recognize that an 'and' instruction that feeds a comparison +; to zero can be simplifed by using the record form when one of its operands +; is known to be zero extended. + +@k = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind +define signext i32 @cmplwi(i32* nocapture readonly %p, i32* nocapture readonly %q, i32 signext %j, i32 signext %r10) { +entry: + %0 = load i32, i32* %q, align 4 + %shl = shl i32 %0, %j + %1 = load i32, i32* %p, align 4 + %and = and i32 %shl, %r10 + %and1 = and i32 %and, %1 + %tobool = icmp eq i32 %and1, 0 + br i1 %tobool, label %cleanup, label %if.then + +if.then: + store i32 %j, i32* @k, align 4 + br label %cleanup + +cleanup: + %retval.0 = phi i32 [ 0, %if.then ], [ 1, %entry ] + ret i32 %retval.0 +} + +; CHECK-LABEL: cmplwi: +; CHECK: lwz [[T1:[0-9]+]], 0(3) +; CHECK: and. {{[0-9]+}}, {{[0-9]+}}, [[T1]] +; CHECK-NOT: cmplwi +; CHECK-NEXT: beq 0, diff --git a/test/CodeGen/PowerPC/zext-bitperm.ll b/test/CodeGen/PowerPC/zext-bitperm.ll new file mode 100644 index 0000000000000..b6d751d6f2fdf --- /dev/null +++ b/test/CodeGen/PowerPC/zext-bitperm.ll @@ -0,0 +1,23 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s + +; Test case for PPCTargetLowering::extendSubTreeForBitPermutation. +; We expect mask and rotate are folded into a rlwinm instruction. + +define zeroext i32 @func(i32* %p, i32 zeroext %i) { +; CHECK-LABEL: @func +; CHECK: addi [[REG1:[0-9]+]], 4, 1 +; CHECK: rlwinm [[REG2:[0-9]+]], [[REG1]], 2, 22, 29 +; CHECK-NOT: sldi +; CHECK: lwzx 3, 3, [[REG2]] +; CHECK: blr +entry: + %add = add i32 %i, 1 + %and = and i32 %add, 255 + %idxprom = zext i32 %and to i64 + %arrayidx = getelementptr inbounds i32, i32* %p, i64 %idxprom + %0 = load i32, i32* %arrayidx, align 4 + ret i32 %0 +} + |