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Diffstat (limited to 'contrib/binutils/gas/doc/c-arm.texi')
| -rw-r--r-- | contrib/binutils/gas/doc/c-arm.texi | 170 |
1 files changed, 157 insertions, 13 deletions
diff --git a/contrib/binutils/gas/doc/c-arm.texi b/contrib/binutils/gas/doc/c-arm.texi index 23cd7bb3fef61..ca0998bea669c 100644 --- a/contrib/binutils/gas/doc/c-arm.texi +++ b/contrib/binutils/gas/doc/c-arm.texi @@ -1,4 +1,4 @@ -@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003 +@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 @c Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @@ -67,6 +67,7 @@ recognized: @code{arm7500fe}, @code{arm7t}, @code{arm7tdmi}, +@code{arm7tdmi-s}, @code{arm8}, @code{arm810}, @code{strongarm}, @@ -82,19 +83,33 @@ recognized: @code{arm9tdmi}, @code{arm9e}, @code{arm926e}, -@code{arm926ejs}, +@code{arm926ej-s}, @code{arm946e-r0}, @code{arm946e}, +@code{arm946e-s}, @code{arm966e-r0}, @code{arm966e}, +@code{arm966e-s}, +@code{arm968e-s}, @code{arm10t}, +@code{arm10tdmi}, @code{arm10e}, @code{arm1020}, @code{arm1020t}, @code{arm1020e}, -@code{arm1026ejs}, -@code{arm1136js}, -@code{arm1136jfs}, +@code{arm1022e}, +@code{arm1026ej-s}, +@code{arm1136j-s}, +@code{arm1136jf-s}, +@code{arm1156t2-s}, +@code{arm1156t2f-s}, +@code{arm1176jz-s}, +@code{arm1176jzf-s}, +@code{mpcore}, +@code{mpcorenovfp}, +@code{cortex-a8}, +@code{cortex-r4}, +@code{cortex-m3}, @code{ep9312} (ARM920 with Cirrus Maverick coprocessor), @code{i80200} (Intel XScale processor) @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) @@ -136,6 +151,13 @@ names are recognized: @code{armv5texp}, @code{armv6}, @code{armv6j}, +@code{armv6k}, +@code{armv6z}, +@code{armv6zk}, +@code{armv7}, +@code{armv7a}, +@code{armv7r}, +@code{armv7m}, @code{iwmmxt} and @code{xscale}. @@ -170,7 +192,7 @@ The following format options are recognized: @code{vfpxd}, @code{arm1020t}, @code{arm1020e}, -@code{arm1136jfs} +@code{arm1136jf-s} and @code{maverick}. @@ -228,6 +250,16 @@ The following values are recognized: and @code{hard}. +@cindex @code{-eabi=} command line option, ARM +@item -meabi=@var{ver} +This option specifies which EABI version the produced object files should +conform to. +The following values are recognised: +@code{gnu}, +@code{4} +and +@code{5}. + @cindex @code{-EB} command line option, ARM @item -EB This option specifies that the output generated by the assembler should @@ -244,13 +276,6 @@ be marked as being encoded for a little-endian processor. This option specifies that the output of the assembler should be marked as position-independent code (PIC). -@cindex @code{-moabi} command line option, ARM -@item -moabi -This indicates that the code should be assembled using the old ARM ELF -conventions, based on a beta release release of the ARM-ELF -specifications, rather than the default conventions which are based on -the final release of the ARM-ELF specifications. - @end table @@ -390,6 +415,125 @@ it prevents accurate control of the placement of literal pools. @item .pool This is a synonym for .ltorg. +@cindex @code{.fnstart} directive, ARM +@item .unwind_fnstart +Marks the start of a function with an unwind table entry. + +@cindex @code{.fnend} directive, ARM +@item .unwind_fnend +Marks the end of a function with an unwind table entry. The unwind index +table entry is created when this directive is processed. + +If no personality routine has been specified then standard personality +routine 0 or 1 will be used, depending on the number of unwind opcodes +required. + +@cindex @code{.cantunwind} directive, ARM +@item .cantunwind +Prevents unwinding through the current function. No personality routine +or exception table data is required or permitted. + +@cindex @code{.personality} directive, ARM +@item .personality @var{name} +Sets the personality routine for the current function to @var{name}. + +@cindex @code{.personalityindex} directive, ARM +@item .personalityindex @var{index} +Sets the personality routine for the current function to the EABI standard +routine number @var{index} + +@cindex @code{.handlerdata} directive, ARM +@item .handlerdata +Marks the end of the current function, and the start of the exception table +entry for that function. Anything between this directive and the +@code{.fnend} directive will be added to the exception table entry. + +Must be preceded by a @code{.personality} or @code{.personalityindex} +directive. + +@cindex @code{.save} directive, ARM +@item .save @var{reglist} +Generate unwinder annotations to restore the registers in @var{reglist}. +The format of @var{reglist} is the same as the corresponding store-multiple +instruction. + +@smallexample +@exdent @emph{core registers} + .save @{r4, r5, r6, lr@} + stmfd sp!, @{r4, r5, r6, lr@} +@exdent @emph{FPA registers} + .save f4, 2 + sfmfd f4, 2, [sp]! +@exdent @emph{VFP registers} + .save @{d8, d9, d10@} + fstmdf sp!, @{d8, d9, d10@} +@exdent @emph{iWMMXt registers} + .save @{wr10, wr11@} + wstrd wr11, [sp, #-8]! + wstrd wr10, [sp, #-8]! +or + .save wr11 + wstrd wr11, [sp, #-8]! + .save wr10 + wstrd wr10, [sp, #-8]! +@end smallexample + +@cindex @code{.pad} directive, ARM +@item .pad #@var{count} +Generate unwinder annotations for a stack adjustment of @var{count} bytes. +A positive value indicates the function prologue allocated stack space by +decrementing the stack pointer. + +@cindex @code{.movsp} directive, ARM +@item .movsp @var{reg} +Tell the unwinder that @var{reg} contains the current stack pointer. + +@cindex @code{.setfp} directive, ARM +@item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}] +Make all unwinder annotations relaive to a frame pointer. Without this +the unwinder will use offsets from the stack pointer. + +The syntax of this directive is the same as the @code{sub} or @code{mov} +instruction used to set the frame pointer. @var{spreg} must be either +@code{sp} or mentioned in a previous @code{.movsp} directive. + +@smallexample +.movsp ip +mov ip, sp +@dots{} +.setfp fp, ip, #4 +sub fp, ip, #4 +@end smallexample + +@cindex @code{.unwind_raw} directive, ARM +@item .raw @var{offset}, @var{byte1}, @dots{} +Insert one of more arbitary unwind opcode bytes, which are known to adjust +the stack pointer by @var{offset} bytes. + +For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to +@code{.save @{r0@}} + +@cindex @code{.cpu} directive, ARM +@item .cpu @var{name} +Select the target processor. Valid values for @var{name} are the same as +for the @option{-mcpu} commandline option. + +@cindex @code{.arch} directive, ARM +@item .arch @var{name} +Select the target architecture. Valid values for @var{name} are the same as +for the @option{-march} commandline option. + +@cindex @code{.fpu} directive, ARM +@item .fpu @var{name} +Select the floating point unit to assemble for. Valid values for @var{name} +are the same as for the @option{-mfpu} commandline option. + +@cindex @code{.eabi_attribute} directive, ARM +@item .eabi_attribute @var{tag}, @var{value} +Set the EABI object attribute number @var{tag} to @var{value}. The value +is either a @code{number}, @code{"string"}, or @code{number, "string"} +depending on the tag. + @end table @node ARM Opcodes |