diff options
Diffstat (limited to 'lib/Target/X86/X86ScheduleSLM.td')
| -rw-r--r-- | lib/Target/X86/X86ScheduleSLM.td | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/X86/X86ScheduleSLM.td b/lib/Target/X86/X86ScheduleSLM.td index 03ed2db2350dd..35ec7488db726 100644 --- a/lib/Target/X86/X86ScheduleSLM.td +++ b/lib/Target/X86/X86ScheduleSLM.td @@ -32,7 +32,6 @@ def SLMModel : SchedMachineModel { let SchedModel = SLMModel in { // Silvermont has 5 reservation stations for micro-ops - def IEC_RSV0 : ProcResource<1>; def IEC_RSV1 : ProcResource<1>; def FPC_RSV0 : ProcResource<1> { let BufferSize = 1; } @@ -78,6 +77,9 @@ def : WriteRes<WriteLoad, [MEC_RSV]> { let Latency = 3; } def : WriteRes<WriteMove, [IEC_RSV01]>; def : WriteRes<WriteZero, []>; +// Treat misc copies as a move. +def : InstRW<[WriteMove], (instrs COPY)>; + defm : SMWriteResPair<WriteALU, IEC_RSV01, 1>; defm : SMWriteResPair<WriteIMul, IEC_RSV1, 3>; defm : SMWriteResPair<WriteShift, IEC_RSV0, 1>; @@ -249,7 +251,7 @@ def : WriteRes<WriteMicrocoded, [FPC_RSV0]> { let Latency = 100; } def : WriteRes<WriteFence, [MEC_RSV]>; def : WriteRes<WriteNop, []>; -// AVX is not supported on that architecture, but we should define the basic +// AVX/FMA is not supported on that architecture, but we should define the basic // scheduling resources anyway. def : WriteRes<WriteIMulH, [FPC_RSV0]>; defm : SMWriteResPair<WriteVarBlend, FPC_RSV0, 1>; @@ -257,4 +259,5 @@ defm : SMWriteResPair<WriteFVarBlend, FPC_RSV0, 1>; defm : SMWriteResPair<WriteFShuffle256, FPC_RSV0, 1>; defm : SMWriteResPair<WriteShuffle256, FPC_RSV0, 1>; defm : SMWriteResPair<WriteVarVecShift, FPC_RSV0, 1>; +defm : SMWriteResPair<WriteFMA, FPC_RSV0, 1>; } // SchedModel |