diff options
Diffstat (limited to 'llvm/lib/Target/Mips/MipsScheduleGeneric.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsScheduleGeneric.td | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td index e8a0a30b8e9b7..faccb37c2361f 100644 --- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td +++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td @@ -720,11 +720,16 @@ def : InstRW<[GenericWriteALU], (instrs BADDu, BBIT0, BBIT032, BBIT1, BBIT132, CINS, CINS32, CINS64_32, CINS_i32, DMFC2_OCTEON, DMTC2_OCTEON, DPOP, EXTS, EXTS32, MTM0, MTM1, MTM2, MTP0, MTP1, MTP2, - POP, SEQ, SEQi, SNE, SNEi, V3MULU, VMM0, - VMULU)>; + POP, SEQ, SEQi, SNE, SNEi, + V3MULU, VMM0, VMULU)>; def : InstRW<[GenericWriteMDUtoGPR], (instrs DMUL)>; +// Cavium Networks MIPS (cnMIPSP) - Octeon+, HasCnMipsP +// ================================================= + +def : InstRW<[GenericWriteALU], (instrs SAA, SAAD)>; + // FPU Pipelines // ============= @@ -1610,5 +1615,6 @@ def : InstRW<[GenericWriteAtomic], def : InstRW<[GenericWriteAtomic], (instregex "^ATOMIC_CMP_SWAP_I(8|16|32|64)_POSTRA$")>; def : InstRW<[GenericWriteAtomic], - (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND)_I(8|16|32|64)_POSTRA$")>; + (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)" + "_I(8|16|32|64)_POSTRA$")>; } |