diff options
Diffstat (limited to 'test/CodeGen/AArch64/fp16-v8-instructions.ll')
| -rw-r--r-- | test/CodeGen/AArch64/fp16-v8-instructions.ll | 524 |
1 files changed, 358 insertions, 166 deletions
diff --git a/test/CodeGen/AArch64/fp16-v8-instructions.ll b/test/CodeGen/AArch64/fp16-v8-instructions.ll index 2f70f3635d195..5215260c23a27 100644 --- a/test/CodeGen/AArch64/fp16-v8-instructions.ll +++ b/test/CodeGen/AArch64/fp16-v8-instructions.ll @@ -1,40 +1,46 @@ -; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s +; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefix=CHECK-CVT --check-prefix=CHECK +; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefix=CHECK-FP16 --check-prefix=CHECK define <8 x half> @add_h(<8 x half> %a, <8 x half> %b) { entry: -; CHECK-LABEL: add_h: -; CHECK: fcvt -; CHECK: fcvt -; CHECK-DAG: fadd -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fadd -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fadd -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fadd -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fadd -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fadd -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fadd -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fadd -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK: fcvt +; CHECK-CVT-LABEL: add_h: +; CHECK-CVT: fcvt +; CHECK-CVT: fcvt +; CHECK-CVT-DAG: fadd +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fadd +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fadd +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fadd +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fadd +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fadd +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fadd +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fadd +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT: fcvt + +; CHECK-FP16-LABEL: add_h: +; CHECK-FP16: fadd v0.8h, v0.8h, v1.8h +; CHECK-FP16-NEXT: ret + %0 = fadd <8 x half> %a, %b ret <8 x half> %0 } @@ -42,39 +48,44 @@ entry: define <8 x half> @sub_h(<8 x half> %a, <8 x half> %b) { entry: -; CHECK-LABEL: sub_h: -; CHECK: fcvt -; CHECK: fcvt -; CHECK-DAG: fsub -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fsub -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fsub -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fsub -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fsub -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fsub -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fsub -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fsub -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK: fcvt +; CHECK-CVT-LABEL: sub_h: +; CHECK-CVT: fcvt +; CHECK-CVT: fcvt +; CHECK-CVT-DAG: fsub +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fsub +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fsub +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fsub +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fsub +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fsub +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fsub +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fsub +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT: fcvt + +; CHECK-FP16-LABEL: sub_h: +; CHECK-FP16: fsub v0.8h, v0.8h, v1.8h +; CHECK-FP16-NEXT: ret + %0 = fsub <8 x half> %a, %b ret <8 x half> %0 } @@ -82,39 +93,44 @@ entry: define <8 x half> @mul_h(<8 x half> %a, <8 x half> %b) { entry: -; CHECK-LABEL: mul_h: -; CHECK: fcvt -; CHECK: fcvt -; CHECK-DAG: fmul -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fmul -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fmul -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fmul -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fmul -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fmul -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fmul -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fmul -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK: fcvt +; CHECK-CVT-LABEL: mul_h: +; CHECK-CVT: fcvt +; CHECK-CVT: fcvt +; CHECK-CVT-DAG: fmul +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fmul +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fmul +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fmul +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fmul +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fmul +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fmul +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fmul +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT: fcvt + +; CHECK-FP16-LABEL: mul_h: +; CHECK-FP16: fmul v0.8h, v0.8h, v1.8h +; CHECK-FP16-NEXT: ret + %0 = fmul <8 x half> %a, %b ret <8 x half> %0 } @@ -122,39 +138,44 @@ entry: define <8 x half> @div_h(<8 x half> %a, <8 x half> %b) { entry: -; CHECK-LABEL: div_h: -; CHECK: fcvt -; CHECK: fcvt -; CHECK-DAG: fdiv -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fdiv -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fdiv -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fdiv -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fdiv -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fdiv -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fdiv -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fdiv -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK-DAG: fcvt -; CHECK: fcvt +; CHECK-CVT-LABEL: div_h: +; CHECK-CVT: fcvt +; CHECK-CVT: fcvt +; CHECK-CVT-DAG: fdiv +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fdiv +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fdiv +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fdiv +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fdiv +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fdiv +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fdiv +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fdiv +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT-DAG: fcvt +; CHECK-CVT: fcvt + +; CHECK-FP16-LABEL: div_h: +; CHECK-FP16: fdiv v0.8h, v0.8h, v1.8h +; CHECK-FP16-NEXT: ret + %0 = fdiv <8 x half> %a, %b ret <8 x half> %0 } @@ -181,7 +202,7 @@ define <8 x half> @s_to_h(<8 x float> %a) { ; CHECK-LABEL: s_to_h: ; CHECK-DAG: fcvtn v0.4h, v0.4s ; CHECK-DAG: fcvtn [[REG:v[0-9+]]].4h, v1.4s -; CHECK: ins v0.d[1], [[REG]].d[0] +; CHECK: mov v0.d[1], [[REG]].d[0] %1 = fptrunc <8 x float> %a to <8 x half> ret <8 x half> %1 } @@ -200,14 +221,14 @@ define <8 x half> @d_to_h(<8 x double> %a) { ; CHECK-DAG: fcvt h ; CHECK-DAG: fcvt h ; CHECK-DAG: fcvt h -; CHECK-DAG: ins v{{[0-9]+}}.h -; CHECK-DAG: ins v{{[0-9]+}}.h -; CHECK-DAG: ins v{{[0-9]+}}.h -; CHECK-DAG: ins v{{[0-9]+}}.h -; CHECK-DAG: ins v{{[0-9]+}}.h -; CHECK-DAG: ins v{{[0-9]+}}.h -; CHECK-DAG: ins v{{[0-9]+}}.h -; CHECK-DAG: ins v{{[0-9]+}}.h +; CHECK-DAG: mov v{{[0-9]+}}.h +; CHECK-DAG: mov v{{[0-9]+}}.h +; CHECK-DAG: mov v{{[0-9]+}}.h +; CHECK-DAG: mov v{{[0-9]+}}.h +; CHECK-DAG: mov v{{[0-9]+}}.h +; CHECK-DAG: mov v{{[0-9]+}}.h +; CHECK-DAG: mov v{{[0-9]+}}.h +; CHECK-DAG: mov v{{[0-9]+}}.h %1 = fptrunc <8 x double> %a to <8 x half> ret <8 x half> %1 } @@ -222,6 +243,13 @@ define <8 x float> @h_to_s(<8 x half> %a) { define <8 x double> @h_to_d(<8 x half> %a) { ; CHECK-LABEL: h_to_d: +; CHECK-DAG: mov h{{[0-9]+}}, v0.h +; CHECK-DAG: mov h{{[0-9]+}}, v0.h +; CHECK-DAG: mov h{{[0-9]+}}, v0.h +; CHECK-DAG: mov h{{[0-9]+}}, v0.h +; CHECK-DAG: mov h{{[0-9]+}}, v0.h +; CHECK-DAG: mov h{{[0-9]+}}, v0.h +; CHECK-DAG: mov h{{[0-9]+}}, v0.h ; CHECK-DAG: fcvt d ; CHECK-DAG: fcvt d ; CHECK-DAG: fcvt d @@ -230,10 +258,6 @@ define <8 x double> @h_to_d(<8 x half> %a) { ; CHECK-DAG: fcvt d ; CHECK-DAG: fcvt d ; CHECK-DAG: fcvt d -; CHECK-DAG: ins -; CHECK-DAG: ins -; CHECK-DAG: ins -; CHECK-DAG: ins %1 = fpext <8 x half> %a to <8 x double> ret <8 x double> %1 } @@ -263,7 +287,7 @@ define <8 x half> @sitofp_i8(<8 x i8> %a) #0 { ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]] ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]] ; CHECK-DAG: fcvtn v0.4h, [[HIF]] -; CHECK: ins v0.d[1], v[[LOREG]].d[0] +; CHECK: mov v0.d[1], v[[LOREG]].d[0] %1 = sitofp <8 x i8> %a to <8 x half> ret <8 x half> %1 } @@ -277,7 +301,7 @@ define <8 x half> @sitofp_i16(<8 x i16> %a) #0 { ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]] ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]] ; CHECK-DAG: fcvtn v0.4h, [[HIF]] -; CHECK: ins v0.d[1], v[[LOREG]].d[0] +; CHECK: mov v0.d[1], v[[LOREG]].d[0] %1 = sitofp <8 x i16> %a to <8 x half> ret <8 x half> %1 } @@ -289,7 +313,7 @@ define <8 x half> @sitofp_i32(<8 x i32> %a) #0 { ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]] ; CHECK-DAG: fcvtn v0.4h, [[OP1]] -; CHECK: ins v0.d[1], v[[REG]].d[0] +; CHECK: mov v0.d[1], v[[REG]].d[0] %1 = sitofp <8 x i32> %a to <8 x half> ret <8 x half> %1 } @@ -315,7 +339,7 @@ define <8 x half> @uitofp_i8(<8 x i8> %a) #0 { ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]] ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]] ; CHECK-DAG: fcvtn v0.4h, [[HIF]] -; CHECK: ins v0.d[1], v[[LOREG]].d[0] +; CHECK: mov v0.d[1], v[[LOREG]].d[0] %1 = uitofp <8 x i8> %a to <8 x half> ret <8 x half> %1 } @@ -329,7 +353,7 @@ define <8 x half> @uitofp_i16(<8 x i16> %a) #0 { ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]] ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]] ; CHECK-DAG: fcvtn v0.4h, [[HIF]] -; CHECK: ins v0.d[1], v[[LOREG]].d[0] +; CHECK: mov v0.d[1], v[[LOREG]].d[0] %1 = uitofp <8 x i16> %a to <8 x half> ret <8 x half> %1 } @@ -341,7 +365,7 @@ define <8 x half> @uitofp_i32(<8 x i32> %a) #0 { ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]] ; CHECK-DAG: fcvtn v0.4h, [[OP1]] -; CHECK: ins v0.d[1], v[[REG]].d[0] +; CHECK: mov v0.d[1], v[[REG]].d[0] %1 = uitofp <8 x i32> %a to <8 x half> ret <8 x half> %1 } @@ -421,86 +445,254 @@ define <8 x i16> @fptoui_i16(<8 x half> %a) #0 { ret <8 x i16> %1 } -; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. define <8 x i1> @test_fcmp_une(<8 x half> %a, <8 x half> %b) #0 { +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. + +; CHECK-FP16-LABEL: test_fcmp_une: +; CHECK-FP16-NOT: fcvt +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} + %1 = fcmp une <8 x half> %a, %b ret <8 x i1> %1 } -; FileCheck checks are unwieldy with 16 fcvt and 16 csel tests. Skipped. define <8 x i1> @test_fcmp_ueq(<8 x half> %a, <8 x half> %b) #0 { +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. + +; CHECK-FP16-LABEL: test_fcmp_ueq: +; CHECK-FP16-NOT: fcvt +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} + %1 = fcmp ueq <8 x half> %a, %b ret <8 x i1> %1 } -; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. define <8 x i1> @test_fcmp_ugt(<8 x half> %a, <8 x half> %b) #0 { +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. + +; CHECK-FP16-LABEL: test_fcmp_ugt: +; CHECK-FP16-NOT: fcvt +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} + %1 = fcmp ugt <8 x half> %a, %b ret <8 x i1> %1 } -; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. define <8 x i1> @test_fcmp_uge(<8 x half> %a, <8 x half> %b) #0 { +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. + +; CHECK-FP16-LABEL: test_fcmp_uge: +; CHECK-FP16-NOT: fcvt +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} + %1 = fcmp uge <8 x half> %a, %b ret <8 x i1> %1 } -; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. define <8 x i1> @test_fcmp_ult(<8 x half> %a, <8 x half> %b) #0 { +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. + +; CHECK-FP16-LABEL: test_fcmp_ult: +; CHECK-FP16-NOT: fcvt +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} + %1 = fcmp ult <8 x half> %a, %b ret <8 x i1> %1 } -; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. define <8 x i1> @test_fcmp_ule(<8 x half> %a, <8 x half> %b) #0 { +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. + +; CHECK-FP16-LABEL: test_fcmp_ule: +; CHECK-FP16-NOT: fcvt +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} + %1 = fcmp ule <8 x half> %a, %b ret <8 x i1> %1 } -; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. define <8 x i1> @test_fcmp_uno(<8 x half> %a, <8 x half> %b) #0 { +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. + +; CHECK-FP16-LABEL: test_fcmp_uno: +; CHECK-FP16-NOT: fcvt +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} + %1 = fcmp uno <8 x half> %a, %b ret <8 x i1> %1 } -; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. define <8 x i1> @test_fcmp_one(<8 x half> %a, <8 x half> %b) #0 { +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. + +; CHECK-FP16-LABEL: test_fcmp_one: +; CHECK-FP16-NOT: fcvt +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} + %1 = fcmp one <8 x half> %a, %b ret <8 x i1> %1 } -; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. define <8 x i1> @test_fcmp_oeq(<8 x half> %a, <8 x half> %b) #0 { +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. + +; CHECK-FP16-LABEL: test_fcmp_oeq: +; CHECK-FP16-NOT: fcvt +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} + %1 = fcmp oeq <8 x half> %a, %b ret <8 x i1> %1 } -; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. define <8 x i1> @test_fcmp_ogt(<8 x half> %a, <8 x half> %b) #0 { +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. + +; CHECK-FP16-LABEL: test_fcmp_ogt: +; CHECK-FP16-NOT: fcvt +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} + %1 = fcmp ogt <8 x half> %a, %b ret <8 x i1> %1 } -; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. define <8 x i1> @test_fcmp_oge(<8 x half> %a, <8 x half> %b) #0 { +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. + +; CHECK-FP16-LABEL: test_fcmp_oge: +; CHECK-FP16-NOT: fcvt +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} + %1 = fcmp oge <8 x half> %a, %b ret <8 x i1> %1 } -; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. define <8 x i1> @test_fcmp_olt(<8 x half> %a, <8 x half> %b) #0 { +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. + +; CHECK-FP16-LABEL: test_fcmp_olt: +; CHECK-FP16-NOT: fcvt +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} + %1 = fcmp olt <8 x half> %a, %b ret <8 x i1> %1 } -; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. define <8 x i1> @test_fcmp_ole(<8 x half> %a, <8 x half> %b) #0 { +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. + +; CHECK-FP16-LABEL: test_fcmp_ole: +; CHECK-FP16-NOT: fcvt +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} + %1 = fcmp ole <8 x half> %a, %b ret <8 x i1> %1 } -; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. define <8 x i1> @test_fcmp_ord(<8 x half> %a, <8 x half> %b) #0 { +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. + +; CHECK-FP16-LABEL: test_fcmp_ord: +; CHECK-FP16-NOT: fcvt +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} +; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} + %1 = fcmp ord <8 x half> %a, %b ret <8 x i1> %1 } |