diff options
Diffstat (limited to 'test/CodeGen/AMDGPU/GlobalISel')
16 files changed, 232 insertions, 60 deletions
diff --git a/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll b/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll index cdfb667c26bd7..8f83feac51d86 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll +++ b/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll @@ -5,7 +5,7 @@ ; Tests for add. ; CHECK: name: addi32 -; CHECK: {{%[0-9]+}}(s32) = G_ADD +; CHECK: {{%[0-9]+}}:_(s32) = G_ADD define amdgpu_kernel void @addi32(i32 %arg1, i32 %arg2) { %res = add i32 %arg1, %arg2 store i32 %res, i32 addrspace(1)* undef diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir index 56a9e7022db9c..9b53b029691eb 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir @@ -13,7 +13,7 @@ legalized: true regBankSelected: true # GCN: global_addrspace -# GCN: [[PTR:%[0-9]+]] = COPY %vgpr0_vgpr1 +# GCN: [[PTR:%[0-9]+]]:vreg_64 = COPY %vgpr0_vgpr1 # GCN: FLAT_LOAD_DWORD [[PTR]], 0, 0, 0 body: | diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir index ea2ad2ba83a52..70e2b5e4ae2b8 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir @@ -14,83 +14,83 @@ legalized: true regBankSelected: true # GCN: body: -# GCN: [[PTR:%[0-9]+]] = COPY %sgpr0_sgpr1 +# GCN: [[PTR:%[0-9]+]]:sreg_64 = COPY %sgpr0_sgpr1 # Immediate offset: # SICI: S_LOAD_DWORD_IMM [[PTR]], 1, 0 -# VI: S_LOAD_DWORD_IMM [[PTR]], 4, 0 +# VI: S_LOAD_DWORD_IMM [[PTR]], 4, 0 # Max immediate offset for SI # SICI: S_LOAD_DWORD_IMM [[PTR]], 255, 0 # VI: S_LOAD_DWORD_IMM [[PTR]], 1020, 0 # Immediate overflow for SI -# SI: [[K1024:%[0-9]+]] = S_MOV_B32 1024 +# SI: [[K1024:%[0-9]+]]:sreg_32 = S_MOV_B32 1024 # SI: S_LOAD_DWORD_SGPR [[PTR]], [[K1024]], 0 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 256, 0 # VI: S_LOAD_DWORD_IMM [[PTR]], 1024, 0 # Max immediate offset for VI -# SI: [[K1048572:%[0-9]+]] = S_MOV_B32 1048572 +# SI: [[K1048572:%[0-9]+]]:sreg_32 = S_MOV_B32 1048572 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262143 # VI: S_LOAD_DWORD_IMM [[PTR]], 1048572 # # Immediate overflow for VI -# SIVI: [[K1048576:%[0-9]+]] = S_MOV_B32 1048576 +# SIVI: [[K1048576:%[0-9]+]]:sreg_32 = S_MOV_B32 1048576 # SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K1048576]], 0 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262144, 0 # Max immediate for CI -# SIVI: [[K_LO:%[0-9]+]] = S_MOV_B32 4294967292 -# SIVI: [[K_HI:%[0-9]+]] = S_MOV_B32 3 -# SIVI: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2 -# SIVI-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0 -# SIVI-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0 -# SIVI: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] -# SIVI-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1 -# SIVI-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1 -# SIVI: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] -# SIVI: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2 +# SIVI: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967292 +# SIVI: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 3 +# SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 +# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0 +# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0 +# SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] +# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 +# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1 +# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] +# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 4294967295, 0 # Immediate overflow for CI -# GCN: [[K_LO:%[0-9]+]] = S_MOV_B32 0 -# GCN: [[K_HI:%[0-9]+]] = S_MOV_B32 4 -# GCN: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2 -# GCN-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0 -# GCN-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0 -# GCN: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] -# GCN-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1 -# GCN-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1 -# GCN: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] -# GCN: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2 +# GCN: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 0 +# GCN: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 4 +# GCN: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 +# GCN-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0 +# GCN-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0 +# GCN: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] +# GCN-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 +# GCN-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1 +# GCN: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] +# GCN: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 # GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0 # Max 32-bit byte offset -# SIVI: [[K4294967292:%[0-9]+]] = S_MOV_B32 4294967292 +# SIVI: [[K4294967292:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967292 # SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K4294967292]], 0 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741823, 0 # Overflow 32-bit byte offset -# SIVI: [[K_LO:%[0-9]+]] = S_MOV_B32 0 -# SIVI: [[K_HI:%[0-9]+]] = S_MOV_B32 1 -# SIVI: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2 -# SIVI-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0 -# SIVI-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0 -# SIVI: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] -# SIVI-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1 -# SIVI-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1 -# SIVI: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] -# SIVI: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2 +# SIVI: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 0 +# SIVI: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 1 +# SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 +# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0 +# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0 +# SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] +# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 +# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1 +# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] +# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741824, 0 body: | bb.0: liveins: %sgpr0_sgpr1 - + %0:sgpr(p2) = COPY %sgpr0_sgpr1 %1:sgpr(s64) = G_CONSTANT i64 4 diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir index ea435725bf25d..0b8092778bd49 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir @@ -13,8 +13,8 @@ legalized: true regBankSelected: true # GCN: global_addrspace -# GCN: [[PTR:%[0-9]+]] = COPY %vgpr0_vgpr1 -# GCN: [[VAL:%[0-9]+]] = COPY %vgpr2 +# GCN: [[PTR:%[0-9]+]]:vreg_64 = COPY %vgpr0_vgpr1 +# GCN: [[VAL:%[0-9]+]]:vgpr_32 = COPY %vgpr2 # GCN: FLAT_STORE_DWORD [[PTR]], [[VAL]], 0, 0, 0 body: | diff --git a/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll b/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll new file mode 100644 index 0000000000000..ebcdac39274a4 --- /dev/null +++ b/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll @@ -0,0 +1,60 @@ +; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=irtranslator -global-isel %s -o - | FileCheck %s + + +; CHECK-LABEL: name: test_f32_inreg +; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY %sgpr0 +; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[S0]] +define amdgpu_vs void @test_f32_inreg(float inreg %arg0) { + call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0 + ret void +} + +; CHECK-LABEL: name: test_f32 +; CHECK: [[V0:%[0-9]+]]:_(s32) = COPY %vgpr0 +; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[V0]] +define amdgpu_vs void @test_f32(float %arg0) { + call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0 + ret void +} + +; CHECK-LABEL: name: test_ptr2_byval +; CHECK: [[S01:%[0-9]+]]:_(p2) = COPY %sgpr0_sgpr1 +; CHECK: G_LOAD [[S01]] +define amdgpu_vs void @test_ptr2_byval(i32 addrspace(2)* byval %arg0) { + %tmp0 = load volatile i32, i32 addrspace(2)* %arg0 + ret void +} + +; CHECK-LABEL: name: test_ptr2_inreg +; CHECK: [[S01:%[0-9]+]]:_(p2) = COPY %sgpr0_sgpr1 +; CHECK: G_LOAD [[S01]] +define amdgpu_vs void @test_ptr2_inreg(i32 addrspace(2)* inreg %arg0) { + %tmp0 = load volatile i32, i32 addrspace(2)* %arg0 + ret void +} + +; CHECK-LABEL: name: test_sgpr_alignment0 +; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY %sgpr0 +; CHECK: [[S23:%[0-9]+]]:_(p2) = COPY %sgpr2_sgpr3 +; CHECK: G_LOAD [[S23]] +; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[S0]] +define amdgpu_vs void @test_sgpr_alignment0(float inreg %arg0, i32 addrspace(2)* inreg %arg1) { + %tmp0 = load volatile i32, i32 addrspace(2)* %arg1 + call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0 + ret void +} + +; CHECK-LABEL: name: test_order +; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY %sgpr0 +; CHECK: [[S1:%[0-9]+]]:_(s32) = COPY %sgpr1 +; CHECK: [[V0:%[0-9]+]]:_(s32) = COPY %vgpr0 +; CHECK: [[V1:%[0-9]+]]:_(s32) = COPY %vgpr1 +; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[V0]](s32), [[S0]](s32), [[V1]](s32), [[S1]](s32) +define amdgpu_vs void @test_order(float inreg %arg0, float inreg %arg1, float %arg2, float %arg3) { + call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg2, float %arg0, float %arg3, float %arg1, i1 false, i1 false) #0 + ret void +} + +declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir index f10c896a7af66..3afb2c7db5e60 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | @@ -13,10 +14,13 @@ registers: body: | bb.0: liveins: %vgpr0, %vgpr1 - ; CHECK-LABEL: name: test_add - ; CHECK: %2(s32) = G_ADD %0, %1 + ; CHECK-LABEL: name: test_add + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1 + ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] %0(s32) = COPY %vgpr0 %1(s32) = COPY %vgpr1 %2(s32) = G_ADD %0, %1 + %vgpr0 = COPY %2 ... diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir index 50ef150510d22..c22355cffe35d 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | @@ -13,10 +14,13 @@ registers: body: | bb.0: liveins: %vgpr0, %vgpr1 - ; CHECK-LABEL: name: test_and - ; CHECK: %2(s32) = G_AND %0, %1 + ; CHECK-LABEL: name: test_and + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1 + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]] %0(s32) = COPY %vgpr0 %1(s32) = COPY %vgpr1 %2(s32) = G_AND %0, %1 + %vgpr0 = COPY %2 ... diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir index e27c313b8ec0f..1f0fbd0a36894 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | @@ -13,11 +14,13 @@ registers: body: | bb.0: liveins: %vgpr0 - ; CHECK-LABEL: name: test_bitcast - ; CHECK: %1(<2 x s16>) = G_BITCAST %0 - ; CHECK: %2(s32) = G_BITCAST %1 + ; CHECK-LABEL: name: test_bitcast + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0 + ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY]](s32) + ; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST]](<2 x s16>) %0(s32) = COPY %vgpr0 %1(<2 x s16>) = G_BITCAST %0 %2(s32) = G_BITCAST %1 + %vgpr0 = COPY %2 ... diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir index b3e41c7751c53..843c03f6cc2ca 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | @@ -24,10 +25,11 @@ registers: - { id: 1, class: _ } body: | bb.0.entry: - ; CHECK-LABEL: name: test_constant - ; CHECK: %0(s32) = G_CONSTANT i32 5 - ; CHECK: %1(s1) = G_CONSTANT i1 false + ; CHECK-LABEL: name: test_constant + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 + ; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false + ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C1]](s1), [[C1]](s1) %0(s32) = G_CONSTANT i32 5 %1(s1) = G_CONSTANT i1 0 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.f32), %0, %0, %0, %0, %0, %0, %1, %1; @@ -40,10 +42,12 @@ registers: - { id: 1, class: _ } body: | bb.0.entry: - ; CHECK-LABEL: name: test_fconstant - ; CHECK: %0(s32) = G_FCONSTANT float 1.000000e+00 - ; CHECK: %1(s32) = G_FCONSTANT float 7.5 + ; CHECK-LABEL: name: test_fconstant + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 7.500000e+00 %0(s32) = G_FCONSTANT float 1.0 + %vgpr0 = COPY %0 %1(s32) = G_FCONSTANT float 7.5 + %vgpr0 = COPY %1 ... diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir new file mode 100644 index 0000000000000..0db061ea8a9c9 --- /dev/null +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir @@ -0,0 +1,27 @@ +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- | + define void @test_fadd() { + entry: + ret void + } + +... + +--- +name: test_fadd +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0.entry: + liveins: %vgpr0, %vgpr1 + ; CHECK-LABEL: name: test_fadd + ; CHECK: %2:_(s32) = G_FADD %0, %1 + + %0(s32) = COPY %vgpr0 + %1(s32) = COPY %vgpr1 + %2(s32) = G_FADD %0, %1 + %vgpr0 = COPY %2 +... diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir new file mode 100644 index 0000000000000..98bbd6a2af307 --- /dev/null +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir @@ -0,0 +1,26 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- | + define void @test_fmul() { ret void } +... + +--- +name: test_fmul +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %vgpr0, %vgpr1 + + ; CHECK-LABEL: name: test_fmul + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1 + ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]] + %0(s32) = COPY %vgpr0 + %1(s32) = COPY %vgpr1 + %2(s32) = G_FMUL %0, %1 + %vgpr0 = COPY %2 +... diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir index ebd473d769b37..bb6b68ad2360c 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -march=amdgcn -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | @@ -16,9 +17,15 @@ registers: body: | bb.0.entry: liveins: %vgpr0 + ; CHECK-LABEL: name: test_icmp + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0 + ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]] + ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]] + ; CHECK: %vgpr0 = COPY [[SELECT]](s32) %0(s32) = G_CONSTANT i32 0 %1(s32) = COPY %vgpr0 - - ; CHECK: %2(s1) = G_ICMP intpred(ne), %0(s32), %1 %2(s1) = G_ICMP intpred(ne), %0, %1 + %3:_(s32) = G_SELECT %2(s1), %0(s32), %1(s32) + %vgpr0 = COPY %3 ... diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir new file mode 100644 index 0000000000000..8780a1e080a20 --- /dev/null +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir @@ -0,0 +1,25 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- | + define void @test_or() { ret void } +... +--- +name: test_or +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %vgpr0, %vgpr1 + + ; CHECK-LABEL: name: test_or + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1 + ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]] + %0(s32) = COPY %vgpr0 + %1(s32) = COPY %vgpr1 + %2(s32) = G_OR %0, %1 + %vgpr0 = COPY %2 +... diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir index d11130936bd9b..af633789182c1 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -march=amdgcn -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | @@ -16,13 +17,20 @@ registers: body: | bb.0: liveins: %vgpr0 + ; CHECK-LABEL: name: test_select + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0 + ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]] + ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]] %0(s32) = G_CONSTANT i32 0 %1(s32) = COPY %vgpr0 %2(s1) = G_ICMP intpred(ne), %0, %1 %3(s32) = G_CONSTANT i32 1 %4(s32) = G_CONSTANT i32 2 - ; CHECK: %5(s32) = G_SELECT %2(s1), %3, %4 %5(s32) = G_SELECT %2, %3, %4 + %vgpr0 = COPY %5 ... diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir index 3d5251d102072..d6320fa3e69a2 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- @@ -9,10 +10,13 @@ registers: body: | bb.0.entry: liveins: %vgpr0, %vgpr1 - ; CHECK-LABEL: name: test_shl - ; CHECK: %2(s32) = G_SHL %0, %1 + ; CHECK-LABEL: name: test_shl + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1 + ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]] %0(s32) = COPY %vgpr0 %1(s32) = COPY %vgpr1 %2(s32) = G_SHL %0, %1 + %vgpr0 = COPY %2 ... diff --git a/test/CodeGen/AMDGPU/GlobalISel/smrd.ll b/test/CodeGen/AMDGPU/GlobalISel/smrd.ll index 8a6b3df9cff8d..6629188131daf 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/smrd.ll +++ b/test/CodeGen/AMDGPU/GlobalISel/smrd.ll @@ -1,5 +1,5 @@ ; FIXME: Need to add support for mubuf stores to enable this on SI. -; XUN: llc < %s -march=amdgcn -mcpu=SI -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=SIVI %s +; XUN: llc < %s -march=amdgcn -mcpu=tahiti -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=SIVI %s ; RUN: llc < %s -march=amdgcn -mcpu=bonaire -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=CI --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=SIVI %s |