diff options
Diffstat (limited to 'test/CodeGen/ARM/misched-int-basic.mir')
| -rw-r--r-- | test/CodeGen/ARM/misched-int-basic.mir | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/test/CodeGen/ARM/misched-int-basic.mir b/test/CodeGen/ARM/misched-int-basic.mir index d5231269d732c..9641348792aed 100644 --- a/test/CodeGen/ARM/misched-int-basic.mir +++ b/test/CodeGen/ARM/misched-int-basic.mir @@ -28,37 +28,37 @@ } # CHECK: ********** MI Scheduling ********** -# CHECK: SU(2): %vreg2<def> = SMULBB %vreg1, %vreg1, pred:14, pred:%noreg; GPR:%vreg2,%vreg1,%vreg1 +# CHECK: SU(2): %2:gpr = SMULBB %1, %1, pred:14, pred:%noreg; GPR:%2,%1,%1 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(3): %vreg3<def> = SMLABB %vreg0, %vreg0, %vreg2, pred:14, pred:%noreg; GPRnopc:%vreg3,%vreg0,%vreg0 GPR:%vreg2 +# CHECK: SU(3): %3:gprnopc = SMLABB %0, %0, %2, pred:14, pred:%noreg; GPRnopc:%3,%0,%0 GPR:%2 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(4): %vreg4<def> = UXTH %vreg3, 0, pred:14, pred:%noreg; GPRnopc:%vreg4,%vreg3 +# CHECK: SU(4): %4:gprnopc = UXTH %3, 0, pred:14, pred:%noreg; GPRnopc:%4,%3 # CHECK_A9: Latency : 1 # CHECK_SWIFT: Latency : 1 # CHECK_R52: Latency : 3 # -# CHECK: SU(5): %vreg5<def> = MUL %vreg4, %vreg4, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg5,%vreg4,%vreg4 +# CHECK: SU(5): %5:gprnopc = MUL %4, %4, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%5,%4,%4 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(6): %vreg6<def> = MLA %vreg5, %vreg5, %vreg5, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg6,%vreg5,%vreg5,%vreg5 +# CHECK: SU(6): %6:gprnopc = MLA %5, %5, %5, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%6,%5,%5,%5 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(7): %vreg7<def>, %vreg8<def> = UMULL %vreg6, %vreg6, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg7,%vreg8,%vreg6,%vreg6 +# CHECK: SU(7): %7:gprnopc, %8:gprnopc = UMULL %6, %6, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%7,%8,%6,%6 # CHECK_A9: Latency : 3 # CHECK_SWIFT: Latency : 5 # CHECK_R52: Latency : 4 # -# CHECK: SU(11): %vreg13<def,tied4>, %vreg14<def,tied5> = UMLAL %vreg6, %vreg6, %vreg13<tied0>, %vreg14<tied1>, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg13 GPRnopc:%vreg14,%vreg6,%vreg6 +# CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6, %6, %13, %14, pred:14, pred:%noreg, opt:%noreg; GPR:%13 GPRnopc:%14,%6,%6 # CHECK_SWIFT: Latency : 7 # CHECK_A9: Latency : 3 # CHECK_R52: Latency : 4 @@ -111,18 +111,18 @@ body: | %1 = COPY %r1 %0 = COPY %r0 - %2 = SMULBB %1, %1, 14, _ - %3 = SMLABB %0, %0, %2, 14, _ - %4 = UXTH %3, 0, 14, _ - %5 = MUL %4, %4, 14, _, _ - %6 = MLA %5, %5, %5, 14, _, _ - %7, %8 = UMULL %6, %6, 14, _, _ - %13, %10 = UMULL %7, %7, 14, _, _ - %11 = MLA %7, %8, %10, 14, _, _ - %14 = MLA %7, %8, %11, 14, _, _ - %13, %14 = UMLAL %6, %6, %13, %14, 14, _, _ + %2 = SMULBB %1, %1, 14, %noreg + %3 = SMLABB %0, %0, %2, 14, %noreg + %4 = UXTH %3, 0, 14, %noreg + %5 = MUL %4, %4, 14, %noreg, %noreg + %6 = MLA %5, %5, %5, 14, %noreg, %noreg + %7, %8 = UMULL %6, %6, 14, %noreg, %noreg + %13, %10 = UMULL %7, %7, 14, %noreg, %noreg + %11 = MLA %7, %8, %10, 14, %noreg, %noreg + %14 = MLA %7, %8, %11, 14, %noreg, %noreg + %13, %14 = UMLAL %6, %6, %13, %14, 14, %noreg, %noreg %r0 = COPY %13 %r1 = COPY %14 - BX_RET 14, _, implicit %r0, implicit %r1 + BX_RET 14, %noreg, implicit %r0, implicit %r1 ... |