diff options
Diffstat (limited to 'test/CodeGen/Mips')
91 files changed, 10382 insertions, 2072 deletions
diff --git a/test/CodeGen/Mips/2008-07-15-SmallSection.ll b/test/CodeGen/Mips/2008-07-15-SmallSection.ll index 79f4d7970e68d..3f42489141f0b 100644 --- a/test/CodeGen/Mips/2008-07-15-SmallSection.ll +++ b/test/CodeGen/Mips/2008-07-15-SmallSection.ll @@ -1,16 +1,51 @@ -; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 -relocation-model=static -mattr=+noabicalls -mgpopt | FileCheck %s +; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 -verify-machineinstrs \ +; RUN: -relocation-model=static -mattr=+noabicalls -mgpopt \ +; RUN: | FileCheck %s --check-prefixes=BASIC,COMMON,ADDR32 +; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 -verify-machineinstrs \ +; RUN: -relocation-model=static -mattr=+noabicalls -mgpopt -membedded-data \ +; RUN: | FileCheck %s --check-prefixes=EMBDATA,COMMON,ADDR32 + +; RUN: llc < %s -march=mips64 -mcpu=mips4 -mips-ssection-threshold=8 -verify-machineinstrs \ +; RUN: -relocation-model=static -mattr=+noabicalls -mgpopt -target-abi n64 \ +; RUN: | FileCheck %s --check-prefixes=BASIC,COMMON,N64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -mips-ssection-threshold=8 -verify-machineinstrs \ +; RUN: -relocation-model=static -mattr=+noabicalls,+sym32 -mgpopt -target-abi n64 \ +; RUN: | FileCheck %s --check-prefixes=BASIC,COMMON,N64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -mips-ssection-threshold=8 -verify-machineinstrs \ +; RUN: -relocation-model=static -mattr=+noabicalls -mgpopt -target-abi n32 \ +; RUN: | FileCheck %s --check-prefixes=BASIC,COMMON,ADDR32 + +; Test the layout of objects when compiling for static, noabicalls environment. %struct.anon = type { i32, i32 } +; Check that when synthesizing a pointer to the second element of foo, that +; we use the correct addition operation. O32 and N32 have 32-bit address +; spaces, so they use addiu. N64 has a 64bit address space, but has a submode +; where symbol sizes are 32 bits. In those cases we use daddiu. + +; CHECK-LABEL: A1: +; N64: daddiu ${{[0-9]+}}, $gp, %gp_rel(foo) +; ADDR32: addiu ${{[0-9]+}}, $gp, %gp_rel(foo) + +; BASIC: .type s0,@object +; BASIC-NEXT: .section .sdata,"aw",@progbits + +; EMDATA: .type s0,@object +; EMDATA-NEXT: .section .rodata,"a",@progbits + @s0 = constant [8 x i8] c"AAAAAAA\00", align 4 -; CHECK: .type foo,@object -; CHECK-NEXT: .section .sdata,"aw",@progbits +; BASIC: .type foo,@object +; BASIC-NOT: .section + +; EMBDATA: .type foo,@object +; EMBDATA-NEXT: .section .sdata,"aw",@progbits @foo = global %struct.anon { i32 2, i32 3 } -; CHECK: .type bar,@object -; CHECK-NEXT: .section .sbss,"aw",@nobits -@bar = global %struct.anon zeroinitializer +; COMMON: .type bar,@object +; COMMON-NEXT: .section .sbss,"aw",@nobits +@bar = global %struct.anon zeroinitializer define i8* @A0() nounwind { entry: diff --git a/test/CodeGen/Mips/br-jmp.ll b/test/CodeGen/Mips/br-jmp.ll index 5e94c755c9697..1323dedb462a9 100644 --- a/test/CodeGen/Mips/br-jmp.ll +++ b/test/CodeGen/Mips/br-jmp.ll @@ -1,7 +1,13 @@ -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC -; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC16 -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 +; RUN: llc -asm-show-inst -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC +; RUN: llc -asm-show-inst -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC +; RUN: llc -asm-show-inst -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC16 +; RUN: llc -asm-show-inst -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC16 +; RUN: llc -asm-show-inst -march=mips -mattr=+micromips -relocation-model=static < %s | FileCheck %s -check-prefix=STATICMM +; RUN: llc -asm-show-inst -march=mips -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=PICMM +; RUN: llc -asm-show-inst -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=static < %s | FileCheck %s -check-prefix=STATICMMR6 +; RUN: llc -asm-show-inst -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC + + define void @count(i32 %x, i32 %y, i32 %z) noreturn nounwind readnone { entry: @@ -11,8 +17,10 @@ bosco: ; preds = %bosco, %entry br label %bosco } -; CHECK-PIC: b $BB0_1 -; CHECK-STATIC: j $BB0_1 -; CHECK-PIC16: b $BB0_1 -; CHECK-STATIC16: b $BB0_1 - +; PIC: b $BB0_1 # <MCInst #{{.*}} BEQ +; PICMM: b $BB0_1 # <MCInst #{{.*}} BEQ_MM +; STATIC: j $BB0_1 # <MCInst #{{.*}} J +; STATICMM: j $BB0_1 # <MCInst #{{.*}} J_MM +; STATICMMR6: bc $BB0_1 # <MCInst #{{.*}} BC_MMR6 +; PIC16: b $BB0_1 +; STATIC16: b $BB0_1 diff --git a/test/CodeGen/Mips/brconge.ll b/test/CodeGen/Mips/brconge.ll index f3f059ff2d54c..910d81c5689a9 100644 --- a/test/CodeGen/Mips/brconge.ll +++ b/test/CodeGen/Mips/brconge.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/test/CodeGen/Mips/brconle.ll b/test/CodeGen/Mips/brconle.ll index 99599f84db17e..4267dc985de3b 100644 --- a/test/CodeGen/Mips/brconle.ll +++ b/test/CodeGen/Mips/brconle.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16 @i = global i32 -5, align 4 @j = global i32 10, align 4 diff --git a/test/CodeGen/Mips/brind-tailcall.ll b/test/CodeGen/Mips/brind-tailcall.ll new file mode 100644 index 0000000000000..78fb0f151077c --- /dev/null +++ b/test/CodeGen/Mips/brind-tailcall.ll @@ -0,0 +1,60 @@ +; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \ +; RUN: -relocation-model=pic < %s 2>&1 | FileCheck --check-prefix=PIC %s +; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \ +; RUN: -relocation-model=static < %s 2>&1 | FileCheck --check-prefix=STATIC %s +; RUN: llc -march=mips64 -debug-only=isel -mips-tail-calls=1 \ +; RUN: -relocation-model=pic < %s 2>&1 | FileCheck --check-prefix=PIC64 %s +; RUN: llc -march=mips64 -debug-only=isel -mips-tail-calls=1 \ +; RUN: -relocation-model=static < %s 2>&1 | FileCheck --check-prefix=STATIC64 %s +; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \ +; RUN: -relocation-model=pic -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=PIC %s +; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \ +; RUN: -relocation-model=static -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=STATIC-MM %s +; RUN: llc -march=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \ +; RUN: -relocation-model=pic -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=PIC %s +; RUN: llc -march=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \ +; RUN: -relocation-model=static -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=STATIC-MM %s +; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \ +; RUN: -relocation-model=pic -mattr=+mips16 < %s 2>&1 | FileCheck --check-prefix=MIPS16 %s +; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \ +; RUN: -relocation-model=static -mattr=+mips16 < %s 2>&1 | FileCheck --check-prefix=MIPS16 %s + +; REQUIRES: asserts + +; Test that the correct pseudo instructions are generated for indirect +; branches and tail calls. Previously, the order of the DAG matcher table +; determined if the correct instruction was selected for mips16. + +declare protected void @a() + +define void @test1(i32 %a) { +entry: + %0 = trunc i32 %a to i1 + %1 = select i1 %0, + i8* blockaddress(@test1, %bb), + i8* blockaddress(@test1, %bb6) + indirectbr i8* %1, [label %bb, label %bb6] + +; STATIC: PseudoIndirectBranch +; STATIC-MM: PseudoIndirectBranch +; STATIC-NOT: PseudoIndirectBranch64 +; STATIC64: PseudoIndirectBranch64 +; PIC: PseudoIndirectBranch +; PIC-NOT: PseudoIndirectBranch64 +; PIC64: PseudoIndirectBranch64 +; MIPS16: JrcRx16 +bb: + ret void + +bb6: + tail call void @a() + +; STATIC: TAILCALL +; STATIC-NOT: TAILCALL_MM +; STATIC-MM: TAILCALL_MM +; PIC: TAILCALLREG +; PIC-NOT: TAILCALLREG64 +; PIC64: TAILCALLREG64 +; MIPS16: RetRA16 + ret void +} diff --git a/test/CodeGen/Mips/cannot-copy-registers.ll b/test/CodeGen/Mips/cannot-copy-registers.ll deleted file mode 100644 index 75cceb2011eb6..0000000000000 --- a/test/CodeGen/Mips/cannot-copy-registers.ll +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+micromips \ -; RUN: -relocation-model=pic -O3 < %s - -; Check that message "Cannot copy registers" is not asserted in case of microMIPS64r6. - -@x = global i32 65504, align 4 -@y = global i32 60929, align 4 -@.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1 - -define i32 @main() nounwind { -entry: - %0 = load i32, i32* @x, align 4 - %and1 = and i32 %0, 4 - %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds - ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and1) - - %1 = load i32, i32* @y, align 4 - %and2 = and i32 %1, 5 - %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds - ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and2) - ret i32 0 -} - -declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/cconv/vector.ll b/test/CodeGen/Mips/cconv/vector.ll index 5a88d064fe735..02d6272bb7eb9 100644 --- a/test/CodeGen/Mips/cconv/vector.ll +++ b/test/CodeGen/Mips/cconv/vector.ll @@ -821,8 +821,10 @@ entry: ; MIPS32R5: jal ; MIPS32R5: sw $2, {{[0-9]+}}($sp) -; MIPS32R5-DAG: sb ${{[0-9]+}}, 1(${{[0-9]+}}) -; MIPS32R5-DAG; sb ${{[0-9]+}}, %lo(gv2i8)(${{[0-9]+}}) +; MIPS32R5-DAG; sh ${{[0-9]+}}, %lo(gv2i8)(${{[0-9]+}}) + +; MIPS32R5-NOT: sb ${{[0-9]+}}, 1(${{[0-9]+}}) +; MIPS32R5-NOT; sb ${{[0-9]+}}, %lo(gv2i8)(${{[0-9]+}}) ; MIPS64EB: daddiu $4, $zero, 1543 ; MIPS64EB: daddiu $5, $zero, 3080 @@ -870,14 +872,14 @@ entry: ; MIPS32-NOT: ori $6 ; MIPS32-NOT: ori $7 -; MIPS32R5-DAG: lw $4, {{[0-9]+}}($sp) -; MIPS32R5-DAG: lw $5, {{[0-9]+}}($sp) +; MIPS32R5-NOT: lw $4, {{[0-9]+}}($sp) +; MIPS32R5-NOT: lw $5, {{[0-9]+}}($sp) ; MIPS64: ori $4 ; MIPS64: ori $5 -; MIPS64R5: lw $4 -; MIPS64R5: lw $5 +; MIPS64R5-NOT: lw $4 +; MIPS64R5-NOT: lw $5 ; MIPS32: jal i8_4 ; MIPS64: jalr $25 @@ -996,14 +998,14 @@ entry: ; MIPS32-DAG: ori $4 ; MIPS32-DAG: ori $5 -; MIPS32R5-DAG: lw $4 -; MIPS32R5-DAG: lw $5 +; MIPS32R5-NOT: lw $4 +; MIPS32R5-NOT: lw $5 ; MIPS64: ori $4 ; MIPS64: ori $5 -; MIPS64R5-DAG: lw $4 -; MIPS64R5-DAG: lw $5 +; MIPS64R5-NOT: lw $4 +; MIPS64R5-NOT: lw $5 ; MIPS32: jal i16_2 ; MIPS64: jalr $25 @@ -1037,8 +1039,8 @@ entry: ; MIPS64-DAG: daddiu $4 ; MIPS64-DAG: daddiu $5 -; MIPS64R5-DAG: ld $4 -; MIPS64R5-DAG: ld $5 +; MIPS64R5-NOT: ld $4 +; MIPS64R5-NOT: ld $5 ; MIPS32: jal i16_4 ; MIPS64: jalr $25 @@ -1133,8 +1135,8 @@ entry: ; MIPS64: daddiu $4 ; MIPS64: daddiu $5 -; MIPS64R5-DAG: ld $4 -; MIPS64R5-DAG: ld $5 +; MIPS64R5-NOT ld $4 +; MIPS64R5-NOT: ld $5 ; MIPS32: jal i32_2 ; MIPS64: jalr $25 diff --git a/test/CodeGen/Mips/compactbranches/empty-block.mir b/test/CodeGen/Mips/compactbranches/empty-block.mir index 7fb1afae91210..5bfaef0cb6933 100644 --- a/test/CodeGen/Mips/compactbranches/empty-block.mir +++ b/test/CodeGen/Mips/compactbranches/empty-block.mir @@ -5,11 +5,11 @@ # CHECK: blezc # CHECK: nop -# CHECK: # BB#1: +# CHECK: # %bb.1: # CHECK: .insn -# CHECK: # BB#2: +# CHECK: # %bb.2: # CHECK: .insn -# CHECK: # BB#3: +# CHECK: # %bb.3: # CHECK: jal --- | diff --git a/test/CodeGen/Mips/const-mult.ll b/test/CodeGen/Mips/const-mult.ll index 7f4e896572a67..459aad61828c4 100644 --- a/test/CodeGen/Mips/const-mult.ll +++ b/test/CodeGen/Mips/const-mult.ll @@ -46,3 +46,48 @@ entry: %mul = mul nsw i64 %a, -9223372036854775805 ret i64 %mul } + +; CHECK64-LABEL: muln170141183460469231731687303715884105725_128: +; CHECK64-DAG: dsrl $[[R0:[0-9]+]], $4, 63 +; CHECK64-DAG: dsll $[[R1:[0-9]+]], $5, 1 +; CHECK64-DAG: or $[[R2:[0-9]+]], $[[R1]], $[[R0]] +; CHECK64-DAG: daddu $[[R3:[0-9]+]], $[[R2]], $5 +; CHECK64-DAG: dsll $[[R4:[0-9]+]], $4, 1 +; CHECK64-DAG: daddu $[[R5:[0-9]+]], $[[R4]], $4 +; CHECK64-DAG: sltu $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK64-DAG: dsll $[[R7:[0-9]+]], $[[R6]], 32 +; CHECK64-DAG: dsrl $[[R8:[0-9]+]], $[[R7]], 32 +; CHECK64-DAG: daddu $[[R9:[0-9]+]], $[[R3]], $[[R8]] +; CHECK64-DAG: dsll $[[R10:[0-9]+]], $4, 63 +; CHECK64: daddu ${{[0-9]+}}, $[[R10]], $[[R9]] + +define i128 @muln170141183460469231731687303715884105725_128(i128 signext %a) { +entry: + %mul = mul nsw i128 %a, -170141183460469231731687303715884105725 + ret i128 %mul +} + +; CHECK64-LABEL: mul170141183460469231731687303715884105723_128: +; CHECK64-DAG: dsrl $[[R0:[0-9]+]], $4, 62 +; CHECK64-DAG: dsll $[[R1:[0-9]+]], $5, 2 +; CHECK64-DAG: or $[[R2:[0-9]+]], $[[R1]], $[[R0]] +; CHECK64-DAG: daddu $[[R3:[0-9]+]], $[[R2]], $5 +; CHECK64-DAG: dsll $[[R4:[0-9]+]], $4, 2 +; CHECK64-DAG: daddu $[[R5:[0-9]+]], $[[R4]], $4 +; CHECK64-DAG: sltu $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK64-DAG: dsll $[[R7:[0-9]+]], $[[R6]], 32 +; CHECK64-DAG: dsrl $[[R8:[0-9]+]], $[[R7]], 32 +; CHECK64-DAG: daddu $[[R9:[0-9]+]], $[[R3]], $[[R8]] +; CHECK64-DAG: dsll $[[R10:[0-9]+]], $4, 63 +; CHECK64-DAG: dsubu $[[R11:[0-9]+]], $[[R10]], $[[R9]] +; CHECK64-DAG: sltu $[[R12:[0-9]+]], $zero, $[[R5]] +; CHECK64-DAG: dsll $[[R13:[0-9]+]], $[[R12]], 32 +; CHECK64-DAG: dsrl $[[R14:[0-9]+]], $[[R13]], 32 +; CHECK64-DAG: dsubu $[[R15:[0-9]+]], $[[R11]], $[[R14]] +; CHECK64: dnegu ${{[0-9]+}}, $[[R5]] + +define i128 @mul170141183460469231731687303715884105723_128(i128 signext %a) { +entry: + %mul = mul nsw i128 %a, 170141183460469231731687303715884105723 + ret i128 %mul +} diff --git a/test/CodeGen/Mips/countleading.ll b/test/CodeGen/Mips/countleading.ll index 1b61be5ed2ac4..35933f668fb97 100644 --- a/test/CodeGen/Mips/countleading.ll +++ b/test/CodeGen/Mips/countleading.ll @@ -5,7 +5,6 @@ ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s ; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s -; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS64 %s ; Prefixes: ; ALL - All @@ -22,8 +21,6 @@ entry: ; MIPS64-GT-R1: clz $2, $4 -; MICROMIPS64: clz $2, $4 - %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true) ret i32 %tmp1 } @@ -40,8 +37,6 @@ entry: ; MIPS64-GT-R1: clo $2, $4 -; MICROMIPS64: clo $2, $4 - %neg = xor i32 %X, -1 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true) ret i32 %tmp1 @@ -63,7 +58,6 @@ entry: ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 ; MIPS64-GT-R1: dclz $2, $4 -; MICROMIPS64: dclz $2, $4 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) ret i64 %tmp1 @@ -89,7 +83,6 @@ entry: ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 ; MIPS64-GT-R1: dclo $2, $4 -; MICROMIPS64: dclo $2, $4 %neg = xor i64 %X, -1 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) diff --git a/test/CodeGen/Mips/cstmaterialization/constMaterialization.ll b/test/CodeGen/Mips/cstmaterialization/constMaterialization.ll new file mode 100644 index 0000000000000..f34c70efa7a80 --- /dev/null +++ b/test/CodeGen/Mips/cstmaterialization/constMaterialization.ll @@ -0,0 +1,136 @@ +; RUN: llc -march=mips < %s | FileCheck %s -check-prefixes=ALL,MIPS +; RUN: llc -march=mips < %s -mattr=+micromips | FileCheck %s -check-prefixes=ALL,MM + +; Test the patterns used for constant materialization. + +; Constants generated using li16 +define i32 @Li16LowBoundary() { +entry: + ; ALL-LABEL: Li16LowBoundary: + ; MIPS: addiu $2, $zero, -1 + ; MM: li16 $2, -1 + ; ALL-NOT: lui + ; ALL-NOT: ori + ; MIPS-NOT: li16 + ; MM-NOT: addiu + + ret i32 -1 +} + +define i32 @Li16HighBoundary() { +entry: + ; ALL-LABEL: Li16HighBoundary: + ; MIPS: addiu $2, $zero, 126 + ; MM: li16 $2, 126 + ; ALL-NOT: lui + ; ALL-NOT: ori + ; MM-NOT: addiu + ; MIPS-NOT: li16 + + ret i32 126 +} + +; Constants generated using addiu +define i32 @AddiuLowBoundary() { +entry: + ; ALL-LABEL: AddiuLowBoundary: + ; ALL: addiu $2, $zero, -32768 + ; ALL-NOT: lui + ; ALL-NOT: ori + ; ALL-NOT: li16 + + ret i32 -32768 +} + +define i32 @AddiuZero() { +entry: + ; ALL-LABEL: AddiuZero: + ; MIPS: addiu $2, $zero, 0 + ; MM: li16 $2, 0 + ; ALL-NOT: lui + ; ALL-NOT: ori + ; MIPS-NOT: li16 + ; MM-NOT: addiu + + ret i32 0 +} + +define i32 @AddiuHighBoundary() { +entry: + ; ALL-LABEL: AddiuHighBoundary: + ; ALL: addiu $2, $zero, 32767 + ; ALL-NOT: lui + ; ALL-NOT: ori + ; ALL-NOT: li16 + + ret i32 32767 +} + +; Constants generated using ori +define i32 @OriLowBoundary() { +entry: + ; ALL-LABEL: OriLowBoundary: + ; ALL: ori $2, $zero, 32768 + ; ALL-NOT: addiu + ; ALL-NOT: lui + ; ALL-NOT: li16 + + ret i32 32768 +} + +define i32 @OriHighBoundary() { +entry: + ; ALL-LABEL: OriHighBoundary: + ; ALL: ori $2, $zero, 65535 + ; ALL-NOT: addiu + ; ALL-NOT: lui + ; ALL-NOT: li16 + + ret i32 65535 +} + +; Constants generated using lui +define i32 @LuiPositive() { +entry: + ; ALL-LABEL: LuiPositive: + ; ALL: lui $2, 1 + ; ALL-NOT: addiu + ; ALL-NOT: ori + ; ALL-NOT: li16 + + ret i32 65536 +} + +define i32 @LuiNegative() { +entry: + ; ALL-LABEL: LuiNegative: + ; ALL: lui $2, 65535 + ; ALL-NOT: addiu + ; ALL-NOT: ori + ; ALL-NOT: li16 + + ret i32 -65536 +} + +; Constants generated using a combination of lui and ori +define i32 @LuiWithLowBitsSet() { +entry: + ; ALL-LABEL: LuiWithLowBitsSet: + ; ALL: lui $1, 1 + ; ALL: ori $2, $1, 1 + ; ALL-NOT: addiu + ; ALL-NOT: li16 + + ret i32 65537 +} + +define i32 @BelowAddiuLowBoundary() { +entry: + ; ALL-LABEL: BelowAddiuLowBoundary: + ; ALL: lui $1, 65535 + ; ALL: ori $2, $1, 32767 + ; ALL-NOT: addiu + ; ALL-NOT: li16 + + ret i32 -32769 +} diff --git a/test/CodeGen/Mips/dagcombine-store-gep-chain-slow.ll b/test/CodeGen/Mips/dagcombine-store-gep-chain-slow.ll new file mode 100644 index 0000000000000..c4ceff83cc183 --- /dev/null +++ b/test/CodeGen/Mips/dagcombine-store-gep-chain-slow.ll @@ -0,0 +1,613 @@ +; RUN: llc < %s -march=mips -mcpu=mips32r6 -o /dev/null + +; Test that this file is compiled in a reasonable time period. Without the +; optimization level check in findBetterNeighbors, this test demonstrates +; a severe compile time regression (30~ minutes) vs. <10 seconds at 'optnone'. + +declare i8 @k(i8*) + +define void @d(i32 signext %e4) #1 { +entry: + %e4.addr = alloca i32, align 4 + %old_val = alloca i8, align 1 + %new_val = alloca i8, align 1 + %simd = alloca i8, align 1 + %code = alloca [269 x i8], align 1 + store i32 %e4, i32* %e4.addr, align 4 + %call = call zeroext i8 @k(i8* %simd) + store i8 %call, i8* %simd, align 1 + + %arrayinit.begin = getelementptr inbounds [269 x i8], [269 x i8]* %code, i32 0, i32 0 + store i8 32, i8* %arrayinit.begin, align 1 + %arrayinit.element = getelementptr inbounds i8, i8* %arrayinit.begin, i32 1 + %a2 = load i8, i8* %old_val, align 1 + store i8 %a2, i8* %arrayinit.element, align 1 + %arrayinit.element1 = getelementptr inbounds i8, i8* %arrayinit.element, i32 1 + store i8 -3, i8* %arrayinit.element1, align 1 + %arrayinit.element2 = getelementptr inbounds i8, i8* %arrayinit.element1, i32 1 + store i8 0, i8* %arrayinit.element2, align 1 + %arrayinit.element3 = getelementptr inbounds i8, i8* %arrayinit.element2, i32 1 + store i8 33, i8* %arrayinit.element3, align 1 + %arrayinit.element4 = getelementptr inbounds i8, i8* %arrayinit.element3, i32 1 + %a3 = load i8, i8* %simd, align 1 + store i8 %a3, i8* %arrayinit.element4, align 1 + %arrayinit.element5 = getelementptr inbounds i8, i8* %arrayinit.element4, i32 1 + store i8 32, i8* %arrayinit.element5, align 1 + %arrayinit.element6 = getelementptr inbounds i8, i8* %arrayinit.element5, i32 1 + %a4 = load i8, i8* %simd, align 1 + store i8 %a4, i8* %arrayinit.element6, align 1 + %arrayinit.element7 = getelementptr inbounds i8, i8* %arrayinit.element6, i32 1 + store i8 32, i8* %arrayinit.element7, align 1 + %arrayinit.element8 = getelementptr inbounds i8, i8* %arrayinit.element7, i32 1 + %a5 = load i8, i8* %new_val, align 1 + store i8 %a5, i8* %arrayinit.element8, align 1 + %arrayinit.element9 = getelementptr inbounds i8, i8* %arrayinit.element8, i32 1 + store i8 -3, i8* %arrayinit.element9, align 1 + %arrayinit.element10 = getelementptr inbounds i8, i8* %arrayinit.element9, i32 1 + store i8 2, i8* %arrayinit.element10, align 1 + %arrayinit.element11 = getelementptr inbounds i8, i8* %arrayinit.element10, i32 1 + store i8 0, i8* %arrayinit.element11, align 1 + %arrayinit.element12 = getelementptr inbounds i8, i8* %arrayinit.element11, i32 1 + store i8 33, i8* %arrayinit.element12, align 1 + %arrayinit.element13 = getelementptr inbounds i8, i8* %arrayinit.element12, i32 1 + %a6 = load i8, i8* %simd, align 1 + store i8 %a6, i8* %arrayinit.element13, align 1 + %arrayinit.element14 = getelementptr inbounds i8, i8* %arrayinit.element13, i32 1 + store i8 32, i8* %arrayinit.element14, align 1 + %arrayinit.element15 = getelementptr inbounds i8, i8* %arrayinit.element14, i32 1 + %a7 = load i8, i8* %new_val, align 1 + store i8 %a7, i8* %arrayinit.element15, align 1 + %arrayinit.element16 = getelementptr inbounds i8, i8* %arrayinit.element15, i32 1 + store i8 32, i8* %arrayinit.element16, align 1 + %arrayinit.element17 = getelementptr inbounds i8, i8* %arrayinit.element16, i32 1 + %a8 = load i8, i8* %simd, align 1 + store i8 %a8, i8* %arrayinit.element17, align 1 + %arrayinit.element18 = getelementptr inbounds i8, i8* %arrayinit.element17, i32 1 + store i8 -3, i8* %arrayinit.element18, align 1 + %arrayinit.element19 = getelementptr inbounds i8, i8* %arrayinit.element18, i32 1 + store i8 1, i8* %arrayinit.element19, align 1 + %arrayinit.element20 = getelementptr inbounds i8, i8* %arrayinit.element19, i32 1 + store i8 0, i8* %arrayinit.element20, align 1 + %arrayinit.element21 = getelementptr inbounds i8, i8* %arrayinit.element20, i32 1 + store i8 92, i8* %arrayinit.element21, align 1 + %arrayinit.element22 = getelementptr inbounds i8, i8* %arrayinit.element21, i32 1 + store i8 4, i8* %arrayinit.element22, align 1 + %arrayinit.element23 = getelementptr inbounds i8, i8* %arrayinit.element22, i32 1 + store i8 64, i8* %arrayinit.element23, align 1 + %arrayinit.element24 = getelementptr inbounds i8, i8* %arrayinit.element23, i32 1 + store i8 65, i8* %arrayinit.element24, align 1 + %arrayinit.element25 = getelementptr inbounds i8, i8* %arrayinit.element24, i32 1 + store i8 0, i8* %arrayinit.element25, align 1 + %arrayinit.element26 = getelementptr inbounds i8, i8* %arrayinit.element25, i32 1 + store i8 15, i8* %arrayinit.element26, align 1 + %arrayinit.element27 = getelementptr inbounds i8, i8* %arrayinit.element26, i32 1 + store i8 11, i8* %arrayinit.element27, align 1 + %arrayinit.element28 = getelementptr inbounds i8, i8* %arrayinit.element27, i32 1 + store i8 32, i8* %arrayinit.element28, align 1 + %arrayinit.element29 = getelementptr inbounds i8, i8* %arrayinit.element28, i32 1 + %a9 = load i8, i8* %old_val, align 1 + store i8 %a9, i8* %arrayinit.element29, align 1 + %arrayinit.element30 = getelementptr inbounds i8, i8* %arrayinit.element29, i32 1 + store i8 32, i8* %arrayinit.element30, align 1 + %arrayinit.element31 = getelementptr inbounds i8, i8* %arrayinit.element30, i32 1 + %a10 = load i8, i8* %simd, align 1 + store i8 %a10, i8* %arrayinit.element31, align 1 + %arrayinit.element32 = getelementptr inbounds i8, i8* %arrayinit.element31, i32 1 + store i8 -3, i8* %arrayinit.element32, align 1 + %arrayinit.element33 = getelementptr inbounds i8, i8* %arrayinit.element32, i32 1 + store i8 1, i8* %arrayinit.element33, align 1 + %arrayinit.element34 = getelementptr inbounds i8, i8* %arrayinit.element33, i32 1 + store i8 1, i8* %arrayinit.element34, align 1 + %arrayinit.element35 = getelementptr inbounds i8, i8* %arrayinit.element34, i32 1 + store i8 92, i8* %arrayinit.element35, align 1 + %arrayinit.element36 = getelementptr inbounds i8, i8* %arrayinit.element35, i32 1 + store i8 4, i8* %arrayinit.element36, align 1 + %arrayinit.element37 = getelementptr inbounds i8, i8* %arrayinit.element36, i32 1 + store i8 64, i8* %arrayinit.element37, align 1 + %arrayinit.element38 = getelementptr inbounds i8, i8* %arrayinit.element37, i32 1 + store i8 65, i8* %arrayinit.element38, align 1 + %arrayinit.element39 = getelementptr inbounds i8, i8* %arrayinit.element38, i32 1 + store i8 0, i8* %arrayinit.element39, align 1 + %arrayinit.element40 = getelementptr inbounds i8, i8* %arrayinit.element39, i32 1 + store i8 15, i8* %arrayinit.element40, align 1 + %arrayinit.element41 = getelementptr inbounds i8, i8* %arrayinit.element40, i32 1 + store i8 11, i8* %arrayinit.element41, align 1 + %arrayinit.element42 = getelementptr inbounds i8, i8* %arrayinit.element41, i32 1 + store i8 32, i8* %arrayinit.element42, align 1 + %arrayinit.element43 = getelementptr inbounds i8, i8* %arrayinit.element42, i32 1 + %a11 = load i8, i8* %old_val, align 1 + store i8 %a11, i8* %arrayinit.element43, align 1 + %arrayinit.element44 = getelementptr inbounds i8, i8* %arrayinit.element43, i32 1 + store i8 32, i8* %arrayinit.element44, align 1 + %arrayinit.element45 = getelementptr inbounds i8, i8* %arrayinit.element44, i32 1 + %a12 = load i8, i8* %simd, align 1 + store i8 %a12, i8* %arrayinit.element45, align 1 + %arrayinit.element46 = getelementptr inbounds i8, i8* %arrayinit.element45, i32 1 + store i8 -3, i8* %arrayinit.element46, align 1 + %arrayinit.element47 = getelementptr inbounds i8, i8* %arrayinit.element46, i32 1 + store i8 1, i8* %arrayinit.element47, align 1 + %arrayinit.element48 = getelementptr inbounds i8, i8* %arrayinit.element47, i32 1 + store i8 2, i8* %arrayinit.element48, align 1 + %arrayinit.element49 = getelementptr inbounds i8, i8* %arrayinit.element48, i32 1 + store i8 92, i8* %arrayinit.element49, align 1 + %arrayinit.element50 = getelementptr inbounds i8, i8* %arrayinit.element49, i32 1 + store i8 4, i8* %arrayinit.element50, align 1 + %arrayinit.element51 = getelementptr inbounds i8, i8* %arrayinit.element50, i32 1 + store i8 64, i8* %arrayinit.element51, align 1 + %arrayinit.element52 = getelementptr inbounds i8, i8* %arrayinit.element51, i32 1 + store i8 65, i8* %arrayinit.element52, align 1 + %arrayinit.element53 = getelementptr inbounds i8, i8* %arrayinit.element52, i32 1 + store i8 0, i8* %arrayinit.element53, align 1 + %arrayinit.element54 = getelementptr inbounds i8, i8* %arrayinit.element53, i32 1 + store i8 15, i8* %arrayinit.element54, align 1 + %arrayinit.element55 = getelementptr inbounds i8, i8* %arrayinit.element54, i32 1 + store i8 11, i8* %arrayinit.element55, align 1 + %arrayinit.element56 = getelementptr inbounds i8, i8* %arrayinit.element55, i32 1 + store i8 32, i8* %arrayinit.element56, align 1 + %arrayinit.element57 = getelementptr inbounds i8, i8* %arrayinit.element56, i32 1 + %a13 = load i8, i8* %old_val, align 1 + store i8 %a13, i8* %arrayinit.element57, align 1 + %arrayinit.element58 = getelementptr inbounds i8, i8* %arrayinit.element57, i32 1 + store i8 32, i8* %arrayinit.element58, align 1 + %arrayinit.element59 = getelementptr inbounds i8, i8* %arrayinit.element58, i32 1 + %a14 = load i8, i8* %simd, align 1 + store i8 %a14, i8* %arrayinit.element59, align 1 + %arrayinit.element60 = getelementptr inbounds i8, i8* %arrayinit.element59, i32 1 + store i8 -3, i8* %arrayinit.element60, align 1 + %arrayinit.element61 = getelementptr inbounds i8, i8* %arrayinit.element60, i32 1 + store i8 1, i8* %arrayinit.element61, align 1 + %arrayinit.element62 = getelementptr inbounds i8, i8* %arrayinit.element61, i32 1 + store i8 3, i8* %arrayinit.element62, align 1 + %arrayinit.element63 = getelementptr inbounds i8, i8* %arrayinit.element62, i32 1 + store i8 92, i8* %arrayinit.element63, align 1 + %arrayinit.element64 = getelementptr inbounds i8, i8* %arrayinit.element63, i32 1 + store i8 4, i8* %arrayinit.element64, align 1 + %arrayinit.element65 = getelementptr inbounds i8, i8* %arrayinit.element64, i32 1 + store i8 64, i8* %arrayinit.element65, align 1 + %arrayinit.element66 = getelementptr inbounds i8, i8* %arrayinit.element65, i32 1 + store i8 65, i8* %arrayinit.element66, align 1 + %arrayinit.element67 = getelementptr inbounds i8, i8* %arrayinit.element66, i32 1 + store i8 0, i8* %arrayinit.element67, align 1 + %arrayinit.element68 = getelementptr inbounds i8, i8* %arrayinit.element67, i32 1 + store i8 15, i8* %arrayinit.element68, align 1 + %arrayinit.element69 = getelementptr inbounds i8, i8* %arrayinit.element68, i32 1 + store i8 11, i8* %arrayinit.element69, align 1 + %arrayinit.element70 = getelementptr inbounds i8, i8* %arrayinit.element69, i32 1 + store i8 32, i8* %arrayinit.element70, align 1 + %arrayinit.element71 = getelementptr inbounds i8, i8* %arrayinit.element70, i32 1 + %a15 = load i8, i8* %simd, align 1 + store i8 %a15, i8* %arrayinit.element71, align 1 + %arrayinit.element72 = getelementptr inbounds i8, i8* %arrayinit.element71, i32 1 + store i8 32, i8* %arrayinit.element72, align 1 + %arrayinit.element73 = getelementptr inbounds i8, i8* %arrayinit.element72, i32 1 + %a16 = load i8, i8* %new_val, align 1 + store i8 %a16, i8* %arrayinit.element73, align 1 + %arrayinit.element74 = getelementptr inbounds i8, i8* %arrayinit.element73, i32 1 + store i8 -3, i8* %arrayinit.element74, align 1 + %arrayinit.element75 = getelementptr inbounds i8, i8* %arrayinit.element74, i32 1 + store i8 2, i8* %arrayinit.element75, align 1 + %arrayinit.element76 = getelementptr inbounds i8, i8* %arrayinit.element75, i32 1 + store i8 1, i8* %arrayinit.element76, align 1 + %arrayinit.element77 = getelementptr inbounds i8, i8* %arrayinit.element76, i32 1 + store i8 33, i8* %arrayinit.element77, align 1 + %arrayinit.element78 = getelementptr inbounds i8, i8* %arrayinit.element77, i32 1 + %a17 = load i8, i8* %simd, align 1 + store i8 %a17, i8* %arrayinit.element78, align 1 + %arrayinit.element79 = getelementptr inbounds i8, i8* %arrayinit.element78, i32 1 + store i8 32, i8* %arrayinit.element79, align 1 + %arrayinit.element80 = getelementptr inbounds i8, i8* %arrayinit.element79, i32 1 + %a18 = load i8, i8* %new_val, align 1 + store i8 %a18, i8* %arrayinit.element80, align 1 + %arrayinit.element81 = getelementptr inbounds i8, i8* %arrayinit.element80, i32 1 + store i8 32, i8* %arrayinit.element81, align 1 + %arrayinit.element82 = getelementptr inbounds i8, i8* %arrayinit.element81, i32 1 + %a19 = load i8, i8* %simd, align 1 + store i8 %a19, i8* %arrayinit.element82, align 1 + %arrayinit.element83 = getelementptr inbounds i8, i8* %arrayinit.element82, i32 1 + store i8 -3, i8* %arrayinit.element83, align 1 + %arrayinit.element84 = getelementptr inbounds i8, i8* %arrayinit.element83, i32 1 + store i8 1, i8* %arrayinit.element84, align 1 + %arrayinit.element85 = getelementptr inbounds i8, i8* %arrayinit.element84, i32 1 + store i8 0, i8* %arrayinit.element85, align 1 + %arrayinit.element86 = getelementptr inbounds i8, i8* %arrayinit.element85, i32 1 + store i8 92, i8* %arrayinit.element86, align 1 + %arrayinit.element87 = getelementptr inbounds i8, i8* %arrayinit.element86, i32 1 + store i8 4, i8* %arrayinit.element87, align 1 + %arrayinit.element88 = getelementptr inbounds i8, i8* %arrayinit.element87, i32 1 + store i8 64, i8* %arrayinit.element88, align 1 + %arrayinit.element89 = getelementptr inbounds i8, i8* %arrayinit.element88, i32 1 + store i8 65, i8* %arrayinit.element89, align 1 + %arrayinit.element90 = getelementptr inbounds i8, i8* %arrayinit.element89, i32 1 + store i8 0, i8* %arrayinit.element90, align 1 + %arrayinit.element91 = getelementptr inbounds i8, i8* %arrayinit.element90, i32 1 + store i8 15, i8* %arrayinit.element91, align 1 + %arrayinit.element92 = getelementptr inbounds i8, i8* %arrayinit.element91, i32 1 + store i8 11, i8* %arrayinit.element92, align 1 + %arrayinit.element93 = getelementptr inbounds i8, i8* %arrayinit.element92, i32 1 + store i8 32, i8* %arrayinit.element93, align 1 + %arrayinit.element94 = getelementptr inbounds i8, i8* %arrayinit.element93, i32 1 + %a20 = load i8, i8* %new_val, align 1 + store i8 %a20, i8* %arrayinit.element94, align 1 + %arrayinit.element95 = getelementptr inbounds i8, i8* %arrayinit.element94, i32 1 + store i8 32, i8* %arrayinit.element95, align 1 + %arrayinit.element96 = getelementptr inbounds i8, i8* %arrayinit.element95, i32 1 + %a21 = load i8, i8* %simd, align 1 + store i8 %a21, i8* %arrayinit.element96, align 1 + %arrayinit.element97 = getelementptr inbounds i8, i8* %arrayinit.element96, i32 1 + store i8 -3, i8* %arrayinit.element97, align 1 + %arrayinit.element98 = getelementptr inbounds i8, i8* %arrayinit.element97, i32 1 + store i8 1, i8* %arrayinit.element98, align 1 + %arrayinit.element99 = getelementptr inbounds i8, i8* %arrayinit.element98, i32 1 + store i8 1, i8* %arrayinit.element99, align 1 + %arrayinit.element100 = getelementptr inbounds i8, i8* %arrayinit.element99, i32 1 + store i8 92, i8* %arrayinit.element100, align 1 + %arrayinit.element101 = getelementptr inbounds i8, i8* %arrayinit.element100, i32 1 + store i8 4, i8* %arrayinit.element101, align 1 + %arrayinit.element102 = getelementptr inbounds i8, i8* %arrayinit.element101, i32 1 + store i8 64, i8* %arrayinit.element102, align 1 + %arrayinit.element103 = getelementptr inbounds i8, i8* %arrayinit.element102, i32 1 + store i8 65, i8* %arrayinit.element103, align 1 + %arrayinit.element104 = getelementptr inbounds i8, i8* %arrayinit.element103, i32 1 + store i8 0, i8* %arrayinit.element104, align 1 + %arrayinit.element105 = getelementptr inbounds i8, i8* %arrayinit.element104, i32 1 + store i8 15, i8* %arrayinit.element105, align 1 + %arrayinit.element106 = getelementptr inbounds i8, i8* %arrayinit.element105, i32 1 + store i8 11, i8* %arrayinit.element106, align 1 + %arrayinit.element107 = getelementptr inbounds i8, i8* %arrayinit.element106, i32 1 + store i8 32, i8* %arrayinit.element107, align 1 + %arrayinit.element108 = getelementptr inbounds i8, i8* %arrayinit.element107, i32 1 + %a22 = load i8, i8* %old_val, align 1 + store i8 %a22, i8* %arrayinit.element108, align 1 + %arrayinit.element109 = getelementptr inbounds i8, i8* %arrayinit.element108, i32 1 + store i8 32, i8* %arrayinit.element109, align 1 + %arrayinit.element110 = getelementptr inbounds i8, i8* %arrayinit.element109, i32 1 + %a23 = load i8, i8* %simd, align 1 + store i8 %a23, i8* %arrayinit.element110, align 1 + %arrayinit.element111 = getelementptr inbounds i8, i8* %arrayinit.element110, i32 1 + store i8 -3, i8* %arrayinit.element111, align 1 + %arrayinit.element112 = getelementptr inbounds i8, i8* %arrayinit.element111, i32 1 + store i8 1, i8* %arrayinit.element112, align 1 + %arrayinit.element113 = getelementptr inbounds i8, i8* %arrayinit.element112, i32 1 + store i8 2, i8* %arrayinit.element113, align 1 + %arrayinit.element114 = getelementptr inbounds i8, i8* %arrayinit.element113, i32 1 + store i8 92, i8* %arrayinit.element114, align 1 + %arrayinit.element115 = getelementptr inbounds i8, i8* %arrayinit.element114, i32 1 + store i8 4, i8* %arrayinit.element115, align 1 + %arrayinit.element116 = getelementptr inbounds i8, i8* %arrayinit.element115, i32 1 + store i8 64, i8* %arrayinit.element116, align 1 + %arrayinit.element117 = getelementptr inbounds i8, i8* %arrayinit.element116, i32 1 + store i8 65, i8* %arrayinit.element117, align 1 + %arrayinit.element118 = getelementptr inbounds i8, i8* %arrayinit.element117, i32 1 + store i8 0, i8* %arrayinit.element118, align 1 + %arrayinit.element119 = getelementptr inbounds i8, i8* %arrayinit.element118, i32 1 + store i8 15, i8* %arrayinit.element119, align 1 + %arrayinit.element120 = getelementptr inbounds i8, i8* %arrayinit.element119, i32 1 + store i8 11, i8* %arrayinit.element120, align 1 + %arrayinit.element121 = getelementptr inbounds i8, i8* %arrayinit.element120, i32 1 + store i8 32, i8* %arrayinit.element121, align 1 + %arrayinit.element122 = getelementptr inbounds i8, i8* %arrayinit.element121, i32 1 + %a24 = load i8, i8* %old_val, align 1 + store i8 %a24, i8* %arrayinit.element122, align 1 + %arrayinit.element123 = getelementptr inbounds i8, i8* %arrayinit.element122, i32 1 + store i8 32, i8* %arrayinit.element123, align 1 + %arrayinit.element124 = getelementptr inbounds i8, i8* %arrayinit.element123, i32 1 + %a25 = load i8, i8* %simd, align 1 + store i8 %a25, i8* %arrayinit.element124, align 1 + %arrayinit.element125 = getelementptr inbounds i8, i8* %arrayinit.element124, i32 1 + store i8 -3, i8* %arrayinit.element125, align 1 + %arrayinit.element126 = getelementptr inbounds i8, i8* %arrayinit.element125, i32 1 + store i8 1, i8* %arrayinit.element126, align 1 + %arrayinit.element127 = getelementptr inbounds i8, i8* %arrayinit.element126, i32 1 + store i8 3, i8* %arrayinit.element127, align 1 + %arrayinit.element128 = getelementptr inbounds i8, i8* %arrayinit.element127, i32 1 + store i8 92, i8* %arrayinit.element128, align 1 + %arrayinit.element129 = getelementptr inbounds i8, i8* %arrayinit.element128, i32 1 + store i8 4, i8* %arrayinit.element129, align 1 + %arrayinit.element130 = getelementptr inbounds i8, i8* %arrayinit.element129, i32 1 + store i8 64, i8* %arrayinit.element130, align 1 + %arrayinit.element131 = getelementptr inbounds i8, i8* %arrayinit.element130, i32 1 + store i8 65, i8* %arrayinit.element131, align 1 + %arrayinit.element132 = getelementptr inbounds i8, i8* %arrayinit.element131, i32 1 + store i8 0, i8* %arrayinit.element132, align 1 + %arrayinit.element133 = getelementptr inbounds i8, i8* %arrayinit.element132, i32 1 + store i8 15, i8* %arrayinit.element133, align 1 + %arrayinit.element134 = getelementptr inbounds i8, i8* %arrayinit.element133, i32 1 + store i8 11, i8* %arrayinit.element134, align 1 + %arrayinit.element135 = getelementptr inbounds i8, i8* %arrayinit.element134, i32 1 + store i8 32, i8* %arrayinit.element135, align 1 + %arrayinit.element136 = getelementptr inbounds i8, i8* %arrayinit.element135, i32 1 + %a26 = load i8, i8* %simd, align 1 + store i8 %a26, i8* %arrayinit.element136, align 1 + %arrayinit.element137 = getelementptr inbounds i8, i8* %arrayinit.element136, i32 1 + store i8 32, i8* %arrayinit.element137, align 1 + %arrayinit.element138 = getelementptr inbounds i8, i8* %arrayinit.element137, i32 1 + %a27 = load i8, i8* %new_val, align 1 + store i8 %a27, i8* %arrayinit.element138, align 1 + %arrayinit.element139 = getelementptr inbounds i8, i8* %arrayinit.element138, i32 1 + store i8 -3, i8* %arrayinit.element139, align 1 + %arrayinit.element140 = getelementptr inbounds i8, i8* %arrayinit.element139, i32 1 + store i8 2, i8* %arrayinit.element140, align 1 + %arrayinit.element141 = getelementptr inbounds i8, i8* %arrayinit.element140, i32 1 + store i8 2, i8* %arrayinit.element141, align 1 + %arrayinit.element142 = getelementptr inbounds i8, i8* %arrayinit.element141, i32 1 + store i8 33, i8* %arrayinit.element142, align 1 + %arrayinit.element143 = getelementptr inbounds i8, i8* %arrayinit.element142, i32 1 + %a28 = load i8, i8* %simd, align 1 + store i8 %a28, i8* %arrayinit.element143, align 1 + %arrayinit.element144 = getelementptr inbounds i8, i8* %arrayinit.element143, i32 1 + store i8 32, i8* %arrayinit.element144, align 1 + %arrayinit.element145 = getelementptr inbounds i8, i8* %arrayinit.element144, i32 1 + %a29 = load i8, i8* %new_val, align 1 + store i8 %a29, i8* %arrayinit.element145, align 1 + %arrayinit.element146 = getelementptr inbounds i8, i8* %arrayinit.element145, i32 1 + store i8 32, i8* %arrayinit.element146, align 1 + %arrayinit.element147 = getelementptr inbounds i8, i8* %arrayinit.element146, i32 1 + %a30 = load i8, i8* %simd, align 1 + store i8 %a30, i8* %arrayinit.element147, align 1 + %arrayinit.element148 = getelementptr inbounds i8, i8* %arrayinit.element147, i32 1 + store i8 -3, i8* %arrayinit.element148, align 1 + %arrayinit.element149 = getelementptr inbounds i8, i8* %arrayinit.element148, i32 1 + store i8 1, i8* %arrayinit.element149, align 1 + %arrayinit.element150 = getelementptr inbounds i8, i8* %arrayinit.element149, i32 1 + store i8 0, i8* %arrayinit.element150, align 1 + %arrayinit.element151 = getelementptr inbounds i8, i8* %arrayinit.element150, i32 1 + store i8 92, i8* %arrayinit.element151, align 1 + %arrayinit.element152 = getelementptr inbounds i8, i8* %arrayinit.element151, i32 1 + store i8 4, i8* %arrayinit.element152, align 1 + %arrayinit.element153 = getelementptr inbounds i8, i8* %arrayinit.element152, i32 1 + store i8 64, i8* %arrayinit.element153, align 1 + %arrayinit.element154 = getelementptr inbounds i8, i8* %arrayinit.element153, i32 1 + store i8 65, i8* %arrayinit.element154, align 1 + %arrayinit.element155 = getelementptr inbounds i8, i8* %arrayinit.element154, i32 1 + store i8 0, i8* %arrayinit.element155, align 1 + %arrayinit.element156 = getelementptr inbounds i8, i8* %arrayinit.element155, i32 1 + store i8 15, i8* %arrayinit.element156, align 1 + %arrayinit.element157 = getelementptr inbounds i8, i8* %arrayinit.element156, i32 1 + store i8 11, i8* %arrayinit.element157, align 1 + %arrayinit.element158 = getelementptr inbounds i8, i8* %arrayinit.element157, i32 1 + store i8 32, i8* %arrayinit.element158, align 1 + %arrayinit.element159 = getelementptr inbounds i8, i8* %arrayinit.element158, i32 1 + %a31 = load i8, i8* %new_val, align 1 + store i8 %a31, i8* %arrayinit.element159, align 1 + %arrayinit.element160 = getelementptr inbounds i8, i8* %arrayinit.element159, i32 1 + store i8 32, i8* %arrayinit.element160, align 1 + %arrayinit.element161 = getelementptr inbounds i8, i8* %arrayinit.element160, i32 1 + %a32 = load i8, i8* %simd, align 1 + store i8 %a32, i8* %arrayinit.element161, align 1 + %arrayinit.element162 = getelementptr inbounds i8, i8* %arrayinit.element161, i32 1 + store i8 -3, i8* %arrayinit.element162, align 1 + %arrayinit.element163 = getelementptr inbounds i8, i8* %arrayinit.element162, i32 1 + store i8 1, i8* %arrayinit.element163, align 1 + %arrayinit.element164 = getelementptr inbounds i8, i8* %arrayinit.element163, i32 1 + store i8 1, i8* %arrayinit.element164, align 1 + %arrayinit.element165 = getelementptr inbounds i8, i8* %arrayinit.element164, i32 1 + store i8 92, i8* %arrayinit.element165, align 1 + %arrayinit.element166 = getelementptr inbounds i8, i8* %arrayinit.element165, i32 1 + store i8 4, i8* %arrayinit.element166, align 1 + %arrayinit.element167 = getelementptr inbounds i8, i8* %arrayinit.element166, i32 1 + store i8 64, i8* %arrayinit.element167, align 1 + %arrayinit.element168 = getelementptr inbounds i8, i8* %arrayinit.element167, i32 1 + store i8 65, i8* %arrayinit.element168, align 1 + %arrayinit.element169 = getelementptr inbounds i8, i8* %arrayinit.element168, i32 1 + store i8 0, i8* %arrayinit.element169, align 1 + %arrayinit.element170 = getelementptr inbounds i8, i8* %arrayinit.element169, i32 1 + store i8 15, i8* %arrayinit.element170, align 1 + %arrayinit.element171 = getelementptr inbounds i8, i8* %arrayinit.element170, i32 1 + store i8 11, i8* %arrayinit.element171, align 1 + %arrayinit.element172 = getelementptr inbounds i8, i8* %arrayinit.element171, i32 1 + store i8 32, i8* %arrayinit.element172, align 1 + %arrayinit.element173 = getelementptr inbounds i8, i8* %arrayinit.element172, i32 1 + %a33 = load i8, i8* %new_val, align 1 + store i8 %a33, i8* %arrayinit.element173, align 1 + %arrayinit.element174 = getelementptr inbounds i8, i8* %arrayinit.element173, i32 1 + store i8 32, i8* %arrayinit.element174, align 1 + %arrayinit.element175 = getelementptr inbounds i8, i8* %arrayinit.element174, i32 1 + %a34 = load i8, i8* %simd, align 1 + store i8 %a34, i8* %arrayinit.element175, align 1 + %arrayinit.element176 = getelementptr inbounds i8, i8* %arrayinit.element175, i32 1 + store i8 -3, i8* %arrayinit.element176, align 1 + %arrayinit.element177 = getelementptr inbounds i8, i8* %arrayinit.element176, i32 1 + store i8 1, i8* %arrayinit.element177, align 1 + %arrayinit.element178 = getelementptr inbounds i8, i8* %arrayinit.element177, i32 1 + store i8 2, i8* %arrayinit.element178, align 1 + %arrayinit.element179 = getelementptr inbounds i8, i8* %arrayinit.element178, i32 1 + store i8 92, i8* %arrayinit.element179, align 1 + %arrayinit.element180 = getelementptr inbounds i8, i8* %arrayinit.element179, i32 1 + store i8 4, i8* %arrayinit.element180, align 1 + %arrayinit.element181 = getelementptr inbounds i8, i8* %arrayinit.element180, i32 1 + store i8 64, i8* %arrayinit.element181, align 1 + %arrayinit.element182 = getelementptr inbounds i8, i8* %arrayinit.element181, i32 1 + store i8 65, i8* %arrayinit.element182, align 1 + %arrayinit.element183 = getelementptr inbounds i8, i8* %arrayinit.element182, i32 1 + store i8 0, i8* %arrayinit.element183, align 1 + %arrayinit.element184 = getelementptr inbounds i8, i8* %arrayinit.element183, i32 1 + store i8 15, i8* %arrayinit.element184, align 1 + %arrayinit.element185 = getelementptr inbounds i8, i8* %arrayinit.element184, i32 1 + store i8 11, i8* %arrayinit.element185, align 1 + %arrayinit.element186 = getelementptr inbounds i8, i8* %arrayinit.element185, i32 1 + store i8 32, i8* %arrayinit.element186, align 1 + %arrayinit.element187 = getelementptr inbounds i8, i8* %arrayinit.element186, i32 1 + %a35 = load i8, i8* %old_val, align 1 + store i8 %a35, i8* %arrayinit.element187, align 1 + %arrayinit.element188 = getelementptr inbounds i8, i8* %arrayinit.element187, i32 1 + store i8 32, i8* %arrayinit.element188, align 1 + %arrayinit.element189 = getelementptr inbounds i8, i8* %arrayinit.element188, i32 1 + %a36 = load i8, i8* %simd, align 1 + store i8 %a36, i8* %arrayinit.element189, align 1 + %arrayinit.element190 = getelementptr inbounds i8, i8* %arrayinit.element189, i32 1 + store i8 -3, i8* %arrayinit.element190, align 1 + %arrayinit.element191 = getelementptr inbounds i8, i8* %arrayinit.element190, i32 1 + store i8 1, i8* %arrayinit.element191, align 1 + %arrayinit.element192 = getelementptr inbounds i8, i8* %arrayinit.element191, i32 1 + store i8 3, i8* %arrayinit.element192, align 1 + %arrayinit.element193 = getelementptr inbounds i8, i8* %arrayinit.element192, i32 1 + store i8 92, i8* %arrayinit.element193, align 1 + %arrayinit.element194 = getelementptr inbounds i8, i8* %arrayinit.element193, i32 1 + store i8 4, i8* %arrayinit.element194, align 1 + %arrayinit.element195 = getelementptr inbounds i8, i8* %arrayinit.element194, i32 1 + store i8 64, i8* %arrayinit.element195, align 1 + %arrayinit.element196 = getelementptr inbounds i8, i8* %arrayinit.element195, i32 1 + store i8 65, i8* %arrayinit.element196, align 1 + %arrayinit.element197 = getelementptr inbounds i8, i8* %arrayinit.element196, i32 1 + store i8 0, i8* %arrayinit.element197, align 1 + %arrayinit.element198 = getelementptr inbounds i8, i8* %arrayinit.element197, i32 1 + store i8 15, i8* %arrayinit.element198, align 1 + %arrayinit.element199 = getelementptr inbounds i8, i8* %arrayinit.element198, i32 1 + store i8 11, i8* %arrayinit.element199, align 1 + %arrayinit.element200 = getelementptr inbounds i8, i8* %arrayinit.element199, i32 1 + store i8 32, i8* %arrayinit.element200, align 1 + %arrayinit.element201 = getelementptr inbounds i8, i8* %arrayinit.element200, i32 1 + %a37 = load i8, i8* %simd, align 1 + store i8 %a37, i8* %arrayinit.element201, align 1 + %arrayinit.element202 = getelementptr inbounds i8, i8* %arrayinit.element201, i32 1 + store i8 32, i8* %arrayinit.element202, align 1 + %arrayinit.element203 = getelementptr inbounds i8, i8* %arrayinit.element202, i32 1 + %a38 = load i8, i8* %new_val, align 1 + store i8 %a38, i8* %arrayinit.element203, align 1 + %arrayinit.element204 = getelementptr inbounds i8, i8* %arrayinit.element203, i32 1 + store i8 -3, i8* %arrayinit.element204, align 1 + %arrayinit.element205 = getelementptr inbounds i8, i8* %arrayinit.element204, i32 1 + store i8 2, i8* %arrayinit.element205, align 1 + %arrayinit.element206 = getelementptr inbounds i8, i8* %arrayinit.element205, i32 1 + store i8 3, i8* %arrayinit.element206, align 1 + %arrayinit.element207 = getelementptr inbounds i8, i8* %arrayinit.element206, i32 1 + store i8 33, i8* %arrayinit.element207, align 1 + %arrayinit.element208 = getelementptr inbounds i8, i8* %arrayinit.element207, i32 1 + %a39 = load i8, i8* %simd, align 1 + store i8 %a39, i8* %arrayinit.element208, align 1 + %arrayinit.element209 = getelementptr inbounds i8, i8* %arrayinit.element208, i32 1 + store i8 32, i8* %arrayinit.element209, align 1 + %arrayinit.element210 = getelementptr inbounds i8, i8* %arrayinit.element209, i32 1 + %a40 = load i8, i8* %new_val, align 1 + store i8 %a40, i8* %arrayinit.element210, align 1 + %arrayinit.element211 = getelementptr inbounds i8, i8* %arrayinit.element210, i32 1 + store i8 32, i8* %arrayinit.element211, align 1 + %arrayinit.element212 = getelementptr inbounds i8, i8* %arrayinit.element211, i32 1 + %a41 = load i8, i8* %simd, align 1 + store i8 %a41, i8* %arrayinit.element212, align 1 + %arrayinit.element213 = getelementptr inbounds i8, i8* %arrayinit.element212, i32 1 + store i8 -3, i8* %arrayinit.element213, align 1 + %arrayinit.element214 = getelementptr inbounds i8, i8* %arrayinit.element213, i32 1 + store i8 1, i8* %arrayinit.element214, align 1 + %arrayinit.element215 = getelementptr inbounds i8, i8* %arrayinit.element214, i32 1 + store i8 0, i8* %arrayinit.element215, align 1 + %arrayinit.element216 = getelementptr inbounds i8, i8* %arrayinit.element215, i32 1 + store i8 92, i8* %arrayinit.element216, align 1 + %arrayinit.element217 = getelementptr inbounds i8, i8* %arrayinit.element216, i32 1 + store i8 4, i8* %arrayinit.element217, align 1 + %arrayinit.element218 = getelementptr inbounds i8, i8* %arrayinit.element217, i32 1 + store i8 64, i8* %arrayinit.element218, align 1 + %arrayinit.element219 = getelementptr inbounds i8, i8* %arrayinit.element218, i32 1 + store i8 65, i8* %arrayinit.element219, align 1 + %arrayinit.element220 = getelementptr inbounds i8, i8* %arrayinit.element219, i32 1 + store i8 0, i8* %arrayinit.element220, align 1 + %arrayinit.element221 = getelementptr inbounds i8, i8* %arrayinit.element220, i32 1 + store i8 15, i8* %arrayinit.element221, align 1 + %arrayinit.element222 = getelementptr inbounds i8, i8* %arrayinit.element221, i32 1 + store i8 11, i8* %arrayinit.element222, align 1 + %arrayinit.element223 = getelementptr inbounds i8, i8* %arrayinit.element222, i32 1 + store i8 32, i8* %arrayinit.element223, align 1 + %arrayinit.element224 = getelementptr inbounds i8, i8* %arrayinit.element223, i32 1 + %a42 = load i8, i8* %new_val, align 1 + store i8 %a42, i8* %arrayinit.element224, align 1 + %arrayinit.element225 = getelementptr inbounds i8, i8* %arrayinit.element224, i32 1 + store i8 32, i8* %arrayinit.element225, align 1 + %arrayinit.element226 = getelementptr inbounds i8, i8* %arrayinit.element225, i32 1 + %a43 = load i8, i8* %simd, align 1 + store i8 %a43, i8* %arrayinit.element226, align 1 + %arrayinit.element227 = getelementptr inbounds i8, i8* %arrayinit.element226, i32 1 + store i8 -3, i8* %arrayinit.element227, align 1 + %arrayinit.element228 = getelementptr inbounds i8, i8* %arrayinit.element227, i32 1 + store i8 1, i8* %arrayinit.element228, align 1 + %arrayinit.element229 = getelementptr inbounds i8, i8* %arrayinit.element228, i32 1 + store i8 1, i8* %arrayinit.element229, align 1 + %arrayinit.element230 = getelementptr inbounds i8, i8* %arrayinit.element229, i32 1 + store i8 92, i8* %arrayinit.element230, align 1 + %arrayinit.element231 = getelementptr inbounds i8, i8* %arrayinit.element230, i32 1 + store i8 4, i8* %arrayinit.element231, align 1 + %arrayinit.element232 = getelementptr inbounds i8, i8* %arrayinit.element231, i32 1 + store i8 64, i8* %arrayinit.element232, align 1 + %arrayinit.element233 = getelementptr inbounds i8, i8* %arrayinit.element232, i32 1 + store i8 65, i8* %arrayinit.element233, align 1 + %arrayinit.element234 = getelementptr inbounds i8, i8* %arrayinit.element233, i32 1 + store i8 0, i8* %arrayinit.element234, align 1 + %arrayinit.element235 = getelementptr inbounds i8, i8* %arrayinit.element234, i32 1 + store i8 15, i8* %arrayinit.element235, align 1 + %arrayinit.element236 = getelementptr inbounds i8, i8* %arrayinit.element235, i32 1 + store i8 11, i8* %arrayinit.element236, align 1 + %arrayinit.element237 = getelementptr inbounds i8, i8* %arrayinit.element236, i32 1 + store i8 32, i8* %arrayinit.element237, align 1 + %arrayinit.element238 = getelementptr inbounds i8, i8* %arrayinit.element237, i32 1 + %a44 = load i8, i8* %new_val, align 1 + store i8 %a44, i8* %arrayinit.element238, align 1 + %arrayinit.element239 = getelementptr inbounds i8, i8* %arrayinit.element238, i32 1 + store i8 32, i8* %arrayinit.element239, align 1 + %arrayinit.element240 = getelementptr inbounds i8, i8* %arrayinit.element239, i32 1 + %a45 = load i8, i8* %simd, align 1 + store i8 %a45, i8* %arrayinit.element240, align 1 + %arrayinit.element241 = getelementptr inbounds i8, i8* %arrayinit.element240, i32 1 + store i8 -3, i8* %arrayinit.element241, align 1 + %arrayinit.element242 = getelementptr inbounds i8, i8* %arrayinit.element241, i32 1 + store i8 1, i8* %arrayinit.element242, align 1 + %arrayinit.element243 = getelementptr inbounds i8, i8* %arrayinit.element242, i32 1 + store i8 2, i8* %arrayinit.element243, align 1 + %arrayinit.element244 = getelementptr inbounds i8, i8* %arrayinit.element243, i32 1 + store i8 92, i8* %arrayinit.element244, align 1 + %arrayinit.element245 = getelementptr inbounds i8, i8* %arrayinit.element244, i32 1 + store i8 4, i8* %arrayinit.element245, align 1 + %arrayinit.element246 = getelementptr inbounds i8, i8* %arrayinit.element245, i32 1 + store i8 64, i8* %arrayinit.element246, align 1 + %arrayinit.element247 = getelementptr inbounds i8, i8* %arrayinit.element246, i32 1 + store i8 65, i8* %arrayinit.element247, align 1 + %arrayinit.element248 = getelementptr inbounds i8, i8* %arrayinit.element247, i32 1 + store i8 0, i8* %arrayinit.element248, align 1 + %arrayinit.element249 = getelementptr inbounds i8, i8* %arrayinit.element248, i32 1 + store i8 15, i8* %arrayinit.element249, align 1 + %arrayinit.element250 = getelementptr inbounds i8, i8* %arrayinit.element249, i32 1 + store i8 11, i8* %arrayinit.element250, align 1 + %arrayinit.element251 = getelementptr inbounds i8, i8* %arrayinit.element250, i32 1 + store i8 32, i8* %arrayinit.element251, align 1 + %arrayinit.element252 = getelementptr inbounds i8, i8* %arrayinit.element251, i32 1 + %a46 = load i8, i8* %new_val, align 1 + store i8 %a46, i8* %arrayinit.element252, align 1 + %arrayinit.element253 = getelementptr inbounds i8, i8* %arrayinit.element252, i32 1 + store i8 32, i8* %arrayinit.element253, align 1 + %arrayinit.element254 = getelementptr inbounds i8, i8* %arrayinit.element253, i32 1 + %a47 = load i8, i8* %simd, align 1 + store i8 %a47, i8* %arrayinit.element254, align 1 + %arrayinit.element255 = getelementptr inbounds i8, i8* %arrayinit.element254, i32 1 + store i8 -3, i8* %arrayinit.element255, align 1 + %arrayinit.element256 = getelementptr inbounds i8, i8* %arrayinit.element255, i32 1 + store i8 1, i8* %arrayinit.element256, align 1 + %arrayinit.element257 = getelementptr inbounds i8, i8* %arrayinit.element256, i32 1 + store i8 3, i8* %arrayinit.element257, align 1 + %arrayinit.element258 = getelementptr inbounds i8, i8* %arrayinit.element257, i32 1 + store i8 92, i8* %arrayinit.element258, align 1 + %arrayinit.element259 = getelementptr inbounds i8, i8* %arrayinit.element258, i32 1 + store i8 4, i8* %arrayinit.element259, align 1 + %arrayinit.element260 = getelementptr inbounds i8, i8* %arrayinit.element259, i32 1 + store i8 64, i8* %arrayinit.element260, align 1 + %arrayinit.element261 = getelementptr inbounds i8, i8* %arrayinit.element260, i32 1 + store i8 65, i8* %arrayinit.element261, align 1 + %arrayinit.element262 = getelementptr inbounds i8, i8* %arrayinit.element261, i32 1 + store i8 0, i8* %arrayinit.element262, align 1 + %arrayinit.element263 = getelementptr inbounds i8, i8* %arrayinit.element262, i32 1 + store i8 15, i8* %arrayinit.element263, align 1 + %arrayinit.element264 = getelementptr inbounds i8, i8* %arrayinit.element263, i32 1 + store i8 11, i8* %arrayinit.element264, align 1 + %arrayinit.element265 = getelementptr inbounds i8, i8* %arrayinit.element264, i32 1 + store i8 65, i8* %arrayinit.element265, align 1 + %arrayinit.element266 = getelementptr inbounds i8, i8* %arrayinit.element265, i32 1 + store i8 1, i8* %arrayinit.element266, align 1 + %arrayinit.element267 = getelementptr inbounds i8, i8* %arrayinit.element266, i32 1 + store i8 15, i8* %arrayinit.element267, align 1 + %arraydecay = getelementptr inbounds [269 x i8], [269 x i8]* %code, i32 0, i32 0 + %arraydecay268 = getelementptr inbounds [269 x i8], [269 x i8]* %code, i32 0, i32 0 + %add.ptr = getelementptr inbounds i8, i8* %arraydecay268, i32 269 + call void @g(i8* %arraydecay, i8* %add.ptr) + ret void +} + +declare void @g(i8*, i8*) + +attributes #1 = { noinline nounwind optnone ssp uwtable } diff --git a/test/CodeGen/Mips/dins.ll b/test/CodeGen/Mips/dins.ll index 2aa824250d3b4..2f7138ca4c5db 100644 --- a/test/CodeGen/Mips/dins.ll +++ b/test/CodeGen/Mips/dins.ll @@ -1,7 +1,11 @@ -; RUN: llc -O2 -march=mips64 -mcpu=mips64r2 -target-abi=n64 < %s -o - | FileCheck %s -check-prefix=MIPS64R2 -; RUN: llc -O2 -march=mips -mcpu=mips32r2 < %s -o - | FileCheck %s -check-prefix=MIPS32R2 -; RUN: llc -O2 -march=mips -mattr=mips16 < %s -o - | FileCheck %s -check-prefix=MIPS16 -; RUN: llc -O2 -march=mips64 -mcpu=mips64r2 -target-abi=n32 < %s -o - | FileCheck %s -check-prefix=MIPS64R2N32 +; RUN: llc -O2 -verify-machineinstrs -march=mips64 -mcpu=mips64r2 \ +; RUN: -target-abi=n64 < %s -o - | FileCheck %s -check-prefix=MIPS64R2 +; RUN: llc -O2 -verify-machineinstrs -march=mips -mcpu=mips32r2 < %s -o - \ +; RUN: | FileCheck %s -check-prefix=MIPS32R2 +; RUN: llc -O2 -verify-machineinstrs -march=mips -mattr=mips16 < %s -o - \ +; RUN: | FileCheck %s -check-prefix=MIPS16 +; RUN: llc -O2 -verify-machineinstrs -march=mips64 -mcpu=mips64r2 \ +; RUN: -target-abi=n32 < %s -o - | FileCheck %s -check-prefix=MIPS64R2N32 ; #include <stdint.h> ; #include <stdio.h> @@ -58,13 +62,13 @@ entry: ; CHECK-LABEL: f123: ; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 123 -; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 27, 37 +; MIPS64R2: dinsm $[[R0:[0-9]+]], $[[R1:[0-9]+]], 27, 37 ; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 4 -; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 28, 6 +; MIPS64R2: dinsm $[[R0:[0-9]+]], $[[R1:[0-9]+]], 28, 6 ; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 5 -; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50, 14 +; MIPS64R2: dinsu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50, 14 ; MIPS64R2: dsrl $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50 -; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 34, 16 +; MIPS64R2: dinsu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 34, 16 ; MIPS32R2: ins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 2, 16 ; MIPS32R2-NOT: ins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 18, 46 ; MIPS16-NOT: ins{{[[:space:]].*}} diff --git a/test/CodeGen/Mips/fcmp.ll b/test/CodeGen/Mips/fcmp.ll index eb6c06db4efff..34088beb2246d 100644 --- a/test/CodeGen/Mips/fcmp.ll +++ b/test/CodeGen/Mips/fcmp.ll @@ -16,8 +16,6 @@ ; RUN: -check-prefixes=ALL,MM,MM32R3 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM,MMR6,MM32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MMR6,MM64R6 define i32 @false_f32(float %a, float %b) nounwind { ; ALL-LABEL: false_f32: @@ -61,7 +59,6 @@ define i32 @oeq_f32(float %a, float %b) nounwind { ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -95,7 +92,6 @@ define i32 @ogt_f32(float %a, float %b) nounwind { ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -129,7 +125,6 @@ define i32 @oge_f32(float %a, float %b) nounwind { ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -163,7 +158,6 @@ define i32 @olt_f32(float %a, float %b) nounwind { ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -197,7 +191,6 @@ define i32 @ole_f32(float %a, float %b) nounwind { ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -233,7 +226,6 @@ define i32 @one_f32(float %a, float %b) nounwind { ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: andi16 $2, $[[T2]], 1 @@ -270,7 +262,6 @@ define i32 @ord_f32(float %a, float %b) nounwind { ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: andi16 $2, $[[T2]], 1 @@ -305,7 +296,6 @@ define i32 @ueq_f32(float %a, float %b) nounwind { ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -339,7 +329,6 @@ define i32 @ugt_f32(float %a, float %b) nounwind { ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -373,7 +362,6 @@ define i32 @uge_f32(float %a, float %b) nounwind { ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -407,7 +395,6 @@ define i32 @ult_f32(float %a, float %b) nounwind { ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -441,7 +428,6 @@ define i32 @ule_f32(float %a, float %b) nounwind { ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -477,7 +463,6 @@ define i32 @une_f32(float %a, float %b) nounwind { ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: andi16 $2, $[[T2]], 1 @@ -512,7 +497,6 @@ define i32 @uno_f32(float %a, float %b) nounwind { ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -580,7 +564,6 @@ define i32 @oeq_f64(double %a, double %b) nounwind { ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -614,7 +597,6 @@ define i32 @ogt_f64(double %a, double %b) nounwind { ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -648,7 +630,6 @@ define i32 @oge_f64(double %a, double %b) nounwind { ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -682,7 +663,6 @@ define i32 @olt_f64(double %a, double %b) nounwind { ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -716,7 +696,6 @@ define i32 @ole_f64(double %a, double %b) nounwind { ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -752,7 +731,6 @@ define i32 @one_f64(double %a, double %b) nounwind { ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: andi16 $2, $[[T2]], 1 @@ -789,7 +767,6 @@ define i32 @ord_f64(double %a, double %b) nounwind { ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: andi16 $2, $[[T2]], 1 @@ -824,7 +801,6 @@ define i32 @ueq_f64(double %a, double %b) nounwind { ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -858,7 +834,6 @@ define i32 @ugt_f64(double %a, double %b) nounwind { ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -892,7 +867,6 @@ define i32 @uge_f64(double %a, double %b) nounwind { ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -926,7 +900,6 @@ define i32 @ult_f64(double %a, double %b) nounwind { ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -960,7 +933,6 @@ define i32 @ule_f64(double %a, double %b) nounwind { ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -996,7 +968,6 @@ define i32 @une_f64(double %a, double %b) nounwind { ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: andi16 $2, $[[T2]], 1 @@ -1031,7 +1002,6 @@ define i32 @uno_f64(double %a, double %b) nounwind { ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -1100,19 +1070,7 @@ entry: ; MM32R6-DAG: cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]] ; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3:f[0-9]+]] ; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1 -; MM32R6-DAG: bnez $[[T5]], - -; MM64R6-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12 -; MM64R6-DAG: lui $[[T1:[0-9]+]], %highest(.LCPI32_0) -; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI32_0) -; MM64R6-DAG: dsll $[[T3:[0-9]+]], $[[T2]], 16 -; MM64R6-DAG: daddiu $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI32_0) -; MM64R6-DAG: dsll $[[T5:[0-9]+]], $[[T4]], 16 -; MM64R6-DAG: lwc1 $[[T6:f[0-9]+]], %lo(.LCPI32_0)($[[T5]]) -; MM64R6-DAG: cmp.le.s $[[T7:f[0-9]+]], $[[T0]], $[[T6]] -; MM64R6-DAG: mfc1 $[[T8:[0-9]+]], $[[T7]] -; MM64R6-DAG: andi16 $[[T9:[0-9]+]], $[[T8]], 1 -; MM64R6-DAG: bnez $[[T9]], +; MM32R6-DAG: bnezc $[[T5]], %add = fadd fast float %at, %angle %cmp = fcmp ogt float %add, 1.000000e+00 @@ -1170,19 +1128,7 @@ entry: ; MM32R6-DAG: cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]] ; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3]] ; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1 -; MM32R6-DAG: bnez $[[T5]], - -; MM64R6-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12 -; MM64R6-DAG: lui $[[T1:[0-9]+]], %highest(.LCPI33_0) -; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI33_0) -; MM64R6-DAG: dsll $[[T3:[0-9]+]], $[[T2]], 16 -; MM64R6-DAG: daddiu $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI33_0) -; MM64R6-DAG: dsll $[[T5:[0-9]+]], $[[T4]], 16 -; MM64R6-DAG: ldc1 $[[T6:f[0-9]+]], %lo(.LCPI33_0)($[[T5]]) -; MM64R6-DAG: cmp.le.d $[[T7:f[0-9]+]], $[[T0]], $[[T6]] -; MM64R6-DAG: mfc1 $[[T8:[0-9]+]], $[[T7]] -; MM64R6-DAG: andi16 $[[T9:[0-9]+]], $[[T8]], 1 -; MM64R6-DAG: bnez $[[T9]], +; MM32R6-DAG: bnezc $[[T5]], %add = fadd fast double %at, %angle %cmp = fcmp ogt double %add, 1.000000e+00 diff --git a/test/CodeGen/Mips/fcopysign-f32-f64.ll b/test/CodeGen/Mips/fcopysign-f32-f64.ll index e0229d14c5267..695431a5ab607 100644 --- a/test/CodeGen/Mips/fcopysign-f32-f64.ll +++ b/test/CodeGen/Mips/fcopysign-f32-f64.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | \ -; RUN: FileCheck %s -check-prefixes=ALL,64 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | \ -; RUN: FileCheck %s -check-prefixes=ALL,64 -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | \ -; RUN: FileCheck %s -check-prefixes=ALL,64R2 +; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips4 \ +; RUN: -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64 +; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips64 \ +; RUN: -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64 +; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips64r2 \ +; RUN: -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2 declare double @copysign(double, double) nounwind readnone @@ -48,7 +48,7 @@ entry: ; 64: dmtc1 $[[OR]], $f0 ; 64R2: ext ${{[0-9]+}}, ${{[0-9]+}}, 31, 1 -; 64R2: dins $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1 +; 64R2: dinsu $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1 ; 64R2: dmtc1 $[[INS]], $f0 %add = fadd double %d, 1.000000e+00 diff --git a/test/CodeGen/Mips/fcopysign.ll b/test/CodeGen/Mips/fcopysign.ll index ffc72a12f23d5..810d0f9580861 100644 --- a/test/CodeGen/Mips/fcopysign.ll +++ b/test/CodeGen/Mips/fcopysign.ll @@ -1,8 +1,13 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=32 -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2 -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s -check-prefix=64 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefix=64 -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefix=64R2 +; RUN: llc < %s -verify-machineinstrs -march=mipsel -mcpu=mips32 \ +; RUN: | FileCheck %s -check-prefix=32 +; RUN: llc < %s -verify-machineinstrs -march=mipsel -mcpu=mips32r2 \ +; RUN: | FileCheck %s -check-prefix=32R2 +; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips4 -target-abi=n64 \ +; RUN: | FileCheck %s -check-prefix=64 +; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips64 -target-abi=n64 \ +; RUN: | FileCheck %s -check-prefix=64 +; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips64r2 -target-abi=n64 \ +; RUN: | FileCheck %s -check-prefix=64R2 define double @func0(double %d0, double %d1) nounwind readnone { entry: @@ -28,8 +33,8 @@ entry: ; 64: dmtc1 $[[OR]], $f0 ; 64R2: dextu $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1 -; 64R2: dins $[[INS:[0-9]+]], $[[EXT]], 63, 1 -; 64R2: dmtc1 $[[INS]], $f0 +; 64R2: dinsu $[[INS:[0-9]+]], $[[EXT]], 63, 1 +; 64R2: dmtc1 $[[INS]], $f0 %call = tail call double @copysign(double %d0, double %d1) nounwind readnone ret double %call diff --git a/test/CodeGen/Mips/gpopt-explict-section.ll b/test/CodeGen/Mips/gpopt-explict-section.ll new file mode 100644 index 0000000000000..f1518ba562c73 --- /dev/null +++ b/test/CodeGen/Mips/gpopt-explict-section.ll @@ -0,0 +1,53 @@ +; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 \ +; RUN: -relocation-model=static -mattr=+noabicalls -mgpopt \ +; RUN: | FileCheck %s + +; Test that object with an explicit section that is not .sdata or .sbss are not +; considered in the small data section if they would otherwise qualify to be in +; small data section. Also test that explicitly placing something in the small +; data section uses %gp_rel addressing mode. + +@a = global [2 x i32] zeroinitializer, section ".rodata", align 4 +@b = global [4 x i32] zeroinitializer, section ".sdata", align 4 +@c = global [4 x i32] zeroinitializer, section ".sbss", align 4 + +; CHECK-LABEL: g +; CHECK: lui $[[R:[0-9]+]], %hi(a) +; CHECK: lw ${{[0-9]+}}, %lo(a)($[[R]]) + +define i32 @g() { +entry: + %0 = load i32, i32* getelementptr inbounds ([2 x i32], [2 x i32]* @a, i32 0, i32 0), align 4 + ret i32 %0 +} + +; CHECK-LABEL: f: +; CHECK-LABEL: lw ${{[0-9]+}}, %gp_rel(b)($gp) + +define i32 @f() { +entry: + %0 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @b, i32 0, i32 0), align 4 + ret i32 %0 +} + +; CHECK-LABEL: h: +; CHECK-LABEL: lw ${{[0-9]+}}, %gp_rel(c)($gp) + +define i32 @h() { +entry: + %0 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @c, i32 0, i32 0), align 4 + ret i32 %0 +} + + +; CHECK: .type a,@object +; CHECK: .section .rodata,"a",@progbits +; CHECK: .globl a + +; CHECK: .type b,@object +; CHECK: .section .sdata,"aw",@progbits +; CHECK: .globl b + +; CHECK: .type c,@object +; CHECK: .section .sbss,"aw",@nobits +; CHECK: .globl c diff --git a/test/CodeGen/Mips/instverify/dext-pos.mir b/test/CodeGen/Mips/instverify/dext-pos.mir new file mode 100644 index 0000000000000..8e3b887ffe9e1 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dext-pos.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in the range 0..31 +--- +name: dext +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXT %0, 55, 10 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dext-size.mir b/test/CodeGen/Mips/instverify/dext-size.mir new file mode 100644 index 0000000000000..968dd4e370fd1 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dext-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in the range 1..32 +--- +name: dext +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXT %0, 5, 50 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dextm-pos-size.mir b/test/CodeGen/Mips/instverify/dextm-pos-size.mir new file mode 100644 index 0000000000000..bdf82ecd0d675 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dextm-pos-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position + Size is out of range! + +# Check that the machine verifier checks the pos + size is in the range 33..64 +--- +name: dextm +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXTM %0, 3, 62 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dextm-pos.mir b/test/CodeGen/Mips/instverify/dextm-pos.mir new file mode 100644 index 0000000000000..987a228a1f8ea --- /dev/null +++ b/test/CodeGen/Mips/instverify/dextm-pos.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in the range 0..31 +--- +name: dextm +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXTM %0, 65, 5 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dextm-size.mir b/test/CodeGen/Mips/instverify/dextm-size.mir new file mode 100644 index 0000000000000..b1e367e027e37 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dextm-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in the range 33..64 +--- +name: dextm +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXTM %0, 31, 67 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dextu-pos-size.mir b/test/CodeGen/Mips/instverify/dextu-pos-size.mir new file mode 100644 index 0000000000000..9b6dac0835005 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dextu-pos-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position + Size is out of range! + +# Check that the machine verifier checks the pos + size is in the range 33..64 +--- +name: dextu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXTU %0, 43, 30 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dextu-pos.mir b/test/CodeGen/Mips/instverify/dextu-pos.mir new file mode 100644 index 0000000000000..65e5bd0e1c1e3 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dextu-pos.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in the range 32..63 +--- +name: dextu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXTU %0, 64, 5 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dextu-size-valid.mir b/test/CodeGen/Mips/instverify/dextu-size-valid.mir new file mode 100644 index 0000000000000..8c548f1c7b4c1 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dextu-size-valid.mir @@ -0,0 +1,49 @@ +# RUN: llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK-NOT: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in the range 1..32 +--- +name: dextu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXTU %0, 63, 1 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dextu-size.mir b/test/CodeGen/Mips/instverify/dextu-size.mir new file mode 100644 index 0000000000000..0511d1ae09dc0 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dextu-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in the range 1..32 +--- +name: dextu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXTU %0, 33, 67 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dins-pos-size.mir b/test/CodeGen/Mips/instverify/dins-pos-size.mir new file mode 100644 index 0000000000000..d1d178575c8f2 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dins-pos-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position + Size is out of range! + +# Check that the machine verifier checks the pos + size is in the range 1..32 +--- +name: dins +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINS %0, 17, 17 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dins-pos.mir b/test/CodeGen/Mips/instverify/dins-pos.mir new file mode 100644 index 0000000000000..1602aa2e25adb --- /dev/null +++ b/test/CodeGen/Mips/instverify/dins-pos.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in the range 0..31 +--- +name: dins +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINS %0, 55, 10 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dins-size.mir b/test/CodeGen/Mips/instverify/dins-size.mir new file mode 100644 index 0000000000000..bf713bf992f3f --- /dev/null +++ b/test/CodeGen/Mips/instverify/dins-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in the range 1..32 +--- +name: dins +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINS %0, 5, 50 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dinsm-pos-size.mir b/test/CodeGen/Mips/instverify/dinsm-pos-size.mir new file mode 100644 index 0000000000000..aa73e7f1a53b6 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dinsm-pos-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position + Size is out of range! + +# Check that the machine verifier checks the pos + size is in the range 33..64 +--- +name: dinsu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINSM %0, 20, 50 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dinsm-pos.mir b/test/CodeGen/Mips/instverify/dinsm-pos.mir new file mode 100644 index 0000000000000..66a6053ca74f2 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dinsm-pos.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in the range 0..31 +--- +name: dinsm +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINSM %0, 65, 5 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dinsm-size.mir b/test/CodeGen/Mips/instverify/dinsm-size.mir new file mode 100644 index 0000000000000..fba3bee969a6d --- /dev/null +++ b/test/CodeGen/Mips/instverify/dinsm-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in the range 2..64 +--- +name: dinsm +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINSM %0, 31, 67 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dinsu-pos-size.mir b/test/CodeGen/Mips/instverify/dinsu-pos-size.mir new file mode 100644 index 0000000000000..9d2d17c3c18f3 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dinsu-pos-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position + Size is out of range! + +# Check that the machine verifier checks the pos + size is in the range 33..64 +--- +name: dinsu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINSU %0, 50, 20 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dinsu-pos.mir b/test/CodeGen/Mips/instverify/dinsu-pos.mir new file mode 100644 index 0000000000000..d89bb2de3aea6 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dinsu-pos.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in the range 32..63 +--- +name: dinsu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINSU %0, 65, 5 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dinsu-size.mir b/test/CodeGen/Mips/instverify/dinsu-size.mir new file mode 100644 index 0000000000000..550f890fbd8ec --- /dev/null +++ b/test/CodeGen/Mips/instverify/dinsu-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in the range 1..32 +--- +name: dinsu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINSU %0, 33, 67 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/ext-pos-size.mir b/test/CodeGen/Mips/instverify/ext-pos-size.mir new file mode 100644 index 0000000000000..94edecd8d24a1 --- /dev/null +++ b/test/CodeGen/Mips/instverify/ext-pos-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position + Size is out of range! + +# Check that the machine verifier checks the pos + size is in the range 1..32 +--- +name: f +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } +liveins: + - { reg: '%a0', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0 + + %0 = COPY %a0 + %1 = EXT %0, 17, 17 + %v0 = COPY %1 + RetRA implicit %v0 + +... diff --git a/test/CodeGen/Mips/instverify/ext-pos.mir b/test/CodeGen/Mips/instverify/ext-pos.mir new file mode 100644 index 0000000000000..7cca1b6a1b3d9 --- /dev/null +++ b/test/CodeGen/Mips/instverify/ext-pos.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in the range 0..31 +--- +name: f +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } +liveins: + - { reg: '%a0', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0 + + %0 = COPY %a0 + %1 = EXT %0, 44, 21 + %v0 = COPY %1 + RetRA implicit %v0 + +... diff --git a/test/CodeGen/Mips/instverify/ext-size.mir b/test/CodeGen/Mips/instverify/ext-size.mir new file mode 100644 index 0000000000000..4c35e1fb6a095 --- /dev/null +++ b/test/CodeGen/Mips/instverify/ext-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in the range 1..32 +--- +name: f +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } +liveins: + - { reg: '%a0', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0 + + %0 = COPY %a0 + %1 = EXT %0, 0, 33 + %v0 = COPY %1 + RetRA implicit %v0 + +... diff --git a/test/CodeGen/Mips/instverify/ins-pos-size.mir b/test/CodeGen/Mips/instverify/ins-pos-size.mir new file mode 100644 index 0000000000000..e825b5997d8b9 --- /dev/null +++ b/test/CodeGen/Mips/instverify/ins-pos-size.mir @@ -0,0 +1,54 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position + Size is out of range! + +# Check that the machine verifier checks the pos + size is in the range 1..32 +--- +name: f +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } + - { id: 2, class: gpr32, preferred-register: '' } + - { id: 3, class: gpr32, preferred-register: '' } +liveins: + - { reg: '%a0', virtual-reg: '%0' } + - { reg: '%a1', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0, %a1 + + %1 = COPY %a1 + %0 = COPY %a0 + %2 = ANDi %1, 15 + %3 = INS killed %2, 17, 17, %0 + %v0 = COPY %3 + RetRA implicit %v0 + +... diff --git a/test/CodeGen/Mips/instverify/ins-pos.mir b/test/CodeGen/Mips/instverify/ins-pos.mir new file mode 100644 index 0000000000000..a284fdb579989 --- /dev/null +++ b/test/CodeGen/Mips/instverify/ins-pos.mir @@ -0,0 +1,54 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in the range 0..31 +--- +name: f +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } + - { id: 2, class: gpr32, preferred-register: '' } + - { id: 3, class: gpr32, preferred-register: '' } +liveins: + - { reg: '%a0', virtual-reg: '%0' } + - { reg: '%a1', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0, %a1 + + %1 = COPY %a1 + %0 = COPY %a0 + %2 = ANDi %1, 15 + %3 = INS killed %2, 32, 4, %0 + %v0 = COPY %3 + RetRA implicit %v0 + +... diff --git a/test/CodeGen/Mips/instverify/ins-size.mir b/test/CodeGen/Mips/instverify/ins-size.mir new file mode 100644 index 0000000000000..6cd839a01c6b4 --- /dev/null +++ b/test/CodeGen/Mips/instverify/ins-size.mir @@ -0,0 +1,54 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in the range 1..32 +--- +name: f +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } + - { id: 2, class: gpr32, preferred-register: '' } + - { id: 3, class: gpr32, preferred-register: '' } +liveins: + - { reg: '%a0', virtual-reg: '%0' } + - { reg: '%a1', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0, %a1 + + %1 = COPY %a1 + %0 = COPY %a0 + %2 = ANDi %1, 15 + %3 = INS killed %2, 0, 40, %0 + %v0 = COPY %3 + RetRA implicit %v0 + +... diff --git a/test/CodeGen/Mips/lcb4a.ll b/test/CodeGen/Mips/lcb4a.ll index 4a99ef26efcae..016e895d12efc 100644 --- a/test/CodeGen/Mips/lcb4a.ll +++ b/test/CodeGen/Mips/lcb4a.ll @@ -26,7 +26,7 @@ if.end: ; preds = %if.else, %if.then } ; ci: beqz $3, $BB0_2 -; ci: # BB#1: # %if.else +; ci: # %bb.1: # %if.else ; Function Attrs: nounwind optsize diff --git a/test/CodeGen/Mips/llvm-ir/add.ll b/test/CodeGen/Mips/llvm-ir/add.ll index 63884eb03b8c5..2a7ae5a715339 100644 --- a/test/CodeGen/Mips/llvm-ir/add.ll +++ b/test/CodeGen/Mips/llvm-ir/add.ll @@ -28,8 +28,6 @@ ; RUN: -check-prefixes=ALL,MMR3,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -O2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM64 ; FIXME: This code sequence is inefficient as it should be 'subu $[[T0]], $zero, $[[T0]'. @@ -122,8 +120,6 @@ entry: ; MM32: sltu $[[T1:[0-9]+]], $3, $5 ; MM32: addu16 $2, $[[T0]], $[[T1]] - ; MM64: daddu $2, $4, $5 - %r = add i64 %a, %b ret i64 %r } @@ -228,13 +224,6 @@ entry: ; MMR6: addu16 $2, $[[T16]], $[[T20]] ; MMR6: addu16 $2, $[[T20]], $[[T21]] - ; MM64: daddu $[[T0:[0-9]+]], $4, $6 - ; MM64: daddu $3, $5, $7 - ; MM64: sltu $[[T1:[0-9]+]], $3, $5 - ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32 - ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32 - ; MM64: daddu $2, $[[T0]], $[[T3]] - %r = add i128 %a, %b ret i128 %r } @@ -262,9 +251,6 @@ define signext i8 @add_i8_4(i8 signext %a) { ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4 ; MM32: seb $2, $[[T0]] - ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4 - ; MM64: seb $2, $[[T0]] - %r = add i8 4, %a ret i8 %r } @@ -283,9 +269,6 @@ define signext i16 @add_i16_4(i16 signext %a) { ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4 ; MM32: seh $2, $[[T0]] - ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4 - ; MM64: seh $2, $[[T0]] - %r = add i16 4, %a ret i16 %r } @@ -299,8 +282,6 @@ define signext i32 @add_i32_4(i32 signext %a) { ; MM32: addiur2 $2, $4, 4 - ; MM64: addiur2 $2, $4, 4 - %r = add i32 4, %a ret i32 %r } @@ -319,8 +300,6 @@ define signext i64 @add_i64_4(i64 signext %a) { ; GP64: daddiu $2, $4, 4 - ; MM64: daddiu $2, $4, 4 - %r = add i64 4, %a ret i64 %r } @@ -384,12 +363,6 @@ define signext i128 @add_i128_4(i128 signext %a) { ; MMR6: move $4, $7 ; MMR6: move $5, $[[T1]] - ; MM64: daddiu $[[T0:[0-9]+]], $5, 4 - ; MM64: sltu $[[T1:[0-9]+]], $[[T0]], $5 - ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32 - ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32 - ; MM64: daddu $2, $4, $[[T3]] - %r = add i128 4, %a ret i128 %r } @@ -477,8 +450,6 @@ define signext i64 @add_i64_3(i64 signext %a) { ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $5 ; MM32: addu16 $2, $4, $[[T2]] - ; MM64: daddiu $2, $4, 3 - %r = add i64 3, %a ret i64 %r } @@ -545,12 +516,6 @@ define signext i128 @add_i128_3(i128 signext %a) { ; MMR6: move $4, $[[T5]] ; MMR6: move $5, $[[T1]] - ; MM64: daddiu $[[T0:[0-9]+]], $5, 3 - ; MM64: sltu $[[T1:[0-9]+]], $[[T0]], $5 - ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32 - ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32 - ; MM64: daddu $2, $4, $[[T3]] - %r = add i128 3, %a ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/and.ll b/test/CodeGen/Mips/llvm-ir/and.ll index c26b60d0ff9a5..c3a973f01ccd4 100644 --- a/test/CodeGen/Mips/llvm-ir/and.ll +++ b/test/CodeGen/Mips/llvm-ir/and.ll @@ -1,703 +1,2135 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM64 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=MIPS +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=MIPS +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R6 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R6 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=MM32R3 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=MM32R6 define signext i1 @and_i1(i1 signext %a, i1 signext %b) { +; MIPS-LABEL: and_i1: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: and $2, $4, $5 +; +; MIPS32R2-LABEL: and_i1: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: and $2, $4, $5 +; +; MIPS32R6-LABEL: and_i1: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: and $2, $4, $5 +; +; MIPS64-LABEL: and_i1: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: and $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: and_i1: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: and $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: and_i1: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: and $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: and_i1: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: and16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i1: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: and16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i1: - - ; GP32: and $2, $4, $5 - - ; GP64: and $2, $4, $5 - - ; MM: and16 $[[T0:[0-9]+]], $5 - ; MM: move $2, $[[T0]] - %r = and i1 %a, %b ret i1 %r } define signext i8 @and_i8(i8 signext %a, i8 signext %b) { +; MIPS-LABEL: and_i8: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: and $2, $4, $5 +; +; MIPS32R2-LABEL: and_i8: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: and $2, $4, $5 +; +; MIPS32R6-LABEL: and_i8: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: and $2, $4, $5 +; +; MIPS64-LABEL: and_i8: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: and $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: and_i8: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: and $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: and_i8: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: and $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: and_i8: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: and16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i8: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: and16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i8: - - ; GP32: and $2, $4, $5 - - ; GP64: and $2, $4, $5 - - ; MM: and16 $[[T0:[0-9]+]], $5 - ; MM: move $2, $[[T0]] - %r = and i8 %a, %b ret i8 %r } define signext i16 @and_i16(i16 signext %a, i16 signext %b) { +; MIPS-LABEL: and_i16: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: and $2, $4, $5 +; +; MIPS32R2-LABEL: and_i16: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: and $2, $4, $5 +; +; MIPS32R6-LABEL: and_i16: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: and $2, $4, $5 +; +; MIPS64-LABEL: and_i16: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: and $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: and_i16: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: and $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: and_i16: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: and $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: and_i16: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: and16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i16: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: and16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i16: - - ; GP32: and $2, $4, $5 - - ; GP64: and $2, $4, $5 - - ; MM: and16 $[[T0:[0-9]+]], $5 - ; MM: move $2, $[[T0]] - %r = and i16 %a, %b ret i16 %r } define signext i32 @and_i32(i32 signext %a, i32 signext %b) { +; MIPS-LABEL: and_i32: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: and $2, $4, $5 +; +; MIPS32R2-LABEL: and_i32: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: and $2, $4, $5 +; +; MIPS32R6-LABEL: and_i32: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: and $2, $4, $5 +; +; MIPS64-LABEL: and_i32: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: and $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: and_i32: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: and $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: and_i32: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: and $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: and_i32: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: and16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i32: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: and16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i32: - - ; GP32: and $2, $4, $5 - - ; GP64: and $[[T0:[0-9]+]], $4, $5 - ; GP64: sll $2, $[[T0]], 0 - - ; MM32: and16 $[[T0:[0-9]+]], $5 - ; MM32: move $2, $[[T0]] - - ; MM64: and $[[T0:[0-9]+]], $4, $5 - ; MM64: sll $2, $[[T0]], 0 - %r = and i32 %a, %b ret i32 %r } define signext i64 @and_i64(i64 signext %a, i64 signext %b) { +; MIPS-LABEL: and_i64: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: and $2, $4, $6 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: and $3, $5, $7 +; +; MIPS32R2-LABEL: and_i64: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: and $2, $4, $6 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: and $3, $5, $7 +; +; MIPS32R6-LABEL: and_i64: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: and $2, $4, $6 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: and $3, $5, $7 +; +; MIPS64-LABEL: and_i64: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: and $2, $4, $5 +; +; MIPS64R2-LABEL: and_i64: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: and $2, $4, $5 +; +; MIPS64R6-LABEL: and_i64: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: and $2, $4, $5 +; +; MM32R3-LABEL: and_i64: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: and16 $4, $6 +; MM32R3-NEXT: and16 $5, $7 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: move $3, $5 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i64: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: and16 $4, $6 +; MM32R6-NEXT: and16 $5, $7 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i64: - - ; GP32: and $2, $4, $6 - ; GP32: and $3, $5, $7 - - ; GP64: and $2, $4, $5 - - ; MM32: and16 $[[T0:[0-9]+]], $6 - ; MM32: and16 $[[T1:[0-9]+]], $7 - ; MM32: move $2, $[[T0]] - ; MM32: move $3, $[[T1]] - - ; MM64: and $2, $4, $5 - %r = and i64 %a, %b ret i64 %r } define signext i128 @and_i128(i128 signext %a, i128 signext %b) { +; MIPS-LABEL: and_i128: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: lw $1, 20($sp) +; MIPS-NEXT: lw $2, 16($sp) +; MIPS-NEXT: and $2, $4, $2 +; MIPS-NEXT: and $3, $5, $1 +; MIPS-NEXT: lw $1, 24($sp) +; MIPS-NEXT: and $4, $6, $1 +; MIPS-NEXT: lw $1, 28($sp) +; MIPS-NEXT: jr $ra +; MIPS-NEXT: and $5, $7, $1 +; +; MIPS32R2-LABEL: and_i128: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: lw $1, 20($sp) +; MIPS32R2-NEXT: lw $2, 16($sp) +; MIPS32R2-NEXT: and $2, $4, $2 +; MIPS32R2-NEXT: and $3, $5, $1 +; MIPS32R2-NEXT: lw $1, 24($sp) +; MIPS32R2-NEXT: and $4, $6, $1 +; MIPS32R2-NEXT: lw $1, 28($sp) +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: and $5, $7, $1 +; +; MIPS32R6-LABEL: and_i128: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: lw $1, 20($sp) +; MIPS32R6-NEXT: lw $2, 16($sp) +; MIPS32R6-NEXT: and $2, $4, $2 +; MIPS32R6-NEXT: and $3, $5, $1 +; MIPS32R6-NEXT: lw $1, 24($sp) +; MIPS32R6-NEXT: and $4, $6, $1 +; MIPS32R6-NEXT: lw $1, 28($sp) +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: and $5, $7, $1 +; +; MIPS64-LABEL: and_i128: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: and $2, $4, $6 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: and $3, $5, $7 +; +; MIPS64R2-LABEL: and_i128: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: and $2, $4, $6 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: and $3, $5, $7 +; +; MIPS64R6-LABEL: and_i128: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: and $2, $4, $6 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: and $3, $5, $7 +; +; MM32R3-LABEL: and_i128: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: lw $3, 20($sp) +; MM32R3-NEXT: lw $2, 16($sp) +; MM32R3-NEXT: and16 $2, $4 +; MM32R3-NEXT: and16 $3, $5 +; MM32R3-NEXT: lw $4, 24($sp) +; MM32R3-NEXT: and16 $4, $6 +; MM32R3-NEXT: lw $5, 28($sp) +; MM32R3-NEXT: and16 $5, $7 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i128: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: lw $3, 20($sp) +; MM32R6-NEXT: lw $2, 16($sp) +; MM32R6-NEXT: and16 $2, $4 +; MM32R6-NEXT: and16 $3, $5 +; MM32R6-NEXT: lw $4, 24($sp) +; MM32R6-NEXT: and16 $4, $6 +; MM32R6-NEXT: lw $5, 28($sp) +; MM32R6-NEXT: and16 $5, $7 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i128: - - ; GP32: lw $[[T0:[0-9]+]], 20($sp) - ; GP32: lw $[[T1:[0-9]+]], 16($sp) - ; GP32: and $2, $4, $[[T1]] - ; GP32: and $3, $5, $[[T0]] - ; GP32: lw $[[T2:[0-9]+]], 24($sp) - ; GP32: and $4, $6, $[[T2]] - ; GP32: lw $[[T3:[0-9]+]], 28($sp) - ; GP32: and $5, $7, $[[T3]] - - ; GP64: and $2, $4, $6 - ; GP64: and $3, $5, $7 - - ; MM32: lw $[[T0:[0-9]+]], 20($sp) - ; MM32: lw $[[T1:[0-9]+]], 16($sp) - ; MM32: and16 $[[T1]], $4 - ; MM32: and16 $[[T0]], $5 - ; MM32: lw $[[T2:[0-9]+]], 24($sp) - ; MM32: and16 $[[T2]], $6 - ; MM32: lw $[[T3:[0-9]+]], 28($sp) - ; MM32: and16 $[[T3]], $7 - - ; MM64: and $2, $4, $6 - ; MM64: and $3, $5, $7 - %r = and i128 %a, %b ret i128 %r } define signext i1 @and_i1_4(i1 signext %b) { +; MIPS-LABEL: and_i1_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i1_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i1_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i1_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: addiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i1_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: addiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i1_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: addiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i1_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i1_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i1_4: - - ; GP32: addiu $2, $zero, 0 - - ; GP64: addiu $2, $zero, 0 - - ; MM: li16 $2, 0 - %r = and i1 4, %b ret i1 %r } define signext i8 @and_i8_4(i8 signext %b) { +; MIPS-LABEL: and_i8_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 4 +; +; MIPS32R2-LABEL: and_i8_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 4 +; +; MIPS32R6-LABEL: and_i8_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 4 +; +; MIPS64-LABEL: and_i8_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 4 +; +; MIPS64R2-LABEL: and_i8_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 4 +; +; MIPS64R6-LABEL: and_i8_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 4 +; +; MM32R3-LABEL: and_i8_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i8_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i8_4: - - ; GP32: andi $2, $4, 4 - - ; GP64: andi $2, $4, 4 - - ; MM: andi16 $2, $4, 4 - %r = and i8 4, %b ret i8 %r } define signext i16 @and_i16_4(i16 signext %b) { +; MIPS-LABEL: and_i16_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 4 +; +; MIPS32R2-LABEL: and_i16_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 4 +; +; MIPS32R6-LABEL: and_i16_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 4 +; +; MIPS64-LABEL: and_i16_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 4 +; +; MIPS64R2-LABEL: and_i16_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 4 +; +; MIPS64R6-LABEL: and_i16_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 4 +; +; MM32R3-LABEL: and_i16_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i16_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i16_4: - - ; GP32: andi $2, $4, 4 - - ; GP64: andi $2, $4, 4 - - ; MM: andi16 $2, $4, 4 - %r = and i16 4, %b ret i16 %r } define signext i32 @and_i32_4(i32 signext %b) { +; MIPS-LABEL: and_i32_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 4 +; +; MIPS32R2-LABEL: and_i32_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 4 +; +; MIPS32R6-LABEL: and_i32_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 4 +; +; MIPS64-LABEL: and_i32_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 4 +; +; MIPS64R2-LABEL: and_i32_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 4 +; +; MIPS64R6-LABEL: and_i32_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 4 +; +; MM32R3-LABEL: and_i32_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i32_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i32_4: - - ; GP32: andi $2, $4, 4 - - ; GP64: andi $2, $4, 4 - - ; MM: andi16 $2, $4, 4 - %r = and i32 4, %b ret i32 %r } define signext i64 @and_i64_4(i64 signext %b) { +; MIPS-LABEL: and_i64_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $3, $5, 4 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i64_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $3, $5, 4 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i64_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $3, $5, 4 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i64_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 4 +; +; MIPS64R2-LABEL: and_i64_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 4 +; +; MIPS64R6-LABEL: and_i64_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 4 +; +; MM32R3-LABEL: and_i64_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $3, $5, 4 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i64_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $3, $5, 4 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i64_4: - - ; GP32: andi $3, $5, 4 - ; GP32: addiu $2, $zero, 0 - - ; GP64: andi $2, $4, 4 - - ; MM32: andi16 $3, $5, 4 - ; MM32: li16 $2, 0 - - ; MM64: andi $2, $4, 4 - %r = and i64 4, %b ret i64 %r } define signext i128 @and_i128_4(i128 signext %b) { +; MIPS-LABEL: and_i128_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $5, $7, 4 +; MIPS-NEXT: addiu $2, $zero, 0 +; MIPS-NEXT: addiu $3, $zero, 0 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $4, $zero, 0 +; +; MIPS32R2-LABEL: and_i128_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $5, $7, 4 +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; MIPS32R2-NEXT: addiu $3, $zero, 0 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $4, $zero, 0 +; +; MIPS32R6-LABEL: and_i128_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $5, $7, 4 +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; MIPS32R6-NEXT: addiu $3, $zero, 0 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $4, $zero, 0 +; +; MIPS64-LABEL: and_i128_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $3, $5, 4 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i128_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $3, $5, 4 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i128_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $3, $5, 4 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: daddiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i128_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $5, $7, 4 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: li16 $3, 0 +; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i128_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $5, $7, 4 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: li16 $3, 0 +; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i128_4: - - ; GP32: andi $5, $7, 4 - ; GP32: addiu $2, $zero, 0 - ; GP32: addiu $3, $zero, 0 - ; GP32: addiu $4, $zero, 0 - - ; GP64: andi $3, $5, 4 - ; GP64: daddiu $2, $zero, 0 - - ; MM32: andi16 $5, $7, 4 - ; MM32: li16 $2, 0 - ; MM32: li16 $3, 0 - ; MM32: li16 $4, 0 - - ; MM64: andi $3, $5, 4 - ; MM64: daddiu $2, $zero, 0 - %r = and i128 4, %b ret i128 %r } define signext i1 @and_i1_31(i1 signext %b) { +; MIPS-LABEL: and_i1_31: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: and_i1_31: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: and_i1_31: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS64-LABEL: and_i1_31: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: and_i1_31: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: and_i1_31: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MM32R3-LABEL: and_i1_31: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i1_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i1_31: - - ; ALL: move $2, $4 - %r = and i1 31, %b ret i1 %r } define signext i8 @and_i8_31(i8 signext %b) { +; MIPS-LABEL: and_i8_31: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 31 +; +; MIPS32R2-LABEL: and_i8_31: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 31 +; +; MIPS32R6-LABEL: and_i8_31: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 31 +; +; MIPS64-LABEL: and_i8_31: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 31 +; +; MIPS64R2-LABEL: and_i8_31: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 31 +; +; MIPS64R6-LABEL: and_i8_31: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 31 +; +; MM32R3-LABEL: and_i8_31: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 31 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i8_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 31 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i8_31: - - ; GP32: andi $2, $4, 31 - - ; GP64: andi $2, $4, 31 - - ; MM: andi16 $2, $4, 31 - %r = and i8 31, %b ret i8 %r } define signext i16 @and_i16_31(i16 signext %b) { +; MIPS-LABEL: and_i16_31: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 31 +; +; MIPS32R2-LABEL: and_i16_31: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 31 +; +; MIPS32R6-LABEL: and_i16_31: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 31 +; +; MIPS64-LABEL: and_i16_31: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 31 +; +; MIPS64R2-LABEL: and_i16_31: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 31 +; +; MIPS64R6-LABEL: and_i16_31: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 31 +; +; MM32R3-LABEL: and_i16_31: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 31 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i16_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 31 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i16_31: - - ; GP32: andi $2, $4, 31 - - ; GP64: andi $2, $4, 31 - - ; MM: andi16 $2, $4, 31 - %r = and i16 31, %b ret i16 %r } define signext i32 @and_i32_31(i32 signext %b) { +; MIPS-LABEL: and_i32_31: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 31 +; +; MIPS32R2-LABEL: and_i32_31: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 31 +; +; MIPS32R6-LABEL: and_i32_31: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 31 +; +; MIPS64-LABEL: and_i32_31: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 31 +; +; MIPS64R2-LABEL: and_i32_31: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 31 +; +; MIPS64R6-LABEL: and_i32_31: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 31 +; +; MM32R3-LABEL: and_i32_31: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 31 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i32_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 31 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i32_31: - - ; GP32: andi $2, $4, 31 - - ; GP64: andi $2, $4, 31 - - ; MM: andi16 $2, $4, 31 - %r = and i32 31, %b ret i32 %r } define signext i64 @and_i64_31(i64 signext %b) { +; MIPS-LABEL: and_i64_31: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $3, $5, 31 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i64_31: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $3, $5, 31 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i64_31: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $3, $5, 31 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i64_31: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 31 +; +; MIPS64R2-LABEL: and_i64_31: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 31 +; +; MIPS64R6-LABEL: and_i64_31: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 31 +; +; MM32R3-LABEL: and_i64_31: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $3, $5, 31 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i64_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $3, $5, 31 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i64_31: - - ; GP32: andi $3, $5, 31 - ; GP32: addiu $2, $zero, 0 - - ; GP64: andi $2, $4, 31 - - ; MM32: andi16 $3, $5, 31 - ; MM32: li16 $2, 0 - - ; MM64: andi $2, $4, 31 - %r = and i64 31, %b ret i64 %r } define signext i128 @and_i128_31(i128 signext %b) { +; MIPS-LABEL: and_i128_31: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $5, $7, 31 +; MIPS-NEXT: addiu $2, $zero, 0 +; MIPS-NEXT: addiu $3, $zero, 0 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $4, $zero, 0 +; +; MIPS32R2-LABEL: and_i128_31: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $5, $7, 31 +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; MIPS32R2-NEXT: addiu $3, $zero, 0 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $4, $zero, 0 +; +; MIPS32R6-LABEL: and_i128_31: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $5, $7, 31 +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; MIPS32R6-NEXT: addiu $3, $zero, 0 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $4, $zero, 0 +; +; MIPS64-LABEL: and_i128_31: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $3, $5, 31 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i128_31: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $3, $5, 31 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i128_31: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $3, $5, 31 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: daddiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i128_31: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $5, $7, 31 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: li16 $3, 0 +; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i128_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $5, $7, 31 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: li16 $3, 0 +; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i128_31: - - ; GP32: andi $5, $7, 31 - ; GP32: addiu $2, $zero, 0 - ; GP32: addiu $3, $zero, 0 - ; GP32: addiu $4, $zero, 0 - - ; GP64: andi $3, $5, 31 - ; GP64: daddiu $2, $zero, 0 - - ; MM32: andi16 $5, $7, 31 - ; MM32: li16 $2, 0 - ; MM32: li16 $3, 0 - ; MM32: li16 $4, 0 - - ; MM64: andi $3, $5, 31 - ; MM64: daddiu $2, $zero, 0 - %r = and i128 31, %b ret i128 %r } define signext i1 @and_i1_255(i1 signext %b) { +; MIPS-LABEL: and_i1_255: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: and_i1_255: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: and_i1_255: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS64-LABEL: and_i1_255: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: and_i1_255: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: and_i1_255: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MM32R3-LABEL: and_i1_255: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i1_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i1_255: - - ; ALL: move $2, $4 - %r = and i1 255, %b ret i1 %r } define signext i8 @and_i8_255(i8 signext %b) { +; MIPS-LABEL: and_i8_255: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: and_i8_255: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: and_i8_255: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS64-LABEL: and_i8_255: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: and_i8_255: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: and_i8_255: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MM32R3-LABEL: and_i8_255: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i8_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i8_255: - - ; ALL: move $2, $4 - %r = and i8 255, %b ret i8 %r } define signext i16 @and_i16_255(i16 signext %b) { +; MIPS-LABEL: and_i16_255: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 255 +; +; MIPS32R2-LABEL: and_i16_255: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 255 +; +; MIPS32R6-LABEL: and_i16_255: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 255 +; +; MIPS64-LABEL: and_i16_255: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 255 +; +; MIPS64R2-LABEL: and_i16_255: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 255 +; +; MIPS64R6-LABEL: and_i16_255: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 255 +; +; MM32R3-LABEL: and_i16_255: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 255 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i16_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 255 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i16_255: - - ; GP32: andi $2, $4, 255 - - ; GP64: andi $2, $4, 255 - - ; MM: andi16 $2, $4, 255 - %r = and i16 255, %b ret i16 %r } define signext i32 @and_i32_255(i32 signext %b) { +; MIPS-LABEL: and_i32_255: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 255 +; +; MIPS32R2-LABEL: and_i32_255: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 255 +; +; MIPS32R6-LABEL: and_i32_255: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 255 +; +; MIPS64-LABEL: and_i32_255: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 255 +; +; MIPS64R2-LABEL: and_i32_255: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 255 +; +; MIPS64R6-LABEL: and_i32_255: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 255 +; +; MM32R3-LABEL: and_i32_255: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 255 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i32_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 255 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i32_255: - - ; GP32: andi $2, $4, 255 - - ; GP64: andi $2, $4, 255 - - ; MM: andi16 $2, $4, 255 - %r = and i32 255, %b ret i32 %r } define signext i64 @and_i64_255(i64 signext %b) { +; MIPS-LABEL: and_i64_255: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $3, $5, 255 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i64_255: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $3, $5, 255 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i64_255: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $3, $5, 255 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i64_255: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 255 +; +; MIPS64R2-LABEL: and_i64_255: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 255 +; +; MIPS64R6-LABEL: and_i64_255: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 255 +; +; MM32R3-LABEL: and_i64_255: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $3, $5, 255 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i64_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $3, $5, 255 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i64_255: - - ; GP32: andi $3, $5, 255 - ; GP32: addiu $2, $zero, 0 - - ; GP64: andi $2, $4, 255 - - ; MM32: andi16 $3, $5, 255 - ; MM32: li16 $2, 0 - - ; MM64: andi $2, $4, 255 - %r = and i64 255, %b ret i64 %r } define signext i128 @and_i128_255(i128 signext %b) { +; MIPS-LABEL: and_i128_255: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $5, $7, 255 +; MIPS-NEXT: addiu $2, $zero, 0 +; MIPS-NEXT: addiu $3, $zero, 0 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $4, $zero, 0 +; +; MIPS32R2-LABEL: and_i128_255: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $5, $7, 255 +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; MIPS32R2-NEXT: addiu $3, $zero, 0 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $4, $zero, 0 +; +; MIPS32R6-LABEL: and_i128_255: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $5, $7, 255 +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; MIPS32R6-NEXT: addiu $3, $zero, 0 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $4, $zero, 0 +; +; MIPS64-LABEL: and_i128_255: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $3, $5, 255 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i128_255: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $3, $5, 255 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i128_255: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $3, $5, 255 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: daddiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i128_255: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $5, $7, 255 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: li16 $3, 0 +; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i128_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $5, $7, 255 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: li16 $3, 0 +; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i128_255: - - ; GP32: andi $5, $7, 255 - ; GP32: addiu $2, $zero, 0 - ; GP32: addiu $3, $zero, 0 - ; GP32: addiu $4, $zero, 0 - - ; GP64: andi $3, $5, 255 - ; GP64: daddiu $2, $zero, 0 - - ; MM32: andi16 $5, $7, 255 - ; MM32: li16 $2, 0 - ; MM32: li16 $3, 0 - ; MM32: li16 $4, 0 - - ; MM64: andi $3, $5, 255 - ; MM64: daddiu $2, $zero, 0 - %r = and i128 255, %b ret i128 %r } define signext i1 @and_i1_32768(i1 signext %b) { +; MIPS-LABEL: and_i1_32768: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i1_32768: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i1_32768: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i1_32768: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: addiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i1_32768: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: addiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i1_32768: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: addiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i1_32768: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i1_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i1_32768: - - ; GP32: addiu $2, $zero, 0 - - ; GP64: addiu $2, $zero, 0 - - ; MM: li16 $2, 0 - %r = and i1 32768, %b ret i1 %r } define signext i8 @and_i8_32768(i8 signext %b) { +; MIPS-LABEL: and_i8_32768: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i8_32768: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i8_32768: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i8_32768: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: addiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i8_32768: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: addiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i8_32768: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: addiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i8_32768: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i8_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i8_32768: - - ; GP32: addiu $2, $zero, 0 - - ; GP64: addiu $2, $zero, 0 - - ; MM: li16 $2, 0 - %r = and i8 32768, %b ret i8 %r } define signext i16 @and_i16_32768(i16 signext %b) { +; MIPS-LABEL: and_i16_32768: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: addiu $1, $zero, -32768 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: and $2, $4, $1 +; +; MIPS32R2-LABEL: and_i16_32768: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: addiu $1, $zero, -32768 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: and $2, $4, $1 +; +; MIPS32R6-LABEL: and_i16_32768: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: addiu $1, $zero, -32768 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: and $2, $4, $1 +; +; MIPS64-LABEL: and_i16_32768: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: addiu $1, $zero, -32768 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: and $2, $4, $1 +; +; MIPS64R2-LABEL: and_i16_32768: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: addiu $1, $zero, -32768 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: and $2, $4, $1 +; +; MIPS64R6-LABEL: and_i16_32768: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: addiu $1, $zero, -32768 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: and $2, $4, $1 +; +; MM32R3-LABEL: and_i16_32768: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: addiu $2, $zero, -32768 +; MM32R3-NEXT: and16 $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i16_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: addiu $2, $zero, -32768 +; MM32R6-NEXT: and16 $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i16_32768: - - ; GP32: addiu $[[T0:[0-9]+]], $zero, -32768 - ; GP32: and $2, $4, $[[T0]] - - ; GP64: addiu $[[T0:[0-9]+]], $zero, -32768 - ; GP64: and $2, $4, $[[T0]] - - ; MM: addiu $2, $zero, -32768 - ; MM: and16 $2, $4 %r = and i16 32768, %b ret i16 %r } define signext i32 @and_i32_32768(i32 signext %b) { +; MIPS-LABEL: and_i32_32768: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 32768 +; +; MIPS32R2-LABEL: and_i32_32768: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 32768 +; +; MIPS32R6-LABEL: and_i32_32768: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 32768 +; +; MIPS64-LABEL: and_i32_32768: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 32768 +; +; MIPS64R2-LABEL: and_i32_32768: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 32768 +; +; MIPS64R6-LABEL: and_i32_32768: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 32768 +; +; MM32R3-LABEL: and_i32_32768: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $2, $4, 32768 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i32_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $2, $4, 32768 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i32_32768: - - ; GP32: andi $2, $4, 32768 - - ; GP64: andi $2, $4, 32768 - - ; MM: andi16 $2, $4, 32768 - %r = and i32 32768, %b ret i32 %r } define signext i64 @and_i64_32768(i64 signext %b) { +; MIPS-LABEL: and_i64_32768: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $3, $5, 32768 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i64_32768: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $3, $5, 32768 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i64_32768: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $3, $5, 32768 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i64_32768: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 32768 +; +; MIPS64R2-LABEL: and_i64_32768: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 32768 +; +; MIPS64R6-LABEL: and_i64_32768: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 32768 +; +; MM32R3-LABEL: and_i64_32768: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $3, $5, 32768 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i64_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $3, $5, 32768 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i64_32768: - - ; GP32: andi $3, $5, 32768 - ; GP32: addiu $2, $zero, 0 - - ; GP64: andi $2, $4, 32768 - - ; MM32: andi16 $3, $5, 32768 - ; MM32: li16 $2, 0 - - ; MM64: andi $2, $4, 32768 - %r = and i64 32768, %b ret i64 %r } define signext i128 @and_i128_32768(i128 signext %b) { +; MIPS-LABEL: and_i128_32768: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $5, $7, 32768 +; MIPS-NEXT: addiu $2, $zero, 0 +; MIPS-NEXT: addiu $3, $zero, 0 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $4, $zero, 0 +; +; MIPS32R2-LABEL: and_i128_32768: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $5, $7, 32768 +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; MIPS32R2-NEXT: addiu $3, $zero, 0 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $4, $zero, 0 +; +; MIPS32R6-LABEL: and_i128_32768: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $5, $7, 32768 +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; MIPS32R6-NEXT: addiu $3, $zero, 0 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $4, $zero, 0 +; +; MIPS64-LABEL: and_i128_32768: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $3, $5, 32768 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i128_32768: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $3, $5, 32768 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i128_32768: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $3, $5, 32768 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: daddiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i128_32768: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: andi16 $5, $7, 32768 +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: li16 $3, 0 +; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i128_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi16 $5, $7, 32768 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: li16 $3, 0 +; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i128_32768: - - ; GP32: andi $5, $7, 32768 - ; GP32: addiu $2, $zero, 0 - ; GP32: addiu $3, $zero, 0 - ; GP32: addiu $4, $zero, 0 - - ; GP64: andi $3, $5, 32768 - ; GP64: daddiu $2, $zero, 0 - - ; MM32: andi16 $5, $7, 32768 - ; MM32: li16 $2, 0 - ; MM32: li16 $3, 0 - ; MM32: li16 $4, 0 - - ; MM64: andi $3, $5, 32768 - ; MM64: daddiu $2, $zero, 0 - %r = and i128 32768, %b ret i128 %r } define signext i1 @and_i1_65(i1 signext %b) { +; MIPS-LABEL: and_i1_65: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: and_i1_65: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: and_i1_65: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS64-LABEL: and_i1_65: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: and_i1_65: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: and_i1_65: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MM32R3-LABEL: and_i1_65: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i1_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i1_65: - - ; ALL: move $2, $4 - %r = and i1 65, %b ret i1 %r } define signext i8 @and_i8_65(i8 signext %b) { +; MIPS-LABEL: and_i8_65: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 65 +; +; MIPS32R2-LABEL: and_i8_65: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 65 +; +; MIPS32R6-LABEL: and_i8_65: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 65 +; +; MIPS64-LABEL: and_i8_65: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 65 +; +; MIPS64R2-LABEL: and_i8_65: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 65 +; +; MIPS64R6-LABEL: and_i8_65: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 65 +; +; MM32R3-LABEL: and_i8_65: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $2, $4, 65 +; +; MM32R6-LABEL: and_i8_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $2, $4, 65 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i8_65: - - ; ALL: andi $2, $4, 65 - %r = and i8 65, %b ret i8 %r } define signext i16 @and_i16_65(i16 signext %b) { +; MIPS-LABEL: and_i16_65: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 65 +; +; MIPS32R2-LABEL: and_i16_65: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 65 +; +; MIPS32R6-LABEL: and_i16_65: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 65 +; +; MIPS64-LABEL: and_i16_65: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 65 +; +; MIPS64R2-LABEL: and_i16_65: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 65 +; +; MIPS64R6-LABEL: and_i16_65: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 65 +; +; MM32R3-LABEL: and_i16_65: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $2, $4, 65 +; +; MM32R6-LABEL: and_i16_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $2, $4, 65 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i16_65: - - ; ALL: andi $2, $4, 65 - %r = and i16 65, %b ret i16 %r } define signext i32 @and_i32_65(i32 signext %b) { +; MIPS-LABEL: and_i32_65: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 65 +; +; MIPS32R2-LABEL: and_i32_65: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 65 +; +; MIPS32R6-LABEL: and_i32_65: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 65 +; +; MIPS64-LABEL: and_i32_65: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 65 +; +; MIPS64R2-LABEL: and_i32_65: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 65 +; +; MIPS64R6-LABEL: and_i32_65: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 65 +; +; MM32R3-LABEL: and_i32_65: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $2, $4, 65 +; +; MM32R6-LABEL: and_i32_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $2, $4, 65 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i32_65: - - ; ALL: andi $2, $4, 65 - %r = and i32 65, %b ret i32 %r } define signext i64 @and_i64_65(i64 signext %b) { +; MIPS-LABEL: and_i64_65: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $3, $5, 65 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i64_65: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $3, $5, 65 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i64_65: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $3, $5, 65 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i64_65: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 65 +; +; MIPS64R2-LABEL: and_i64_65: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 65 +; +; MIPS64R6-LABEL: and_i64_65: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 65 +; +; MM32R3-LABEL: and_i64_65: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $3, $5, 65 +; +; MM32R6-LABEL: and_i64_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $3, $5, 65 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i64_65: - - ; GP32: andi $3, $5, 65 - ; GP32: addiu $2, $zero, 0 - - ; GP64: andi $2, $4, 65 - - ; MM32-DAG: andi $3, $5, 65 - ; MM32-DAG: li16 $2, 0 - - ; MM64: andi $2, $4, 65 - %r = and i64 65, %b ret i64 %r } define signext i128 @and_i128_65(i128 signext %b) { +; MIPS-LABEL: and_i128_65: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $5, $7, 65 +; MIPS-NEXT: addiu $2, $zero, 0 +; MIPS-NEXT: addiu $3, $zero, 0 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $4, $zero, 0 +; +; MIPS32R2-LABEL: and_i128_65: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $5, $7, 65 +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; MIPS32R2-NEXT: addiu $3, $zero, 0 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $4, $zero, 0 +; +; MIPS32R6-LABEL: and_i128_65: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $5, $7, 65 +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; MIPS32R6-NEXT: addiu $3, $zero, 0 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $4, $zero, 0 +; +; MIPS64-LABEL: and_i128_65: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $3, $5, 65 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i128_65: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $3, $5, 65 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i128_65: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $3, $5, 65 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: daddiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i128_65: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: li16 $3, 0 +; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $5, $7, 65 +; +; MM32R6-LABEL: and_i128_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $5, $7, 65 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: li16 $3, 0 +; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i128_65: - - ; GP32: andi $5, $7, 65 - ; GP32: addiu $2, $zero, 0 - ; GP32: addiu $3, $zero, 0 - ; GP32: addiu $4, $zero, 0 - - ; GP64: andi $3, $5, 65 - ; GP64: daddiu $2, $zero, 0 - - ; MM32-DAG: andi $5, $7, 65 - ; MM32-DAG: li16 $2, 0 - ; MM32-DAG: li16 $3, 0 - ; MM32-DAG: li16 $4, 0 - - ; MM64: andi $3, $5, 65 - ; MM64: daddiu $2, $zero, 0 - %r = and i128 65, %b ret i128 %r } define signext i1 @and_i1_256(i1 signext %b) { +; MIPS-LABEL: and_i1_256: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i1_256: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i1_256: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i1_256: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: addiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i1_256: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: addiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i1_256: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: addiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i1_256: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i1_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i1_256: - - ; GP32: addiu $2, $zero, 0 - - ; GP64: addiu $2, $zero, 0 - - ; MM: li16 $2, 0 - %r = and i1 256, %b ret i1 %r } define signext i8 @and_i8_256(i8 signext %b) { +; MIPS-LABEL: and_i8_256: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i8_256: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i8_256: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i8_256: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: addiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i8_256: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: addiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i8_256: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: addiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i8_256: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: and_i8_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i8_256: - - ; GP32: addiu $2, $zero, 0 - - ; GP64: addiu $2, $zero, 0 - - ; MM: li16 $2, 0 - %r = and i8 256, %b ret i8 %r } define signext i16 @and_i16_256(i16 signext %b) { +; MIPS-LABEL: and_i16_256: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 256 +; +; MIPS32R2-LABEL: and_i16_256: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 256 +; +; MIPS32R6-LABEL: and_i16_256: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 256 +; +; MIPS64-LABEL: and_i16_256: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 256 +; +; MIPS64R2-LABEL: and_i16_256: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 256 +; +; MIPS64R6-LABEL: and_i16_256: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 256 +; +; MM32R3-LABEL: and_i16_256: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $2, $4, 256 +; +; MM32R6-LABEL: and_i16_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $2, $4, 256 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i16_256: - - ; ALL: andi $2, $4, 256 - %r = and i16 256, %b ret i16 %r } define signext i32 @and_i32_256(i32 signext %b) { +; MIPS-LABEL: and_i32_256: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: andi $2, $4, 256 +; +; MIPS32R2-LABEL: and_i32_256: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $4, 256 +; +; MIPS32R6-LABEL: and_i32_256: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $4, 256 +; +; MIPS64-LABEL: and_i32_256: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 256 +; +; MIPS64R2-LABEL: and_i32_256: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 256 +; +; MIPS64R6-LABEL: and_i32_256: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 256 +; +; MM32R3-LABEL: and_i32_256: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $2, $4, 256 +; +; MM32R6-LABEL: and_i32_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $2, $4, 256 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i32_256: - - ; ALL: andi $2, $4, 256 - %r = and i32 256, %b ret i32 %r } define signext i64 @and_i64_256(i64 signext %b) { +; MIPS-LABEL: and_i64_256: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $3, $5, 256 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $2, $zero, 0 +; +; MIPS32R2-LABEL: and_i64_256: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $3, $5, 256 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; +; MIPS32R6-LABEL: and_i64_256: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $3, $5, 256 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; +; MIPS64-LABEL: and_i64_256: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $4, 256 +; +; MIPS64R2-LABEL: and_i64_256: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $4, 256 +; +; MIPS64R6-LABEL: and_i64_256: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $4, 256 +; +; MM32R3-LABEL: and_i64_256: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $3, $5, 256 +; +; MM32R6-LABEL: and_i64_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $3, $5, 256 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i64_256: - - ; GP32: andi $3, $5, 256 - ; GP32: addiu $2, $zero, 0 - - ; GP64: andi $2, $4, 256 - - ; MM32-DAG: andi $3, $5, 256 - ; MM32-DAG: li16 $2, 0 - - ; MM64: andi $2, $4, 256 - %r = and i64 256, %b ret i64 %r } define signext i128 @and_i128_256(i128 signext %b) { +; MIPS-LABEL: and_i128_256: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $5, $7, 256 +; MIPS-NEXT: addiu $2, $zero, 0 +; MIPS-NEXT: addiu $3, $zero, 0 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $4, $zero, 0 +; +; MIPS32R2-LABEL: and_i128_256: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $5, $7, 256 +; MIPS32R2-NEXT: addiu $2, $zero, 0 +; MIPS32R2-NEXT: addiu $3, $zero, 0 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: addiu $4, $zero, 0 +; +; MIPS32R6-LABEL: and_i128_256: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $5, $7, 256 +; MIPS32R6-NEXT: addiu $2, $zero, 0 +; MIPS32R6-NEXT: addiu $3, $zero, 0 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $4, $zero, 0 +; +; MIPS64-LABEL: and_i128_256: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $3, $5, 256 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R2-LABEL: and_i128_256: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $3, $5, 256 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: daddiu $2, $zero, 0 +; +; MIPS64R6-LABEL: and_i128_256: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $3, $5, 256 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: daddiu $2, $zero, 0 +; +; MM32R3-LABEL: and_i128_256: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: li16 $2, 0 +; MM32R3-NEXT: li16 $3, 0 +; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: andi $5, $7, 256 +; +; MM32R6-LABEL: and_i128_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: andi $5, $7, 256 +; MM32R6-NEXT: li16 $2, 0 +; MM32R6-NEXT: li16 $3, 0 +; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: and_i128_256: - - ; GP32: andi $5, $7, 256 - ; GP32: addiu $2, $zero, 0 - ; GP32: addiu $3, $zero, 0 - ; GP32: addiu $4, $zero, 0 - - ; GP64: andi $3, $5, 256 - ; GP64: daddiu $2, $zero, 0 - - ; MM32-DAG: andi $5, $7, 256 - ; MM32-DAG: li16 $2, 0 - ; MM32-DAG: li16 $3, 0 - ; MM32-DAG: li16 $4, 0 - - ; MM64: andi $3, $5, 256 - ; MM64: daddiu $2, $zero, 0 - %r = and i128 256, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/ashr.ll b/test/CodeGen/Mips/llvm-ir/ashr.ll index f9fb91be09064..ec1e9b03b4526 100644 --- a/test/CodeGen/Mips/llvm-ir/ashr.ll +++ b/test/CodeGen/Mips/llvm-ir/ashr.ll @@ -1,225 +1,985 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,M2 -; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,64R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MMR3 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MMR6 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=32R6 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS3 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R6 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MMR3 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MMR6 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) { +; MIPS-LABEL: ashr_i1: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $2, $4 +; +; MIPS32-LABEL: ashr_i1: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: move $2, $4 +; +; 32R2-LABEL: ashr_i1: +; 32R2: # %bb.0: # %entry +; 32R2-NEXT: jr $ra +; 32R2-NEXT: move $2, $4 +; +; 32R6-LABEL: ashr_i1: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: jr $ra +; 32R6-NEXT: move $2, $4 +; +; MIPS3-LABEL: ashr_i1: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: move $2, $4 +; +; MIPS64-LABEL: ashr_i1: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: ashr_i1: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: ashr_i1: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MMR3-LABEL: ashr_i1: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: move $2, $4 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: ashr_i1: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: move $2, $4 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: ashr_i1: - - ; ALL: move $2, $4 - %r = ashr i1 %a, %b ret i1 %r } define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) { +; MIPS-LABEL: ashr_i8: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $1, $5, 255 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: srav $2, $4, $1 +; +; MIPS32-LABEL: ashr_i8: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: andi $1, $5, 255 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: srav $2, $4, $1 +; +; 32R2-LABEL: ashr_i8: +; 32R2: # %bb.0: # %entry +; 32R2-NEXT: andi $1, $5, 255 +; 32R2-NEXT: jr $ra +; 32R2-NEXT: srav $2, $4, $1 +; +; 32R6-LABEL: ashr_i8: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: andi $1, $5, 255 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: srav $2, $4, $1 +; +; MIPS3-LABEL: ashr_i8: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: andi $1, $5, 255 +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: srav $2, $4, $1 +; +; MIPS64-LABEL: ashr_i8: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $1, $5, 255 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: srav $2, $4, $1 +; +; MIPS64R2-LABEL: ashr_i8: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $1, $5, 255 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: srav $2, $4, $1 +; +; MIPS64R6-LABEL: ashr_i8: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $1, $5, 255 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: srav $2, $4, $1 +; +; MMR3-LABEL: ashr_i8: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: andi16 $2, $5, 255 +; MMR3-NEXT: jr $ra +; MMR3-NEXT: srav $2, $4, $2 +; +; MMR6-LABEL: ashr_i8: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: andi16 $2, $5, 255 +; MMR6-NEXT: srav $2, $4, $2 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: ashr_i8: - ; FIXME: The andi instruction is redundant. - ; GP32: andi $[[T0:[0-9]+]], $5, 255 - ; GP64: andi $[[T0:[0-9]+]], $5, 255 - ; MM: andi16 $[[T0:[0-9]+]], $5, 255 - ; ALL: srav $2, $4, $[[T0]] - %r = ashr i8 %a, %b ret i8 %r } define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) { +; MIPS-LABEL: ashr_i16: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: andi $1, $5, 65535 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: srav $2, $4, $1 +; +; MIPS32-LABEL: ashr_i16: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: andi $1, $5, 65535 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: srav $2, $4, $1 +; +; 32R2-LABEL: ashr_i16: +; 32R2: # %bb.0: # %entry +; 32R2-NEXT: andi $1, $5, 65535 +; 32R2-NEXT: jr $ra +; 32R2-NEXT: srav $2, $4, $1 +; +; 32R6-LABEL: ashr_i16: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: andi $1, $5, 65535 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: srav $2, $4, $1 +; +; MIPS3-LABEL: ashr_i16: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: andi $1, $5, 65535 +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: srav $2, $4, $1 +; +; MIPS64-LABEL: ashr_i16: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $1, $5, 65535 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: srav $2, $4, $1 +; +; MIPS64R2-LABEL: ashr_i16: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $1, $5, 65535 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: srav $2, $4, $1 +; +; MIPS64R6-LABEL: ashr_i16: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $1, $5, 65535 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: srav $2, $4, $1 +; +; MMR3-LABEL: ashr_i16: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: andi16 $2, $5, 65535 +; MMR3-NEXT: jr $ra +; MMR3-NEXT: srav $2, $4, $2 +; +; MMR6-LABEL: ashr_i16: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: andi16 $2, $5, 65535 +; MMR6-NEXT: srav $2, $4, $2 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: ashr_i16: - ; FIXME: The andi instruction is redundant. - ; GP32: andi $[[T0:[0-9]+]], $5, 65535 - ; GP64: andi $[[T0:[0-9]+]], $5, 65535 - ; MM: andi16 $[[T0:[0-9]+]], $5, 65535 - ; ALL: srav $2, $4, $[[T0]] - %r = ashr i16 %a, %b ret i16 %r } define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) { +; MIPS-LABEL: ashr_i32: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: srav $2, $4, $5 +; +; MIPS32-LABEL: ashr_i32: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: srav $2, $4, $5 +; +; 32R2-LABEL: ashr_i32: +; 32R2: # %bb.0: # %entry +; 32R2-NEXT: jr $ra +; 32R2-NEXT: srav $2, $4, $5 +; +; 32R6-LABEL: ashr_i32: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: jr $ra +; 32R6-NEXT: srav $2, $4, $5 +; +; MIPS3-LABEL: ashr_i32: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: srav $2, $4, $5 +; +; MIPS64-LABEL: ashr_i32: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: srav $2, $4, $5 +; +; MIPS64R2-LABEL: ashr_i32: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: srav $2, $4, $5 +; +; MIPS64R6-LABEL: ashr_i32: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: srav $2, $4, $5 +; +; MMR3-LABEL: ashr_i32: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: jr $ra +; MMR3-NEXT: srav $2, $4, $5 +; +; MMR6-LABEL: ashr_i32: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: srav $2, $4, $5 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: ashr_i32: - - ; ALL: srav $2, $4, $5 - %r = ashr i32 %a, %b ret i32 %r } define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) { +; MIPS-LABEL: ashr_i64: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: srav $2, $4, $7 +; MIPS-NEXT: andi $6, $7, 32 +; MIPS-NEXT: beqz $6, $BB4_3 +; MIPS-NEXT: move $3, $2 +; MIPS-NEXT: # %bb.1: # %entry +; MIPS-NEXT: bnez $6, $BB4_4 +; MIPS-NEXT: nop +; MIPS-NEXT: $BB4_2: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: nop +; MIPS-NEXT: $BB4_3: # %entry +; MIPS-NEXT: srlv $1, $5, $7 +; MIPS-NEXT: not $3, $7 +; MIPS-NEXT: sll $5, $4, 1 +; MIPS-NEXT: sllv $3, $5, $3 +; MIPS-NEXT: beqz $6, $BB4_2 +; MIPS-NEXT: or $3, $3, $1 +; MIPS-NEXT: $BB4_4: +; MIPS-NEXT: jr $ra +; MIPS-NEXT: sra $2, $4, 31 +; +; MIPS32-LABEL: ashr_i64: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: srlv $1, $5, $7 +; MIPS32-NEXT: not $2, $7 +; MIPS32-NEXT: sll $3, $4, 1 +; MIPS32-NEXT: sllv $2, $3, $2 +; MIPS32-NEXT: or $3, $2, $1 +; MIPS32-NEXT: srav $2, $4, $7 +; MIPS32-NEXT: andi $1, $7, 32 +; MIPS32-NEXT: movn $3, $2, $1 +; MIPS32-NEXT: sra $4, $4, 31 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: movn $2, $4, $1 +; +; 32R2-LABEL: ashr_i64: +; 32R2: # %bb.0: # %entry +; 32R2-NEXT: srlv $1, $5, $7 +; 32R2-NEXT: not $2, $7 +; 32R2-NEXT: sll $3, $4, 1 +; 32R2-NEXT: sllv $2, $3, $2 +; 32R2-NEXT: or $3, $2, $1 +; 32R2-NEXT: srav $2, $4, $7 +; 32R2-NEXT: andi $1, $7, 32 +; 32R2-NEXT: movn $3, $2, $1 +; 32R2-NEXT: sra $4, $4, 31 +; 32R2-NEXT: jr $ra +; 32R2-NEXT: movn $2, $4, $1 +; +; 32R6-LABEL: ashr_i64: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: srav $1, $4, $7 +; 32R6-NEXT: andi $3, $7, 32 +; 32R6-NEXT: seleqz $2, $1, $3 +; 32R6-NEXT: sra $6, $4, 31 +; 32R6-NEXT: selnez $6, $6, $3 +; 32R6-NEXT: or $2, $6, $2 +; 32R6-NEXT: srlv $5, $5, $7 +; 32R6-NEXT: not $6, $7 +; 32R6-NEXT: sll $4, $4, 1 +; 32R6-NEXT: sllv $4, $4, $6 +; 32R6-NEXT: or $4, $4, $5 +; 32R6-NEXT: seleqz $4, $4, $3 +; 32R6-NEXT: selnez $1, $1, $3 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: or $3, $1, $4 +; +; MIPS3-LABEL: ashr_i64: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: dsrav $2, $4, $5 +; +; MIPS64-LABEL: ashr_i64: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: dsrav $2, $4, $5 +; +; MIPS64R2-LABEL: ashr_i64: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: dsrav $2, $4, $5 +; +; MIPS64R6-LABEL: ashr_i64: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: dsrav $2, $4, $5 +; +; MMR3-LABEL: ashr_i64: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: srlv $2, $5, $7 +; MMR3-NEXT: not16 $3, $7 +; MMR3-NEXT: sll16 $5, $4, 1 +; MMR3-NEXT: sllv $3, $5, $3 +; MMR3-NEXT: or16 $3, $2 +; MMR3-NEXT: srav $2, $4, $7 +; MMR3-NEXT: andi16 $5, $7, 32 +; MMR3-NEXT: movn $3, $2, $5 +; MMR3-NEXT: sra $1, $4, 31 +; MMR3-NEXT: jr $ra +; MMR3-NEXT: movn $2, $1, $5 +; +; MMR6-LABEL: ashr_i64: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: srav $1, $4, $7 +; MMR6-NEXT: andi16 $3, $7, 32 +; MMR6-NEXT: seleqz $2, $1, $3 +; MMR6-NEXT: sra $6, $4, 31 +; MMR6-NEXT: selnez $6, $6, $3 +; MMR6-NEXT: or $2, $6, $2 +; MMR6-NEXT: srlv $5, $5, $7 +; MMR6-NEXT: not16 $6, $7 +; MMR6-NEXT: sll16 $4, $4, 1 +; MMR6-NEXT: sllv $4, $4, $6 +; MMR6-NEXT: or16 $4, $5 +; MMR6-NEXT: seleqz $4, $4, $3 +; MMR6-NEXT: selnez $1, $1, $3 +; MMR6-NEXT: or $3, $1, $4 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: ashr_i64: - - ; M2: srav $[[T0:[0-9]+]], $4, $7 - ; M2: andi $[[T1:[0-9]+]], $7, 32 - ; M2: beqz $[[T1]], $[[BB0:BB[0-9_]+]] - ; M2: move $3, $[[T0]] - ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]] - ; M2: nop - ; M2: $[[EXIT:BB[0-9_]+]]: - ; M2: jr $ra - ; M2: nop - ; M2: $[[BB0]]: - ; M2: srlv $[[T2:[0-9]+]], $5, $7 - ; M2: not $[[T3:[0-9]+]], $7 - ; M2: sll $[[T4:[0-9]+]], $4, 1 - ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]] - ; M2: beqz $[[T1]], $[[EXIT]] - ; M2: or $3, $[[T3]], $[[T2]] - ; M2: $[[BB1]]: - ; M2: jr $ra - ; M2: sra $2, $4, 31 - - ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7 - ; 32R1-R5: not $[[T1:[0-9]+]], $7 - ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1 - ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; 32R1-R5: or $3, $[[T3]], $[[T0]] - ; 32R1-R5: srav $[[T4:[0-9]+]], $4, $7 - ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32 - ; 32R1-R5: movn $3, $[[T4]], $[[T5]] - ; 32R1-R5: sra $4, $4, 31 - ; 32R1-R5: jr $ra - ; 32R1-R5: movn $2, $4, $[[T5]] - - ; 32R6: srav $[[T0:[0-9]+]], $4, $7 - ; 32R6: andi $[[T1:[0-9]+]], $7, 32 - ; 32R6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]] - ; 32R6: sra $[[T3:[0-9]+]], $4, 31 - ; 32R6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]] - ; 32R6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]] - ; 32R6: srlv $[[T6:[0-9]+]], $5, $7 - ; 32R6: not $[[T7:[0-9]+]], $7 - ; 32R6: sll $[[T8:[0-9]+]], $4, 1 - ; 32R6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]] - ; 32R6: or $[[T10:[0-9]+]], $[[T9]], $[[T6]] - ; 32R6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]] - ; 32R6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]] - ; 32R6: jr $ra - ; 32R6: or $3, $[[T0]], $[[T11]] - - ; GP64: dsrav $2, $4, $5 - - ; MMR3: srlv $[[T0:[0-9]+]], $5, $7 - ; MMR3: not16 $[[T1:[0-9]+]], $7 - ; MMR3: sll16 $[[T2:[0-9]+]], $4, 1 - ; MMR3: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] - ; MMR3: srav $[[T5:[0-9]+]], $4, $7 - ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 - ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] - ; MMR3: sra $[[T8:[0-9]+]], $4, 31 - ; MMR3: movn $2, $[[T8]], $[[T6]] - - ; MMR6: srav $[[T0:[0-9]+]], $4, $7 - ; MMR6: andi16 $[[T1:[0-9]+]], $7, 32 - ; MMR6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]] - ; MMR6: sra $[[T3:[0-9]+]], $4, 31 - ; MMR6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]] - ; MMR6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]] - ; MMR6: srlv $[[T6:[0-9]+]], $5, $7 - ; MMR6: not16 $[[T7:[0-9]+]], $7 - ; MMR6: sll16 $[[T8:[0-9]+]], $4, 1 - ; MMR6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]] - ; MMR6: or16 $[[T10:[0-9]+]], $[[T6]] - ; MMR6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]] - ; MMR6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]] - ; MMR6: or $3, $[[T12]], $[[T11]] - %r = ashr i64 %a, %b ret i64 %r } define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) { +; MIPS-LABEL: ashr_i128: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: addiu $sp, $sp, -8 +; MIPS-NEXT: .cfi_def_cfa_offset 8 +; MIPS-NEXT: sw $17, 4($sp) # 4-byte Folded Spill +; MIPS-NEXT: sw $16, 0($sp) # 4-byte Folded Spill +; MIPS-NEXT: .cfi_offset 17, -4 +; MIPS-NEXT: .cfi_offset 16, -8 +; MIPS-NEXT: lw $25, 36($sp) +; MIPS-NEXT: addiu $1, $zero, 64 +; MIPS-NEXT: subu $11, $1, $25 +; MIPS-NEXT: sllv $9, $5, $11 +; MIPS-NEXT: andi $13, $11, 32 +; MIPS-NEXT: addiu $2, $zero, 0 +; MIPS-NEXT: bnez $13, $BB5_2 +; MIPS-NEXT: addiu $3, $zero, 0 +; MIPS-NEXT: # %bb.1: # %entry +; MIPS-NEXT: move $3, $9 +; MIPS-NEXT: $BB5_2: # %entry +; MIPS-NEXT: not $gp, $25 +; MIPS-NEXT: srlv $12, $6, $25 +; MIPS-NEXT: andi $8, $25, 32 +; MIPS-NEXT: bnez $8, $BB5_4 +; MIPS-NEXT: move $15, $12 +; MIPS-NEXT: # %bb.3: # %entry +; MIPS-NEXT: srlv $1, $7, $25 +; MIPS-NEXT: sll $10, $6, 1 +; MIPS-NEXT: sllv $10, $10, $gp +; MIPS-NEXT: or $15, $10, $1 +; MIPS-NEXT: $BB5_4: # %entry +; MIPS-NEXT: addiu $10, $25, -64 +; MIPS-NEXT: sll $17, $4, 1 +; MIPS-NEXT: srav $14, $4, $10 +; MIPS-NEXT: andi $24, $10, 32 +; MIPS-NEXT: bnez $24, $BB5_6 +; MIPS-NEXT: move $16, $14 +; MIPS-NEXT: # %bb.5: # %entry +; MIPS-NEXT: srlv $1, $5, $10 +; MIPS-NEXT: not $10, $10 +; MIPS-NEXT: sllv $10, $17, $10 +; MIPS-NEXT: or $16, $10, $1 +; MIPS-NEXT: $BB5_6: # %entry +; MIPS-NEXT: sltiu $10, $25, 64 +; MIPS-NEXT: beqz $10, $BB5_8 +; MIPS-NEXT: nop +; MIPS-NEXT: # %bb.7: +; MIPS-NEXT: or $16, $15, $3 +; MIPS-NEXT: $BB5_8: # %entry +; MIPS-NEXT: srav $15, $4, $25 +; MIPS-NEXT: beqz $8, $BB5_20 +; MIPS-NEXT: move $3, $15 +; MIPS-NEXT: # %bb.9: # %entry +; MIPS-NEXT: sltiu $gp, $25, 1 +; MIPS-NEXT: beqz $gp, $BB5_21 +; MIPS-NEXT: nop +; MIPS-NEXT: $BB5_10: # %entry +; MIPS-NEXT: beqz $10, $BB5_22 +; MIPS-NEXT: sra $25, $4, 31 +; MIPS-NEXT: $BB5_11: # %entry +; MIPS-NEXT: beqz $13, $BB5_23 +; MIPS-NEXT: nop +; MIPS-NEXT: $BB5_12: # %entry +; MIPS-NEXT: beqz $8, $BB5_24 +; MIPS-NEXT: nop +; MIPS-NEXT: $BB5_13: # %entry +; MIPS-NEXT: beqz $24, $BB5_25 +; MIPS-NEXT: move $4, $25 +; MIPS-NEXT: $BB5_14: # %entry +; MIPS-NEXT: bnez $10, $BB5_26 +; MIPS-NEXT: nop +; MIPS-NEXT: $BB5_15: # %entry +; MIPS-NEXT: beqz $gp, $BB5_27 +; MIPS-NEXT: nop +; MIPS-NEXT: $BB5_16: # %entry +; MIPS-NEXT: beqz $8, $BB5_28 +; MIPS-NEXT: move $2, $25 +; MIPS-NEXT: $BB5_17: # %entry +; MIPS-NEXT: bnez $10, $BB5_19 +; MIPS-NEXT: nop +; MIPS-NEXT: $BB5_18: # %entry +; MIPS-NEXT: move $2, $25 +; MIPS-NEXT: $BB5_19: # %entry +; MIPS-NEXT: move $4, $6 +; MIPS-NEXT: move $5, $7 +; MIPS-NEXT: lw $16, 0($sp) # 4-byte Folded Reload +; MIPS-NEXT: lw $17, 4($sp) # 4-byte Folded Reload +; MIPS-NEXT: jr $ra +; MIPS-NEXT: addiu $sp, $sp, 8 +; MIPS-NEXT: $BB5_20: # %entry +; MIPS-NEXT: srlv $1, $5, $25 +; MIPS-NEXT: sllv $3, $17, $gp +; MIPS-NEXT: sltiu $gp, $25, 1 +; MIPS-NEXT: bnez $gp, $BB5_10 +; MIPS-NEXT: or $3, $3, $1 +; MIPS-NEXT: $BB5_21: # %entry +; MIPS-NEXT: move $7, $16 +; MIPS-NEXT: bnez $10, $BB5_11 +; MIPS-NEXT: sra $25, $4, 31 +; MIPS-NEXT: $BB5_22: # %entry +; MIPS-NEXT: bnez $13, $BB5_12 +; MIPS-NEXT: move $3, $25 +; MIPS-NEXT: $BB5_23: # %entry +; MIPS-NEXT: not $1, $11 +; MIPS-NEXT: srl $5, $5, 1 +; MIPS-NEXT: sllv $4, $4, $11 +; MIPS-NEXT: srlv $1, $5, $1 +; MIPS-NEXT: bnez $8, $BB5_13 +; MIPS-NEXT: or $9, $4, $1 +; MIPS-NEXT: $BB5_24: # %entry +; MIPS-NEXT: move $2, $12 +; MIPS-NEXT: bnez $24, $BB5_14 +; MIPS-NEXT: move $4, $25 +; MIPS-NEXT: $BB5_25: # %entry +; MIPS-NEXT: beqz $10, $BB5_15 +; MIPS-NEXT: move $4, $14 +; MIPS-NEXT: $BB5_26: +; MIPS-NEXT: bnez $gp, $BB5_16 +; MIPS-NEXT: or $4, $2, $9 +; MIPS-NEXT: $BB5_27: # %entry +; MIPS-NEXT: move $6, $4 +; MIPS-NEXT: bnez $8, $BB5_17 +; MIPS-NEXT: move $2, $25 +; MIPS-NEXT: $BB5_28: # %entry +; MIPS-NEXT: bnez $10, $BB5_19 +; MIPS-NEXT: move $2, $15 +; MIPS-NEXT: # %bb.29: # %entry +; MIPS-NEXT: b $BB5_18 +; MIPS-NEXT: nop +; +; MIPS32-LABEL: ashr_i128: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lw $9, 28($sp) +; MIPS32-NEXT: srlv $1, $7, $9 +; MIPS32-NEXT: not $2, $9 +; MIPS32-NEXT: sll $3, $6, 1 +; MIPS32-NEXT: sllv $3, $3, $2 +; MIPS32-NEXT: addiu $8, $zero, 64 +; MIPS32-NEXT: or $1, $3, $1 +; MIPS32-NEXT: srlv $10, $6, $9 +; MIPS32-NEXT: subu $3, $8, $9 +; MIPS32-NEXT: sllv $11, $5, $3 +; MIPS32-NEXT: andi $12, $3, 32 +; MIPS32-NEXT: andi $13, $9, 32 +; MIPS32-NEXT: move $8, $11 +; MIPS32-NEXT: movn $8, $zero, $12 +; MIPS32-NEXT: movn $1, $10, $13 +; MIPS32-NEXT: addiu $14, $9, -64 +; MIPS32-NEXT: srlv $15, $5, $14 +; MIPS32-NEXT: sll $24, $4, 1 +; MIPS32-NEXT: not $25, $14 +; MIPS32-NEXT: sllv $25, $24, $25 +; MIPS32-NEXT: or $gp, $1, $8 +; MIPS32-NEXT: or $1, $25, $15 +; MIPS32-NEXT: srav $8, $4, $14 +; MIPS32-NEXT: andi $14, $14, 32 +; MIPS32-NEXT: movn $1, $8, $14 +; MIPS32-NEXT: sllv $15, $4, $3 +; MIPS32-NEXT: not $3, $3 +; MIPS32-NEXT: srl $25, $5, 1 +; MIPS32-NEXT: srlv $3, $25, $3 +; MIPS32-NEXT: sltiu $25, $9, 64 +; MIPS32-NEXT: movn $1, $gp, $25 +; MIPS32-NEXT: or $15, $15, $3 +; MIPS32-NEXT: srlv $3, $5, $9 +; MIPS32-NEXT: sllv $2, $24, $2 +; MIPS32-NEXT: or $5, $2, $3 +; MIPS32-NEXT: srav $24, $4, $9 +; MIPS32-NEXT: movn $5, $24, $13 +; MIPS32-NEXT: sra $2, $4, 31 +; MIPS32-NEXT: movz $1, $7, $9 +; MIPS32-NEXT: move $3, $2 +; MIPS32-NEXT: movn $3, $5, $25 +; MIPS32-NEXT: movn $15, $11, $12 +; MIPS32-NEXT: movn $10, $zero, $13 +; MIPS32-NEXT: or $4, $10, $15 +; MIPS32-NEXT: movn $8, $2, $14 +; MIPS32-NEXT: movn $8, $4, $25 +; MIPS32-NEXT: movz $8, $6, $9 +; MIPS32-NEXT: movn $24, $2, $13 +; MIPS32-NEXT: movn $2, $24, $25 +; MIPS32-NEXT: move $4, $8 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: move $5, $1 +; +; 32R2-LABEL: ashr_i128: +; 32R2: # %bb.0: # %entry +; 32R2-NEXT: lw $9, 28($sp) +; 32R2-NEXT: srlv $1, $7, $9 +; 32R2-NEXT: not $2, $9 +; 32R2-NEXT: sll $3, $6, 1 +; 32R2-NEXT: sllv $3, $3, $2 +; 32R2-NEXT: addiu $8, $zero, 64 +; 32R2-NEXT: or $1, $3, $1 +; 32R2-NEXT: srlv $10, $6, $9 +; 32R2-NEXT: subu $3, $8, $9 +; 32R2-NEXT: sllv $11, $5, $3 +; 32R2-NEXT: andi $12, $3, 32 +; 32R2-NEXT: andi $13, $9, 32 +; 32R2-NEXT: move $8, $11 +; 32R2-NEXT: movn $8, $zero, $12 +; 32R2-NEXT: movn $1, $10, $13 +; 32R2-NEXT: addiu $14, $9, -64 +; 32R2-NEXT: srlv $15, $5, $14 +; 32R2-NEXT: sll $24, $4, 1 +; 32R2-NEXT: not $25, $14 +; 32R2-NEXT: sllv $25, $24, $25 +; 32R2-NEXT: or $gp, $1, $8 +; 32R2-NEXT: or $1, $25, $15 +; 32R2-NEXT: srav $8, $4, $14 +; 32R2-NEXT: andi $14, $14, 32 +; 32R2-NEXT: movn $1, $8, $14 +; 32R2-NEXT: sllv $15, $4, $3 +; 32R2-NEXT: not $3, $3 +; 32R2-NEXT: srl $25, $5, 1 +; 32R2-NEXT: srlv $3, $25, $3 +; 32R2-NEXT: sltiu $25, $9, 64 +; 32R2-NEXT: movn $1, $gp, $25 +; 32R2-NEXT: or $15, $15, $3 +; 32R2-NEXT: srlv $3, $5, $9 +; 32R2-NEXT: sllv $2, $24, $2 +; 32R2-NEXT: or $5, $2, $3 +; 32R2-NEXT: srav $24, $4, $9 +; 32R2-NEXT: movn $5, $24, $13 +; 32R2-NEXT: sra $2, $4, 31 +; 32R2-NEXT: movz $1, $7, $9 +; 32R2-NEXT: move $3, $2 +; 32R2-NEXT: movn $3, $5, $25 +; 32R2-NEXT: movn $15, $11, $12 +; 32R2-NEXT: movn $10, $zero, $13 +; 32R2-NEXT: or $4, $10, $15 +; 32R2-NEXT: movn $8, $2, $14 +; 32R2-NEXT: movn $8, $4, $25 +; 32R2-NEXT: movz $8, $6, $9 +; 32R2-NEXT: movn $24, $2, $13 +; 32R2-NEXT: movn $2, $24, $25 +; 32R2-NEXT: move $4, $8 +; 32R2-NEXT: jr $ra +; 32R2-NEXT: move $5, $1 +; +; 32R6-LABEL: ashr_i128: +; 32R6: # %bb.0: # %entry +; 32R6-NEXT: lw $3, 28($sp) +; 32R6-NEXT: addiu $1, $zero, 64 +; 32R6-NEXT: subu $1, $1, $3 +; 32R6-NEXT: sllv $2, $5, $1 +; 32R6-NEXT: andi $8, $1, 32 +; 32R6-NEXT: selnez $9, $2, $8 +; 32R6-NEXT: sllv $10, $4, $1 +; 32R6-NEXT: not $1, $1 +; 32R6-NEXT: srl $11, $5, 1 +; 32R6-NEXT: srlv $1, $11, $1 +; 32R6-NEXT: or $1, $10, $1 +; 32R6-NEXT: seleqz $1, $1, $8 +; 32R6-NEXT: or $1, $9, $1 +; 32R6-NEXT: srlv $9, $7, $3 +; 32R6-NEXT: not $10, $3 +; 32R6-NEXT: sll $11, $6, 1 +; 32R6-NEXT: sllv $11, $11, $10 +; 32R6-NEXT: or $9, $11, $9 +; 32R6-NEXT: andi $11, $3, 32 +; 32R6-NEXT: seleqz $9, $9, $11 +; 32R6-NEXT: srlv $12, $6, $3 +; 32R6-NEXT: selnez $13, $12, $11 +; 32R6-NEXT: seleqz $12, $12, $11 +; 32R6-NEXT: or $1, $12, $1 +; 32R6-NEXT: seleqz $2, $2, $8 +; 32R6-NEXT: or $8, $13, $9 +; 32R6-NEXT: addiu $9, $3, -64 +; 32R6-NEXT: srlv $12, $5, $9 +; 32R6-NEXT: sll $13, $4, 1 +; 32R6-NEXT: not $14, $9 +; 32R6-NEXT: sllv $14, $13, $14 +; 32R6-NEXT: sltiu $15, $3, 64 +; 32R6-NEXT: or $2, $8, $2 +; 32R6-NEXT: selnez $1, $1, $15 +; 32R6-NEXT: or $8, $14, $12 +; 32R6-NEXT: srav $12, $4, $9 +; 32R6-NEXT: andi $9, $9, 32 +; 32R6-NEXT: seleqz $14, $12, $9 +; 32R6-NEXT: sra $24, $4, 31 +; 32R6-NEXT: selnez $25, $24, $9 +; 32R6-NEXT: seleqz $8, $8, $9 +; 32R6-NEXT: or $14, $25, $14 +; 32R6-NEXT: seleqz $14, $14, $15 +; 32R6-NEXT: selnez $9, $12, $9 +; 32R6-NEXT: seleqz $12, $24, $15 +; 32R6-NEXT: or $1, $1, $14 +; 32R6-NEXT: selnez $14, $1, $3 +; 32R6-NEXT: selnez $1, $2, $15 +; 32R6-NEXT: or $2, $9, $8 +; 32R6-NEXT: srav $8, $4, $3 +; 32R6-NEXT: seleqz $4, $8, $11 +; 32R6-NEXT: selnez $9, $24, $11 +; 32R6-NEXT: or $4, $9, $4 +; 32R6-NEXT: selnez $9, $4, $15 +; 32R6-NEXT: seleqz $2, $2, $15 +; 32R6-NEXT: seleqz $4, $6, $3 +; 32R6-NEXT: seleqz $6, $7, $3 +; 32R6-NEXT: or $1, $1, $2 +; 32R6-NEXT: selnez $1, $1, $3 +; 32R6-NEXT: or $1, $6, $1 +; 32R6-NEXT: or $4, $4, $14 +; 32R6-NEXT: or $2, $9, $12 +; 32R6-NEXT: srlv $3, $5, $3 +; 32R6-NEXT: sllv $5, $13, $10 +; 32R6-NEXT: or $3, $5, $3 +; 32R6-NEXT: seleqz $3, $3, $11 +; 32R6-NEXT: selnez $5, $8, $11 +; 32R6-NEXT: or $3, $5, $3 +; 32R6-NEXT: selnez $3, $3, $15 +; 32R6-NEXT: or $3, $3, $12 +; 32R6-NEXT: jr $ra +; 32R6-NEXT: move $5, $1 +; +; MIPS3-LABEL: ashr_i128: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: sll $8, $7, 0 +; MIPS3-NEXT: dsrav $2, $4, $7 +; MIPS3-NEXT: andi $6, $8, 64 +; MIPS3-NEXT: beqz $6, .LBB5_3 +; MIPS3-NEXT: move $3, $2 +; MIPS3-NEXT: # %bb.1: # %entry +; MIPS3-NEXT: bnez $6, .LBB5_4 +; MIPS3-NEXT: nop +; MIPS3-NEXT: .LBB5_2: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: nop +; MIPS3-NEXT: .LBB5_3: # %entry +; MIPS3-NEXT: dsrlv $1, $5, $7 +; MIPS3-NEXT: dsll $3, $4, 1 +; MIPS3-NEXT: not $5, $8 +; MIPS3-NEXT: dsllv $3, $3, $5 +; MIPS3-NEXT: beqz $6, .LBB5_2 +; MIPS3-NEXT: or $3, $3, $1 +; MIPS3-NEXT: .LBB5_4: +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: dsra $2, $4, 63 +; +; MIPS64-LABEL: ashr_i128: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: dsrlv $1, $5, $7 +; MIPS64-NEXT: dsll $2, $4, 1 +; MIPS64-NEXT: sll $5, $7, 0 +; MIPS64-NEXT: not $3, $5 +; MIPS64-NEXT: dsllv $2, $2, $3 +; MIPS64-NEXT: or $3, $2, $1 +; MIPS64-NEXT: dsrav $2, $4, $7 +; MIPS64-NEXT: andi $1, $5, 64 +; MIPS64-NEXT: movn $3, $2, $1 +; MIPS64-NEXT: dsra $4, $4, 63 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: movn $2, $4, $1 +; +; MIPS64R2-LABEL: ashr_i128: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: dsrlv $1, $5, $7 +; MIPS64R2-NEXT: dsll $2, $4, 1 +; MIPS64R2-NEXT: sll $5, $7, 0 +; MIPS64R2-NEXT: not $3, $5 +; MIPS64R2-NEXT: dsllv $2, $2, $3 +; MIPS64R2-NEXT: or $3, $2, $1 +; MIPS64R2-NEXT: dsrav $2, $4, $7 +; MIPS64R2-NEXT: andi $1, $5, 64 +; MIPS64R2-NEXT: movn $3, $2, $1 +; MIPS64R2-NEXT: dsra $4, $4, 63 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movn $2, $4, $1 +; +; MIPS64R6-LABEL: ashr_i128: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: dsrav $1, $4, $7 +; MIPS64R6-NEXT: sll $3, $7, 0 +; MIPS64R6-NEXT: andi $2, $3, 64 +; MIPS64R6-NEXT: sll $6, $2, 0 +; MIPS64R6-NEXT: seleqz $2, $1, $6 +; MIPS64R6-NEXT: dsra $8, $4, 63 +; MIPS64R6-NEXT: selnez $8, $8, $6 +; MIPS64R6-NEXT: or $2, $8, $2 +; MIPS64R6-NEXT: dsrlv $5, $5, $7 +; MIPS64R6-NEXT: dsll $4, $4, 1 +; MIPS64R6-NEXT: not $3, $3 +; MIPS64R6-NEXT: dsllv $3, $4, $3 +; MIPS64R6-NEXT: or $3, $3, $5 +; MIPS64R6-NEXT: seleqz $3, $3, $6 +; MIPS64R6-NEXT: selnez $1, $1, $6 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: or $3, $1, $3 +; +; MMR3-LABEL: ashr_i128: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: addiusp -48 +; MMR3-NEXT: .cfi_def_cfa_offset 48 +; MMR3-NEXT: sw $17, 44($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $16, 40($sp) # 4-byte Folded Spill +; MMR3-NEXT: .cfi_offset 17, -4 +; MMR3-NEXT: .cfi_offset 16, -8 +; MMR3-NEXT: move $8, $7 +; MMR3-NEXT: sw $6, 32($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $5, 36($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill +; MMR3-NEXT: lw $16, 76($sp) +; MMR3-NEXT: srlv $4, $8, $16 +; MMR3-NEXT: not16 $3, $16 +; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill +; MMR3-NEXT: sll16 $2, $6, 1 +; MMR3-NEXT: sllv $3, $2, $3 +; MMR3-NEXT: li16 $2, 64 +; MMR3-NEXT: or16 $3, $4 +; MMR3-NEXT: srlv $6, $6, $16 +; MMR3-NEXT: sw $6, 12($sp) # 4-byte Folded Spill +; MMR3-NEXT: subu16 $7, $2, $16 +; MMR3-NEXT: sllv $9, $5, $7 +; MMR3-NEXT: andi16 $2, $7, 32 +; MMR3-NEXT: sw $2, 28($sp) # 4-byte Folded Spill +; MMR3-NEXT: andi16 $5, $16, 32 +; MMR3-NEXT: sw $5, 16($sp) # 4-byte Folded Spill +; MMR3-NEXT: move $4, $9 +; MMR3-NEXT: li16 $17, 0 +; MMR3-NEXT: movn $4, $17, $2 +; MMR3-NEXT: movn $3, $6, $5 +; MMR3-NEXT: addiu $2, $16, -64 +; MMR3-NEXT: lw $5, 36($sp) # 4-byte Folded Reload +; MMR3-NEXT: srlv $5, $5, $2 +; MMR3-NEXT: sw $5, 20($sp) # 4-byte Folded Spill +; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload +; MMR3-NEXT: sll16 $6, $17, 1 +; MMR3-NEXT: sw $6, 4($sp) # 4-byte Folded Spill +; MMR3-NEXT: not16 $5, $2 +; MMR3-NEXT: sllv $5, $6, $5 +; MMR3-NEXT: or16 $3, $4 +; MMR3-NEXT: lw $4, 20($sp) # 4-byte Folded Reload +; MMR3-NEXT: or16 $5, $4 +; MMR3-NEXT: srav $1, $17, $2 +; MMR3-NEXT: andi16 $2, $2, 32 +; MMR3-NEXT: sw $2, 20($sp) # 4-byte Folded Spill +; MMR3-NEXT: movn $5, $1, $2 +; MMR3-NEXT: sllv $2, $17, $7 +; MMR3-NEXT: not16 $4, $7 +; MMR3-NEXT: lw $7, 36($sp) # 4-byte Folded Reload +; MMR3-NEXT: srl16 $6, $7, 1 +; MMR3-NEXT: srlv $6, $6, $4 +; MMR3-NEXT: sltiu $10, $16, 64 +; MMR3-NEXT: movn $5, $3, $10 +; MMR3-NEXT: or16 $6, $2 +; MMR3-NEXT: srlv $2, $7, $16 +; MMR3-NEXT: lw $3, 24($sp) # 4-byte Folded Reload +; MMR3-NEXT: lw $4, 4($sp) # 4-byte Folded Reload +; MMR3-NEXT: sllv $3, $4, $3 +; MMR3-NEXT: or16 $3, $2 +; MMR3-NEXT: srav $11, $17, $16 +; MMR3-NEXT: lw $4, 16($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $3, $11, $4 +; MMR3-NEXT: sra $2, $17, 31 +; MMR3-NEXT: movz $5, $8, $16 +; MMR3-NEXT: move $8, $2 +; MMR3-NEXT: movn $8, $3, $10 +; MMR3-NEXT: lw $3, 28($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $6, $9, $3 +; MMR3-NEXT: li16 $3, 0 +; MMR3-NEXT: lw $7, 12($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $7, $3, $4 +; MMR3-NEXT: or16 $7, $6 +; MMR3-NEXT: lw $3, 20($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $1, $2, $3 +; MMR3-NEXT: movn $1, $7, $10 +; MMR3-NEXT: lw $3, 32($sp) # 4-byte Folded Reload +; MMR3-NEXT: movz $1, $3, $16 +; MMR3-NEXT: movn $11, $2, $4 +; MMR3-NEXT: movn $2, $11, $10 +; MMR3-NEXT: move $3, $8 +; MMR3-NEXT: move $4, $1 +; MMR3-NEXT: lw $16, 40($sp) # 4-byte Folded Reload +; MMR3-NEXT: lw $17, 44($sp) # 4-byte Folded Reload +; MMR3-NEXT: addiusp 48 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: ashr_i128: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: addiu $sp, $sp, -40 +; MMR6-NEXT: .cfi_def_cfa_offset 40 +; MMR6-NEXT: sw $17, 36($sp) # 4-byte Folded Spill +; MMR6-NEXT: sw $16, 32($sp) # 4-byte Folded Spill +; MMR6-NEXT: .cfi_offset 17, -4 +; MMR6-NEXT: .cfi_offset 16, -8 +; MMR6-NEXT: move $1, $7 +; MMR6-NEXT: sw $6, 28($sp) # 4-byte Folded Spill +; MMR6-NEXT: move $6, $5 +; MMR6-NEXT: sw $4, 12($sp) # 4-byte Folded Spill +; MMR6-NEXT: lw $3, 68($sp) +; MMR6-NEXT: li16 $2, 64 +; MMR6-NEXT: subu16 $7, $2, $3 +; MMR6-NEXT: sllv $8, $6, $7 +; MMR6-NEXT: andi16 $5, $7, 32 +; MMR6-NEXT: selnez $9, $8, $5 +; MMR6-NEXT: sllv $16, $4, $7 +; MMR6-NEXT: not16 $7, $7 +; MMR6-NEXT: srl16 $17, $6, 1 +; MMR6-NEXT: sw $6, 20($sp) # 4-byte Folded Spill +; MMR6-NEXT: srlv $7, $17, $7 +; MMR6-NEXT: or16 $7, $16 +; MMR6-NEXT: seleqz $7, $7, $5 +; MMR6-NEXT: or $7, $9, $7 +; MMR6-NEXT: srlv $17, $1, $3 +; MMR6-NEXT: not16 $2, $3 +; MMR6-NEXT: sw $2, 24($sp) # 4-byte Folded Spill +; MMR6-NEXT: lw $4, 28($sp) # 4-byte Folded Reload +; MMR6-NEXT: sll16 $16, $4, 1 +; MMR6-NEXT: sllv $16, $16, $2 +; MMR6-NEXT: or16 $16, $17 +; MMR6-NEXT: andi16 $17, $3, 32 +; MMR6-NEXT: seleqz $9, $16, $17 +; MMR6-NEXT: srlv $10, $4, $3 +; MMR6-NEXT: selnez $11, $10, $17 +; MMR6-NEXT: seleqz $16, $10, $17 +; MMR6-NEXT: or16 $16, $7 +; MMR6-NEXT: seleqz $2, $8, $5 +; MMR6-NEXT: sw $2, 8($sp) # 4-byte Folded Spill +; MMR6-NEXT: or $7, $11, $9 +; MMR6-NEXT: addiu $2, $3, -64 +; MMR6-NEXT: srlv $4, $6, $2 +; MMR6-NEXT: sw $4, 4($sp) # 4-byte Folded Spill +; MMR6-NEXT: lw $5, 12($sp) # 4-byte Folded Reload +; MMR6-NEXT: sll16 $4, $5, 1 +; MMR6-NEXT: sw $4, 16($sp) # 4-byte Folded Spill +; MMR6-NEXT: not16 $6, $2 +; MMR6-NEXT: sllv $6, $4, $6 +; MMR6-NEXT: sltiu $8, $3, 64 +; MMR6-NEXT: move $4, $7 +; MMR6-NEXT: lw $7, 8($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $4, $7 +; MMR6-NEXT: selnez $9, $16, $8 +; MMR6-NEXT: lw $7, 4($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $6, $7 +; MMR6-NEXT: srav $7, $5, $2 +; MMR6-NEXT: andi16 $2, $2, 32 +; MMR6-NEXT: seleqz $10, $7, $2 +; MMR6-NEXT: sra $11, $5, 31 +; MMR6-NEXT: selnez $12, $11, $2 +; MMR6-NEXT: seleqz $6, $6, $2 +; MMR6-NEXT: or $10, $12, $10 +; MMR6-NEXT: seleqz $10, $10, $8 +; MMR6-NEXT: selnez $2, $7, $2 +; MMR6-NEXT: seleqz $7, $11, $8 +; MMR6-NEXT: or $9, $9, $10 +; MMR6-NEXT: selnez $9, $9, $3 +; MMR6-NEXT: selnez $4, $4, $8 +; MMR6-NEXT: or $2, $2, $6 +; MMR6-NEXT: srav $5, $5, $3 +; MMR6-NEXT: seleqz $6, $5, $17 +; MMR6-NEXT: selnez $10, $11, $17 +; MMR6-NEXT: or $6, $10, $6 +; MMR6-NEXT: selnez $6, $6, $8 +; MMR6-NEXT: seleqz $2, $2, $8 +; MMR6-NEXT: lw $16, 28($sp) # 4-byte Folded Reload +; MMR6-NEXT: seleqz $10, $16, $3 +; MMR6-NEXT: seleqz $1, $1, $3 +; MMR6-NEXT: or $2, $4, $2 +; MMR6-NEXT: selnez $2, $2, $3 +; MMR6-NEXT: or $1, $1, $2 +; MMR6-NEXT: or $4, $10, $9 +; MMR6-NEXT: or $2, $6, $7 +; MMR6-NEXT: lw $6, 20($sp) # 4-byte Folded Reload +; MMR6-NEXT: srlv $3, $6, $3 +; MMR6-NEXT: lw $6, 24($sp) # 4-byte Folded Reload +; MMR6-NEXT: lw $16, 16($sp) # 4-byte Folded Reload +; MMR6-NEXT: sllv $6, $16, $6 +; MMR6-NEXT: or16 $6, $3 +; MMR6-NEXT: seleqz $3, $6, $17 +; MMR6-NEXT: selnez $5, $5, $17 +; MMR6-NEXT: or $3, $5, $3 +; MMR6-NEXT: selnez $3, $3, $8 +; MMR6-NEXT: or $3, $3, $7 +; MMR6-NEXT: move $5, $1 +; MMR6-NEXT: lw $16, 32($sp) # 4-byte Folded Reload +; MMR6-NEXT: lw $17, 36($sp) # 4-byte Folded Reload +; MMR6-NEXT: addiu $sp, $sp, 40 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: ashr_i128: - - ; o32 shouldn't use TImode helpers. - ; GP32-NOT: lw $25, %call16(__ashrti3)($gp) - ; MM-NOT: lw $25, %call16(__ashrti3)($2) - - ; M3: sll $[[T0:[0-9]+]], $7, 0 - ; M3: dsrav $[[T1:[0-9]+]], $4, $7 - ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 - ; M3: beqz $[[T3:[0-9]+]], [[BB0:.LBB[0-9_]+]] - ; M3: move $3, $[[T1]] - ; M3: bnez $[[T3]], [[BB1:.LBB[0-9_]+]] - ; M3: nop - ; M3: [[EXIT:.LBB[0-9_]+]]: - ; M3: jr $ra - ; M3: nop - ; M3: [[BB0]]: - ; M3: dsrlv $[[T4:[0-9]+]], $5, $7 - ; M3: dsll $[[T5:[0-9]+]], $4, 1 - ; M3: not $[[T6:[0-9]+]], $[[T0]] - ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] - ; M3: beqz $[[T3]], [[EXIT]] - ; M3: or $3, $[[T7]], $[[T4]] - ; M3: [[BB1]]: - ; M3: jr $ra - ; M3: dsra $2, $4, 63 - - ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7 - ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1 - ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 - ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] - ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] - ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]] - ; GP64-NOT-R6: dsrav $2, $4, $7 - ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64 - ; GP64-NOT-R6: movn $3, $2, $[[T5]] - ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 63 - ; GP64-NOT-R6: jr $ra - ; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]] - - ; 64R6: dsrav $[[T0:[0-9]+]], $4, $7 - ; 64R6: sll $[[T1:[0-9]+]], $7, 0 - ; 64R6: andi $[[T2:[0-9]+]], $[[T1]], 64 - ; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0 - ; 64R6: seleqz $[[T4:[0-9]+]], $[[T0]], $[[T3]] - ; 64R6: dsra $[[T5:[0-9]+]], $4, 63 - ; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]] - ; 64R6: or $2, $[[T6]], $[[T4]] - ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $7 - ; 64R6: dsll $[[T8:[0-9]+]], $4, 1 - ; 64R6: not $[[T9:[0-9]+]], $[[T1]] - ; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]] - ; 64R6: or $[[T11:[0-9]+]], $[[T10]], $[[T7]] - ; 64R6: seleqz $[[T12:[0-9]+]], $[[T11]], $[[T3]] - ; 64R6: selnez $[[T13:[0-9]+]], $[[T0]], $[[T3]] - ; 64R6: jr $ra - ; 64R6: or $3, $[[T13]], $[[T12]] +; o32 shouldn't use TImode helpers. +; GP32-NOT: lw $25, %call16(__ashrti3)($gp) +; MM-NOT: lw $25, %call16(__ashrti3)($2) %r = ashr i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/call.ll b/test/CodeGen/Mips/llvm-ir/call.ll index a036fafbe9691..2f5349f641a87 100644 --- a/test/CodeGen/Mips/llvm-ir/call.ll +++ b/test/CodeGen/Mips/llvm-ir/call.ll @@ -161,8 +161,8 @@ declare hidden void @undef_double(i32 %this, double %volume) unnamed_addr align define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr align 2 { ; ALL-LABEL: thunk_undef_double: -; O32: # implicit-def: %A2 -; O32: # implicit-def: %A3 +; O32: # implicit-def: %a2 +; O32: # implicit-def: %a3 ; NOT-R6C: jr $[[TGT]] ; R6C: jrc $[[TGT]] diff --git a/test/CodeGen/Mips/llvm-ir/extractelement.ll b/test/CodeGen/Mips/llvm-ir/extractelement.ll index 3c7df4a5e99fc..f7b8ea5f9e15e 100644 --- a/test/CodeGen/Mips/llvm-ir/extractelement.ll +++ b/test/CodeGen/Mips/llvm-ir/extractelement.ll @@ -12,8 +12,7 @@ define i1 @via_stack_bug(i8 signext %idx) { ; ALL-LABEL: via_stack_bug: ; ALL-DAG: addiu [[ONE:\$[0-9]+]], $zero, 1 -; ALL-DAG: sb [[ONE]], 7($sp) -; ALL-DAG: sb $zero, 6($sp) +; ALL-DAG: sh [[ONE]], 6($sp) ; ALL-DAG: andi [[MASKED_IDX:\$[0-9]+]], $4, 1 ; ALL-DAG: addiu [[VPTR:\$[0-9]+]], $sp, 6 ; ALL-DAG: or [[EPTR:\$[0-9]+]], [[MASKED_IDX]], [[VPTR]] diff --git a/test/CodeGen/Mips/llvm-ir/lh_lhu.ll b/test/CodeGen/Mips/llvm-ir/lh_lhu.ll index fadcfdb0fb4fe..192e10ae8fc7d 100644 --- a/test/CodeGen/Mips/llvm-ir/lh_lhu.ll +++ b/test/CodeGen/Mips/llvm-ir/lh_lhu.ll @@ -1,7 +1,6 @@ ; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s @us = global i16 0, align 2 diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll index 926f3e4c8d798..057a7fb237edf 100644 --- a/test/CodeGen/Mips/llvm-ir/lshr.ll +++ b/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -1,214 +1,1017 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,M2 -; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,64R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MMR3 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MMR6 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R6 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS3 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS4 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R6 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MMR3 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MMR6 define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) { +; MIPS2-LABEL: lshr_i1: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: move $2, $4 +; +; MIPS32-LABEL: lshr_i1: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: lshr_i1: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: lshr_i1: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS3-LABEL: lshr_i1: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: move $2, $4 +; +; MIPS4-LABEL: lshr_i1: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: move $2, $4 +; +; MIPS64-LABEL: lshr_i1: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: lshr_i1: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: lshr_i1: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MMR3-LABEL: lshr_i1: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: move $2, $4 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: lshr_i1: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: move $2, $4 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: lshr_i1: - - ; ALL: move $2, $4 %r = lshr i1 %a, %b ret i1 %r } define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) { +; MIPS2-LABEL: lshr_i8: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: srlv $1, $4, $5 +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: andi $2, $1, 255 +; +; MIPS32-LABEL: lshr_i8: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: srlv $1, $4, $5 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: andi $2, $1, 255 +; +; MIPS32R2-LABEL: lshr_i8: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: srlv $1, $4, $5 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $1, 255 +; +; MIPS32R6-LABEL: lshr_i8: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: srlv $1, $4, $5 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $1, 255 +; +; MIPS3-LABEL: lshr_i8: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: srlv $1, $4, $5 +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: andi $2, $1, 255 +; +; MIPS4-LABEL: lshr_i8: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: srlv $1, $4, $5 +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: andi $2, $1, 255 +; +; MIPS64-LABEL: lshr_i8: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: srlv $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $1, 255 +; +; MIPS64R2-LABEL: lshr_i8: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: srlv $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $1, 255 +; +; MIPS64R6-LABEL: lshr_i8: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: srlv $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $1, 255 +; +; MMR3-LABEL: lshr_i8: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: srlv $2, $4, $5 +; MMR3-NEXT: andi16 $2, $2, 255 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: lshr_i8: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: srlv $2, $4, $5 +; MMR6-NEXT: andi16 $2, $2, 255 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: lshr_i8: - - ; ALL: srlv $[[T0:[0-9]+]], $4, $5 - ; GP32: andi $2, $[[T0]], 255 - ; GP64: andi $2, $[[T0]], 255 - ; MM: andi16 $2, $[[T0]], 255 %r = lshr i8 %a, %b ret i8 %r } define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) { +; MIPS2-LABEL: lshr_i16: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: srlv $1, $4, $5 +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: andi $2, $1, 65535 +; +; MIPS32-LABEL: lshr_i16: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: srlv $1, $4, $5 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: andi $2, $1, 65535 +; +; MIPS32R2-LABEL: lshr_i16: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: srlv $1, $4, $5 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: andi $2, $1, 65535 +; +; MIPS32R6-LABEL: lshr_i16: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: srlv $1, $4, $5 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: andi $2, $1, 65535 +; +; MIPS3-LABEL: lshr_i16: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: srlv $1, $4, $5 +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: andi $2, $1, 65535 +; +; MIPS4-LABEL: lshr_i16: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: srlv $1, $4, $5 +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: andi $2, $1, 65535 +; +; MIPS64-LABEL: lshr_i16: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: srlv $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: andi $2, $1, 65535 +; +; MIPS64R2-LABEL: lshr_i16: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: srlv $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: andi $2, $1, 65535 +; +; MIPS64R6-LABEL: lshr_i16: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: srlv $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: andi $2, $1, 65535 +; +; MMR3-LABEL: lshr_i16: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: srlv $2, $4, $5 +; MMR3-NEXT: andi16 $2, $2, 65535 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: lshr_i16: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: srlv $2, $4, $5 +; MMR6-NEXT: andi16 $2, $2, 65535 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: lshr_i16: - - ; ALL: srlv $[[T0:[0-9]+]], $4, $5 - ; GP32: andi $2, $[[T0]], 65535 - ; GP64: andi $2, $[[T0]], 65535 - ; MM: andi16 $2, $[[T0]], 65535 %r = lshr i16 %a, %b ret i16 %r } define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) { +; MIPS2-LABEL: lshr_i32: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: srlv $2, $4, $5 +; +; MIPS32-LABEL: lshr_i32: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: srlv $2, $4, $5 +; +; MIPS32R2-LABEL: lshr_i32: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: srlv $2, $4, $5 +; +; MIPS32R6-LABEL: lshr_i32: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: srlv $2, $4, $5 +; +; MIPS3-LABEL: lshr_i32: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: srlv $2, $4, $5 +; +; MIPS4-LABEL: lshr_i32: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: srlv $2, $4, $5 +; +; MIPS64-LABEL: lshr_i32: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: srlv $2, $4, $5 +; +; MIPS64R2-LABEL: lshr_i32: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: srlv $2, $4, $5 +; +; MIPS64R6-LABEL: lshr_i32: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: srlv $2, $4, $5 +; +; MMR3-LABEL: lshr_i32: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: jr $ra +; MMR3-NEXT: srlv $2, $4, $5 +; +; MMR6-LABEL: lshr_i32: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: srlv $2, $4, $5 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: lshr_i32: - - ; ALL: srlv $2, $4, $5 %r = lshr i32 %a, %b ret i32 %r } define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) { +; MIPS2-LABEL: lshr_i64: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: srlv $6, $4, $7 +; MIPS2-NEXT: andi $8, $7, 32 +; MIPS2-NEXT: beqz $8, $BB4_3 +; MIPS2-NEXT: move $3, $6 +; MIPS2-NEXT: # %bb.1: # %entry +; MIPS2-NEXT: beqz $8, $BB4_4 +; MIPS2-NEXT: addiu $2, $zero, 0 +; MIPS2-NEXT: $BB4_2: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB4_3: # %entry +; MIPS2-NEXT: srlv $1, $5, $7 +; MIPS2-NEXT: not $2, $7 +; MIPS2-NEXT: sll $3, $4, 1 +; MIPS2-NEXT: sllv $2, $3, $2 +; MIPS2-NEXT: or $3, $2, $1 +; MIPS2-NEXT: bnez $8, $BB4_2 +; MIPS2-NEXT: addiu $2, $zero, 0 +; MIPS2-NEXT: $BB4_4: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: move $2, $6 +; +; MIPS32-LABEL: lshr_i64: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: srlv $1, $5, $7 +; MIPS32-NEXT: not $2, $7 +; MIPS32-NEXT: sll $3, $4, 1 +; MIPS32-NEXT: sllv $2, $3, $2 +; MIPS32-NEXT: or $3, $2, $1 +; MIPS32-NEXT: srlv $2, $4, $7 +; MIPS32-NEXT: andi $1, $7, 32 +; MIPS32-NEXT: movn $3, $2, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: movn $2, $zero, $1 +; +; MIPS32R2-LABEL: lshr_i64: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: srlv $1, $5, $7 +; MIPS32R2-NEXT: not $2, $7 +; MIPS32R2-NEXT: sll $3, $4, 1 +; MIPS32R2-NEXT: sllv $2, $3, $2 +; MIPS32R2-NEXT: or $3, $2, $1 +; MIPS32R2-NEXT: srlv $2, $4, $7 +; MIPS32R2-NEXT: andi $1, $7, 32 +; MIPS32R2-NEXT: movn $3, $2, $1 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: movn $2, $zero, $1 +; +; MIPS32R6-LABEL: lshr_i64: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: srlv $1, $5, $7 +; MIPS32R6-NEXT: not $2, $7 +; MIPS32R6-NEXT: sll $3, $4, 1 +; MIPS32R6-NEXT: sllv $2, $3, $2 +; MIPS32R6-NEXT: or $1, $2, $1 +; MIPS32R6-NEXT: andi $2, $7, 32 +; MIPS32R6-NEXT: seleqz $1, $1, $2 +; MIPS32R6-NEXT: srlv $4, $4, $7 +; MIPS32R6-NEXT: selnez $3, $4, $2 +; MIPS32R6-NEXT: or $3, $3, $1 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: seleqz $2, $4, $2 +; +; MIPS3-LABEL: lshr_i64: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: dsrlv $2, $4, $5 +; +; MIPS4-LABEL: lshr_i64: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: dsrlv $2, $4, $5 +; +; MIPS64-LABEL: lshr_i64: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: dsrlv $2, $4, $5 +; +; MIPS64R2-LABEL: lshr_i64: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: dsrlv $2, $4, $5 +; +; MIPS64R6-LABEL: lshr_i64: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: dsrlv $2, $4, $5 +; +; MMR3-LABEL: lshr_i64: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: srlv $2, $5, $7 +; MMR3-NEXT: not16 $3, $7 +; MMR3-NEXT: sll16 $5, $4, 1 +; MMR3-NEXT: sllv $3, $5, $3 +; MMR3-NEXT: or16 $3, $2 +; MMR3-NEXT: srlv $2, $4, $7 +; MMR3-NEXT: andi16 $4, $7, 32 +; MMR3-NEXT: movn $3, $2, $4 +; MMR3-NEXT: li16 $5, 0 +; MMR3-NEXT: jr $ra +; MMR3-NEXT: movn $2, $5, $4 +; +; MMR6-LABEL: lshr_i64: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: srlv $2, $5, $7 +; MMR6-NEXT: not16 $3, $7 +; MMR6-NEXT: sll16 $5, $4, 1 +; MMR6-NEXT: sllv $3, $5, $3 +; MMR6-NEXT: or16 $3, $2 +; MMR6-NEXT: andi16 $2, $7, 32 +; MMR6-NEXT: seleqz $1, $3, $2 +; MMR6-NEXT: srlv $4, $4, $7 +; MMR6-NEXT: selnez $3, $4, $2 +; MMR6-NEXT: or $3, $3, $1 +; MMR6-NEXT: seleqz $2, $4, $2 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: lshr_i64: - - ; M2: srlv $[[T0:[0-9]+]], $4, $7 - ; M2: andi $[[T1:[0-9]+]], $7, 32 - ; M2: beqz $[[T1]], $[[BB0:BB[0-9_]+]] - ; M2: move $3, $[[T0]] - ; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]] - ; M2: addiu $2, $zero, 0 - ; M2: $[[EXIT:BB[0-9_]+]]: - ; M2: jr $ra - ; M2: nop - ; M2: $[[BB0]]: - ; M2: srlv $[[T2:[0-9]+]], $5, $7 - ; M2: not $[[T3:[0-9]+]], $7 - ; M2: sll $[[T4:[0-9]+]], $4, 1 - ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]] - ; M2: or $3, $[[T3]], $[[T2]] - ; M2: bnez $[[T1]], $[[EXIT:BB[0-9_]+]] - ; M2: addiu $2, $zero, 0 - ; M2: $[[BB1]]: - ; M2: jr $ra - ; M2: move $2, $[[T0]] - - ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7 - ; 32R1-R5: not $[[T1:[0-9]+]], $7 - ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1 - ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; 32R1-R5: or $3, $[[T3]], $[[T0]] - ; 32R1-R5: srlv $[[T4:[0-9]+]], $4, $7 - ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32 - ; 32R1-R5: movn $3, $[[T4]], $[[T5]] - ; 32R1-R5: jr $ra - ; 32R1-R5: movn $2, $zero, $[[T5]] - - ; 32R6: srlv $[[T0:[0-9]+]], $5, $7 - ; 32R6: not $[[T1:[0-9]+]], $7 - ; 32R6: sll $[[T2:[0-9]+]], $4, 1 - ; 32R6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; 32R6: or $[[T4:[0-9]+]], $[[T3]], $[[T0]] - ; 32R6: andi $[[T5:[0-9]+]], $7, 32 - ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T3]] - ; 32R6: srlv $[[T7:[0-9]+]], $4, $7 - ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] - ; 32R6: or $3, $[[T8]], $[[T6]] - ; 32R6: jr $ra - ; 32R6: seleqz $2, $[[T7]], $[[T5]] - - ; GP64: dsrlv $2, $4, $5 - - ; MMR3: srlv $[[T0:[0-9]+]], $5, $7 - ; MMR3: not16 $[[T1:[0-9]+]], $7 - ; MMR3: sll16 $[[T2:[0-9]+]], $4, 1 - ; MMR3: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] - ; MMR3: srlv $[[T5:[0-9]+]], $4, $7 - ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 - ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] - ; MMR3: li16 $[[T8:[0-9]+]], 0 - ; MMR3: movn $2, $[[T8]], $[[T6]] - - ; MMR6: srlv $[[T0:[0-9]+]], $5, $7 - ; MMR6: not16 $[[T1:[0-9]+]], $7 - ; MMR6: sll16 $[[T2:[0-9]+]], $4, 1 - ; MMR6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]] - ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32 - ; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]] - ; MMR6: srlv $[[T7:[0-9]+]], $4, $7 - ; MMR6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] - ; MMR6: or $3, $[[T8]], $[[T6]] - ; MMR6: seleqz $2, $[[T7]], $[[T5]] %r = lshr i64 %a, %b ret i64 %r } define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { +; MIPS2-LABEL: lshr_i128: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: addiu $sp, $sp, -8 +; MIPS2-NEXT: .cfi_def_cfa_offset 8 +; MIPS2-NEXT: sw $17, 4($sp) # 4-byte Folded Spill +; MIPS2-NEXT: sw $16, 0($sp) # 4-byte Folded Spill +; MIPS2-NEXT: .cfi_offset 17, -4 +; MIPS2-NEXT: .cfi_offset 16, -8 +; MIPS2-NEXT: lw $2, 36($sp) +; MIPS2-NEXT: addiu $1, $zero, 64 +; MIPS2-NEXT: subu $10, $1, $2 +; MIPS2-NEXT: sllv $9, $5, $10 +; MIPS2-NEXT: andi $13, $10, 32 +; MIPS2-NEXT: addiu $8, $zero, 0 +; MIPS2-NEXT: bnez $13, $BB5_2 +; MIPS2-NEXT: addiu $25, $zero, 0 +; MIPS2-NEXT: # %bb.1: # %entry +; MIPS2-NEXT: move $25, $9 +; MIPS2-NEXT: $BB5_2: # %entry +; MIPS2-NEXT: not $3, $2 +; MIPS2-NEXT: srlv $11, $6, $2 +; MIPS2-NEXT: andi $12, $2, 32 +; MIPS2-NEXT: bnez $12, $BB5_4 +; MIPS2-NEXT: move $16, $11 +; MIPS2-NEXT: # %bb.3: # %entry +; MIPS2-NEXT: srlv $1, $7, $2 +; MIPS2-NEXT: sll $14, $6, 1 +; MIPS2-NEXT: sllv $14, $14, $3 +; MIPS2-NEXT: or $16, $14, $1 +; MIPS2-NEXT: $BB5_4: # %entry +; MIPS2-NEXT: addiu $24, $2, -64 +; MIPS2-NEXT: sll $17, $4, 1 +; MIPS2-NEXT: srlv $14, $4, $24 +; MIPS2-NEXT: andi $15, $24, 32 +; MIPS2-NEXT: bnez $15, $BB5_6 +; MIPS2-NEXT: move $gp, $14 +; MIPS2-NEXT: # %bb.5: # %entry +; MIPS2-NEXT: srlv $1, $5, $24 +; MIPS2-NEXT: not $24, $24 +; MIPS2-NEXT: sllv $24, $17, $24 +; MIPS2-NEXT: or $gp, $24, $1 +; MIPS2-NEXT: $BB5_6: # %entry +; MIPS2-NEXT: sltiu $24, $2, 64 +; MIPS2-NEXT: beqz $24, $BB5_8 +; MIPS2-NEXT: nop +; MIPS2-NEXT: # %bb.7: +; MIPS2-NEXT: or $gp, $16, $25 +; MIPS2-NEXT: $BB5_8: # %entry +; MIPS2-NEXT: srlv $25, $4, $2 +; MIPS2-NEXT: bnez $12, $BB5_10 +; MIPS2-NEXT: move $16, $25 +; MIPS2-NEXT: # %bb.9: # %entry +; MIPS2-NEXT: srlv $1, $5, $2 +; MIPS2-NEXT: sllv $3, $17, $3 +; MIPS2-NEXT: or $16, $3, $1 +; MIPS2-NEXT: $BB5_10: # %entry +; MIPS2-NEXT: bnez $12, $BB5_12 +; MIPS2-NEXT: addiu $3, $zero, 0 +; MIPS2-NEXT: # %bb.11: # %entry +; MIPS2-NEXT: move $3, $25 +; MIPS2-NEXT: $BB5_12: # %entry +; MIPS2-NEXT: addiu $1, $zero, 63 +; MIPS2-NEXT: sltiu $25, $2, 1 +; MIPS2-NEXT: beqz $25, $BB5_22 +; MIPS2-NEXT: sltu $17, $1, $2 +; MIPS2-NEXT: # %bb.13: # %entry +; MIPS2-NEXT: beqz $17, $BB5_23 +; MIPS2-NEXT: addiu $2, $zero, 0 +; MIPS2-NEXT: $BB5_14: # %entry +; MIPS2-NEXT: beqz $17, $BB5_24 +; MIPS2-NEXT: addiu $3, $zero, 0 +; MIPS2-NEXT: $BB5_15: # %entry +; MIPS2-NEXT: beqz $13, $BB5_25 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_16: # %entry +; MIPS2-NEXT: beqz $12, $BB5_26 +; MIPS2-NEXT: addiu $4, $zero, 0 +; MIPS2-NEXT: $BB5_17: # %entry +; MIPS2-NEXT: beqz $15, $BB5_27 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_18: # %entry +; MIPS2-NEXT: bnez $24, $BB5_28 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_19: # %entry +; MIPS2-NEXT: bnez $25, $BB5_21 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_20: # %entry +; MIPS2-NEXT: move $6, $8 +; MIPS2-NEXT: $BB5_21: # %entry +; MIPS2-NEXT: move $4, $6 +; MIPS2-NEXT: move $5, $7 +; MIPS2-NEXT: lw $16, 0($sp) # 4-byte Folded Reload +; MIPS2-NEXT: lw $17, 4($sp) # 4-byte Folded Reload +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: addiu $sp, $sp, 8 +; MIPS2-NEXT: $BB5_22: # %entry +; MIPS2-NEXT: move $7, $gp +; MIPS2-NEXT: bnez $17, $BB5_14 +; MIPS2-NEXT: addiu $2, $zero, 0 +; MIPS2-NEXT: $BB5_23: # %entry +; MIPS2-NEXT: move $2, $3 +; MIPS2-NEXT: bnez $17, $BB5_15 +; MIPS2-NEXT: addiu $3, $zero, 0 +; MIPS2-NEXT: $BB5_24: # %entry +; MIPS2-NEXT: bnez $13, $BB5_16 +; MIPS2-NEXT: move $3, $16 +; MIPS2-NEXT: $BB5_25: # %entry +; MIPS2-NEXT: not $1, $10 +; MIPS2-NEXT: srl $5, $5, 1 +; MIPS2-NEXT: sllv $4, $4, $10 +; MIPS2-NEXT: srlv $1, $5, $1 +; MIPS2-NEXT: or $9, $4, $1 +; MIPS2-NEXT: bnez $12, $BB5_17 +; MIPS2-NEXT: addiu $4, $zero, 0 +; MIPS2-NEXT: $BB5_26: # %entry +; MIPS2-NEXT: bnez $15, $BB5_18 +; MIPS2-NEXT: move $4, $11 +; MIPS2-NEXT: $BB5_27: # %entry +; MIPS2-NEXT: beqz $24, $BB5_19 +; MIPS2-NEXT: move $8, $14 +; MIPS2-NEXT: $BB5_28: +; MIPS2-NEXT: bnez $25, $BB5_21 +; MIPS2-NEXT: or $8, $4, $9 +; MIPS2-NEXT: # %bb.29: +; MIPS2-NEXT: b $BB5_20 +; MIPS2-NEXT: nop +; +; MIPS32-LABEL: lshr_i128: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lw $9, 28($sp) +; MIPS32-NEXT: addiu $1, $zero, 64 +; MIPS32-NEXT: subu $2, $1, $9 +; MIPS32-NEXT: sllv $10, $5, $2 +; MIPS32-NEXT: andi $11, $2, 32 +; MIPS32-NEXT: move $1, $10 +; MIPS32-NEXT: movn $1, $zero, $11 +; MIPS32-NEXT: srlv $3, $7, $9 +; MIPS32-NEXT: not $12, $9 +; MIPS32-NEXT: sll $8, $6, 1 +; MIPS32-NEXT: sllv $8, $8, $12 +; MIPS32-NEXT: or $3, $8, $3 +; MIPS32-NEXT: srlv $13, $6, $9 +; MIPS32-NEXT: andi $14, $9, 32 +; MIPS32-NEXT: movn $3, $13, $14 +; MIPS32-NEXT: addiu $15, $9, -64 +; MIPS32-NEXT: or $3, $3, $1 +; MIPS32-NEXT: srlv $1, $5, $15 +; MIPS32-NEXT: sll $24, $4, 1 +; MIPS32-NEXT: not $8, $15 +; MIPS32-NEXT: sllv $8, $24, $8 +; MIPS32-NEXT: or $1, $8, $1 +; MIPS32-NEXT: srlv $8, $4, $15 +; MIPS32-NEXT: andi $15, $15, 32 +; MIPS32-NEXT: movn $1, $8, $15 +; MIPS32-NEXT: sltiu $25, $9, 64 +; MIPS32-NEXT: movn $1, $3, $25 +; MIPS32-NEXT: sllv $3, $4, $2 +; MIPS32-NEXT: not $2, $2 +; MIPS32-NEXT: srl $gp, $5, 1 +; MIPS32-NEXT: srlv $2, $gp, $2 +; MIPS32-NEXT: or $gp, $3, $2 +; MIPS32-NEXT: srlv $2, $5, $9 +; MIPS32-NEXT: sllv $3, $24, $12 +; MIPS32-NEXT: or $3, $3, $2 +; MIPS32-NEXT: srlv $2, $4, $9 +; MIPS32-NEXT: movn $3, $2, $14 +; MIPS32-NEXT: movz $1, $7, $9 +; MIPS32-NEXT: movz $3, $zero, $25 +; MIPS32-NEXT: movn $gp, $10, $11 +; MIPS32-NEXT: movn $13, $zero, $14 +; MIPS32-NEXT: or $4, $13, $gp +; MIPS32-NEXT: movn $8, $zero, $15 +; MIPS32-NEXT: movn $8, $4, $25 +; MIPS32-NEXT: movz $8, $6, $9 +; MIPS32-NEXT: movn $2, $zero, $14 +; MIPS32-NEXT: movz $2, $zero, $25 +; MIPS32-NEXT: move $4, $8 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: move $5, $1 +; +; MIPS32R2-LABEL: lshr_i128: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: lw $9, 28($sp) +; MIPS32R2-NEXT: addiu $1, $zero, 64 +; MIPS32R2-NEXT: subu $2, $1, $9 +; MIPS32R2-NEXT: sllv $10, $5, $2 +; MIPS32R2-NEXT: andi $11, $2, 32 +; MIPS32R2-NEXT: move $1, $10 +; MIPS32R2-NEXT: movn $1, $zero, $11 +; MIPS32R2-NEXT: srlv $3, $7, $9 +; MIPS32R2-NEXT: not $12, $9 +; MIPS32R2-NEXT: sll $8, $6, 1 +; MIPS32R2-NEXT: sllv $8, $8, $12 +; MIPS32R2-NEXT: or $3, $8, $3 +; MIPS32R2-NEXT: srlv $13, $6, $9 +; MIPS32R2-NEXT: andi $14, $9, 32 +; MIPS32R2-NEXT: movn $3, $13, $14 +; MIPS32R2-NEXT: addiu $15, $9, -64 +; MIPS32R2-NEXT: or $3, $3, $1 +; MIPS32R2-NEXT: srlv $1, $5, $15 +; MIPS32R2-NEXT: sll $24, $4, 1 +; MIPS32R2-NEXT: not $8, $15 +; MIPS32R2-NEXT: sllv $8, $24, $8 +; MIPS32R2-NEXT: or $1, $8, $1 +; MIPS32R2-NEXT: srlv $8, $4, $15 +; MIPS32R2-NEXT: andi $15, $15, 32 +; MIPS32R2-NEXT: movn $1, $8, $15 +; MIPS32R2-NEXT: sltiu $25, $9, 64 +; MIPS32R2-NEXT: movn $1, $3, $25 +; MIPS32R2-NEXT: sllv $3, $4, $2 +; MIPS32R2-NEXT: not $2, $2 +; MIPS32R2-NEXT: srl $gp, $5, 1 +; MIPS32R2-NEXT: srlv $2, $gp, $2 +; MIPS32R2-NEXT: or $gp, $3, $2 +; MIPS32R2-NEXT: srlv $2, $5, $9 +; MIPS32R2-NEXT: sllv $3, $24, $12 +; MIPS32R2-NEXT: or $3, $3, $2 +; MIPS32R2-NEXT: srlv $2, $4, $9 +; MIPS32R2-NEXT: movn $3, $2, $14 +; MIPS32R2-NEXT: movz $1, $7, $9 +; MIPS32R2-NEXT: movz $3, $zero, $25 +; MIPS32R2-NEXT: movn $gp, $10, $11 +; MIPS32R2-NEXT: movn $13, $zero, $14 +; MIPS32R2-NEXT: or $4, $13, $gp +; MIPS32R2-NEXT: movn $8, $zero, $15 +; MIPS32R2-NEXT: movn $8, $4, $25 +; MIPS32R2-NEXT: movz $8, $6, $9 +; MIPS32R2-NEXT: movn $2, $zero, $14 +; MIPS32R2-NEXT: movz $2, $zero, $25 +; MIPS32R2-NEXT: move $4, $8 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $5, $1 +; +; MIPS32R6-LABEL: lshr_i128: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: addiu $sp, $sp, -8 +; MIPS32R6-NEXT: .cfi_def_cfa_offset 8 +; MIPS32R6-NEXT: sw $16, 4($sp) # 4-byte Folded Spill +; MIPS32R6-NEXT: .cfi_offset 16, -4 +; MIPS32R6-NEXT: lw $1, 36($sp) +; MIPS32R6-NEXT: srlv $2, $7, $1 +; MIPS32R6-NEXT: not $3, $1 +; MIPS32R6-NEXT: sll $8, $6, 1 +; MIPS32R6-NEXT: sllv $8, $8, $3 +; MIPS32R6-NEXT: or $2, $8, $2 +; MIPS32R6-NEXT: addiu $8, $1, -64 +; MIPS32R6-NEXT: srlv $9, $5, $8 +; MIPS32R6-NEXT: sll $10, $4, 1 +; MIPS32R6-NEXT: not $11, $8 +; MIPS32R6-NEXT: sllv $11, $10, $11 +; MIPS32R6-NEXT: andi $12, $1, 32 +; MIPS32R6-NEXT: seleqz $2, $2, $12 +; MIPS32R6-NEXT: or $9, $11, $9 +; MIPS32R6-NEXT: srlv $11, $6, $1 +; MIPS32R6-NEXT: selnez $13, $11, $12 +; MIPS32R6-NEXT: addiu $14, $zero, 64 +; MIPS32R6-NEXT: subu $14, $14, $1 +; MIPS32R6-NEXT: sllv $15, $5, $14 +; MIPS32R6-NEXT: andi $24, $14, 32 +; MIPS32R6-NEXT: andi $25, $8, 32 +; MIPS32R6-NEXT: seleqz $9, $9, $25 +; MIPS32R6-NEXT: seleqz $gp, $15, $24 +; MIPS32R6-NEXT: or $2, $13, $2 +; MIPS32R6-NEXT: selnez $13, $15, $24 +; MIPS32R6-NEXT: sllv $15, $4, $14 +; MIPS32R6-NEXT: not $14, $14 +; MIPS32R6-NEXT: srl $16, $5, 1 +; MIPS32R6-NEXT: srlv $14, $16, $14 +; MIPS32R6-NEXT: or $14, $15, $14 +; MIPS32R6-NEXT: seleqz $14, $14, $24 +; MIPS32R6-NEXT: srlv $8, $4, $8 +; MIPS32R6-NEXT: or $13, $13, $14 +; MIPS32R6-NEXT: or $2, $2, $gp +; MIPS32R6-NEXT: srlv $5, $5, $1 +; MIPS32R6-NEXT: selnez $14, $8, $25 +; MIPS32R6-NEXT: sltiu $15, $1, 64 +; MIPS32R6-NEXT: selnez $2, $2, $15 +; MIPS32R6-NEXT: or $9, $14, $9 +; MIPS32R6-NEXT: sllv $3, $10, $3 +; MIPS32R6-NEXT: seleqz $10, $11, $12 +; MIPS32R6-NEXT: or $10, $10, $13 +; MIPS32R6-NEXT: or $3, $3, $5 +; MIPS32R6-NEXT: seleqz $5, $9, $15 +; MIPS32R6-NEXT: seleqz $9, $zero, $15 +; MIPS32R6-NEXT: srlv $4, $4, $1 +; MIPS32R6-NEXT: seleqz $11, $4, $12 +; MIPS32R6-NEXT: selnez $11, $11, $15 +; MIPS32R6-NEXT: seleqz $7, $7, $1 +; MIPS32R6-NEXT: or $2, $2, $5 +; MIPS32R6-NEXT: selnez $2, $2, $1 +; MIPS32R6-NEXT: or $5, $7, $2 +; MIPS32R6-NEXT: or $2, $9, $11 +; MIPS32R6-NEXT: seleqz $3, $3, $12 +; MIPS32R6-NEXT: selnez $7, $4, $12 +; MIPS32R6-NEXT: seleqz $4, $6, $1 +; MIPS32R6-NEXT: selnez $6, $10, $15 +; MIPS32R6-NEXT: seleqz $8, $8, $25 +; MIPS32R6-NEXT: seleqz $8, $8, $15 +; MIPS32R6-NEXT: or $6, $6, $8 +; MIPS32R6-NEXT: selnez $1, $6, $1 +; MIPS32R6-NEXT: or $4, $4, $1 +; MIPS32R6-NEXT: or $1, $7, $3 +; MIPS32R6-NEXT: selnez $1, $1, $15 +; MIPS32R6-NEXT: or $3, $9, $1 +; MIPS32R6-NEXT: lw $16, 4($sp) # 4-byte Folded Reload +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: addiu $sp, $sp, 8 +; +; MIPS3-LABEL: lshr_i128: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: sll $2, $7, 0 +; MIPS3-NEXT: dsrlv $6, $4, $7 +; MIPS3-NEXT: andi $8, $2, 64 +; MIPS3-NEXT: beqz $8, .LBB5_3 +; MIPS3-NEXT: move $3, $6 +; MIPS3-NEXT: # %bb.1: # %entry +; MIPS3-NEXT: beqz $8, .LBB5_4 +; MIPS3-NEXT: daddiu $2, $zero, 0 +; MIPS3-NEXT: .LBB5_2: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: nop +; MIPS3-NEXT: .LBB5_3: # %entry +; MIPS3-NEXT: dsrlv $1, $5, $7 +; MIPS3-NEXT: dsll $3, $4, 1 +; MIPS3-NEXT: not $2, $2 +; MIPS3-NEXT: dsllv $2, $3, $2 +; MIPS3-NEXT: or $3, $2, $1 +; MIPS3-NEXT: bnez $8, .LBB5_2 +; MIPS3-NEXT: daddiu $2, $zero, 0 +; MIPS3-NEXT: .LBB5_4: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: move $2, $6 +; +; MIPS4-LABEL: lshr_i128: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: dsrlv $1, $5, $7 +; MIPS4-NEXT: dsll $2, $4, 1 +; MIPS4-NEXT: sll $5, $7, 0 +; MIPS4-NEXT: not $3, $5 +; MIPS4-NEXT: dsllv $2, $2, $3 +; MIPS4-NEXT: or $3, $2, $1 +; MIPS4-NEXT: dsrlv $2, $4, $7 +; MIPS4-NEXT: andi $1, $5, 64 +; MIPS4-NEXT: movn $3, $2, $1 +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: movn $2, $zero, $1 +; +; MIPS64-LABEL: lshr_i128: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: dsrlv $1, $5, $7 +; MIPS64-NEXT: dsll $2, $4, 1 +; MIPS64-NEXT: sll $5, $7, 0 +; MIPS64-NEXT: not $3, $5 +; MIPS64-NEXT: dsllv $2, $2, $3 +; MIPS64-NEXT: or $3, $2, $1 +; MIPS64-NEXT: dsrlv $2, $4, $7 +; MIPS64-NEXT: andi $1, $5, 64 +; MIPS64-NEXT: movn $3, $2, $1 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: movn $2, $zero, $1 +; +; MIPS64R2-LABEL: lshr_i128: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: dsrlv $1, $5, $7 +; MIPS64R2-NEXT: dsll $2, $4, 1 +; MIPS64R2-NEXT: sll $5, $7, 0 +; MIPS64R2-NEXT: not $3, $5 +; MIPS64R2-NEXT: dsllv $2, $2, $3 +; MIPS64R2-NEXT: or $3, $2, $1 +; MIPS64R2-NEXT: dsrlv $2, $4, $7 +; MIPS64R2-NEXT: andi $1, $5, 64 +; MIPS64R2-NEXT: movn $3, $2, $1 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movn $2, $zero, $1 +; +; MIPS64R6-LABEL: lshr_i128: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: dsrlv $1, $5, $7 +; MIPS64R6-NEXT: dsll $2, $4, 1 +; MIPS64R6-NEXT: sll $3, $7, 0 +; MIPS64R6-NEXT: not $5, $3 +; MIPS64R6-NEXT: dsllv $2, $2, $5 +; MIPS64R6-NEXT: or $1, $2, $1 +; MIPS64R6-NEXT: andi $2, $3, 64 +; MIPS64R6-NEXT: sll $2, $2, 0 +; MIPS64R6-NEXT: seleqz $1, $1, $2 +; MIPS64R6-NEXT: dsrlv $4, $4, $7 +; MIPS64R6-NEXT: selnez $3, $4, $2 +; MIPS64R6-NEXT: or $3, $3, $1 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: seleqz $2, $4, $2 +; +; MMR3-LABEL: lshr_i128: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: addiusp -48 +; MMR3-NEXT: .cfi_def_cfa_offset 48 +; MMR3-NEXT: sw $17, 44($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $16, 40($sp) # 4-byte Folded Spill +; MMR3-NEXT: .cfi_offset 17, -4 +; MMR3-NEXT: .cfi_offset 16, -8 +; MMR3-NEXT: move $8, $7 +; MMR3-NEXT: sw $6, 32($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $5, 36($sp) # 4-byte Folded Spill +; MMR3-NEXT: move $17, $5 +; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill +; MMR3-NEXT: lw $16, 76($sp) +; MMR3-NEXT: srlv $7, $8, $16 +; MMR3-NEXT: not16 $3, $16 +; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill +; MMR3-NEXT: sll16 $2, $6, 1 +; MMR3-NEXT: sllv $3, $2, $3 +; MMR3-NEXT: li16 $4, 64 +; MMR3-NEXT: or16 $3, $7 +; MMR3-NEXT: srlv $5, $6, $16 +; MMR3-NEXT: sw $5, 12($sp) # 4-byte Folded Spill +; MMR3-NEXT: subu16 $7, $4, $16 +; MMR3-NEXT: sllv $9, $17, $7 +; MMR3-NEXT: andi16 $2, $7, 32 +; MMR3-NEXT: sw $2, 28($sp) # 4-byte Folded Spill +; MMR3-NEXT: andi16 $17, $16, 32 +; MMR3-NEXT: sw $17, 16($sp) # 4-byte Folded Spill +; MMR3-NEXT: move $4, $9 +; MMR3-NEXT: li16 $6, 0 +; MMR3-NEXT: movn $4, $6, $2 +; MMR3-NEXT: movn $3, $5, $17 +; MMR3-NEXT: addiu $2, $16, -64 +; MMR3-NEXT: lw $5, 36($sp) # 4-byte Folded Reload +; MMR3-NEXT: srlv $5, $5, $2 +; MMR3-NEXT: sw $5, 20($sp) # 4-byte Folded Spill +; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload +; MMR3-NEXT: sll16 $6, $17, 1 +; MMR3-NEXT: sw $6, 4($sp) # 4-byte Folded Spill +; MMR3-NEXT: not16 $5, $2 +; MMR3-NEXT: sllv $5, $6, $5 +; MMR3-NEXT: or16 $3, $4 +; MMR3-NEXT: lw $4, 20($sp) # 4-byte Folded Reload +; MMR3-NEXT: or16 $5, $4 +; MMR3-NEXT: srlv $1, $17, $2 +; MMR3-NEXT: andi16 $2, $2, 32 +; MMR3-NEXT: sw $2, 20($sp) # 4-byte Folded Spill +; MMR3-NEXT: movn $5, $1, $2 +; MMR3-NEXT: sllv $2, $17, $7 +; MMR3-NEXT: not16 $4, $7 +; MMR3-NEXT: lw $7, 36($sp) # 4-byte Folded Reload +; MMR3-NEXT: srl16 $6, $7, 1 +; MMR3-NEXT: srlv $4, $6, $4 +; MMR3-NEXT: sltiu $11, $16, 64 +; MMR3-NEXT: movn $5, $3, $11 +; MMR3-NEXT: or16 $4, $2 +; MMR3-NEXT: srlv $2, $7, $16 +; MMR3-NEXT: lw $3, 24($sp) # 4-byte Folded Reload +; MMR3-NEXT: lw $6, 4($sp) # 4-byte Folded Reload +; MMR3-NEXT: sllv $3, $6, $3 +; MMR3-NEXT: or16 $3, $2 +; MMR3-NEXT: srlv $2, $17, $16 +; MMR3-NEXT: lw $6, 16($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $3, $2, $6 +; MMR3-NEXT: sltiu $10, $16, 64 +; MMR3-NEXT: movz $5, $8, $16 +; MMR3-NEXT: li16 $7, 0 +; MMR3-NEXT: movz $3, $7, $10 +; MMR3-NEXT: lw $17, 28($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $4, $9, $17 +; MMR3-NEXT: lw $7, 12($sp) # 4-byte Folded Reload +; MMR3-NEXT: li16 $17, 0 +; MMR3-NEXT: movn $7, $17, $6 +; MMR3-NEXT: or16 $7, $4 +; MMR3-NEXT: lw $4, 20($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $1, $17, $4 +; MMR3-NEXT: li16 $17, 0 +; MMR3-NEXT: movn $1, $7, $11 +; MMR3-NEXT: lw $4, 32($sp) # 4-byte Folded Reload +; MMR3-NEXT: movz $1, $4, $16 +; MMR3-NEXT: movn $2, $17, $6 +; MMR3-NEXT: li16 $4, 0 +; MMR3-NEXT: movz $2, $4, $10 +; MMR3-NEXT: move $4, $1 +; MMR3-NEXT: lw $16, 40($sp) # 4-byte Folded Reload +; MMR3-NEXT: lw $17, 44($sp) # 4-byte Folded Reload +; MMR3-NEXT: addiusp 48 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: lshr_i128: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: addiu $sp, $sp, -48 +; MMR6-NEXT: .cfi_def_cfa_offset 48 +; MMR6-NEXT: sw $17, 44($sp) # 4-byte Folded Spill +; MMR6-NEXT: sw $16, 40($sp) # 4-byte Folded Spill +; MMR6-NEXT: .cfi_offset 17, -4 +; MMR6-NEXT: .cfi_offset 16, -8 +; MMR6-NEXT: move $1, $7 +; MMR6-NEXT: sw $5, 8($sp) # 4-byte Folded Spill +; MMR6-NEXT: move $16, $4 +; MMR6-NEXT: sw $16, 32($sp) # 4-byte Folded Spill +; MMR6-NEXT: lw $3, 76($sp) +; MMR6-NEXT: srlv $2, $1, $3 +; MMR6-NEXT: not16 $5, $3 +; MMR6-NEXT: sw $5, 24($sp) # 4-byte Folded Spill +; MMR6-NEXT: move $4, $6 +; MMR6-NEXT: sw $4, 28($sp) # 4-byte Folded Spill +; MMR6-NEXT: sll16 $6, $4, 1 +; MMR6-NEXT: sllv $17, $6, $5 +; MMR6-NEXT: or16 $17, $2 +; MMR6-NEXT: addiu $7, $3, -64 +; MMR6-NEXT: sw $7, 36($sp) # 4-byte Folded Spill +; MMR6-NEXT: lw $5, 8($sp) # 4-byte Folded Reload +; MMR6-NEXT: srlv $6, $5, $7 +; MMR6-NEXT: sll16 $2, $16, 1 +; MMR6-NEXT: sw $2, 20($sp) # 4-byte Folded Spill +; MMR6-NEXT: not16 $16, $7 +; MMR6-NEXT: sllv $7, $2, $16 +; MMR6-NEXT: andi16 $16, $3, 32 +; MMR6-NEXT: seleqz $8, $17, $16 +; MMR6-NEXT: or16 $7, $6 +; MMR6-NEXT: srlv $10, $4, $3 +; MMR6-NEXT: selnez $9, $10, $16 +; MMR6-NEXT: li16 $17, 64 +; MMR6-NEXT: subu16 $6, $17, $3 +; MMR6-NEXT: sllv $11, $5, $6 +; MMR6-NEXT: move $17, $5 +; MMR6-NEXT: andi16 $4, $6, 32 +; MMR6-NEXT: lw $2, 36($sp) # 4-byte Folded Reload +; MMR6-NEXT: andi16 $2, $2, 32 +; MMR6-NEXT: sw $2, 16($sp) # 4-byte Folded Spill +; MMR6-NEXT: seleqz $12, $7, $2 +; MMR6-NEXT: seleqz $2, $11, $4 +; MMR6-NEXT: sw $2, 12($sp) # 4-byte Folded Spill +; MMR6-NEXT: or $5, $9, $8 +; MMR6-NEXT: selnez $8, $11, $4 +; MMR6-NEXT: lw $2, 32($sp) # 4-byte Folded Reload +; MMR6-NEXT: sllv $7, $2, $6 +; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill +; MMR6-NEXT: not16 $6, $6 +; MMR6-NEXT: move $7, $17 +; MMR6-NEXT: srl16 $17, $7, 1 +; MMR6-NEXT: srlv $6, $17, $6 +; MMR6-NEXT: lw $17, 4($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $6, $17 +; MMR6-NEXT: seleqz $4, $6, $4 +; MMR6-NEXT: lw $6, 36($sp) # 4-byte Folded Reload +; MMR6-NEXT: srlv $9, $2, $6 +; MMR6-NEXT: or $4, $8, $4 +; MMR6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $5, $2 +; MMR6-NEXT: srlv $2, $7, $3 +; MMR6-NEXT: lw $17, 16($sp) # 4-byte Folded Reload +; MMR6-NEXT: selnez $6, $9, $17 +; MMR6-NEXT: sltiu $8, $3, 64 +; MMR6-NEXT: selnez $13, $5, $8 +; MMR6-NEXT: or $11, $6, $12 +; MMR6-NEXT: lw $5, 24($sp) # 4-byte Folded Reload +; MMR6-NEXT: lw $6, 20($sp) # 4-byte Folded Reload +; MMR6-NEXT: sllv $7, $6, $5 +; MMR6-NEXT: seleqz $6, $10, $16 +; MMR6-NEXT: li16 $5, 0 +; MMR6-NEXT: or16 $6, $4 +; MMR6-NEXT: or16 $7, $2 +; MMR6-NEXT: seleqz $4, $11, $8 +; MMR6-NEXT: seleqz $10, $5, $8 +; MMR6-NEXT: lw $2, 32($sp) # 4-byte Folded Reload +; MMR6-NEXT: srlv $11, $2, $3 +; MMR6-NEXT: seleqz $5, $11, $16 +; MMR6-NEXT: selnez $12, $5, $8 +; MMR6-NEXT: seleqz $1, $1, $3 +; MMR6-NEXT: or $2, $13, $4 +; MMR6-NEXT: selnez $2, $2, $3 +; MMR6-NEXT: or $5, $1, $2 +; MMR6-NEXT: or $2, $10, $12 +; MMR6-NEXT: seleqz $1, $7, $16 +; MMR6-NEXT: selnez $7, $11, $16 +; MMR6-NEXT: lw $4, 28($sp) # 4-byte Folded Reload +; MMR6-NEXT: seleqz $4, $4, $3 +; MMR6-NEXT: selnez $6, $6, $8 +; MMR6-NEXT: seleqz $9, $9, $17 +; MMR6-NEXT: seleqz $9, $9, $8 +; MMR6-NEXT: or $6, $6, $9 +; MMR6-NEXT: selnez $3, $6, $3 +; MMR6-NEXT: or $4, $4, $3 +; MMR6-NEXT: or $1, $7, $1 +; MMR6-NEXT: selnez $1, $1, $8 +; MMR6-NEXT: or $3, $10, $1 +; MMR6-NEXT: lw $16, 40($sp) # 4-byte Folded Reload +; MMR6-NEXT: lw $17, 44($sp) # 4-byte Folded Reload +; MMR6-NEXT: addiu $sp, $sp, 48 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: lshr_i128: - - ; o32 shouldn't use TImode helpers. - ; GP32-NOT: lw $25, %call16(__lshrti3)($gp) - ; MM-NOT: lw $25, %call16(__lshrti3)($2) - - ; M3: sll $[[T0:[0-9]+]], $7, 0 - ; M3: dsrlv $[[T1:[0-9]+]], $4, $7 - ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 - ; M3: beqz $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]] - ; M3: move $3, $[[T1]] - ; M3: beqz $[[T3]], [[BB1:\.LBB[0-9_]+]] - ; M3: daddiu $2, $zero, 0 - ; M3: [[EXIT:\.LBB[0-9_]+]]: - ; M3: jr $ra - ; M3: nop - ; M3: [[BB0]]: - ; M3: dsrlv $[[T4:[0-9]+]], $5, $7 - ; M3: dsll $[[T5:[0-9]+]], $4, 1 - ; M3: not $[[T6:[0-9]+]], $[[T0]] - ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] - ; M3: or $3, $[[T7]], $[[T4]] - ; M3: bnez $[[T3]], [[EXIT]] - ; M3: daddiu $2, $zero, 0 - ; M3: [[BB1]]: - ; M3: jr $ra - ; M3: move $2, $[[T1]] - - ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7 - ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1 - ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 - ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] - ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] - ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]] - ; GP64-NOT-R6: dsrlv $2, $4, $7 - ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64 - ; GP64-NOT-R6: movn $3, $2, $[[T5]] - ; GP64-NOT-R6: jr $ra - ; GP64-NOT-R6: movn $2, $zero, $1 - ; 64R6: dsrlv $[[T0:[0-9]+]], $5, $7 - ; 64R6: dsll $[[T1:[0-9]+]], $4, 1 - ; 64R6: sll $[[T2:[0-9]+]], $7, 0 - ; 64R6: not $[[T3:[0-9]+]], $[[T2]] - ; 64R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] - ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T0]] - ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64 - ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 - ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] - ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $7 - ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] - ; 64R6: or $3, $[[T10]], $[[T8]] - ; 64R6: jr $ra - ; 64R6: seleqz $2, $[[T9]], $[[T7]] +; o32 shouldn't use TImode helpers. +; GP32-NOT: lw $25, %call16(__lshrti3)($gp) +; MM-NOT: lw $25, %call16(__lshrti3)($2) %r = lshr i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/mul.ll b/test/CodeGen/Mips/llvm-ir/mul.ll index 1562372ce9a09..5e85ecf2a9379 100644 --- a/test/CodeGen/Mips/llvm-ir/mul.ll +++ b/test/CodeGen/Mips/llvm-ir/mul.ll @@ -26,8 +26,6 @@ ; RUN: FileCheck %s -check-prefixes=MM32,MM32R3 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=MM32,MM32R6 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | \ -; RUN: FileCheck %s -check-prefix=MM64R6 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) { entry: @@ -59,11 +57,6 @@ entry: ; 64R6: andi $[[T0]], $[[T0]], 1 ; 64R6: negu $2, $[[T0]] - ; MM64R6: mul $[[T0:[0-9]+]], $4, $5 - ; MM64R6: andi16 $[[T0]], $[[T0]], 1 - ; MM64R6: li16 $[[T1:[0-9]+]], 0 - ; MM64R6: subu16 $2, $[[T1]], $[[T0]] - ; MM32: mul $[[T0:[0-9]+]], $4, $5 ; MM32: andi16 $[[T0]], $[[T0]], 1 ; MM32: li16 $[[T1:[0-9]+]], 0 @@ -107,9 +100,6 @@ entry: ; 64R6: mul $[[T0:[0-9]+]], $4, $5 ; 64R6: seb $2, $[[T0]] - ; MM64R6: mul $[[T0:[0-9]+]], $4, $5 - ; MM64R6: seb $2, $[[T0]] - ; MM32: mul $[[T0:[0-9]+]], $4, $5 ; MM32: seb $2, $[[T0]] @@ -151,9 +141,6 @@ entry: ; 64R6: mul $[[T0:[0-9]+]], $4, $5 ; 64R6: seh $2, $[[T0]] - ; MM64R6: mul $[[T0:[0-9]+]], $4, $5 - ; MM64R6: seh $2, $[[T0]] - ; MM32: mul $[[T0:[0-9]+]], $4, $5 ; MM32: seh $2, $[[T0]] @@ -173,7 +160,6 @@ entry: ; 64R1-R5: mul $2, $4, $5 ; 64R6: mul $2, $4, $5 - ; MM64R6: mul $2, $4, $5 ; MM32: mul $2, $4, $5 @@ -217,7 +203,6 @@ entry: ; 64R1-R5: mflo $2 ; 64R6: dmul $2, $4, $5 - ; MM64R6: dmul $2, $4, $5 ; MM32R3: multu $[[T0:[0-9]+]], $7 ; MM32R3: mflo $[[T1:[0-9]+]] @@ -261,13 +246,6 @@ entry: ; 64R6: daddu $2, $[[T1]], $[[T0]] ; 64R6-DAG: dmul $3, $5, $7 - ; MM64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6 - ; MM64R6: dmuhu $[[T2:[0-9]+]], $5, $7 - ; MM64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; MM64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7 - ; MM64R6: daddu $2, $[[T1]], $[[T0]] - ; MM64R6-DAG: dmul $3, $5, $7 - ; MM32: lw $25, %call16(__multi3)($16) %r = mul i128 %a, %b diff --git a/test/CodeGen/Mips/llvm-ir/not.ll b/test/CodeGen/Mips/llvm-ir/not.ll index 914b6164ad00a..6a27612c0e2b6 100644 --- a/test/CodeGen/Mips/llvm-ir/not.ll +++ b/test/CodeGen/Mips/llvm-ir/not.ll @@ -26,8 +26,6 @@ ; RUN: -check-prefixes=ALL,MM,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM64 define signext i1 @not_i1(i1 signext %a) { entry: @@ -98,9 +96,6 @@ entry: ; MM32: not16 $2, $4 ; MM32: not16 $3, $5 - ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1 - ; MM64: xor $2, $4, $[[T0]] - %r = xor i64 %a, -1 ret i64 %r } @@ -123,10 +118,6 @@ entry: ; MM32: not16 $4, $6 ; MM32: not16 $5, $7 - ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1 - ; MM64: xor $2, $4, $[[T0]] - ; MM64: xor $3, $5, $[[T0]] - %r = xor i128 %a, -1 ret i128 %r } @@ -135,7 +126,9 @@ define signext i1 @nor_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: nor_i1: - ; ALL: nor $2, $5, $4 + ; GP32: nor $2, $5, $4 + ; GP64: or $1, $5, $4 + ; MM32: nor $2, $5, $4 %or = or i1 %b, %a %r = xor i1 %or, -1 @@ -146,7 +139,9 @@ define signext i8 @nor_i8(i8 signext %a, i8 signext %b) { entry: ; ALL-LABEL: nor_i8: - ; ALL: nor $2, $5, $4 + ; GP32: nor $2, $5, $4 + ; GP64: or $1, $5, $4 + ; MM32: nor $2, $5, $4 %or = or i8 %b, %a %r = xor i8 %or, -1 @@ -157,7 +152,9 @@ define signext i16 @nor_i16(i16 signext %a, i16 signext %b) { entry: ; ALL-LABEL: nor_i16: - ; ALL: nor $2, $5, $4 + ; GP32: nor $2, $5, $4 + ; GP64: or $1, $5, $4 + ; MM32: nor $2, $5, $4 %or = or i16 %b, %a %r = xor i16 %or, -1 @@ -176,10 +173,6 @@ entry: ; MM32: nor $2, $5, $4 - ; MM64: or $[[T0:[0-9]+]], $5, $4 - ; MM64: sll $[[T1:[0-9]+]], $[[T0]], 0 - ; MM64: not16 $2, $[[T1]] - %or = or i32 %b, %a %r = xor i32 %or, -1 ret i32 %r @@ -198,8 +191,6 @@ entry: ; MM32: nor $2, $6, $4 ; MM32: nor $3, $7, $5 - ; MM64: nor $2, $5, $4 - %or = or i64 %b, %a %r = xor i64 %or, -1 ret i64 %r @@ -230,9 +221,6 @@ entry: ; MM32: lw $[[T3:[0-9]+]], 28($sp) ; MM32: nor $5, $[[T3]], $7 - ; MM64: nor $2, $6, $4 - ; MM64: nor $3, $7, $5 - %or = or i128 %b, %a %r = xor i128 %or, -1 ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/or.ll b/test/CodeGen/Mips/llvm-ir/or.ll index c7f89ef5d2262..4eae6e49f8a9f 100644 --- a/test/CodeGen/Mips/llvm-ir/or.ll +++ b/test/CodeGen/Mips/llvm-ir/or.ll @@ -1,663 +1,1209 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM64 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=MM32 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=MM32R6 define signext i1 @or_i1(i1 signext %a, i1 signext %b) { +; GP32-LABEL: or_i1: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: or $2, $4, $5 +; +; GP64-LABEL: or_i1: +; GP64: # %bb.0: # %entry +; GP64-NEXT: or $1, $4, $5 +; GP64-NEXT: jr $ra +; GP64-NEXT: sll $2, $1, 0 +; +; MM32-LABEL: or_i1: +; MM32: # %bb.0: # %entry +; MM32-NEXT: or16 $4, $5 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i1: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: or16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i1: - - ; GP32: or $2, $4, $5 - - ; GP64: or $2, $4, $5 - - ; MM: or16 $[[T0:[0-9]+]], $5 - ; MM: move $2, $[[T0]] - %r = or i1 %a, %b ret i1 %r } define signext i8 @or_i8(i8 signext %a, i8 signext %b) { +; GP32-LABEL: or_i8: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: or $2, $4, $5 +; +; GP64-LABEL: or_i8: +; GP64: # %bb.0: # %entry +; GP64-NEXT: or $1, $4, $5 +; GP64-NEXT: jr $ra +; GP64-NEXT: sll $2, $1, 0 +; +; MM32-LABEL: or_i8: +; MM32: # %bb.0: # %entry +; MM32-NEXT: or16 $4, $5 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i8: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: or16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i8: - - ; GP32: or $2, $4, $5 - - ; GP64: or $2, $4, $5 - - ; MM: or16 $[[T0:[0-9]+]], $5 - ; MM: move $2, $[[T0]] - %r = or i8 %a, %b ret i8 %r } define signext i16 @or_i16(i16 signext %a, i16 signext %b) { +; GP32-LABEL: or_i16: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: or $2, $4, $5 +; +; GP64-LABEL: or_i16: +; GP64: # %bb.0: # %entry +; GP64-NEXT: or $1, $4, $5 +; GP64-NEXT: jr $ra +; GP64-NEXT: sll $2, $1, 0 +; +; MM32-LABEL: or_i16: +; MM32: # %bb.0: # %entry +; MM32-NEXT: or16 $4, $5 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i16: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: or16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i16: - - ; GP32: or $2, $4, $5 - - ; GP64: or $2, $4, $5 - - ; MM: or16 $[[T0:[0-9]+]], $5 - ; MM: move $2, $[[T0]] - %r = or i16 %a, %b ret i16 %r } define signext i32 @or_i32(i32 signext %a, i32 signext %b) { +; GP32-LABEL: or_i32: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: or $2, $4, $5 +; +; GP64-LABEL: or_i32: +; GP64: # %bb.0: # %entry +; GP64-NEXT: or $1, $4, $5 +; GP64-NEXT: jr $ra +; GP64-NEXT: sll $2, $1, 0 +; +; MM32-LABEL: or_i32: +; MM32: # %bb.0: # %entry +; MM32-NEXT: or16 $4, $5 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i32: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: or16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i32: - - ; GP32: or $2, $4, $5 - - ; GP64: or $[[T0:[0-9]+]], $4, $5 - ; FIXME: The sll instruction below is redundant. - ; GP64: sll $2, $[[T0]], 0 - - ; MM32: or16 $[[T0:[0-9]+]], $5 - ; MM32: move $2, $[[T0]] - - ; MM64: or $[[T0:[0-9]+]], $4, $5 - ; MM64: sll $2, $[[T0]], 0 - %r = or i32 %a, %b ret i32 %r } define signext i64 @or_i64(i64 signext %a, i64 signext %b) { +; GP32-LABEL: or_i64: +; GP32: # %bb.0: # %entry +; GP32-NEXT: or $2, $4, $6 +; GP32-NEXT: jr $ra +; GP32-NEXT: or $3, $5, $7 +; +; GP64-LABEL: or_i64: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: or $2, $4, $5 +; +; MM32-LABEL: or_i64: +; MM32: # %bb.0: # %entry +; MM32-NEXT: or16 $4, $6 +; MM32-NEXT: or16 $5, $7 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: move $3, $5 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i64: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: or16 $4, $6 +; MM32R6-NEXT: or16 $5, $7 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i64: - - ; GP32: or $2, $4, $6 - ; GP32: or $3, $5, $7 - - ; GP64: or $2, $4, $5 - - ; MM32: or16 $[[T0:[0-9]+]], $6 - ; MM32: or16 $[[T1:[0-9]+]], $7 - ; MM32: move $2, $[[T0]] - ; MM32: move $3, $[[T1]] - - ; MM64: or $2, $4, $5 - %r = or i64 %a, %b ret i64 %r } define signext i128 @or_i128(i128 signext %a, i128 signext %b) { +; GP32-LABEL: or_i128: +; GP32: # %bb.0: # %entry +; GP32-NEXT: lw $1, 20($sp) +; GP32-NEXT: lw $2, 16($sp) +; GP32-NEXT: or $2, $4, $2 +; GP32-NEXT: or $3, $5, $1 +; GP32-NEXT: lw $1, 24($sp) +; GP32-NEXT: or $4, $6, $1 +; GP32-NEXT: lw $1, 28($sp) +; GP32-NEXT: jr $ra +; GP32-NEXT: or $5, $7, $1 +; +; GP64-LABEL: or_i128: +; GP64: # %bb.0: # %entry +; GP64-NEXT: or $2, $4, $6 +; GP64-NEXT: jr $ra +; GP64-NEXT: or $3, $5, $7 +; +; MM32-LABEL: or_i128: +; MM32: # %bb.0: # %entry +; MM32-NEXT: lw $3, 20($sp) +; MM32-NEXT: lw $2, 16($sp) +; MM32-NEXT: or16 $2, $4 +; MM32-NEXT: or16 $3, $5 +; MM32-NEXT: lw $4, 24($sp) +; MM32-NEXT: or16 $4, $6 +; MM32-NEXT: lw $5, 28($sp) +; MM32-NEXT: or16 $5, $7 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i128: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: lw $3, 20($sp) +; MM32R6-NEXT: lw $2, 16($sp) +; MM32R6-NEXT: or16 $2, $4 +; MM32R6-NEXT: or16 $3, $5 +; MM32R6-NEXT: lw $4, 24($sp) +; MM32R6-NEXT: or16 $4, $6 +; MM32R6-NEXT: lw $5, 28($sp) +; MM32R6-NEXT: or16 $5, $7 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i128: - - ; GP32: lw $[[T1:[0-9]+]], 20($sp) - ; GP32: lw $[[T2:[0-9]+]], 16($sp) - ; GP32: or $2, $4, $[[T2]] - ; GP32: or $3, $5, $[[T1]] - ; GP32: lw $[[T0:[0-9]+]], 24($sp) - ; GP32: or $4, $6, $[[T0]] - ; GP32: lw $[[T3:[0-9]+]], 28($sp) - ; GP32: or $5, $7, $[[T3]] - - ; GP64: or $2, $4, $6 - ; GP64: or $3, $5, $7 - - ; MM32: lw $[[T1:[0-9]+]], 20($sp) - ; MM32: lw $[[T2:[0-9]+]], 16($sp) - ; MM32: or16 $[[T2]], $4 - ; MM32: or16 $[[T1]], $5 - ; MM32: lw $[[T0:[0-9]+]], 24($sp) - ; MM32: or16 $[[T0]], $6 - ; MM32: lw $[[T3:[0-9]+]], 28($sp) - ; MM32: or16 $[[T3]], $7 - - ; MM64: or $2, $4, $6 - ; MM64: or $3, $5, $7 - %r = or i128 %a, %b ret i128 %r } define signext i1 @or_i1_4(i1 signext %b) { +; GP32-LABEL: or_i1_4: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i1_4: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i1_4: +; MM32: # %bb.0: # %entry +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i1_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i1_4: - - ; ALL: move $2, $4 - %r = or i1 4, %b ret i1 %r } define signext i8 @or_i8_4(i8 signext %b) { +; GP32-LABEL: or_i8_4: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 4 +; +; GP64-LABEL: or_i8_4: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 4 +; +; MM32-LABEL: or_i8_4: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 4 +; +; MM32R6-LABEL: or_i8_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i8_4: - - ; ALL: ori $2, $4, 4 - %r = or i8 4, %b ret i8 %r } define signext i16 @or_i16_4(i16 signext %b) { +; GP32-LABEL: or_i16_4: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 4 +; +; GP64-LABEL: or_i16_4: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 4 +; +; MM32-LABEL: or_i16_4: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 4 +; +; MM32R6-LABEL: or_i16_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i16_4: - - ; ALL: ori $2, $4, 4 - %r = or i16 4, %b ret i16 %r } define signext i32 @or_i32_4(i32 signext %b) { +; GP32-LABEL: or_i32_4: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 4 +; +; GP64-LABEL: or_i32_4: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 4 +; +; MM32-LABEL: or_i32_4: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 4 +; +; MM32R6-LABEL: or_i32_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i32_4: - - ; ALL: ori $2, $4, 4 - %r = or i32 4, %b ret i32 %r } define signext i64 @or_i64_4(i64 signext %b) { +; GP32-LABEL: or_i64_4: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $3, $5, 4 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i64_4: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 4 +; +; MM32-LABEL: or_i64_4: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $3, $5, 4 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i64_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $3, $5, 4 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i64_4: - - ; GP32: ori $3, $5, 4 - ; GP32: move $2, $4 - - ; GP64: ori $2, $4, 4 - - ; MM32: ori $3, $5, 4 - ; MM32: move $2, $4 - - ; MM64: ori $2, $4, 4 - %r = or i64 4, %b ret i64 %r } define signext i128 @or_i128_4(i128 signext %b) { +; GP32-LABEL: or_i128_4: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $1, $7, 4 +; GP32-NEXT: move $2, $4 +; GP32-NEXT: move $3, $5 +; GP32-NEXT: move $4, $6 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $5, $1 +; +; GP64-LABEL: or_i128_4: +; GP64: # %bb.0: # %entry +; GP64-NEXT: ori $3, $5, 4 +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i128_4: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $1, $7, 4 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: move $3, $5 +; MM32-NEXT: move $4, $6 +; MM32-NEXT: move $5, $1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i128_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $1, $7, 4 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: move $4, $6 +; MM32R6-NEXT: move $5, $1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i128_4: - - ; GP32: ori $[[T0:[0-9]+]], $7, 4 - ; GP32: move $2, $4 - ; GP32: move $3, $5 - ; GP32: move $4, $6 - ; GP32: move $5, $[[T0]] - - ; GP64: ori $3, $5, 4 - ; GP64: move $2, $4 - - ; MM32: ori $[[T0:[0-9]+]], $7, 4 - ; MM32: move $2, $4 - ; MM32: move $3, $5 - ; MM32: move $4, $6 - ; MM32: move $5, $[[T0]] - - ; MM64: ori $3, $5, 4 - ; MM64: move $2, $4 - %r = or i128 4, %b ret i128 %r } define signext i1 @or_i1_31(i1 signext %b) { +; GP32-LABEL: or_i1_31: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: addiu $2, $zero, -1 +; +; GP64-LABEL: or_i1_31: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: addiu $2, $zero, -1 +; +; MM32-LABEL: or_i1_31: +; MM32: # %bb.0: # %entry +; MM32-NEXT: li16 $2, -1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i1_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, -1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i1_31: - - ; GP32: addiu $2, $zero, -1 - - ; GP64: addiu $2, $zero, -1 - - ; MM: li16 $2, -1 - %r = or i1 31, %b ret i1 %r } define signext i8 @or_i8_31(i8 signext %b) { +; GP32-LABEL: or_i8_31: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 31 +; +; GP64-LABEL: or_i8_31: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 31 +; +; MM32-LABEL: or_i8_31: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 31 +; +; MM32R6-LABEL: or_i8_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 31 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i8_31: - - ; ALL: ori $2, $4, 31 - %r = or i8 31, %b ret i8 %r } define signext i16 @or_i16_31(i16 signext %b) { +; GP32-LABEL: or_i16_31: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 31 +; +; GP64-LABEL: or_i16_31: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 31 +; +; MM32-LABEL: or_i16_31: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 31 +; +; MM32R6-LABEL: or_i16_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 31 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i16_31: - - ; ALL: ori $2, $4, 31 - %r = or i16 31, %b ret i16 %r } define signext i32 @or_i32_31(i32 signext %b) { +; GP32-LABEL: or_i32_31: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 31 +; +; GP64-LABEL: or_i32_31: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 31 +; +; MM32-LABEL: or_i32_31: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 31 +; +; MM32R6-LABEL: or_i32_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 31 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i32_31: - - ; ALL: ori $2, $4, 31 - %r = or i32 31, %b ret i32 %r } define signext i64 @or_i64_31(i64 signext %b) { +; GP32-LABEL: or_i64_31: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $3, $5, 31 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i64_31: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 31 +; +; MM32-LABEL: or_i64_31: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $3, $5, 31 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i64_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $3, $5, 31 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i64_31: - - ; GP32: ori $3, $5, 31 - ; GP32: move $2, $4 - - ; GP64: ori $2, $4, 31 - - ; MM32: ori $3, $5, 31 - ; MM32: move $2, $4 - - ; MM64: ori $2, $4, 31 - %r = or i64 31, %b ret i64 %r } define signext i128 @or_i128_31(i128 signext %b) { +; GP32-LABEL: or_i128_31: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $1, $7, 31 +; GP32-NEXT: move $2, $4 +; GP32-NEXT: move $3, $5 +; GP32-NEXT: move $4, $6 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $5, $1 +; +; GP64-LABEL: or_i128_31: +; GP64: # %bb.0: # %entry +; GP64-NEXT: ori $3, $5, 31 +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i128_31: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $1, $7, 31 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: move $3, $5 +; MM32-NEXT: move $4, $6 +; MM32-NEXT: move $5, $1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i128_31: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $1, $7, 31 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: move $4, $6 +; MM32R6-NEXT: move $5, $1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i128_31: - - ; GP32: ori $[[T0:[0-9]+]], $7, 31 - ; GP32: move $2, $4 - ; GP32: move $3, $5 - ; GP32: move $4, $6 - ; GP32: move $5, $[[T0]] - - ; GP64: ori $3, $5, 31 - ; GP64: move $2, $4 - - ; MM32: ori $[[T0:[0-9]+]], $7, 31 - ; MM32: move $2, $4 - ; MM32: move $3, $5 - ; MM32: move $4, $6 - ; MM32: move $5, $[[T0]] - - ; MM64: ori $3, $5, 31 - ; MM64: move $2, $4 - %r = or i128 31, %b ret i128 %r } define signext i1 @or_i1_255(i1 signext %b) { +; GP32-LABEL: or_i1_255: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: addiu $2, $zero, -1 +; +; GP64-LABEL: or_i1_255: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: addiu $2, $zero, -1 +; +; MM32-LABEL: or_i1_255: +; MM32: # %bb.0: # %entry +; MM32-NEXT: li16 $2, -1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i1_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, -1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i1_255: - - ; GP32: addiu $2, $zero, -1 - - ; GP64: addiu $2, $zero, -1 - - ; MM: li16 $2, -1 - %r = or i1 255, %b ret i1 %r } define signext i8 @or_i8_255(i8 signext %b) { +; GP32-LABEL: or_i8_255: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: addiu $2, $zero, -1 +; +; GP64-LABEL: or_i8_255: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: addiu $2, $zero, -1 +; +; MM32-LABEL: or_i8_255: +; MM32: # %bb.0: # %entry +; MM32-NEXT: li16 $2, -1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i8_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, -1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i8_255: - - ; GP32: addiu $2, $zero, -1 - - ; GP64: addiu $2, $zero, -1 - - ; MM: li16 $2, -1 - %r = or i8 255, %b ret i8 %r } define signext i16 @or_i16_255(i16 signext %b) { +; GP32-LABEL: or_i16_255: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 255 +; +; GP64-LABEL: or_i16_255: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 255 +; +; MM32-LABEL: or_i16_255: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 255 +; +; MM32R6-LABEL: or_i16_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 255 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i16_255: - - ; ALL: ori $2, $4, 255 - %r = or i16 255, %b ret i16 %r } define signext i32 @or_i32_255(i32 signext %b) { +; GP32-LABEL: or_i32_255: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 255 +; +; GP64-LABEL: or_i32_255: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 255 +; +; MM32-LABEL: or_i32_255: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 255 +; +; MM32R6-LABEL: or_i32_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 255 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i32_255: - - ; ALL: ori $2, $4, 255 - %r = or i32 255, %b ret i32 %r } define signext i64 @or_i64_255(i64 signext %b) { +; GP32-LABEL: or_i64_255: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $3, $5, 255 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i64_255: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 255 +; +; MM32-LABEL: or_i64_255: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $3, $5, 255 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i64_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $3, $5, 255 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i64_255: - - ; GP32: ori $3, $5, 255 - ; GP32: move $2, $4 - - ; GP64: ori $2, $4, 255 - - ; MM32: ori $3, $5, 255 - ; MM32: move $2, $4 - - ; MM64: ori $2, $4, 255 - %r = or i64 255, %b ret i64 %r } define signext i128 @or_i128_255(i128 signext %b) { +; GP32-LABEL: or_i128_255: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $1, $7, 255 +; GP32-NEXT: move $2, $4 +; GP32-NEXT: move $3, $5 +; GP32-NEXT: move $4, $6 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $5, $1 +; +; GP64-LABEL: or_i128_255: +; GP64: # %bb.0: # %entry +; GP64-NEXT: ori $3, $5, 255 +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i128_255: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $1, $7, 255 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: move $3, $5 +; MM32-NEXT: move $4, $6 +; MM32-NEXT: move $5, $1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i128_255: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $1, $7, 255 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: move $4, $6 +; MM32R6-NEXT: move $5, $1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i128_255: - - ; GP32: ori $[[T0:[0-9]+]], $7, 255 - ; GP32: move $2, $4 - ; GP32: move $3, $5 - ; GP32: move $4, $6 - ; GP32: move $5, $[[T0]] - - ; GP64: ori $3, $5, 255 - ; GP64: move $2, $4 - - ; MM32: ori $[[T0:[0-9]+]], $7, 255 - ; MM32: move $2, $4 - ; MM32: move $3, $5 - ; MM32: move $4, $6 - ; MM32: move $5, $[[T0]] - - ; MM64: ori $3, $5, 255 - ; MM64: move $2, $4 - %r = or i128 255, %b ret i128 %r } define signext i1 @or_i1_32768(i1 signext %b) { +; GP32-LABEL: or_i1_32768: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i1_32768: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i1_32768: +; MM32: # %bb.0: # %entry +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i1_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i1_32768: - - ; ALL: move $2, $4 - %r = or i1 32768, %b ret i1 %r } define signext i8 @or_i8_32768(i8 signext %b) { +; GP32-LABEL: or_i8_32768: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i8_32768: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i8_32768: +; MM32: # %bb.0: # %entry +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i8_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i8_32768: - - ; ALL: move $2, $4 - %r = or i8 32768, %b ret i8 %r } define signext i16 @or_i16_32768(i16 signext %b) { +; GP32-LABEL: or_i16_32768: +; GP32: # %bb.0: # %entry +; GP32-NEXT: addiu $1, $zero, -32768 +; GP32-NEXT: jr $ra +; GP32-NEXT: or $2, $4, $1 +; +; GP64-LABEL: or_i16_32768: +; GP64: # %bb.0: # %entry +; GP64-NEXT: addiu $1, $zero, -32768 +; GP64-NEXT: jr $ra +; GP64-NEXT: or $2, $4, $1 +; +; MM32-LABEL: or_i16_32768: +; MM32: # %bb.0: # %entry +; MM32-NEXT: addiu $2, $zero, -32768 +; MM32-NEXT: or16 $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i16_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: addiu $2, $zero, -32768 +; MM32R6-NEXT: or16 $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i16_32768: - - ; GP32: addiu $[[T0:[0-9]+]], $zero, -32768 - ; GP32: or $2, $4, $[[T0]] - - ; GP64: addiu $[[T0:[0-9]+]], $zero, -32768 - ; GP64: or $2, $4, $[[T0]] - - ; MM: addiu $2, $zero, -32768 - ; MM: or16 $2, $4 - %r = or i16 32768, %b ret i16 %r } define signext i32 @or_i32_32768(i32 signext %b) { +; GP32-LABEL: or_i32_32768: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 32768 +; +; GP64-LABEL: or_i32_32768: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 32768 +; +; MM32-LABEL: or_i32_32768: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 32768 +; +; MM32R6-LABEL: or_i32_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 32768 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i32_32768: - - ; ALL: ori $2, $4, 32768 - %r = or i32 32768, %b ret i32 %r } define signext i64 @or_i64_32768(i64 signext %b) { +; GP32-LABEL: or_i64_32768: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $3, $5, 32768 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i64_32768: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 32768 +; +; MM32-LABEL: or_i64_32768: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $3, $5, 32768 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i64_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $3, $5, 32768 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i64_32768: - - ; GP32: ori $3, $5, 32768 - ; GP32: move $2, $4 - - ; GP64: ori $2, $4, 32768 - - ; MM32: ori $3, $5, 32768 - ; MM32: move $2, $4 - - ; MM64: ori $2, $4, 32768 - %r = or i64 32768, %b ret i64 %r } define signext i128 @or_i128_32768(i128 signext %b) { +; GP32-LABEL: or_i128_32768: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $1, $7, 32768 +; GP32-NEXT: move $2, $4 +; GP32-NEXT: move $3, $5 +; GP32-NEXT: move $4, $6 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $5, $1 +; +; GP64-LABEL: or_i128_32768: +; GP64: # %bb.0: # %entry +; GP64-NEXT: ori $3, $5, 32768 +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i128_32768: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $1, $7, 32768 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: move $3, $5 +; MM32-NEXT: move $4, $6 +; MM32-NEXT: move $5, $1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i128_32768: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $1, $7, 32768 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: move $4, $6 +; MM32R6-NEXT: move $5, $1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i128_32768: - - ; GP32: ori $[[T0:[0-9]+]], $7, 32768 - ; GP32: move $2, $4 - ; GP32: move $3, $5 - ; GP32: move $4, $6 - ; GP32: move $5, $[[T0]] - - ; GP64: ori $3, $5, 32768 - ; GP64: move $2, $4 - - ; MM32: ori $[[T0:[0-9]+]], $7, 32768 - ; MM32: move $2, $4 - ; MM32: move $3, $5 - ; MM32: move $4, $6 - ; MM32: move $5, $[[T0]] - - ; MM64: ori $3, $5, 32768 - ; MM64: move $2, $4 - %r = or i128 32768, %b ret i128 %r } define signext i1 @or_i1_65(i1 signext %b) { +; GP32-LABEL: or_i1_65: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: addiu $2, $zero, -1 +; +; GP64-LABEL: or_i1_65: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: addiu $2, $zero, -1 +; +; MM32-LABEL: or_i1_65: +; MM32: # %bb.0: # %entry +; MM32-NEXT: li16 $2, -1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i1_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: li16 $2, -1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i1_65: - - ; GP32: addiu $2, $zero, -1 - - ; GP64: addiu $2, $zero, -1 - - ; MM: li16 $2, -1 - %r = or i1 65, %b ret i1 %r } define signext i8 @or_i8_65(i8 signext %b) { +; GP32-LABEL: or_i8_65: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 65 +; +; GP64-LABEL: or_i8_65: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 65 +; +; MM32-LABEL: or_i8_65: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 65 +; +; MM32R6-LABEL: or_i8_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 65 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i8_65: - - ; ALL: ori $2, $4, 65 - %r = or i8 65, %b ret i8 %r } define signext i16 @or_i16_65(i16 signext %b) { +; GP32-LABEL: or_i16_65: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 65 +; +; GP64-LABEL: or_i16_65: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 65 +; +; MM32-LABEL: or_i16_65: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 65 +; +; MM32R6-LABEL: or_i16_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 65 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i16_65: - - ; ALL: ori $2, $4, 65 - %r = or i16 65, %b ret i16 %r } define signext i32 @or_i32_65(i32 signext %b) { +; GP32-LABEL: or_i32_65: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 65 +; +; GP64-LABEL: or_i32_65: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 65 +; +; MM32-LABEL: or_i32_65: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 65 +; +; MM32R6-LABEL: or_i32_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 65 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i32_65: - - ; ALL: ori $2, $4, 65 - %r = or i32 65, %b ret i32 %r } define signext i64 @or_i64_65(i64 signext %b) { +; GP32-LABEL: or_i64_65: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $3, $5, 65 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i64_65: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 65 +; +; MM32-LABEL: or_i64_65: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $3, $5, 65 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i64_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $3, $5, 65 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i64_65: - - ; GP32: ori $3, $5, 65 - ; GP32: move $2, $4 - - ; GP64: ori $2, $4, 65 - - ; MM32: ori $3, $5, 65 - ; MM32: move $2, $4 - - ; MM64: ori $2, $4, 65 - %r = or i64 65, %b ret i64 %r } define signext i128 @or_i128_65(i128 signext %b) { +; GP32-LABEL: or_i128_65: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $1, $7, 65 +; GP32-NEXT: move $2, $4 +; GP32-NEXT: move $3, $5 +; GP32-NEXT: move $4, $6 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $5, $1 +; +; GP64-LABEL: or_i128_65: +; GP64: # %bb.0: # %entry +; GP64-NEXT: ori $3, $5, 65 +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i128_65: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $1, $7, 65 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: move $3, $5 +; MM32-NEXT: move $4, $6 +; MM32-NEXT: move $5, $1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i128_65: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $1, $7, 65 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: move $4, $6 +; MM32R6-NEXT: move $5, $1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i128_65: - - ; GP32: ori $[[T0:[0-9]+]], $7, 65 - ; GP32: move $2, $4 - ; GP32: move $3, $5 - ; GP32: move $4, $6 - ; GP32: move $5, $[[T0]] - - ; GP64: ori $3, $5, 65 - ; GP64: move $2, $4 - - ; MM32: ori $[[T0:[0-9]+]], $7, 65 - ; MM32: move $2, $4 - ; MM32: move $3, $5 - ; MM32: move $4, $6 - ; MM32: move $5, $[[T0]] - - ; MM64: ori $3, $5, 65 - ; MM64: move $2, $4 - %r = or i128 65, %b ret i128 %r } define signext i1 @or_i1_256(i1 signext %b) { +; GP32-LABEL: or_i1_256: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i1_256: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i1_256: +; MM32: # %bb.0: # %entry +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i1_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i1_256: - - ; ALL: move $2, $4 - %r = or i1 256, %b ret i1 %r } define signext i8 @or_i8_256(i8 signext %b) { +; GP32-LABEL: or_i8_256: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i8_256: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i8_256: +; MM32: # %bb.0: # %entry +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i8_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i8_256: - - ; ALL: move $2, $4 - %r = or i8 256, %b ret i8 %r } define signext i16 @or_i16_256(i16 signext %b) { +; GP32-LABEL: or_i16_256: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 256 +; +; GP64-LABEL: or_i16_256: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 256 +; +; MM32-LABEL: or_i16_256: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 256 +; +; MM32R6-LABEL: or_i16_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 256 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i16_256: - - ; ALL: ori $2, $4, 256 - %r = or i16 256, %b ret i16 %r } define signext i32 @or_i32_256(i32 signext %b) { +; GP32-LABEL: or_i32_256: +; GP32: # %bb.0: # %entry +; GP32-NEXT: jr $ra +; GP32-NEXT: ori $2, $4, 256 +; +; GP64-LABEL: or_i32_256: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 256 +; +; MM32-LABEL: or_i32_256: +; MM32: # %bb.0: # %entry +; MM32-NEXT: jr $ra +; MM32-NEXT: ori $2, $4, 256 +; +; MM32R6-LABEL: or_i32_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $2, $4, 256 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i32_256: - - ; ALL: ori $2, $4, 256 - %r = or i32 256, %b ret i32 %r } define signext i64 @or_i64_256(i64 signext %b) { +; GP32-LABEL: or_i64_256: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $3, $5, 256 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $2, $4 +; +; GP64-LABEL: or_i64_256: +; GP64: # %bb.0: # %entry +; GP64-NEXT: jr $ra +; GP64-NEXT: ori $2, $4, 256 +; +; MM32-LABEL: or_i64_256: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $3, $5, 256 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i64_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $3, $5, 256 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i64_256: - - ; GP32: ori $3, $5, 256 - ; GP32: move $2, $4 - - ; GP64: ori $2, $4, 256 - - ; MM32: ori $3, $5, 256 - ; MM32: move $2, $4 - - ; MM64: ori $2, $4, 256 - %r = or i64 256, %b ret i64 %r } define signext i128 @or_i128_256(i128 signext %b) { +; GP32-LABEL: or_i128_256: +; GP32: # %bb.0: # %entry +; GP32-NEXT: ori $1, $7, 256 +; GP32-NEXT: move $2, $4 +; GP32-NEXT: move $3, $5 +; GP32-NEXT: move $4, $6 +; GP32-NEXT: jr $ra +; GP32-NEXT: move $5, $1 +; +; GP64-LABEL: or_i128_256: +; GP64: # %bb.0: # %entry +; GP64-NEXT: ori $3, $5, 256 +; GP64-NEXT: jr $ra +; GP64-NEXT: move $2, $4 +; +; MM32-LABEL: or_i128_256: +; MM32: # %bb.0: # %entry +; MM32-NEXT: ori $1, $7, 256 +; MM32-NEXT: move $2, $4 +; MM32-NEXT: move $3, $5 +; MM32-NEXT: move $4, $6 +; MM32-NEXT: move $5, $1 +; MM32-NEXT: jrc $ra +; +; MM32R6-LABEL: or_i128_256: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: ori $1, $7, 256 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: move $4, $6 +; MM32R6-NEXT: move $5, $1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: or_i128_256: - - ; GP32: ori $[[T0:[0-9]+]], $7, 256 - ; GP32: move $2, $4 - ; GP32: move $3, $5 - ; GP32: move $4, $6 - ; GP32: move $5, $[[T0]] - - ; GP64: ori $3, $5, 256 - ; GP64: move $2, $4 - - ; MM32: ori $[[T0:[0-9]+]], $7, 256 - ; MM32: move $2, $4 - ; MM32: move $3, $5 - ; MM32: move $4, $6 - ; MM32: move $5, $[[T0]] - - ; MM64: ori $3, $5, 256 - ; MM64: move $2, $4 - %r = or i128 256, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/sdiv.ll b/test/CodeGen/Mips/llvm-ir/sdiv.ll index defd25bb41acf..11e766319e785 100644 --- a/test/CodeGen/Mips/llvm-ir/sdiv.ll +++ b/test/CodeGen/Mips/llvm-ir/sdiv.ll @@ -30,8 +30,6 @@ ; RUN: -check-prefixes=ALL,MMR3,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) { entry: @@ -174,9 +172,6 @@ entry: ; MM32: lw $25, %call16(__divdi3)($2) - ; MM64: ddiv $2, $4, $5 - ; MM64: teq $5, $zero, 7 - %r = sdiv i64 %a, %b ret i64 %r } @@ -192,8 +187,6 @@ entry: ; MM32: lw $25, %call16(__divti3)($16) - ; MM64: ld $25, %call16(__divti3)($2) - %r = sdiv i128 %a, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/select-dbl.ll b/test/CodeGen/Mips/llvm-ir/select-dbl.ll index 42f02c4cbabf4..a7174d25937ea 100644 --- a/test/CodeGen/Mips/llvm-ir/select-dbl.ll +++ b/test/CodeGen/Mips/llvm-ir/select-dbl.ll @@ -1,32 +1,32 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips2 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,M2,M2-M3 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,SEL-32,32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: llc < %s -march=mips64 -mcpu=mips3 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,M3,M2-M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: llc < %s -march=mips64 -mcpu=mips4 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: llc < %s -march=mips64 -mcpu=mips64 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,SEL-64,64R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM32R3 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM32R6,SEL-32 define double @tst_select_i1_double(i1 signext %s, double %x, double %y) { @@ -53,8 +53,8 @@ entry: ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]] ; SEL-32: mthc1 $6, $[[F0]] - ; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp) ; SEL-32: mtc1 $4, $f0 + ; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp) ; SEL-32: sel.d $f0, $[[F1]], $[[F0]] ; M3: andi $[[T0:[0-9]+]], $4, 1 diff --git a/test/CodeGen/Mips/llvm-ir/select-flt.ll b/test/CodeGen/Mips/llvm-ir/select-flt.ll index ebdbd8a5e3c1c..2b3a9b689c000 100644 --- a/test/CodeGen/Mips/llvm-ir/select-flt.ll +++ b/test/CodeGen/Mips/llvm-ir/select-flt.ll @@ -1,32 +1,32 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips2 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,M2,M2-M3 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,SEL-32,32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: llc < %s -march=mips64 -mcpu=mips3 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,M3,M2-M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: llc < %s -march=mips64 -mcpu=mips4 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: llc < %s -march=mips64 -mcpu=mips64 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,SEL-64,64R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM32R3 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM32R6,SEL-32 define float @tst_select_i1_float(i1 signext %s, float %x, float %y) { diff --git a/test/CodeGen/Mips/llvm-ir/shl.ll b/test/CodeGen/Mips/llvm-ir/shl.ll index 13545907e21e5..6c764b8ad4302 100644 --- a/test/CodeGen/Mips/llvm-ir/shl.ll +++ b/test/CodeGen/Mips/llvm-ir/shl.ll @@ -1,230 +1,1039 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,M2,NOT-R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,NOT-R2-R6,32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32,32R6,R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,M3,NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64,64R6,R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MMR3 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MMR6 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS2 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS32R6 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS3 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS4 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MIPS64R6 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MMR3 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=MMR6 define signext i1 @shl_i1(i1 signext %a, i1 signext %b) { +; MIPS2-LABEL: shl_i1: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: move $2, $4 +; +; MIPS32-LABEL: shl_i1: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: shl_i1: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: shl_i1: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS3-LABEL: shl_i1: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: move $2, $4 +; +; MIPS4-LABEL: shl_i1: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: move $2, $4 +; +; MIPS64-LABEL: shl_i1: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: shl_i1: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: shl_i1: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MMR3-LABEL: shl_i1: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: move $2, $4 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: shl_i1: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: move $2, $4 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: shl_i1: - - ; ALL: move $2, $4 %r = shl i1 %a, %b ret i1 %r } define signext i8 @shl_i8(i8 signext %a, i8 signext %b) { +; MIPS2-LABEL: shl_i8: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: andi $1, $5, 255 +; MIPS2-NEXT: sllv $1, $4, $1 +; MIPS2-NEXT: sll $1, $1, 24 +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: sra $2, $1, 24 +; +; MIPS32-LABEL: shl_i8: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: andi $1, $5, 255 +; MIPS32-NEXT: sllv $1, $4, $1 +; MIPS32-NEXT: sll $1, $1, 24 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: sra $2, $1, 24 +; +; MIPS32R2-LABEL: shl_i8: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $1, $5, 255 +; MIPS32R2-NEXT: sllv $1, $4, $1 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: seb $2, $1 +; +; MIPS32R6-LABEL: shl_i8: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $1, $5, 255 +; MIPS32R6-NEXT: sllv $1, $4, $1 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: seb $2, $1 +; +; MIPS3-LABEL: shl_i8: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: andi $1, $5, 255 +; MIPS3-NEXT: sllv $1, $4, $1 +; MIPS3-NEXT: sll $1, $1, 24 +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: sra $2, $1, 24 +; +; MIPS4-LABEL: shl_i8: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: andi $1, $5, 255 +; MIPS4-NEXT: sllv $1, $4, $1 +; MIPS4-NEXT: sll $1, $1, 24 +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: sra $2, $1, 24 +; +; MIPS64-LABEL: shl_i8: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $1, $5, 255 +; MIPS64-NEXT: sllv $1, $4, $1 +; MIPS64-NEXT: sll $1, $1, 24 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sra $2, $1, 24 +; +; MIPS64R2-LABEL: shl_i8: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $1, $5, 255 +; MIPS64R2-NEXT: sllv $1, $4, $1 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: seb $2, $1 +; +; MIPS64R6-LABEL: shl_i8: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $1, $5, 255 +; MIPS64R6-NEXT: sllv $1, $4, $1 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: seb $2, $1 +; +; MMR3-LABEL: shl_i8: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: andi16 $2, $5, 255 +; MMR3-NEXT: sllv $1, $4, $2 +; MMR3-NEXT: jr $ra +; MMR3-NEXT: seb $2, $1 +; +; MMR6-LABEL: shl_i8: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: andi16 $2, $5, 255 +; MMR6-NEXT: sllv $1, $4, $2 +; MMR6-NEXT: seb $2, $1 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: shl_i8: - - ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255 - ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] - ; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 24 - ; NOT-R2-R6: sra $2, $[[T2]], 24 - - ; R2-R6: andi $[[T0:[0-9]+]], $5, 255 - ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] - ; R2-R6: seb $2, $[[T1]] - - ; MM: andi16 $[[T0:[0-9]+]], $5, 255 - ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]] - ; MM: seb $2, $[[T1]] %r = shl i8 %a, %b ret i8 %r } define signext i16 @shl_i16(i16 signext %a, i16 signext %b) { +; MIPS2-LABEL: shl_i16: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: andi $1, $5, 65535 +; MIPS2-NEXT: sllv $1, $4, $1 +; MIPS2-NEXT: sll $1, $1, 16 +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: sra $2, $1, 16 +; +; MIPS32-LABEL: shl_i16: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: andi $1, $5, 65535 +; MIPS32-NEXT: sllv $1, $4, $1 +; MIPS32-NEXT: sll $1, $1, 16 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: sra $2, $1, 16 +; +; MIPS32R2-LABEL: shl_i16: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: andi $1, $5, 65535 +; MIPS32R2-NEXT: sllv $1, $4, $1 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: seh $2, $1 +; +; MIPS32R6-LABEL: shl_i16: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: andi $1, $5, 65535 +; MIPS32R6-NEXT: sllv $1, $4, $1 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: seh $2, $1 +; +; MIPS3-LABEL: shl_i16: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: andi $1, $5, 65535 +; MIPS3-NEXT: sllv $1, $4, $1 +; MIPS3-NEXT: sll $1, $1, 16 +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: sra $2, $1, 16 +; +; MIPS4-LABEL: shl_i16: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: andi $1, $5, 65535 +; MIPS4-NEXT: sllv $1, $4, $1 +; MIPS4-NEXT: sll $1, $1, 16 +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: sra $2, $1, 16 +; +; MIPS64-LABEL: shl_i16: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: andi $1, $5, 65535 +; MIPS64-NEXT: sllv $1, $4, $1 +; MIPS64-NEXT: sll $1, $1, 16 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sra $2, $1, 16 +; +; MIPS64R2-LABEL: shl_i16: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: andi $1, $5, 65535 +; MIPS64R2-NEXT: sllv $1, $4, $1 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: seh $2, $1 +; +; MIPS64R6-LABEL: shl_i16: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: andi $1, $5, 65535 +; MIPS64R6-NEXT: sllv $1, $4, $1 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: seh $2, $1 +; +; MMR3-LABEL: shl_i16: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: andi16 $2, $5, 65535 +; MMR3-NEXT: sllv $1, $4, $2 +; MMR3-NEXT: jr $ra +; MMR3-NEXT: seh $2, $1 +; +; MMR6-LABEL: shl_i16: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: andi16 $2, $5, 65535 +; MMR6-NEXT: sllv $1, $4, $2 +; MMR6-NEXT: seh $2, $1 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: shl_i16: - - ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535 - ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] - ; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 16 - ; NOT-R2-R6: sra $2, $[[T2]], 16 - - ; R2-R6: andi $[[T0:[0-9]+]], $5, 65535 - ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] - ; R2-R6: seh $2, $[[T1]] - - ; MM: andi16 $[[T0:[0-9]+]], $5, 65535 - ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]] - ; MM: seh $2, $[[T1]] %r = shl i16 %a, %b ret i16 %r } define signext i32 @shl_i32(i32 signext %a, i32 signext %b) { +; MIPS2-LABEL: shl_i32: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: sllv $2, $4, $5 +; +; MIPS32-LABEL: shl_i32: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: sllv $2, $4, $5 +; +; MIPS32R2-LABEL: shl_i32: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: sllv $2, $4, $5 +; +; MIPS32R6-LABEL: shl_i32: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: sllv $2, $4, $5 +; +; MIPS3-LABEL: shl_i32: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: sllv $2, $4, $5 +; +; MIPS4-LABEL: shl_i32: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: sllv $2, $4, $5 +; +; MIPS64-LABEL: shl_i32: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sllv $2, $4, $5 +; +; MIPS64R2-LABEL: shl_i32: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sllv $2, $4, $5 +; +; MIPS64R6-LABEL: shl_i32: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sllv $2, $4, $5 +; +; MMR3-LABEL: shl_i32: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: jr $ra +; MMR3-NEXT: sllv $2, $4, $5 +; +; MMR6-LABEL: shl_i32: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: sllv $2, $4, $5 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: shl_i32: - - ; ALL: sllv $2, $4, $5 %r = shl i32 %a, %b ret i32 %r } define signext i64 @shl_i64(i64 signext %a, i64 signext %b) { +; MIPS2-LABEL: shl_i64: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: sllv $6, $5, $7 +; MIPS2-NEXT: andi $8, $7, 32 +; MIPS2-NEXT: beqz $8, $BB4_3 +; MIPS2-NEXT: move $2, $6 +; MIPS2-NEXT: # %bb.1: # %entry +; MIPS2-NEXT: beqz $8, $BB4_4 +; MIPS2-NEXT: addiu $3, $zero, 0 +; MIPS2-NEXT: $BB4_2: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB4_3: # %entry +; MIPS2-NEXT: sllv $1, $4, $7 +; MIPS2-NEXT: not $2, $7 +; MIPS2-NEXT: srl $3, $5, 1 +; MIPS2-NEXT: srlv $2, $3, $2 +; MIPS2-NEXT: or $2, $1, $2 +; MIPS2-NEXT: bnez $8, $BB4_2 +; MIPS2-NEXT: addiu $3, $zero, 0 +; MIPS2-NEXT: $BB4_4: # %entry +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: move $3, $6 +; +; MIPS32-LABEL: shl_i64: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: sllv $1, $4, $7 +; MIPS32-NEXT: not $2, $7 +; MIPS32-NEXT: srl $3, $5, 1 +; MIPS32-NEXT: srlv $2, $3, $2 +; MIPS32-NEXT: or $2, $1, $2 +; MIPS32-NEXT: sllv $3, $5, $7 +; MIPS32-NEXT: andi $1, $7, 32 +; MIPS32-NEXT: movn $2, $3, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: movn $3, $zero, $1 +; +; MIPS32R2-LABEL: shl_i64: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: sllv $1, $4, $7 +; MIPS32R2-NEXT: not $2, $7 +; MIPS32R2-NEXT: srl $3, $5, 1 +; MIPS32R2-NEXT: srlv $2, $3, $2 +; MIPS32R2-NEXT: or $2, $1, $2 +; MIPS32R2-NEXT: sllv $3, $5, $7 +; MIPS32R2-NEXT: andi $1, $7, 32 +; MIPS32R2-NEXT: movn $2, $3, $1 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: movn $3, $zero, $1 +; +; MIPS32R6-LABEL: shl_i64: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: sllv $1, $4, $7 +; MIPS32R6-NEXT: not $2, $7 +; MIPS32R6-NEXT: srl $3, $5, 1 +; MIPS32R6-NEXT: srlv $2, $3, $2 +; MIPS32R6-NEXT: or $1, $1, $2 +; MIPS32R6-NEXT: andi $3, $7, 32 +; MIPS32R6-NEXT: seleqz $1, $1, $3 +; MIPS32R6-NEXT: sllv $4, $5, $7 +; MIPS32R6-NEXT: selnez $2, $4, $3 +; MIPS32R6-NEXT: or $2, $2, $1 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: seleqz $3, $4, $3 +; +; MIPS3-LABEL: shl_i64: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: dsllv $2, $4, $5 +; +; MIPS4-LABEL: shl_i64: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: dsllv $2, $4, $5 +; +; MIPS64-LABEL: shl_i64: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: dsllv $2, $4, $5 +; +; MIPS64R2-LABEL: shl_i64: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: dsllv $2, $4, $5 +; +; MIPS64R6-LABEL: shl_i64: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: dsllv $2, $4, $5 +; +; MMR3-LABEL: shl_i64: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: sllv $3, $4, $7 +; MMR3-NEXT: not16 $2, $7 +; MMR3-NEXT: srl16 $4, $5, 1 +; MMR3-NEXT: srlv $2, $4, $2 +; MMR3-NEXT: or16 $2, $3 +; MMR3-NEXT: sllv $3, $5, $7 +; MMR3-NEXT: andi16 $4, $7, 32 +; MMR3-NEXT: movn $2, $3, $4 +; MMR3-NEXT: li16 $5, 0 +; MMR3-NEXT: jr $ra +; MMR3-NEXT: movn $3, $5, $4 +; +; MMR6-LABEL: shl_i64: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: sllv $2, $4, $7 +; MMR6-NEXT: not16 $3, $7 +; MMR6-NEXT: srl16 $4, $5, 1 +; MMR6-NEXT: srlv $3, $4, $3 +; MMR6-NEXT: or16 $3, $2 +; MMR6-NEXT: andi16 $4, $7, 32 +; MMR6-NEXT: seleqz $1, $3, $4 +; MMR6-NEXT: sllv $3, $5, $7 +; MMR6-NEXT: selnez $2, $3, $4 +; MMR6-NEXT: or $2, $2, $1 +; MMR6-NEXT: seleqz $3, $3, $4 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: shl_i64: - - ; M2: sllv $[[T0:[0-9]+]], $5, $7 - ; M2: andi $[[T1:[0-9]+]], $7, 32 - ; M2: beqz $[[T1]], $[[BB0:BB[0-9_]+]] - ; M2: move $2, $[[T0]] - ; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]] - ; M2: addiu $3, $zero, 0 - ; M2: $[[EXIT:BB[0-9_]+]]: - ; M2: jr $ra - ; M2: nop - ; M2: $[[BB0]]: - ; M2: sllv $[[T2:[0-9]+]], $4, $7 - ; M2: not $[[T3:[0-9]+]], $7 - ; M2: srl $[[T4:[0-9]+]], $5, 1 - ; M2: srlv $[[T5:[0-9]+]], $[[T4]], $[[T3]] - ; M2: or $2, $[[T2]], $[[T3]] - ; M2: bnez $[[T1]], $[[EXIT]] - ; M2: addiu $3, $zero, 0 - ; M2: $[[BB1]]: - ; M2: jr $ra - ; M2: move $3, $[[T0]] - - ; 32R1-R5: sllv $[[T0:[0-9]+]], $4, $7 - ; 32R1-R5: not $[[T1:[0-9]+]], $7 - ; 32R1-R5: srl $[[T2:[0-9]+]], $5, 1 - ; 32R1-R5: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; 32R1-R5: or $2, $[[T0]], $[[T3]] - ; 32R1-R5: sllv $[[T4:[0-9]+]], $5, $7 - ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32 - ; 32R1-R5: movn $2, $[[T4]], $[[T5]] - ; 32R1-R5: jr $ra - ; 32R1-R5: movn $3, $zero, $[[T5]] - - ; 32R6: sllv $[[T0:[0-9]+]], $4, $7 - ; 32R6: not $[[T1:[0-9]+]], $7 - ; 32R6: srl $[[T2:[0-9]+]], $5, 1 - ; 32R6: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; 32R6: or $[[T4:[0-9]+]], $[[T0]], $[[T3]] - ; 32R6: andi $[[T5:[0-9]+]], $7, 32 - ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T2]] - ; 32R6: sllv $[[T7:[0-9]+]], $5, $7 - ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] - ; 32R6: or $2, $[[T8]], $[[T6]] - ; 32R6: jr $ra - ; 32R6: seleqz $3, $[[T7]], $[[T5]] - - ; GP64: dsllv $2, $4, $5 - - ; MMR3: sllv $[[T0:[0-9]+]], $4, $7 - ; MMR3: not16 $[[T1:[0-9]+]], $7 - ; MMR3: srl16 $[[T2:[0-9]+]], $5, 1 - ; MMR3: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] - ; MMR3: sllv $[[T5:[0-9]+]], $5, $7 - ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 - ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] - ; MMR3: li16 $[[T8:[0-9]+]], 0 - ; MMR3: movn $3, $[[T8]], $[[T6]] - - ; MMR6: sllv $[[T0:[0-9]+]], $4, $7 - ; MMR6: not16 $[[T1:[0-9]+]], $7 - ; MMR6: srl16 $[[T2:[0-9]+]], $5, 1 - ; MMR6: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]] - ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32 - ; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]] - ; MMR6: sllv $[[T7:[0-9]+]], $5, $7 - ; MMR6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] - ; MMR6: or $2, $[[T8]], $[[T6]] - ; MMR6: seleqz $3, $[[T7]], $[[T5]] %r = shl i64 %a, %b ret i64 %r } define signext i128 @shl_i128(i128 signext %a, i128 signext %b) { +; MIPS2-LABEL: shl_i128: +; MIPS2: # %bb.0: # %entry +; MIPS2-NEXT: addiu $sp, $sp, -8 +; MIPS2-NEXT: .cfi_def_cfa_offset 8 +; MIPS2-NEXT: sw $17, 4($sp) # 4-byte Folded Spill +; MIPS2-NEXT: sw $16, 0($sp) # 4-byte Folded Spill +; MIPS2-NEXT: .cfi_offset 17, -4 +; MIPS2-NEXT: .cfi_offset 16, -8 +; MIPS2-NEXT: lw $8, 36($sp) +; MIPS2-NEXT: addiu $1, $zero, 64 +; MIPS2-NEXT: subu $10, $1, $8 +; MIPS2-NEXT: srlv $3, $6, $10 +; MIPS2-NEXT: andi $13, $10, 32 +; MIPS2-NEXT: addiu $2, $zero, 0 +; MIPS2-NEXT: bnez $13, $BB5_2 +; MIPS2-NEXT: addiu $25, $zero, 0 +; MIPS2-NEXT: # %bb.1: # %entry +; MIPS2-NEXT: move $25, $3 +; MIPS2-NEXT: $BB5_2: # %entry +; MIPS2-NEXT: not $9, $8 +; MIPS2-NEXT: sllv $11, $5, $8 +; MIPS2-NEXT: andi $12, $8, 32 +; MIPS2-NEXT: bnez $12, $BB5_4 +; MIPS2-NEXT: move $16, $11 +; MIPS2-NEXT: # %bb.3: # %entry +; MIPS2-NEXT: sllv $1, $4, $8 +; MIPS2-NEXT: srl $14, $5, 1 +; MIPS2-NEXT: srlv $14, $14, $9 +; MIPS2-NEXT: or $16, $1, $14 +; MIPS2-NEXT: $BB5_4: # %entry +; MIPS2-NEXT: addiu $24, $8, -64 +; MIPS2-NEXT: srl $17, $7, 1 +; MIPS2-NEXT: sllv $14, $7, $24 +; MIPS2-NEXT: andi $15, $24, 32 +; MIPS2-NEXT: bnez $15, $BB5_6 +; MIPS2-NEXT: move $gp, $14 +; MIPS2-NEXT: # %bb.5: # %entry +; MIPS2-NEXT: sllv $1, $6, $24 +; MIPS2-NEXT: not $24, $24 +; MIPS2-NEXT: srlv $24, $17, $24 +; MIPS2-NEXT: or $gp, $1, $24 +; MIPS2-NEXT: $BB5_6: # %entry +; MIPS2-NEXT: sltiu $24, $8, 64 +; MIPS2-NEXT: beqz $24, $BB5_8 +; MIPS2-NEXT: nop +; MIPS2-NEXT: # %bb.7: +; MIPS2-NEXT: or $gp, $16, $25 +; MIPS2-NEXT: $BB5_8: # %entry +; MIPS2-NEXT: sllv $25, $7, $8 +; MIPS2-NEXT: bnez $12, $BB5_10 +; MIPS2-NEXT: move $16, $25 +; MIPS2-NEXT: # %bb.9: # %entry +; MIPS2-NEXT: sllv $1, $6, $8 +; MIPS2-NEXT: srlv $9, $17, $9 +; MIPS2-NEXT: or $16, $1, $9 +; MIPS2-NEXT: $BB5_10: # %entry +; MIPS2-NEXT: bnez $12, $BB5_12 +; MIPS2-NEXT: addiu $9, $zero, 0 +; MIPS2-NEXT: # %bb.11: # %entry +; MIPS2-NEXT: move $9, $25 +; MIPS2-NEXT: $BB5_12: # %entry +; MIPS2-NEXT: addiu $1, $zero, 63 +; MIPS2-NEXT: sltiu $25, $8, 1 +; MIPS2-NEXT: beqz $25, $BB5_22 +; MIPS2-NEXT: sltu $17, $1, $8 +; MIPS2-NEXT: # %bb.13: # %entry +; MIPS2-NEXT: beqz $17, $BB5_23 +; MIPS2-NEXT: addiu $8, $zero, 0 +; MIPS2-NEXT: $BB5_14: # %entry +; MIPS2-NEXT: beqz $17, $BB5_24 +; MIPS2-NEXT: addiu $9, $zero, 0 +; MIPS2-NEXT: $BB5_15: # %entry +; MIPS2-NEXT: beqz $13, $BB5_25 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_16: # %entry +; MIPS2-NEXT: beqz $12, $BB5_26 +; MIPS2-NEXT: addiu $6, $zero, 0 +; MIPS2-NEXT: $BB5_17: # %entry +; MIPS2-NEXT: beqz $15, $BB5_27 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_18: # %entry +; MIPS2-NEXT: bnez $24, $BB5_28 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_19: # %entry +; MIPS2-NEXT: bnez $25, $BB5_21 +; MIPS2-NEXT: nop +; MIPS2-NEXT: $BB5_20: # %entry +; MIPS2-NEXT: move $5, $2 +; MIPS2-NEXT: $BB5_21: # %entry +; MIPS2-NEXT: move $2, $4 +; MIPS2-NEXT: move $3, $5 +; MIPS2-NEXT: move $4, $9 +; MIPS2-NEXT: move $5, $8 +; MIPS2-NEXT: lw $16, 0($sp) # 4-byte Folded Reload +; MIPS2-NEXT: lw $17, 4($sp) # 4-byte Folded Reload +; MIPS2-NEXT: jr $ra +; MIPS2-NEXT: addiu $sp, $sp, 8 +; MIPS2-NEXT: $BB5_22: # %entry +; MIPS2-NEXT: move $4, $gp +; MIPS2-NEXT: bnez $17, $BB5_14 +; MIPS2-NEXT: addiu $8, $zero, 0 +; MIPS2-NEXT: $BB5_23: # %entry +; MIPS2-NEXT: move $8, $9 +; MIPS2-NEXT: bnez $17, $BB5_15 +; MIPS2-NEXT: addiu $9, $zero, 0 +; MIPS2-NEXT: $BB5_24: # %entry +; MIPS2-NEXT: bnez $13, $BB5_16 +; MIPS2-NEXT: move $9, $16 +; MIPS2-NEXT: $BB5_25: # %entry +; MIPS2-NEXT: not $1, $10 +; MIPS2-NEXT: sll $3, $6, 1 +; MIPS2-NEXT: srlv $6, $7, $10 +; MIPS2-NEXT: sllv $1, $3, $1 +; MIPS2-NEXT: or $3, $1, $6 +; MIPS2-NEXT: bnez $12, $BB5_17 +; MIPS2-NEXT: addiu $6, $zero, 0 +; MIPS2-NEXT: $BB5_26: # %entry +; MIPS2-NEXT: bnez $15, $BB5_18 +; MIPS2-NEXT: move $6, $11 +; MIPS2-NEXT: $BB5_27: # %entry +; MIPS2-NEXT: beqz $24, $BB5_19 +; MIPS2-NEXT: move $2, $14 +; MIPS2-NEXT: $BB5_28: +; MIPS2-NEXT: bnez $25, $BB5_21 +; MIPS2-NEXT: or $2, $6, $3 +; MIPS2-NEXT: # %bb.29: +; MIPS2-NEXT: b $BB5_20 +; MIPS2-NEXT: nop +; +; MIPS32-LABEL: shl_i128: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lw $8, 28($sp) +; MIPS32-NEXT: addiu $1, $zero, 64 +; MIPS32-NEXT: subu $1, $1, $8 +; MIPS32-NEXT: srlv $9, $6, $1 +; MIPS32-NEXT: andi $10, $1, 32 +; MIPS32-NEXT: move $2, $9 +; MIPS32-NEXT: movn $2, $zero, $10 +; MIPS32-NEXT: sllv $3, $4, $8 +; MIPS32-NEXT: not $11, $8 +; MIPS32-NEXT: srl $12, $5, 1 +; MIPS32-NEXT: srlv $12, $12, $11 +; MIPS32-NEXT: or $3, $3, $12 +; MIPS32-NEXT: sllv $12, $5, $8 +; MIPS32-NEXT: andi $13, $8, 32 +; MIPS32-NEXT: movn $3, $12, $13 +; MIPS32-NEXT: addiu $14, $8, -64 +; MIPS32-NEXT: or $15, $3, $2 +; MIPS32-NEXT: sllv $2, $6, $14 +; MIPS32-NEXT: srl $24, $7, 1 +; MIPS32-NEXT: not $3, $14 +; MIPS32-NEXT: srlv $3, $24, $3 +; MIPS32-NEXT: or $2, $2, $3 +; MIPS32-NEXT: sllv $3, $7, $14 +; MIPS32-NEXT: andi $14, $14, 32 +; MIPS32-NEXT: movn $2, $3, $14 +; MIPS32-NEXT: sltiu $25, $8, 64 +; MIPS32-NEXT: movn $2, $15, $25 +; MIPS32-NEXT: srlv $15, $7, $1 +; MIPS32-NEXT: not $1, $1 +; MIPS32-NEXT: sll $gp, $6, 1 +; MIPS32-NEXT: sllv $1, $gp, $1 +; MIPS32-NEXT: or $15, $1, $15 +; MIPS32-NEXT: sllv $1, $6, $8 +; MIPS32-NEXT: srlv $6, $24, $11 +; MIPS32-NEXT: or $1, $1, $6 +; MIPS32-NEXT: sllv $6, $7, $8 +; MIPS32-NEXT: movn $1, $6, $13 +; MIPS32-NEXT: movz $2, $4, $8 +; MIPS32-NEXT: movz $1, $zero, $25 +; MIPS32-NEXT: movn $15, $9, $10 +; MIPS32-NEXT: movn $12, $zero, $13 +; MIPS32-NEXT: or $4, $12, $15 +; MIPS32-NEXT: movn $3, $zero, $14 +; MIPS32-NEXT: movn $3, $4, $25 +; MIPS32-NEXT: movz $3, $5, $8 +; MIPS32-NEXT: movn $6, $zero, $13 +; MIPS32-NEXT: movz $6, $zero, $25 +; MIPS32-NEXT: move $4, $1 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: move $5, $6 +; +; MIPS32R2-LABEL: shl_i128: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: lw $8, 28($sp) +; MIPS32R2-NEXT: addiu $1, $zero, 64 +; MIPS32R2-NEXT: subu $1, $1, $8 +; MIPS32R2-NEXT: srlv $9, $6, $1 +; MIPS32R2-NEXT: andi $10, $1, 32 +; MIPS32R2-NEXT: move $2, $9 +; MIPS32R2-NEXT: movn $2, $zero, $10 +; MIPS32R2-NEXT: sllv $3, $4, $8 +; MIPS32R2-NEXT: not $11, $8 +; MIPS32R2-NEXT: srl $12, $5, 1 +; MIPS32R2-NEXT: srlv $12, $12, $11 +; MIPS32R2-NEXT: or $3, $3, $12 +; MIPS32R2-NEXT: sllv $12, $5, $8 +; MIPS32R2-NEXT: andi $13, $8, 32 +; MIPS32R2-NEXT: movn $3, $12, $13 +; MIPS32R2-NEXT: addiu $14, $8, -64 +; MIPS32R2-NEXT: or $15, $3, $2 +; MIPS32R2-NEXT: sllv $2, $6, $14 +; MIPS32R2-NEXT: srl $24, $7, 1 +; MIPS32R2-NEXT: not $3, $14 +; MIPS32R2-NEXT: srlv $3, $24, $3 +; MIPS32R2-NEXT: or $2, $2, $3 +; MIPS32R2-NEXT: sllv $3, $7, $14 +; MIPS32R2-NEXT: andi $14, $14, 32 +; MIPS32R2-NEXT: movn $2, $3, $14 +; MIPS32R2-NEXT: sltiu $25, $8, 64 +; MIPS32R2-NEXT: movn $2, $15, $25 +; MIPS32R2-NEXT: srlv $15, $7, $1 +; MIPS32R2-NEXT: not $1, $1 +; MIPS32R2-NEXT: sll $gp, $6, 1 +; MIPS32R2-NEXT: sllv $1, $gp, $1 +; MIPS32R2-NEXT: or $15, $1, $15 +; MIPS32R2-NEXT: sllv $1, $6, $8 +; MIPS32R2-NEXT: srlv $6, $24, $11 +; MIPS32R2-NEXT: or $1, $1, $6 +; MIPS32R2-NEXT: sllv $6, $7, $8 +; MIPS32R2-NEXT: movn $1, $6, $13 +; MIPS32R2-NEXT: movz $2, $4, $8 +; MIPS32R2-NEXT: movz $1, $zero, $25 +; MIPS32R2-NEXT: movn $15, $9, $10 +; MIPS32R2-NEXT: movn $12, $zero, $13 +; MIPS32R2-NEXT: or $4, $12, $15 +; MIPS32R2-NEXT: movn $3, $zero, $14 +; MIPS32R2-NEXT: movn $3, $4, $25 +; MIPS32R2-NEXT: movz $3, $5, $8 +; MIPS32R2-NEXT: movn $6, $zero, $13 +; MIPS32R2-NEXT: movz $6, $zero, $25 +; MIPS32R2-NEXT: move $4, $1 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $5, $6 +; +; MIPS32R6-LABEL: shl_i128: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: lw $3, 28($sp) +; MIPS32R6-NEXT: sllv $1, $4, $3 +; MIPS32R6-NEXT: not $2, $3 +; MIPS32R6-NEXT: srl $8, $5, 1 +; MIPS32R6-NEXT: srlv $8, $8, $2 +; MIPS32R6-NEXT: or $1, $1, $8 +; MIPS32R6-NEXT: sllv $8, $5, $3 +; MIPS32R6-NEXT: andi $9, $3, 32 +; MIPS32R6-NEXT: seleqz $1, $1, $9 +; MIPS32R6-NEXT: selnez $10, $8, $9 +; MIPS32R6-NEXT: addiu $11, $zero, 64 +; MIPS32R6-NEXT: subu $11, $11, $3 +; MIPS32R6-NEXT: srlv $12, $6, $11 +; MIPS32R6-NEXT: andi $13, $11, 32 +; MIPS32R6-NEXT: seleqz $14, $12, $13 +; MIPS32R6-NEXT: or $1, $10, $1 +; MIPS32R6-NEXT: selnez $10, $12, $13 +; MIPS32R6-NEXT: srlv $12, $7, $11 +; MIPS32R6-NEXT: not $11, $11 +; MIPS32R6-NEXT: sll $15, $6, 1 +; MIPS32R6-NEXT: sllv $11, $15, $11 +; MIPS32R6-NEXT: or $11, $11, $12 +; MIPS32R6-NEXT: seleqz $11, $11, $13 +; MIPS32R6-NEXT: addiu $12, $3, -64 +; MIPS32R6-NEXT: or $10, $10, $11 +; MIPS32R6-NEXT: or $1, $1, $14 +; MIPS32R6-NEXT: sllv $11, $6, $12 +; MIPS32R6-NEXT: srl $13, $7, 1 +; MIPS32R6-NEXT: not $14, $12 +; MIPS32R6-NEXT: srlv $14, $13, $14 +; MIPS32R6-NEXT: or $11, $11, $14 +; MIPS32R6-NEXT: andi $14, $12, 32 +; MIPS32R6-NEXT: seleqz $11, $11, $14 +; MIPS32R6-NEXT: sllv $12, $7, $12 +; MIPS32R6-NEXT: selnez $15, $12, $14 +; MIPS32R6-NEXT: sltiu $24, $3, 64 +; MIPS32R6-NEXT: selnez $1, $1, $24 +; MIPS32R6-NEXT: or $11, $15, $11 +; MIPS32R6-NEXT: sllv $6, $6, $3 +; MIPS32R6-NEXT: srlv $2, $13, $2 +; MIPS32R6-NEXT: seleqz $8, $8, $9 +; MIPS32R6-NEXT: or $8, $8, $10 +; MIPS32R6-NEXT: or $6, $6, $2 +; MIPS32R6-NEXT: seleqz $2, $11, $24 +; MIPS32R6-NEXT: seleqz $10, $zero, $24 +; MIPS32R6-NEXT: sllv $7, $7, $3 +; MIPS32R6-NEXT: seleqz $11, $7, $9 +; MIPS32R6-NEXT: selnez $11, $11, $24 +; MIPS32R6-NEXT: seleqz $4, $4, $3 +; MIPS32R6-NEXT: or $1, $1, $2 +; MIPS32R6-NEXT: selnez $1, $1, $3 +; MIPS32R6-NEXT: or $2, $4, $1 +; MIPS32R6-NEXT: or $1, $10, $11 +; MIPS32R6-NEXT: seleqz $4, $6, $9 +; MIPS32R6-NEXT: selnez $6, $7, $9 +; MIPS32R6-NEXT: seleqz $5, $5, $3 +; MIPS32R6-NEXT: selnez $7, $8, $24 +; MIPS32R6-NEXT: seleqz $8, $12, $14 +; MIPS32R6-NEXT: seleqz $8, $8, $24 +; MIPS32R6-NEXT: or $7, $7, $8 +; MIPS32R6-NEXT: selnez $3, $7, $3 +; MIPS32R6-NEXT: or $3, $5, $3 +; MIPS32R6-NEXT: or $4, $6, $4 +; MIPS32R6-NEXT: selnez $4, $4, $24 +; MIPS32R6-NEXT: or $4, $10, $4 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $5, $1 +; +; MIPS3-LABEL: shl_i128: +; MIPS3: # %bb.0: # %entry +; MIPS3-NEXT: sll $3, $7, 0 +; MIPS3-NEXT: dsllv $6, $5, $7 +; MIPS3-NEXT: andi $8, $3, 64 +; MIPS3-NEXT: beqz $8, .LBB5_3 +; MIPS3-NEXT: move $2, $6 +; MIPS3-NEXT: # %bb.1: # %entry +; MIPS3-NEXT: beqz $8, .LBB5_4 +; MIPS3-NEXT: daddiu $3, $zero, 0 +; MIPS3-NEXT: .LBB5_2: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: nop +; MIPS3-NEXT: .LBB5_3: # %entry +; MIPS3-NEXT: dsllv $1, $4, $7 +; MIPS3-NEXT: dsrl $2, $5, 1 +; MIPS3-NEXT: not $3, $3 +; MIPS3-NEXT: dsrlv $2, $2, $3 +; MIPS3-NEXT: or $2, $1, $2 +; MIPS3-NEXT: bnez $8, .LBB5_2 +; MIPS3-NEXT: daddiu $3, $zero, 0 +; MIPS3-NEXT: .LBB5_4: # %entry +; MIPS3-NEXT: jr $ra +; MIPS3-NEXT: move $3, $6 +; +; MIPS4-LABEL: shl_i128: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: dsllv $1, $4, $7 +; MIPS4-NEXT: dsrl $2, $5, 1 +; MIPS4-NEXT: sll $4, $7, 0 +; MIPS4-NEXT: not $3, $4 +; MIPS4-NEXT: dsrlv $2, $2, $3 +; MIPS4-NEXT: or $2, $1, $2 +; MIPS4-NEXT: dsllv $3, $5, $7 +; MIPS4-NEXT: andi $1, $4, 64 +; MIPS4-NEXT: movn $2, $3, $1 +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: movn $3, $zero, $1 +; +; MIPS64-LABEL: shl_i128: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: dsllv $1, $4, $7 +; MIPS64-NEXT: dsrl $2, $5, 1 +; MIPS64-NEXT: sll $4, $7, 0 +; MIPS64-NEXT: not $3, $4 +; MIPS64-NEXT: dsrlv $2, $2, $3 +; MIPS64-NEXT: or $2, $1, $2 +; MIPS64-NEXT: dsllv $3, $5, $7 +; MIPS64-NEXT: andi $1, $4, 64 +; MIPS64-NEXT: movn $2, $3, $1 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: movn $3, $zero, $1 +; +; MIPS64R2-LABEL: shl_i128: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: dsllv $1, $4, $7 +; MIPS64R2-NEXT: dsrl $2, $5, 1 +; MIPS64R2-NEXT: sll $4, $7, 0 +; MIPS64R2-NEXT: not $3, $4 +; MIPS64R2-NEXT: dsrlv $2, $2, $3 +; MIPS64R2-NEXT: or $2, $1, $2 +; MIPS64R2-NEXT: dsllv $3, $5, $7 +; MIPS64R2-NEXT: andi $1, $4, 64 +; MIPS64R2-NEXT: movn $2, $3, $1 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: movn $3, $zero, $1 +; +; MIPS64R6-LABEL: shl_i128: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: dsllv $1, $4, $7 +; MIPS64R6-NEXT: dsrl $2, $5, 1 +; MIPS64R6-NEXT: sll $3, $7, 0 +; MIPS64R6-NEXT: not $4, $3 +; MIPS64R6-NEXT: dsrlv $2, $2, $4 +; MIPS64R6-NEXT: or $1, $1, $2 +; MIPS64R6-NEXT: andi $2, $3, 64 +; MIPS64R6-NEXT: sll $3, $2, 0 +; MIPS64R6-NEXT: seleqz $1, $1, $3 +; MIPS64R6-NEXT: dsllv $4, $5, $7 +; MIPS64R6-NEXT: selnez $2, $4, $3 +; MIPS64R6-NEXT: or $2, $2, $1 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: seleqz $3, $4, $3 +; +; MMR3-LABEL: shl_i128: +; MMR3: # %bb.0: # %entry +; MMR3-NEXT: addiusp -48 +; MMR3-NEXT: .cfi_def_cfa_offset 48 +; MMR3-NEXT: sw $17, 44($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $16, 40($sp) # 4-byte Folded Spill +; MMR3-NEXT: .cfi_offset 17, -4 +; MMR3-NEXT: .cfi_offset 16, -8 +; MMR3-NEXT: sw $7, 8($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $6, 36($sp) # 4-byte Folded Spill +; MMR3-NEXT: move $17, $6 +; MMR3-NEXT: sw $5, 32($sp) # 4-byte Folded Spill +; MMR3-NEXT: move $1, $4 +; MMR3-NEXT: lw $16, 76($sp) +; MMR3-NEXT: sllv $2, $1, $16 +; MMR3-NEXT: not16 $4, $16 +; MMR3-NEXT: sw $4, 24($sp) # 4-byte Folded Spill +; MMR3-NEXT: srl16 $3, $5, 1 +; MMR3-NEXT: srlv $4, $3, $4 +; MMR3-NEXT: li16 $3, 64 +; MMR3-NEXT: or16 $4, $2 +; MMR3-NEXT: sllv $6, $5, $16 +; MMR3-NEXT: sw $6, 20($sp) # 4-byte Folded Spill +; MMR3-NEXT: subu16 $7, $3, $16 +; MMR3-NEXT: srlv $9, $17, $7 +; MMR3-NEXT: andi16 $2, $7, 32 +; MMR3-NEXT: sw $2, 28($sp) # 4-byte Folded Spill +; MMR3-NEXT: andi16 $3, $16, 32 +; MMR3-NEXT: sw $3, 12($sp) # 4-byte Folded Spill +; MMR3-NEXT: move $5, $9 +; MMR3-NEXT: li16 $17, 0 +; MMR3-NEXT: movn $5, $17, $2 +; MMR3-NEXT: movn $4, $6, $3 +; MMR3-NEXT: addiu $2, $16, -64 +; MMR3-NEXT: lw $3, 36($sp) # 4-byte Folded Reload +; MMR3-NEXT: sllv $3, $3, $2 +; MMR3-NEXT: sw $3, 16($sp) # 4-byte Folded Spill +; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload +; MMR3-NEXT: srl16 $6, $17, 1 +; MMR3-NEXT: sw $6, 4($sp) # 4-byte Folded Spill +; MMR3-NEXT: not16 $3, $2 +; MMR3-NEXT: srlv $3, $6, $3 +; MMR3-NEXT: or16 $4, $5 +; MMR3-NEXT: lw $5, 16($sp) # 4-byte Folded Reload +; MMR3-NEXT: or16 $3, $5 +; MMR3-NEXT: sllv $8, $17, $2 +; MMR3-NEXT: andi16 $2, $2, 32 +; MMR3-NEXT: sw $2, 16($sp) # 4-byte Folded Spill +; MMR3-NEXT: movn $3, $8, $2 +; MMR3-NEXT: srlv $2, $17, $7 +; MMR3-NEXT: not16 $5, $7 +; MMR3-NEXT: lw $7, 36($sp) # 4-byte Folded Reload +; MMR3-NEXT: sll16 $6, $7, 1 +; MMR3-NEXT: sllv $5, $6, $5 +; MMR3-NEXT: sltiu $10, $16, 64 +; MMR3-NEXT: movn $3, $4, $10 +; MMR3-NEXT: or16 $5, $2 +; MMR3-NEXT: sllv $2, $7, $16 +; MMR3-NEXT: lw $4, 24($sp) # 4-byte Folded Reload +; MMR3-NEXT: lw $6, 4($sp) # 4-byte Folded Reload +; MMR3-NEXT: srlv $4, $6, $4 +; MMR3-NEXT: or16 $4, $2 +; MMR3-NEXT: sllv $6, $17, $16 +; MMR3-NEXT: lw $2, 12($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $4, $6, $2 +; MMR3-NEXT: sltiu $11, $16, 64 +; MMR3-NEXT: movz $3, $1, $16 +; MMR3-NEXT: li16 $7, 0 +; MMR3-NEXT: movz $4, $7, $11 +; MMR3-NEXT: lw $17, 28($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $5, $9, $17 +; MMR3-NEXT: lw $7, 20($sp) # 4-byte Folded Reload +; MMR3-NEXT: li16 $17, 0 +; MMR3-NEXT: movn $7, $17, $2 +; MMR3-NEXT: or16 $7, $5 +; MMR3-NEXT: lw $5, 16($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $8, $17, $5 +; MMR3-NEXT: li16 $17, 0 +; MMR3-NEXT: movn $8, $7, $10 +; MMR3-NEXT: lw $5, 32($sp) # 4-byte Folded Reload +; MMR3-NEXT: movz $8, $5, $16 +; MMR3-NEXT: movn $6, $17, $2 +; MMR3-NEXT: li16 $5, 0 +; MMR3-NEXT: movz $6, $5, $11 +; MMR3-NEXT: move $2, $3 +; MMR3-NEXT: move $3, $8 +; MMR3-NEXT: move $5, $6 +; MMR3-NEXT: lw $16, 40($sp) # 4-byte Folded Reload +; MMR3-NEXT: lw $17, 44($sp) # 4-byte Folded Reload +; MMR3-NEXT: addiusp 48 +; MMR3-NEXT: jrc $ra +; +; MMR6-LABEL: shl_i128: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: addiu $sp, $sp, -32 +; MMR6-NEXT: .cfi_def_cfa_offset 32 +; MMR6-NEXT: sw $17, 28($sp) # 4-byte Folded Spill +; MMR6-NEXT: sw $16, 24($sp) # 4-byte Folded Spill +; MMR6-NEXT: .cfi_offset 17, -4 +; MMR6-NEXT: .cfi_offset 16, -8 +; MMR6-NEXT: sw $6, 4($sp) # 4-byte Folded Spill +; MMR6-NEXT: move $1, $4 +; MMR6-NEXT: lw $3, 60($sp) +; MMR6-NEXT: sllv $2, $1, $3 +; MMR6-NEXT: not16 $4, $3 +; MMR6-NEXT: sw $4, 16($sp) # 4-byte Folded Spill +; MMR6-NEXT: sw $5, 20($sp) # 4-byte Folded Spill +; MMR6-NEXT: srl16 $16, $5, 1 +; MMR6-NEXT: srlv $17, $16, $4 +; MMR6-NEXT: or16 $17, $2 +; MMR6-NEXT: sllv $8, $5, $3 +; MMR6-NEXT: andi16 $16, $3, 32 +; MMR6-NEXT: seleqz $4, $17, $16 +; MMR6-NEXT: selnez $9, $8, $16 +; MMR6-NEXT: li16 $17, 64 +; MMR6-NEXT: subu16 $17, $17, $3 +; MMR6-NEXT: srlv $10, $6, $17 +; MMR6-NEXT: andi16 $2, $17, 32 +; MMR6-NEXT: seleqz $5, $10, $2 +; MMR6-NEXT: sw $5, 8($sp) # 4-byte Folded Spill +; MMR6-NEXT: or $4, $9, $4 +; MMR6-NEXT: selnez $9, $10, $2 +; MMR6-NEXT: srlv $5, $7, $17 +; MMR6-NEXT: sw $5, 12($sp) # 4-byte Folded Spill +; MMR6-NEXT: not16 $17, $17 +; MMR6-NEXT: sll16 $5, $6, 1 +; MMR6-NEXT: sllv $5, $5, $17 +; MMR6-NEXT: lw $17, 12($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $5, $17 +; MMR6-NEXT: seleqz $2, $5, $2 +; MMR6-NEXT: addiu $5, $3, -64 +; MMR6-NEXT: or $2, $9, $2 +; MMR6-NEXT: sw $2, 12($sp) # 4-byte Folded Spill +; MMR6-NEXT: lw $2, 8($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $4, $2 +; MMR6-NEXT: sllv $2, $6, $5 +; MMR6-NEXT: sw $2, 8($sp) # 4-byte Folded Spill +; MMR6-NEXT: srl16 $6, $7, 1 +; MMR6-NEXT: not16 $17, $5 +; MMR6-NEXT: srlv $2, $6, $17 +; MMR6-NEXT: lw $17, 8($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $2, $17 +; MMR6-NEXT: andi16 $17, $5, 32 +; MMR6-NEXT: seleqz $2, $2, $17 +; MMR6-NEXT: sllv $12, $7, $5 +; MMR6-NEXT: selnez $9, $12, $17 +; MMR6-NEXT: sltiu $10, $3, 64 +; MMR6-NEXT: selnez $11, $4, $10 +; MMR6-NEXT: or $9, $9, $2 +; MMR6-NEXT: lw $2, 4($sp) # 4-byte Folded Reload +; MMR6-NEXT: sllv $5, $2, $3 +; MMR6-NEXT: lw $4, 16($sp) # 4-byte Folded Reload +; MMR6-NEXT: srlv $6, $6, $4 +; MMR6-NEXT: seleqz $4, $8, $16 +; MMR6-NEXT: lw $2, 12($sp) # 4-byte Folded Reload +; MMR6-NEXT: or16 $4, $2 +; MMR6-NEXT: or16 $6, $5 +; MMR6-NEXT: seleqz $2, $9, $10 +; MMR6-NEXT: li16 $5, 0 +; MMR6-NEXT: seleqz $5, $5, $10 +; MMR6-NEXT: sllv $7, $7, $3 +; MMR6-NEXT: seleqz $8, $7, $16 +; MMR6-NEXT: selnez $8, $8, $10 +; MMR6-NEXT: seleqz $1, $1, $3 +; MMR6-NEXT: or $2, $11, $2 +; MMR6-NEXT: selnez $2, $2, $3 +; MMR6-NEXT: or $2, $1, $2 +; MMR6-NEXT: or $1, $5, $8 +; MMR6-NEXT: seleqz $6, $6, $16 +; MMR6-NEXT: selnez $7, $7, $16 +; MMR6-NEXT: lw $16, 20($sp) # 4-byte Folded Reload +; MMR6-NEXT: seleqz $8, $16, $3 +; MMR6-NEXT: selnez $4, $4, $10 +; MMR6-NEXT: seleqz $9, $12, $17 +; MMR6-NEXT: seleqz $9, $9, $10 +; MMR6-NEXT: or $4, $4, $9 +; MMR6-NEXT: selnez $3, $4, $3 +; MMR6-NEXT: or $3, $8, $3 +; MMR6-NEXT: or $4, $7, $6 +; MMR6-NEXT: selnez $4, $4, $10 +; MMR6-NEXT: or $4, $5, $4 +; MMR6-NEXT: move $5, $1 +; MMR6-NEXT: lw $16, 24($sp) # 4-byte Folded Reload +; MMR6-NEXT: lw $17, 28($sp) # 4-byte Folded Reload +; MMR6-NEXT: addiu $sp, $sp, 32 +; MMR6-NEXT: jrc $ra entry: -; ALL-LABEL: shl_i128: - - ; o32 shouldn't use TImode helpers. - ; GP32-NOT: lw $25, %call16(__ashlti3)($gp) - ; MM-NOT: lw $25, %call16(__ashlti3)($2) - - ; M3: sll $[[T0:[0-9]+]], $7, 0 - ; M3: dsllv $[[T1:[0-9]+]], $5, $7 - ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 - ; M3: beqz $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]] - ; M3: move $2, $[[T1]] - ; M3: beqz $[[T3]], [[BB1:\.LBB[0-9_]+]] - ; M3: daddiu $3, $zero, 0 - ; M3: [[EXIT:\.LBB[0-9_]+]]: - ; M3: jr $ra - ; M3: nop - ; M3: [[BB0]]: - ; M3: dsllv $[[T4:[0-9]+]], $4, $7 - ; M3: dsrl $[[T5:[0-9]+]], $5, 1 - ; M3: not $[[T6:[0-9]+]], $[[T0]] - ; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]] - ; M3: or $2, $[[T4]], $[[T7]] - ; M3: bnez $[[T3]], [[EXIT]] - ; M3: daddiu $3, $zero, 0 - ; M3: [[BB1]]: - ; M3: jr $ra - ; M3: move $3, $[[T1]] - - ; GP64-NOT-R6: dsllv $[[T0:[0-9]+]], $4, $7 - ; GP64-NOT-R6: dsrl $[[T1:[0-9]+]], $5, 1 - ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 - ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] - ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]] - ; GP64-NOT-R6: or $2, $[[T0]], $[[T4]] - ; GP64-NOT-R6: dsllv $3, $5, $7 - ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64 - ; GP64-NOT-R6: movn $2, $3, $[[T5]] - ; GP64-NOT-R6: jr $ra - ; GP64-NOT-R6: movn $3, $zero, $1 - ; 64R6: dsllv $[[T0:[0-9]+]], $4, $7 - ; 64R6: dsrl $[[T1:[0-9]+]], $5, 1 - ; 64R6: sll $[[T2:[0-9]+]], $7, 0 - ; 64R6: not $[[T3:[0-9]+]], $[[T2]] - ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]] - ; 64R6: or $[[T5:[0-9]+]], $[[T0]], $[[T4]] - ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64 - ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 - ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] - ; 64R6: dsllv $[[T9:[0-9]+]], $5, $7 - ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] - ; 64R6: or $2, $[[T10]], $[[T8]] - ; 64R6: jr $ra - ; 64R6: seleqz $3, $[[T9]], $[[T7]] +; o32 shouldn't use TImode helpers. +; GP32-NOT: lw $25, %call16(__ashlti3)($gp) +; MM-NOT: lw $25, %call16(__ashlti3)($2) %r = shl i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/srem.ll b/test/CodeGen/Mips/llvm-ir/srem.ll index 42664d7457e5a..971b1e00d8a10 100644 --- a/test/CodeGen/Mips/llvm-ir/srem.ll +++ b/test/CodeGen/Mips/llvm-ir/srem.ll @@ -30,8 +30,6 @@ ; RUN: -check-prefixes=ALL,MMR3,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @srem_i1(i1 signext %a, i1 signext %b) { entry: @@ -166,9 +164,6 @@ entry: ; MM32: lw $25, %call16(__moddi3)($2) - ; MM64: dmod $2, $4, $5 - ; MM64: teq $5, $zero, 7 - %r = srem i64 %a, %b ret i64 %r } @@ -184,8 +179,6 @@ entry: ; MM32: lw $25, %call16(__modti3)($16) - ; MM64: ld $25, %call16(__modti3)($2) - %r = srem i128 %a, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/sub.ll b/test/CodeGen/Mips/llvm-ir/sub.ll index 655addb10a64e..d06170f1db15d 100644 --- a/test/CodeGen/Mips/llvm-ir/sub.ll +++ b/test/CodeGen/Mips/llvm-ir/sub.ll @@ -28,8 +28,6 @@ ; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=GP64,MM64 define signext i1 @sub_i1(i1 signext %a, i1 signext %b) { entry: @@ -213,17 +211,6 @@ entry: ; GP64-R2: dsubu $2, $1, $[[T1]] ; GP64-R2: dsubu $3, $5, $7 -; FIXME: Again, redundant sign extension. Also, microMIPSR6 has the -; dext instruction which should be used here. - -; MM64: dsubu $[[T0:[0-9]+]], $4, $6 -; MM64: sltu $[[T1:[0-9]+]], $5, $7 -; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32 -; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32 -; MM64: dsubu $2, $[[T0]], $[[T3]] -; MM64: dsubu $3, $5, $7 -; MM64: jr $ra - %r = sub i128 %a, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/udiv.ll b/test/CodeGen/Mips/llvm-ir/udiv.ll index 78ab36442a9ae..70882a3386954 100644 --- a/test/CodeGen/Mips/llvm-ir/udiv.ll +++ b/test/CodeGen/Mips/llvm-ir/udiv.ll @@ -30,8 +30,6 @@ ; RUN: -check-prefixes=ALL,MMR3,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MMR6,MM64 define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) { entry: @@ -136,9 +134,6 @@ entry: ; MM32: lw $25, %call16(__udivdi3)($2) - ; MM64: ddivu $2, $4, $5 - ; MM64: teq $5, $zero, 7 - %r = udiv i64 %a, %b ret i64 %r } @@ -154,8 +149,6 @@ entry: ; MM32: lw $25, %call16(__udivti3)($16) - ; MM64: ld $25, %call16(__udivti3)($2) - %r = udiv i128 %a, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/urem.ll b/test/CodeGen/Mips/llvm-ir/urem.ll index 160c126c7e3ab..d0ac39d61dcb0 100644 --- a/test/CodeGen/Mips/llvm-ir/urem.ll +++ b/test/CodeGen/Mips/llvm-ir/urem.ll @@ -30,8 +30,6 @@ ; RUN: -check-prefixes=ALL,MMR3,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @urem_i1(i1 signext %a, i1 signext %b) { entry: @@ -192,9 +190,6 @@ entry: ; MM32: lw $25, %call16(__umoddi3)($2) - ; MM64: dmodu $2, $4, $5 - ; MM64: teq $5, $zero, 7 - %r = urem i64 %a, %b ret i64 %r } @@ -210,8 +205,6 @@ entry: ; MM32: lw $25, %call16(__umodti3)($16) - ; MM64: ld $25, %call16(__umodti3)($2) - %r = urem i128 %a, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/xor.ll b/test/CodeGen/Mips/llvm-ir/xor.ll index 1d45e200a2edd..1fb51876608b0 100644 --- a/test/CodeGen/Mips/llvm-ir/xor.ll +++ b/test/CodeGen/Mips/llvm-ir/xor.ll @@ -1,230 +1,664 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM64 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 | FileCheck %s -check-prefix=MIPS +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 | FileCheck %s -check-prefix=MIPS +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=MIPS32R6 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=MIPS64R6 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=MM32R3 +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=MM32R6 define signext i1 @xor_i1(i1 signext %a, i1 signext %b) { +; MIPS-LABEL: xor_i1: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xor $2, $4, $5 +; +; MIPS32R2-LABEL: xor_i1: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xor $2, $4, $5 +; +; MIPS32R6-LABEL: xor_i1: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xor $2, $4, $5 +; +; MIPS64-LABEL: xor_i1: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: xor $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: xor_i1: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: xor $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: xor_i1: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: xor $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: xor_i1: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: xor16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i1: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xor16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i1: - - ; GP32: xor $2, $4, $5 - - ; GP64: xor $2, $4, $5 - - ; MM: xor16 $[[T0:[0-9]+]], $5 - ; MM: move $2, $[[T0]] - %r = xor i1 %a, %b ret i1 %r } define signext i8 @xor_i8(i8 signext %a, i8 signext %b) { +; MIPS-LABEL: xor_i8: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xor $2, $4, $5 +; +; MIPS32R2-LABEL: xor_i8: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xor $2, $4, $5 +; +; MIPS32R6-LABEL: xor_i8: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xor $2, $4, $5 +; +; MIPS64-LABEL: xor_i8: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: xor $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: xor_i8: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: xor $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: xor_i8: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: xor $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: xor_i8: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: xor16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i8: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xor16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i8: - - ; GP32: xor $2, $4, $5 - - ; GP64: xor $2, $4, $5 - - ; MM: xor16 $[[T0:[0-9]+]], $5 - ; MM: move $2, $[[T0]] - %r = xor i8 %a, %b ret i8 %r } define signext i16 @xor_i16(i16 signext %a, i16 signext %b) { +; MIPS-LABEL: xor_i16: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xor $2, $4, $5 +; +; MIPS32R2-LABEL: xor_i16: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xor $2, $4, $5 +; +; MIPS32R6-LABEL: xor_i16: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xor $2, $4, $5 +; +; MIPS64-LABEL: xor_i16: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: xor $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: xor_i16: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: xor $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: xor_i16: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: xor $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: xor_i16: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: xor16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i16: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xor16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i16: - - ; GP32: xor $2, $4, $5 - - ; GP64: xor $2, $4, $5 - - ; MM: xor16 $[[T0:[0-9]+]], $5 - ; MM: move $2, $[[T0]] - %r = xor i16 %a, %b ret i16 %r } define signext i32 @xor_i32(i32 signext %a, i32 signext %b) { +; MIPS-LABEL: xor_i32: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xor $2, $4, $5 +; +; MIPS32R2-LABEL: xor_i32: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xor $2, $4, $5 +; +; MIPS32R6-LABEL: xor_i32: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xor $2, $4, $5 +; +; MIPS64-LABEL: xor_i32: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: xor $1, $4, $5 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $1, 0 +; +; MIPS64R2-LABEL: xor_i32: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: xor $1, $4, $5 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: sll $2, $1, 0 +; +; MIPS64R6-LABEL: xor_i32: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: xor $1, $4, $5 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: sll $2, $1, 0 +; +; MM32R3-LABEL: xor_i32: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: xor16 $4, $5 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i32: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xor16 $4, $5 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i32: - - ; GP32: xor $2, $4, $5 - - ; GP64: xor $[[T0:[0-9]+]], $4, $5 - ; GP64: sll $2, $[[T0]], 0 - - ; MM32: xor16 $[[T0:[0-9]+]], $5 - ; MM32: move $2, $[[T0]] - - ; MM64: xor $[[T0:[0-9]+]], $4, $5 - ; MM64: sll $2, $[[T0]], 0 - %r = xor i32 %a, %b ret i32 %r } define signext i64 @xor_i64(i64 signext %a, i64 signext %b) { +; MIPS-LABEL: xor_i64: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: xor $2, $4, $6 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xor $3, $5, $7 +; +; MIPS32R2-LABEL: xor_i64: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: xor $2, $4, $6 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xor $3, $5, $7 +; +; MIPS32R6-LABEL: xor_i64: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: xor $2, $4, $6 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xor $3, $5, $7 +; +; MIPS64-LABEL: xor_i64: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: xor $2, $4, $5 +; +; MIPS64R2-LABEL: xor_i64: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: xor $2, $4, $5 +; +; MIPS64R6-LABEL: xor_i64: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: xor $2, $4, $5 +; +; MM32R3-LABEL: xor_i64: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: xor16 $4, $6 +; MM32R3-NEXT: xor16 $5, $7 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: move $3, $5 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i64: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xor16 $4, $6 +; MM32R6-NEXT: xor16 $5, $7 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i64: - - ; GP32: xor $2, $4, $6 - ; GP32: xor $3, $5, $7 - - ; GP64: xor $2, $4, $5 - - ; MM32: xor16 $[[T0:[0-9]+]], $6 - ; MM32: xor16 $[[T1:[0-9]+]], $7 - ; MM32: move $2, $[[T0]] - ; MM32: move $3, $[[T1]] - - ; MM64: xor $2, $4, $5 - %r = xor i64 %a, %b ret i64 %r } define signext i128 @xor_i128(i128 signext %a, i128 signext %b) { +; MIPS-LABEL: xor_i128: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: lw $1, 20($sp) +; MIPS-NEXT: lw $2, 16($sp) +; MIPS-NEXT: xor $2, $4, $2 +; MIPS-NEXT: xor $3, $5, $1 +; MIPS-NEXT: lw $1, 24($sp) +; MIPS-NEXT: xor $4, $6, $1 +; MIPS-NEXT: lw $1, 28($sp) +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xor $5, $7, $1 +; +; MIPS32R2-LABEL: xor_i128: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: lw $1, 20($sp) +; MIPS32R2-NEXT: lw $2, 16($sp) +; MIPS32R2-NEXT: xor $2, $4, $2 +; MIPS32R2-NEXT: xor $3, $5, $1 +; MIPS32R2-NEXT: lw $1, 24($sp) +; MIPS32R2-NEXT: xor $4, $6, $1 +; MIPS32R2-NEXT: lw $1, 28($sp) +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xor $5, $7, $1 +; +; MIPS32R6-LABEL: xor_i128: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: lw $1, 20($sp) +; MIPS32R6-NEXT: lw $2, 16($sp) +; MIPS32R6-NEXT: xor $2, $4, $2 +; MIPS32R6-NEXT: xor $3, $5, $1 +; MIPS32R6-NEXT: lw $1, 24($sp) +; MIPS32R6-NEXT: xor $4, $6, $1 +; MIPS32R6-NEXT: lw $1, 28($sp) +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xor $5, $7, $1 +; +; MIPS64-LABEL: xor_i128: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: xor $2, $4, $6 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: xor $3, $5, $7 +; +; MIPS64R2-LABEL: xor_i128: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: xor $2, $4, $6 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: xor $3, $5, $7 +; +; MIPS64R6-LABEL: xor_i128: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: xor $2, $4, $6 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: xor $3, $5, $7 +; +; MM32R3-LABEL: xor_i128: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: lw $3, 20($sp) +; MM32R3-NEXT: lw $2, 16($sp) +; MM32R3-NEXT: xor16 $2, $4 +; MM32R3-NEXT: xor16 $3, $5 +; MM32R3-NEXT: lw $4, 24($sp) +; MM32R3-NEXT: xor16 $4, $6 +; MM32R3-NEXT: lw $5, 28($sp) +; MM32R3-NEXT: xor16 $5, $7 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i128: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: lw $3, 20($sp) +; MM32R6-NEXT: lw $2, 16($sp) +; MM32R6-NEXT: xor16 $2, $4 +; MM32R6-NEXT: xor16 $3, $5 +; MM32R6-NEXT: lw $4, 24($sp) +; MM32R6-NEXT: xor16 $4, $6 +; MM32R6-NEXT: lw $5, 28($sp) +; MM32R6-NEXT: xor16 $5, $7 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i128: - - ; GP32: lw $[[T1:[0-9]+]], 20($sp) - ; GP32: lw $[[T2:[0-9]+]], 16($sp) - ; GP32: xor $2, $4, $[[T2]] - ; GP32: xor $3, $5, $[[T1]] - ; GP32: lw $[[T0:[0-9]+]], 24($sp) - ; GP32: xor $4, $6, $[[T0]] - ; GP32: lw $[[T3:[0-9]+]], 28($sp) - ; GP32: xor $5, $7, $[[T3]] - - ; GP64: xor $2, $4, $6 - ; GP64: xor $3, $5, $7 - - ; MM32: lw $[[T1:[0-9]+]], 20($sp) - ; MM32: lw $[[T2:[0-9]+]], 16($sp) - ; MM32: xor16 $[[T2]], $4 - ; MM32: xor16 $[[T1]], $5 - ; MM32: lw $[[T0:[0-9]+]], 24($sp) - ; MM32: xor16 $[[T0]], $6 - ; MM32: lw $[[T3:[0-9]+]], 28($sp) - ; MM32: xor16 $[[T3]], $7 - - ; MM64: xor $2, $4, $6 - ; MM64: xor $3, $5, $7 - %r = xor i128 %a, %b ret i128 %r } define signext i1 @xor_i1_4(i1 signext %b) { +; MIPS-LABEL: xor_i1_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: xor_i1_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: xor_i1_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS64-LABEL: xor_i1_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: xor_i1_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: xor_i1_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MM32R3-LABEL: xor_i1_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i1_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i1_4: - - ; ALL: move $2, $4 - %r = xor i1 4, %b ret i1 %r } define signext i8 @xor_i8_4(i8 signext %b) { +; MIPS-LABEL: xor_i8_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xori $2, $4, 4 +; +; MIPS32R2-LABEL: xor_i8_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xori $2, $4, 4 +; +; MIPS32R6-LABEL: xor_i8_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xori $2, $4, 4 +; +; MIPS64-LABEL: xor_i8_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: xori $2, $4, 4 +; +; MIPS64R2-LABEL: xor_i8_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: xori $2, $4, 4 +; +; MIPS64R6-LABEL: xor_i8_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: xori $2, $4, 4 +; +; MM32R3-LABEL: xor_i8_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: xori $2, $4, 4 +; +; MM32R6-LABEL: xor_i8_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xori $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i8_4: - - ; ALL: xori $2, $4, 4 - %r = xor i8 4, %b ret i8 %r } define signext i16 @xor_i16_4(i16 signext %b) { +; MIPS-LABEL: xor_i16_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xori $2, $4, 4 +; +; MIPS32R2-LABEL: xor_i16_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xori $2, $4, 4 +; +; MIPS32R6-LABEL: xor_i16_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xori $2, $4, 4 +; +; MIPS64-LABEL: xor_i16_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: xori $2, $4, 4 +; +; MIPS64R2-LABEL: xor_i16_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: xori $2, $4, 4 +; +; MIPS64R6-LABEL: xor_i16_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: xori $2, $4, 4 +; +; MM32R3-LABEL: xor_i16_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: xori $2, $4, 4 +; +; MM32R6-LABEL: xor_i16_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xori $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i16_4: - - ; ALL: xori $2, $4, 4 - %r = xor i16 4, %b ret i16 %r } define signext i32 @xor_i32_4(i32 signext %b) { +; MIPS-LABEL: xor_i32_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: jr $ra +; MIPS-NEXT: xori $2, $4, 4 +; +; MIPS32R2-LABEL: xor_i32_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: xori $2, $4, 4 +; +; MIPS32R6-LABEL: xor_i32_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: xori $2, $4, 4 +; +; MIPS64-LABEL: xor_i32_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: xori $2, $4, 4 +; +; MIPS64R2-LABEL: xor_i32_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: xori $2, $4, 4 +; +; MIPS64R6-LABEL: xor_i32_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: xori $2, $4, 4 +; +; MM32R3-LABEL: xor_i32_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: jr $ra +; MM32R3-NEXT: xori $2, $4, 4 +; +; MM32R6-LABEL: xor_i32_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xori $2, $4, 4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i32_4: - - ; ALL: xori $2, $4, 4 - %r = xor i32 4, %b ret i32 %r } define signext i64 @xor_i64_4(i64 signext %b) { +; MIPS-LABEL: xor_i64_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: xori $3, $5, 4 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $2, $4 +; +; MIPS32R2-LABEL: xor_i64_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: xori $3, $5, 4 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $2, $4 +; +; MIPS32R6-LABEL: xor_i64_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: xori $3, $5, 4 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $2, $4 +; +; MIPS64-LABEL: xor_i64_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: xori $2, $4, 4 +; +; MIPS64R2-LABEL: xor_i64_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: xori $2, $4, 4 +; +; MIPS64R6-LABEL: xor_i64_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: xori $2, $4, 4 +; +; MM32R3-LABEL: xor_i64_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: xori $3, $5, 4 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i64_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xori $3, $5, 4 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i64_4: - - ; GP32: xori $3, $5, 4 - ; GP32: move $2, $4 - - ; GP64: xori $2, $4, 4 - - ; MM32: xori $3, $5, 4 - ; MM32: move $2, $4 - - ; MM64: xori $2, $4, 4 - %r = xor i64 4, %b ret i64 %r } define signext i128 @xor_i128_4(i128 signext %b) { +; MIPS-LABEL: xor_i128_4: +; MIPS: # %bb.0: # %entry +; MIPS-NEXT: xori $1, $7, 4 +; MIPS-NEXT: move $2, $4 +; MIPS-NEXT: move $3, $5 +; MIPS-NEXT: move $4, $6 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $5, $1 +; +; MIPS32R2-LABEL: xor_i128_4: +; MIPS32R2: # %bb.0: # %entry +; MIPS32R2-NEXT: xori $1, $7, 4 +; MIPS32R2-NEXT: move $2, $4 +; MIPS32R2-NEXT: move $3, $5 +; MIPS32R2-NEXT: move $4, $6 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $5, $1 +; +; MIPS32R6-LABEL: xor_i128_4: +; MIPS32R6: # %bb.0: # %entry +; MIPS32R6-NEXT: xori $1, $7, 4 +; MIPS32R6-NEXT: move $2, $4 +; MIPS32R6-NEXT: move $3, $5 +; MIPS32R6-NEXT: move $4, $6 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $5, $1 +; +; MIPS64-LABEL: xor_i128_4: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: xori $3, $5, 4 +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: move $2, $4 +; +; MIPS64R2-LABEL: xor_i128_4: +; MIPS64R2: # %bb.0: # %entry +; MIPS64R2-NEXT: xori $3, $5, 4 +; MIPS64R2-NEXT: jr $ra +; MIPS64R2-NEXT: move $2, $4 +; +; MIPS64R6-LABEL: xor_i128_4: +; MIPS64R6: # %bb.0: # %entry +; MIPS64R6-NEXT: xori $3, $5, 4 +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: move $2, $4 +; +; MM32R3-LABEL: xor_i128_4: +; MM32R3: # %bb.0: # %entry +; MM32R3-NEXT: xori $1, $7, 4 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: move $3, $5 +; MM32R3-NEXT: move $4, $6 +; MM32R3-NEXT: move $5, $1 +; MM32R3-NEXT: jrc $ra +; +; MM32R6-LABEL: xor_i128_4: +; MM32R6: # %bb.0: # %entry +; MM32R6-NEXT: xori $1, $7, 4 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $5 +; MM32R6-NEXT: move $4, $6 +; MM32R6-NEXT: move $5, $1 +; MM32R6-NEXT: jrc $ra entry: -; ALL-LABEL: xor_i128_4: - - ; GP32: xori $[[T0:[0-9]+]], $7, 4 - ; GP32: move $2, $4 - ; GP32: move $3, $5 - ; GP32: move $4, $6 - ; GP32: move $5, $[[T0]] - - ; GP64: xori $3, $5, 4 - ; GP64: move $2, $4 - - ; MM32: xori $[[T0:[0-9]+]], $7, 4 - ; MM32: move $2, $4 - ; MM32: move $3, $5 - ; MM32: move $4, $6 - ; MM32: move $5, $[[T0]] - - ; MM64: xori $3, $5, 4 - ; MM64: move $2, $4 - %r = xor i128 4, %b ret i128 %r } diff --git a/test/CodeGen/Mips/long-call-attr.ll b/test/CodeGen/Mips/long-call-attr.ll new file mode 100644 index 0000000000000..5b6ba94aaa356 --- /dev/null +++ b/test/CodeGen/Mips/long-call-attr.ll @@ -0,0 +1,42 @@ +; RUN: llc -march=mips -target-abi o32 --mattr=+long-calls,+noabicalls < %s \ +; RUN: | FileCheck -check-prefix=O32 %s +; RUN: llc -march=mips -target-abi o32 --mattr=-long-calls,+noabicalls < %s \ +; RUN: | FileCheck -check-prefix=O32 %s +; RUN: llc -march=mips64 -target-abi n64 --mattr=+long-calls,+noabicalls < %s \ +; RUN: | FileCheck -check-prefix=N64 %s +; RUN: llc -march=mips64 -target-abi n64 --mattr=-long-calls,+noabicalls < %s \ +; RUN: | FileCheck -check-prefix=N64 %s + +declare void @far() #0 + +define void @near() #1 { + ret void +} + +define void @foo() { + call void @far() + +; O32-LABEL: foo: +; O32: lui $1, %hi(far) +; O32-NEXT: addiu $25, $1, %lo(far) +; O32-NEXT: jalr $25 + +; N64-LABEL: foo: +; N64: lui $1, %highest(far) +; N64-NEXT: daddiu $1, $1, %higher(far) +; N64-NEXT: dsll $1, $1, 16 +; N64-NEXT: daddiu $1, $1, %hi(far) +; N64-NEXT: dsll $1, $1, 16 +; N64-NEXT: daddiu $25, $1, %lo(far) +; N64-NEXT: jalr $25 + + call void @near() + +; O32: jal near +; N64: jal near + + ret void +} + +attributes #0 = { "long-call" } +attributes #1 = { "short-call" } diff --git a/test/CodeGen/Mips/longbranch.ll b/test/CodeGen/Mips/longbranch.ll index 11bc6d390319d..69eb18978e5dc 100644 --- a/test/CodeGen/Mips/longbranch.ll +++ b/test/CodeGen/Mips/longbranch.ll @@ -1,16 +1,35 @@ -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -force-mips-long-branch -O3 -relocation-model=pic < %s \ -; RUN: | FileCheck %s -check-prefix=O32 -; RUN: llc -march=mipsel -mcpu=mips32r6 -force-mips-long-branch -O3 \ -; RUN: -relocation-model=pic -asm-show-inst < %s | FileCheck %s -check-prefix=O32-R6 -; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \ -; RUN: < %s | FileCheck %s -check-prefix=N64 -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \ -; RUN: < %s | FileCheck %s -check-prefix=N64 -; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -force-mips-long-branch -O3 \ -; RUN: -relocation-model=pic -asm-show-inst < %s | FileCheck %s -check-prefix=N64-R6 -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=micromips \ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; Except for the NACL version which isn't parsed by update_llc_test_checks.py +; RUN: llc -mtriple=mipsel-unknown-linux-gnu -O3 -relocation-model=pic < %s \ +; RUN: | FileCheck %s -check-prefix=NOLONGBRANCH + +; RUN: llc -mtriple=mipsel-unknown-linux-gnu -force-mips-long-branch -O3 -relocation-model=pic < %s \ +; RUN: | FileCheck %s -check-prefix=O32-PIC +; RUN: llc -mtriple=mipsel-unknown-linux-gnu -force-mips-long-branch -O3 -relocation-model=static < %s \ +; RUN: | FileCheck %s -check-prefix=O32-STATIC +; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -force-mips-long-branch -O3 \ +; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=O32-R6-PIC +; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -force-mips-long-branch -O3 \ +; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=O32-R6-STATIC + +; RUN: llc -mtriple=mips64el-unknown-linux-gnu -mcpu=mips4 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \ +; RUN: < %s | FileCheck %s -check-prefix=MIPS4 +; RUN: llc -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \ +; RUN: < %s | FileCheck %s -check-prefix=MIPS64 +; RUN: llc -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r6 -target-abi=n64 -force-mips-long-branch -O3 \ +; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=N64-R6 + +; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r2 -mattr=micromips \ ; RUN: -force-mips-long-branch -O3 -relocation-model=pic < %s | FileCheck %s -check-prefix=MICROMIPS +; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r2 -mattr=micromips \ +; RUN: -force-mips-long-branch -O3 -relocation-model=static < %s | FileCheck %s -check-prefix=MICROMIPSSTATIC + +; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -mattr=micromips \ +; RUN: -force-mips-long-branch -O3 -relocation-model=static < %s | FileCheck %s -check-prefix=MICROMIPSR6STATIC +; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -mattr=micromips \ +; RUN: -force-mips-long-branch -O3 -relocation-model=pic < %s | FileCheck %s -check-prefix=MICROMIPSR6PIC + + ; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 -relocation-model=pic < %s \ ; RUN: | FileCheck %s -check-prefix=NACL @@ -18,6 +37,284 @@ @x = external global i32 define void @test1(i32 signext %s) { +; NOLONGBRANCH-LABEL: test1: +; NOLONGBRANCH: # %bb.0: # %entry +; NOLONGBRANCH-NEXT: lui $2, %hi(_gp_disp) +; NOLONGBRANCH-NEXT: addiu $2, $2, %lo(_gp_disp) +; NOLONGBRANCH-NEXT: beqz $4, $BB0_2 +; NOLONGBRANCH-NEXT: addu $2, $2, $25 +; NOLONGBRANCH-NEXT: # %bb.1: # %then +; NOLONGBRANCH-NEXT: lw $1, %got(x)($2) +; NOLONGBRANCH-NEXT: addiu $2, $zero, 1 +; NOLONGBRANCH-NEXT: sw $2, 0($1) +; NOLONGBRANCH-NEXT: $BB0_2: # %end +; NOLONGBRANCH-NEXT: jr $ra +; NOLONGBRANCH-NEXT: nop +; +; O32-PIC-LABEL: test1: +; O32-PIC: # %bb.0: # %entry +; O32-PIC-NEXT: lui $2, %hi(_gp_disp) +; O32-PIC-NEXT: addiu $2, $2, %lo(_gp_disp) +; O32-PIC-NEXT: bnez $4, $BB0_3 +; O32-PIC-NEXT: addu $2, $2, $25 +; O32-PIC-NEXT: # %bb.1: # %entry +; O32-PIC-NEXT: addiu $sp, $sp, -8 +; O32-PIC-NEXT: sw $ra, 0($sp) +; O32-PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2)) +; O32-PIC-NEXT: bal $BB0_2 +; O32-PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2)) +; O32-PIC-NEXT: $BB0_2: # %entry +; O32-PIC-NEXT: addu $1, $ra, $1 +; O32-PIC-NEXT: lw $ra, 0($sp) +; O32-PIC-NEXT: jr $1 +; O32-PIC-NEXT: addiu $sp, $sp, 8 +; O32-PIC-NEXT: $BB0_3: # %then +; O32-PIC-NEXT: lw $1, %got(x)($2) +; O32-PIC-NEXT: addiu $2, $zero, 1 +; O32-PIC-NEXT: sw $2, 0($1) +; O32-PIC-NEXT: $BB0_4: # %end +; O32-PIC-NEXT: jr $ra +; O32-PIC-NEXT: nop +; +; O32-STATIC-LABEL: test1: +; O32-STATIC: # %bb.0: # %entry +; O32-STATIC-NEXT: bnez $4, $BB0_2 +; O32-STATIC-NEXT: nop +; O32-STATIC-NEXT: # %bb.1: # %entry +; O32-STATIC-NEXT: j $BB0_3 +; O32-STATIC-NEXT: nop +; O32-STATIC-NEXT: $BB0_2: # %then +; O32-STATIC-NEXT: lui $1, %hi(x) +; O32-STATIC-NEXT: addiu $2, $zero, 1 +; O32-STATIC-NEXT: sw $2, %lo(x)($1) +; O32-STATIC-NEXT: $BB0_3: # %end +; O32-STATIC-NEXT: jr $ra +; O32-STATIC-NEXT: nop +; +; O32-R6-PIC-LABEL: test1: +; O32-R6-PIC: # %bb.0: # %entry +; O32-R6-PIC-NEXT: lui $2, %hi(_gp_disp) +; O32-R6-PIC-NEXT: addiu $2, $2, %lo(_gp_disp) +; O32-R6-PIC-NEXT: bnez $4, $BB0_3 +; O32-R6-PIC-NEXT: addu $2, $2, $25 +; O32-R6-PIC-NEXT: # %bb.1: # %entry +; O32-R6-PIC-NEXT: addiu $sp, $sp, -8 +; O32-R6-PIC-NEXT: sw $ra, 0($sp) +; O32-R6-PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2)) +; O32-R6-PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2)) +; O32-R6-PIC-NEXT: balc $BB0_2 +; O32-R6-PIC-NEXT: $BB0_2: # %entry +; O32-R6-PIC-NEXT: addu $1, $ra, $1 +; O32-R6-PIC-NEXT: lw $ra, 0($sp) +; O32-R6-PIC-NEXT: addiu $sp, $sp, 8 +; O32-R6-PIC-NEXT: jrc $1 +; O32-R6-PIC-NEXT: $BB0_3: # %then +; O32-R6-PIC-NEXT: lw $1, %got(x)($2) +; O32-R6-PIC-NEXT: addiu $2, $zero, 1 +; O32-R6-PIC-NEXT: sw $2, 0($1) +; O32-R6-PIC-NEXT: $BB0_4: # %end +; O32-R6-PIC-NEXT: jrc $ra +; +; O32-R6-STATIC-LABEL: test1: +; O32-R6-STATIC: # %bb.0: # %entry +; O32-R6-STATIC-NEXT: bnezc $4, $BB0_2 +; O32-R6-STATIC-NEXT: nop +; O32-R6-STATIC-NEXT: # %bb.1: # %entry +; O32-R6-STATIC-NEXT: bc $BB0_3 +; O32-R6-STATIC-NEXT: $BB0_2: # %then +; O32-R6-STATIC-NEXT: lui $1, %hi(x) +; O32-R6-STATIC-NEXT: addiu $2, $zero, 1 +; O32-R6-STATIC-NEXT: sw $2, %lo(x)($1) +; O32-R6-STATIC-NEXT: $BB0_3: # %end +; O32-R6-STATIC-NEXT: jrc $ra +; +; MIPS4-LABEL: test1: +; MIPS4: # %bb.0: # %entry +; MIPS4-NEXT: lui $1, %hi(%neg(%gp_rel(test1))) +; MIPS4-NEXT: bnez $4, .LBB0_3 +; MIPS4-NEXT: daddu $2, $1, $25 +; MIPS4-NEXT: # %bb.1: # %entry +; MIPS4-NEXT: daddiu $sp, $sp, -16 +; MIPS4-NEXT: sd $ra, 0($sp) +; MIPS4-NEXT: daddiu $1, $zero, %hi(.LBB0_4-.LBB0_2) +; MIPS4-NEXT: dsll $1, $1, 16 +; MIPS4-NEXT: bal .LBB0_2 +; MIPS4-NEXT: daddiu $1, $1, %lo(.LBB0_4-.LBB0_2) +; MIPS4-NEXT: .LBB0_2: # %entry +; MIPS4-NEXT: daddu $1, $ra, $1 +; MIPS4-NEXT: ld $ra, 0($sp) +; MIPS4-NEXT: jr $1 +; MIPS4-NEXT: daddiu $sp, $sp, 16 +; MIPS4-NEXT: .LBB0_3: # %then +; MIPS4-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test1))) +; MIPS4-NEXT: addiu $2, $zero, 1 +; MIPS4-NEXT: ld $1, %got_disp(x)($1) +; MIPS4-NEXT: sw $2, 0($1) +; MIPS4-NEXT: .LBB0_4: # %end +; MIPS4-NEXT: jr $ra +; MIPS4-NEXT: nop +; +; MIPS64-LABEL: test1: +; MIPS64: # %bb.0: # %entry +; MIPS64-NEXT: lui $1, %hi(%neg(%gp_rel(test1))) +; MIPS64-NEXT: bnez $4, .LBB0_3 +; MIPS64-NEXT: daddu $2, $1, $25 +; MIPS64-NEXT: # %bb.1: # %entry +; MIPS64-NEXT: daddiu $sp, $sp, -16 +; MIPS64-NEXT: sd $ra, 0($sp) +; MIPS64-NEXT: daddiu $1, $zero, %hi(.LBB0_4-.LBB0_2) +; MIPS64-NEXT: dsll $1, $1, 16 +; MIPS64-NEXT: bal .LBB0_2 +; MIPS64-NEXT: daddiu $1, $1, %lo(.LBB0_4-.LBB0_2) +; MIPS64-NEXT: .LBB0_2: # %entry +; MIPS64-NEXT: daddu $1, $ra, $1 +; MIPS64-NEXT: ld $ra, 0($sp) +; MIPS64-NEXT: jr $1 +; MIPS64-NEXT: daddiu $sp, $sp, 16 +; MIPS64-NEXT: .LBB0_3: # %then +; MIPS64-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test1))) +; MIPS64-NEXT: addiu $2, $zero, 1 +; MIPS64-NEXT: ld $1, %got_disp(x)($1) +; MIPS64-NEXT: sw $2, 0($1) +; MIPS64-NEXT: .LBB0_4: # %end +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: nop +; +; N64-R6-LABEL: test1: +; N64-R6: # %bb.0: # %entry +; N64-R6-NEXT: lui $1, %hi(%neg(%gp_rel(test1))) +; N64-R6-NEXT: bnez $4, .LBB0_3 +; N64-R6-NEXT: daddu $2, $1, $25 +; N64-R6-NEXT: # %bb.1: # %entry +; N64-R6-NEXT: daddiu $sp, $sp, -16 +; N64-R6-NEXT: sd $ra, 0($sp) +; N64-R6-NEXT: daddiu $1, $zero, %hi(.LBB0_4-.LBB0_2) +; N64-R6-NEXT: dsll $1, $1, 16 +; N64-R6-NEXT: daddiu $1, $1, %lo(.LBB0_4-.LBB0_2) +; N64-R6-NEXT: balc .LBB0_2 +; N64-R6-NEXT: .LBB0_2: # %entry +; N64-R6-NEXT: daddu $1, $ra, $1 +; N64-R6-NEXT: ld $ra, 0($sp) +; N64-R6-NEXT: daddiu $sp, $sp, 16 +; N64-R6-NEXT: jrc $1 +; N64-R6-NEXT: .LBB0_3: # %then +; N64-R6-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test1))) +; N64-R6-NEXT: addiu $2, $zero, 1 +; N64-R6-NEXT: ld $1, %got_disp(x)($1) +; N64-R6-NEXT: sw $2, 0($1) +; N64-R6-NEXT: .LBB0_4: # %end +; N64-R6-NEXT: jrc $ra +; +; MICROMIPS-LABEL: test1: +; MICROMIPS: # %bb.0: # %entry +; MICROMIPS-NEXT: lui $2, %hi(_gp_disp) +; MICROMIPS-NEXT: addiu $2, $2, %lo(_gp_disp) +; MICROMIPS-NEXT: bnez $4, $BB0_3 +; MICROMIPS-NEXT: addu $2, $2, $25 +; MICROMIPS-NEXT: # %bb.1: # %entry +; MICROMIPS-NEXT: addiu $sp, $sp, -8 +; MICROMIPS-NEXT: sw $ra, 0($sp) +; MICROMIPS-NEXT: lui $1, %hi(($BB0_4)-($BB0_2)) +; MICROMIPS-NEXT: bal $BB0_2 +; MICROMIPS-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2)) +; MICROMIPS-NEXT: $BB0_2: # %entry +; MICROMIPS-NEXT: addu $1, $ra, $1 +; MICROMIPS-NEXT: lw $ra, 0($sp) +; MICROMIPS-NEXT: jr $1 +; MICROMIPS-NEXT: addiu $sp, $sp, 8 +; MICROMIPS-NEXT: $BB0_3: # %then +; MICROMIPS-NEXT: lw $2, %got(x)($2) +; MICROMIPS-NEXT: li16 $3, 1 +; MICROMIPS-NEXT: sw16 $3, 0($2) +; MICROMIPS-NEXT: $BB0_4: # %end +; MICROMIPS-NEXT: jrc $ra +; +; MICROMIPSSTATIC-LABEL: test1: +; MICROMIPSSTATIC: # %bb.0: # %entry +; MICROMIPSSTATIC-NEXT: bnezc $4, $BB0_2 +; MICROMIPSSTATIC-NEXT: # %bb.1: # %entry +; MICROMIPSSTATIC-NEXT: j $BB0_4 +; MICROMIPSSTATIC-NEXT: nop +; MICROMIPSSTATIC-NEXT: $BB0_2: # %entry +; MICROMIPSSTATIC-NEXT: j $BB0_3 +; MICROMIPSSTATIC-NEXT: nop +; MICROMIPSSTATIC-NEXT: $BB0_3: # %then +; MICROMIPSSTATIC-NEXT: lui $1, %hi(x) +; MICROMIPSSTATIC-NEXT: li16 $2, 1 +; MICROMIPSSTATIC-NEXT: sw $2, %lo(x)($1) +; MICROMIPSSTATIC-NEXT: $BB0_4: # %end +; MICROMIPSSTATIC-NEXT: jrc $ra +; +; MICROMIPSR6STATIC-LABEL: test1: +; MICROMIPSR6STATIC: # %bb.0: # %entry +; MICROMIPSR6STATIC-NEXT: bnezc $4, $BB0_2 +; MICROMIPSR6STATIC-NEXT: # %bb.1: # %entry +; MICROMIPSR6STATIC-NEXT: bc $BB0_4 +; MICROMIPSR6STATIC-NEXT: $BB0_2: # %entry +; MICROMIPSR6STATIC-NEXT: bc $BB0_3 +; MICROMIPSR6STATIC-NEXT: $BB0_3: # %then +; MICROMIPSR6STATIC-NEXT: lui $1, %hi(x) +; MICROMIPSR6STATIC-NEXT: li16 $2, 1 +; MICROMIPSR6STATIC-NEXT: sw $2, %lo(x)($1) +; MICROMIPSR6STATIC-NEXT: $BB0_4: # %end +; MICROMIPSR6STATIC-NEXT: jrc $ra +; +; MICROMIPSR6PIC-LABEL: test1: +; MICROMIPSR6PIC: # %bb.0: # %entry +; MICROMIPSR6PIC-NEXT: lui $2, %hi(_gp_disp) +; MICROMIPSR6PIC-NEXT: addiu $2, $2, %lo(_gp_disp) +; MICROMIPSR6PIC-NEXT: addu $2, $2, $25 +; MICROMIPSR6PIC-NEXT: bnezc $4, $BB0_3 +; MICROMIPSR6PIC-NEXT: # %bb.1: # %entry +; MICROMIPSR6PIC-NEXT: addiu $sp, $sp, -8 +; MICROMIPSR6PIC-NEXT: sw $ra, 0($sp) +; MICROMIPSR6PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2)) +; MICROMIPSR6PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2)) +; MICROMIPSR6PIC-NEXT: balc $BB0_2 +; MICROMIPSR6PIC-NEXT: $BB0_2: # %entry +; MICROMIPSR6PIC-NEXT: addu $1, $ra, $1 +; MICROMIPSR6PIC-NEXT: lw $ra, 0($sp) +; MICROMIPSR6PIC-NEXT: addiu $sp, $sp, 8 +; MICROMIPSR6PIC-NEXT: jic $1, 0 +; MICROMIPSR6PIC-NEXT: $BB0_3: # %then +; MICROMIPSR6PIC-NEXT: lw $2, %got(x)($2) +; MICROMIPSR6PIC-NEXT: li16 $3, 1 +; MICROMIPSR6PIC-NEXT: sw16 $3, 0($2) +; MICROMIPSR6PIC-NEXT: $BB0_4: # %end +; MICROMIPSR6PIC-NEXT: jrc $ra + +; NACL-LABEL: test1: +; NACL: # %bb.0: +; NACL-NEXT: lui $2, %hi(_gp_disp) +; NACL-NEXT: addiu $2, $2, %lo(_gp_disp) +; NACL-NEXT: bnez $4, $BB0_3 +; NACL-NEXT: addu $2, $2, $25 +; NACL-NEXT: # %bb.1: +; NACL-NEXT: addiu $sp, $sp, -8 +; NACL-NEXT: sw $ra, 0($sp) +; NACL-NEXT: lui $1, %hi(($BB0_4)-($BB0_2)) +; NACL-NEXT: bal $BB0_2 +; NACL-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2)) +; NACL-NEXT: $BB0_2: +; NACL-NEXT: addu $1, $ra, $1 +; NACL-NEXT: lw $ra, 0($sp) +; NACL-NEXT: addiu $sp, $sp, 8 +; NACL-NEXT: jr $1 +; NACL-NEXT: nop +; NACL-NEXT: $BB0_3: +; NACL-NEXT: lw $1, %got(x)($2) +; NACL-NEXT: addiu $2, $zero, 1 +; NACL-NEXT: sw $2, 0($1) +; NACL-NEXT: .p2align 4 +; NACL-NEXT: $BB0_4: +; NACL-NEXT: jr $ra +; NACL-NEXT: nop + + +; Check the NaCl version. Check that sp change is not in the branch delay slot +; of "jr $1" instruction. Check that target of indirect branch "jr $1" is +; bundle aligned. + entry: %cmp = icmp eq i32 %s, 0 br i1 %cmp, label %end, label %then @@ -29,147 +326,4 @@ then: end: ret void - -; First check the normal version (without long branch). beqz jumps to return, -; and fallthrough block stores 1 to global variable. - -; CHECK: lui $[[R0:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[R0]], $[[R0]], %lo(_gp_disp) -; CHECK: beqz $4, $[[BB0:BB[0-9_]+]] -; CHECK: addu $[[GP:[0-9]+]], $[[R0]], $25 -; CHECK: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) -; CHECK: addiu $[[R2:[0-9]+]], $zero, 1 -; CHECK: sw $[[R2]], 0($[[R1]]) -; CHECK: $[[BB0]]: -; CHECK: jr $ra -; CHECK: nop - - -; Check the MIPS32 version. Check that branch logic is inverted, so that the -; target of the new branch (bnez) is the fallthrough block of the original -; branch. Check that fallthrough block of the new branch contains long branch -; expansion which at the end indirectly jumps to the target of the original -; branch. - -; O32: lui $[[R0:[0-9]+]], %hi(_gp_disp) -; O32: addiu $[[R0]], $[[R0]], %lo(_gp_disp) -; O32: bnez $4, $[[BB0:BB[0-9_]+]] -; O32: addu $[[GP:[0-9]+]], $[[R0]], $25 - -; Check for long branch expansion: -; O32: addiu $sp, $sp, -8 -; O32-NEXT: sw $ra, 0($sp) -; O32-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) -; O32-NEXT: bal $[[BB1]] -; O32-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) -; O32-NEXT: $[[BB1]]: -; O32-NEXT: addu $1, $ra, $1 -; O32-NEXT: lw $ra, 0($sp) -; O32-NEXT: jr $1 -; O32-NEXT: addiu $sp, $sp, 8 - -; O32: $[[BB0]]: -; O32: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) -; O32: addiu $[[R2:[0-9]+]], $zero, 1 -; O32: sw $[[R2]], 0($[[R1]]) -; O32: $[[BB2]]: -; O32: jr $ra -; O32: nop - -; In MIPS32R6 JR is an alias to JALR with $rd=0. As everything else remains the -; same with the O32 prefix, we use -asm-show-inst in order to make sure that -; the opcode of the MachineInst is a JALR. -; O32-R6: JALR - -; Check the MIPS64 version. - -; N64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test1))) -; N64: bnez $4, [[BB0:\.LBB[0-9_]+]] -; N64: daddu $[[R1:[0-9]+]], $[[R0]], $25 - -; Check for long branch expansion: -; N64: daddiu $sp, $sp, -16 -; N64-NEXT: sd $ra, 0($sp) -; N64-NEXT: daddiu $1, $zero, %hi([[BB2:\.LBB[0-9_]+]]-[[BB1:\.LBB[0-9_]+]]) -; N64-NEXT: dsll $1, $1, 16 -; N64-NEXT: bal [[BB1]] -; N64-NEXT: daddiu $1, $1, %lo([[BB2]]-[[BB1]]) -; N64-NEXT: [[BB1]]: -; N64-NEXT: daddu $1, $ra, $1 -; N64-NEXT: ld $ra, 0($sp) -; N64-NEXT: jr $1 -; N64-NEXT: daddiu $sp, $sp, 16 - -; N64: [[BB0]]: -; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1))) -; N64: addiu $[[R3:[0-9]+]], $zero, 1 -; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]]) -; N64: sw $[[R3]], 0($[[R2]]) -; N64: [[BB2]]: -; N64: jr $ra -; N64: nop - -; In MIPS64R6 JR is an alias to JALR with $rd=0. As everything else remains the -; same with the N64 prefix, we use -asm-show-inst in order to make sure that -; the opcode of the MachineInst is a JALR. -; N64-R6: JALR64 - - -; Check the microMIPS version. - -; MICROMIPS: lui $[[R0:[0-9]+]], %hi(_gp_disp) -; MICROMIPS: addiu $[[R0]], $[[R0]], %lo(_gp_disp) -; MICROMIPS: bnez $4, $[[BB0:BB[0-9_]+]] -; MICROMIPS: addu $[[GP:[0-9]+]], $[[R0]], $25 - -; Check for long branch expansion: -; MICROMIPS: addiu $sp, $sp, -8 -; MICROMIPS-NEXT: sw $ra, 0($sp) -; MICROMIPS-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) -; MICROMIPS-NEXT: bal $[[BB1]] -; MICROMIPS-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) -; MICROMIPS-NEXT: $[[BB1]]: -; MICROMIPS-NEXT: addu $1, $ra, $1 -; MICROMIPS-NEXT: lw $ra, 0($sp) -; MICROMIPS-NEXT: jr $1 -; MICROMIPS-NEXT: addiu $sp, $sp, 8 - -; MICROMIPS: $[[BB0]]: -; MICROMIPS: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) -; MICROMIPS: li16 $[[R2:[0-9]+]], 1 -; MICROMIPS: sw16 $[[R2]], 0($[[R1]]) -; MICROMIPS: $[[BB2]]: -; MICROMIPS: jrc $ra - - -; Check the NaCl version. Check that sp change is not in the branch delay slot -; of "jr $1" instruction. Check that target of indirect branch "jr $1" is -; bundle aligned. - -; NACL: lui $[[R0:[0-9]+]], %hi(_gp_disp) -; NACL: addiu $[[R0]], $[[R0]], %lo(_gp_disp) -; NACL: bnez $4, $[[BB0:BB[0-9_]+]] -; NACL: addu $[[GP:[0-9]+]], $[[R0]], $25 - -; Check for long branch expansion: -; NACL: addiu $sp, $sp, -8 -; NACL-NEXT: sw $ra, 0($sp) -; NACL-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) -; NACL-NEXT: bal $[[BB1]] -; NACL-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) -; NACL-NEXT: $[[BB1]]: -; NACL-NEXT: addu $1, $ra, $1 -; NACL-NEXT: lw $ra, 0($sp) -; NACL-NEXT: addiu $sp, $sp, 8 -; NACL-NEXT: jr $1 -; NACL-NEXT: nop - -; NACL: $[[BB0]]: -; NACL: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) -; NACL: addiu $[[R2:[0-9]+]], $zero, 1 -; NACL: sw $[[R2]], 0($[[R1]]) -; NACL: .p2align 4 -; NACL-NEXT: $[[BB2]]: -; NACL: jr $ra -; NACL: nop } diff --git a/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll b/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll new file mode 100644 index 0000000000000..709cd477a778e --- /dev/null +++ b/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll @@ -0,0 +1,154 @@ +; RUN: llc < %s -march=mips -mcpu=mips32r6 -force-mips-long-branch | FileCheck %s + +; Check that when MIPS32R6 with the static relocation model with the usage of +; long branches, that there is a nop between any compact branch and the static +; relocation method of expanding branches. Previously, it could result in 'j' +; following a b(ne|eq)zc, which would raise a reserved instruction exception. + +declare i32 @f(i32) + +declare i32 @g() + +; CHECK-LABEL: test1: +; CHECK: bnezc +; CHECK-NEXT: nop + +define i32 @test1(i32 %a) { +entry: + %0 = icmp eq i32 %a, 0 + br i1 %0, label %cond.true, label %cond.false +cond.true: + %1 = call i32 @f(i32 %a) + ret i32 %1 +cond.false: + %2 = call i32 @g() + ret i32 %2 +} + +; CHECK-LABEL: test2: +; CHECK: bgezc +; CHECK-NEXT: nop + +define i32 @test2(i32 %a) { +entry: + %0 = icmp sge i32 %a, 0 + br i1 %0, label %cond.true, label %cond.false +cond.true: + %1 = call i32 @f(i32 %a) + ret i32 %1 +cond.false: + %2 = call i32 @g() + ret i32 %2 +} + +; CHECK-LABEL: test3: +; CHECK: blezc +; CHECK-NEXT: nop + +define i32 @test3(i32 %a) { +entry: + %0 = icmp sle i32 %a, 0 + br i1 %0, label %cond.true, label %cond.false +cond.true: + %1 = call i32 @f(i32 %a) + ret i32 %1 +cond.false: + %2 = call i32 @g() + ret i32 %2 +} + +; CHECK-LABEL: test4: +; CHECK: bgtzc +; CHECK-NEXT: nop + +define i32 @test4(i32 %a) { +entry: + %0 = icmp sgt i32 %a, 0 + br i1 %0, label %cond.true, label %cond.false +cond.true: + %1 = call i32 @f(i32 %a) + ret i32 %1 +cond.false: + %2 = call i32 @g() + ret i32 %2 +} + +; CHECK-LABEL: test5: +; CHECK: bgezc +; CHECK-NEXT: nop + +define i32 @test5(i32 %a) { +entry: + %0 = icmp slt i32 %a, 0 + br i1 %0, label %cond.true, label %cond.false +cond.true: + %1 = call i32 @f(i32 %a) + ret i32 %1 +cond.false: + %2 = call i32 @g() + ret i32 %2 +} + +; CHECK-LABEL: test6: +; CHECK: bnezc +; CHECK-NEXT: nop + +define i32 @test6(i32 %a, i32 %b) { +entry: + %0 = icmp ugt i32 %a, %b + br i1 %0, label %cond.true, label %cond.false +cond.true: + %1 = call i32 @f(i32 %a) + ret i32 %1 +cond.false: + %2 = call i32 @g() + ret i32 %2 +} + +; CHECK-LABEL: test7: +; CHECK: beqzc +; CHECK-NEXT: nop + +define i32 @test7(i32 %a, i32 %b) { +entry: + %0 = icmp uge i32 %a, %b + br i1 %0, label %cond.true, label %cond.false +cond.true: + %1 = call i32 @f(i32 %a) + ret i32 %1 +cond.false: + %2 = call i32 @g() + ret i32 %2 +} + +; CHECK-LABEL: test8: +; CHECK: bnezc +; CHECK-NEXT: nop + +define i32 @test8(i32 %a, i32 %b) { +entry: + %0 = icmp ult i32 %a, %b + br i1 %0, label %cond.true, label %cond.false +cond.true: + %1 = call i32 @f(i32 %a) + ret i32 %1 +cond.false: + %2 = call i32 @g() + ret i32 %2 +} + +; CHECK-LABEL: test9: +; CHECK: beqzc +; CHECK-NEXT: nop + +define i32 @test9(i32 %a, i32 %b) { +entry: + %0 = icmp ule i32 %a, %b + br i1 %0, label %cond.true, label %cond.false +cond.true: + %1 = call i32 @f(i32 %a) + ret i32 %1 +cond.false: + %2 = call i32 @g() + ret i32 %2 +} diff --git a/test/CodeGen/Mips/lw16-base-reg.ll b/test/CodeGen/Mips/lw16-base-reg.ll index 09150421a9605..9eeb5d2113535 100644 --- a/test/CodeGen/Mips/lw16-base-reg.ll +++ b/test/CodeGen/Mips/lw16-base-reg.ll @@ -1,7 +1,5 @@ ; RUN: llc %s -march=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \ ; RUN: -relocation-model=pic -O3 -o - | FileCheck %s -; RUN: llc %s -march=mips64 -mcpu=mips64r6 -mattr=micromips -filetype=asm \ -; RUN: -relocation-model=pic -O3 -o - | FileCheck %s ; The purpose of this test is to check whether the CodeGen selects ; LW16 instruction with the base register in a range of $2-$7, $16, $17. diff --git a/test/CodeGen/Mips/micromips-ase-function-attribute.ll b/test/CodeGen/Mips/micromips-ase-function-attribute.ll new file mode 100644 index 0000000000000..bbb6ff56ea9e4 --- /dev/null +++ b/test/CodeGen/Mips/micromips-ase-function-attribute.ll @@ -0,0 +1,11 @@ +; RUN: llc -mtriple=mips-unknown-linux -filetype=obj %s -o - | \ +; RUN: llvm-readobj -mips-abi-flags | \ +; RUN: FileCheck --check-prefix=ASE-MICROMIPS %s + +define void @_Z3foov() #0 { +entry: + ret void +} +attributes #0 = { "micromips" } + +; ASE-MICROMIPS: microMIPS (0x800) diff --git a/test/CodeGen/Mips/micromips-lwc1-swc1.ll b/test/CodeGen/Mips/micromips-lwc1-swc1.ll index a1a10a5de259e..b08ea6bfbff1e 100644 --- a/test/CodeGen/Mips/micromips-lwc1-swc1.ll +++ b/test/CodeGen/Mips/micromips-lwc1-swc1.ll @@ -4,9 +4,6 @@ ; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips \ ; RUN: -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,MM32 -; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 \ -; RUN: -relocation-model=pic < %s | \ -; RUN: FileCheck %s -check-prefixes=ALL,MM64 @gf0 = external global float @@ -19,12 +16,6 @@ entry: ; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]]) ; MM32: lwc1 $f0, 0($[[R3]]) -; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_lwc1))) -; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25 -; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_lwc1))) -; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]]) -; MM64: lwc1 $f0, 0($[[R3]]) - %0 = load float, float* @gf0, align 4 ret float %0 } @@ -38,12 +29,6 @@ entry: ; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]]) ; MM32: swc1 $f12, 0($[[R3]]) -; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_swc1))) -; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25 -; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_swc1))) -; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]]) -; MM64: swc1 $f12, 0($[[R3]]) - store float %a, float* @gf0, align 4 ret void } diff --git a/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll b/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll new file mode 100644 index 0000000000000..c7e96da379aa3 --- /dev/null +++ b/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s + +define i32 @f1() { +entry: +; CHECK-LABEL: f1: +; CHECK: addiusp +; CHECK: addiur1sp +; CHECK: addiusp + %a = alloca [10 x i32], align 4 + %index = getelementptr inbounds [10 x i32], [10 x i32]* %a, i32 0, i32 0 + call void @init(i32* %index) + %0 = load i32, i32* %index, align 4 + ret i32 %0 +} + +declare void @init(i32*) + diff --git a/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll b/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll new file mode 100644 index 0000000000000..e953df62bf2ad --- /dev/null +++ b/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll @@ -0,0 +1,14 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s + +; Function Attrs: nounwind readnone +define i1 @fun(i32 %a, i32 %b) { +entry: +; CHECK-LABEL: fun: +; CHECK: xor16 + %reg1 = or i32 %a, %b + %reg2 = xor i32 %reg1, -1 + %bool1 = icmp ne i32 %a, -1 + %bool1.ext = zext i1 %bool1 to i32 + %bool2 = icmp eq i32 %bool1.ext, %reg2 + ret i1 %bool2 +} diff --git a/test/CodeGen/Mips/micromips64r6-unsupported.ll b/test/CodeGen/Mips/micromips64r6-unsupported.ll new file mode 100644 index 0000000000000..6c3cd1be3e47b --- /dev/null +++ b/test/CodeGen/Mips/micromips64r6-unsupported.ll @@ -0,0 +1,5 @@ +; RUN: not llc -mtriple=mips64-unknown-linux -mcpu=mips64r6 -mattr=+micromips %s 2>&1 | FileCheck %s + +; Test that microMIPS64R6 is not supported. + +; CHECK: LLVM ERROR: microMIPS64R6 is not supported diff --git a/test/CodeGen/Mips/mips64-f128.ll b/test/CodeGen/Mips/mips64-f128.ll index aa73c522eda54..33a65070c7fe6 100644 --- a/test/CodeGen/Mips/mips64-f128.ll +++ b/test/CodeGen/Mips/mips64-f128.ll @@ -425,7 +425,7 @@ declare fp128 @llvm.powi.f128(fp128, i32) #3 ; NOT-R2R6-DAG: and $[[R4:[0-9]+]], $[[R1]], $[[R3]] ; ALL-DAG: ld $[[R5:[0-9]+]], %got_disp(gld0) ; ALL-DAG: ld $[[R6:[0-9]+]], 8($[[R5]]) -; R2R6: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 63, 1 +; R2R6: dinsu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 63, 1 ; NOT-R2R6-DAG: daddiu $[[R7:[0-9]+]], $[[R3]], -1 ; NOT-R2R6-DAG: and $[[R8:[0-9]+]], $[[R6]], $[[R7]] ; NOT-R2R6-DAG: or $4, $[[R8]], $[[R4]] diff --git a/test/CodeGen/Mips/mips64extins.ll b/test/CodeGen/Mips/mips64extins.ll index 7876266fb856a..f160603c2507e 100644 --- a/test/CodeGen/Mips/mips64extins.ll +++ b/test/CodeGen/Mips/mips64extins.ll @@ -41,7 +41,7 @@ entry: define i64 @dinsm(i64 %i, i64 %j) nounwind readnone { entry: ; CHECK-LABEL: dinsm: -; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 10, 33 +; CHECK: dinsm ${{[0-9]+}}, ${{[0-9]+}}, 10, 33 %shl4 = shl i64 %j, 10 %and = and i64 %shl4, 8796093021184 %and5 = and i64 %i, -8796093021185 @@ -52,7 +52,7 @@ entry: define i64 @dinsu(i64 %i, i64 %j) nounwind readnone { entry: ; CHECK-LABEL: dinsu: -; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13 +; CHECK: dinsu ${{[0-9]+}}, ${{[0-9]+}}, 40, 13 %shl4 = shl i64 %j, 40 %and = and i64 %shl4, 9006099743113216 %and5 = and i64 %i, -9006099743113217 diff --git a/test/CodeGen/Mips/mips64fpldst.ll b/test/CodeGen/Mips/mips64fpldst.ll index 564ffdd2f691b..c439b4ba62334 100644 --- a/test/CodeGen/Mips/mips64fpldst.ll +++ b/test/CodeGen/Mips/mips64fpldst.ll @@ -2,8 +2,6 @@ ; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 ; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 ; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 -; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 -; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 @f0 = common global float 0.000000e+00, align 4 @d0 = common global double 0.000000e+00, align 8 diff --git a/test/CodeGen/Mips/mips64shift.ll b/test/CodeGen/Mips/mips64shift.ll index e93140f18c9ba..0b1294d3afb85 100644 --- a/test/CodeGen/Mips/mips64shift.ll +++ b/test/CodeGen/Mips/mips64shift.ll @@ -1,5 +1,4 @@ ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS %s -; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS %s define i64 @f0(i64 %a0, i64 %a1) nounwind readnone { entry: diff --git a/test/CodeGen/Mips/mips64signextendsesf.ll b/test/CodeGen/Mips/mips64signextendsesf.ll index d0ce1b86bf561..2ee1e09f50029 100644 --- a/test/CodeGen/Mips/mips64signextendsesf.ll +++ b/test/CodeGen/Mips/mips64signextendsesf.ll @@ -211,4 +211,4 @@ declare float @fminf(float, float) #1 attributes #0 = { nounwind "use-soft-float"="true" } -attributes #1 = { nounwind readnone "use-soft-float"="true" }
\ No newline at end of file +attributes #1 = { nounwind readnone "use-soft-float"="true" } diff --git a/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir b/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir new file mode 100644 index 0000000000000..05923377ec6f9 --- /dev/null +++ b/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir @@ -0,0 +1,275 @@ +# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \ +# RUN: -stop-after=expand-isel-pseudos -relocation-model=pic -mxgot \ +# RUN: -o /dev/null %s + +# A simple test to show that we can parse the target specific flags: gpoff-hi, +# gpoff-lo, tlsgd, tlsldm, dtprel-hi, dtprel-lo, got-hi, got-lo, call-hi, +# call-lo. + +--- | + @v = global i32 0, align 4 + @k = thread_local global i32 0, align 4 + @j = external thread_local global i32, align 4 + @__tls_guard = internal thread_local global i1 false, align 1 + declare extern_weak void @_ZTH1j() + + declare i32 @_Z1gi(i32 signext) + + define i32 @_Z2k1i(i32 signext %asd) { + entry: + %call = tail call i32 @_Z1gi(i32 signext %asd) + %add = add nsw i32 %call, %asd + %0 = load i32, i32* @v, align 4 + %add1 = add nsw i32 %add, %0 + %.b.i.i = load i1, i1* @__tls_guard, align 1 + br i1 %.b.i.i, label %entry._ZTW1k.exit_crit_edge, label %init.i.i + + entry._ZTW1k.exit_crit_edge: + %.pre = load i32, i32* @k, align 4 + br label %_ZTW1k.exit + + init.i.i: + store i1 true, i1* @__tls_guard, align 1 + %call.i.i.i = tail call i32 @_Z1gi(i32 signext 3) + store i32 %call.i.i.i, i32* @k, align 4 + br label %_ZTW1k.exit + + _ZTW1k.exit: + %1 = phi i32 [ %.pre, %entry._ZTW1k.exit_crit_edge ], [ %call.i.i.i, %init.i.i ] + %add2 = add nsw i32 %add1, %1 + br i1 icmp ne (void ()* @_ZTH1j, void ()* null), label %2, label %_ZTW1j.exit + + ; <label>:2: + tail call void @_ZTH1j() + br label %_ZTW1j.exit + + _ZTW1j.exit: + %3 = load i32, i32* @j, align 4 + %add3 = add nsw i32 %add2, %3 + ret i32 %add3 + } +... +--- +name: _Z2k1i +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } + - { id: 2, class: gpr32, preferred-register: '' } + - { id: 3, class: gpr32, preferred-register: '' } + - { id: 4, class: gpr32, preferred-register: '' } + - { id: 5, class: gpr64, preferred-register: '' } + - { id: 6, class: gpr64, preferred-register: '' } + - { id: 7, class: gpr64, preferred-register: '' } + - { id: 8, class: gpr64, preferred-register: '' } + - { id: 9, class: gpr64, preferred-register: '' } + - { id: 10, class: gpr32, preferred-register: '' } + - { id: 11, class: gpr32, preferred-register: '' } + - { id: 12, class: gpr32, preferred-register: '' } + - { id: 13, class: gpr64, preferred-register: '' } + - { id: 14, class: gpr64, preferred-register: '' } + - { id: 15, class: gpr64, preferred-register: '' } + - { id: 16, class: gpr32, preferred-register: '' } + - { id: 17, class: gpr64, preferred-register: '' } + - { id: 18, class: gpr64, preferred-register: '' } + - { id: 19, class: gpr64, preferred-register: '' } + - { id: 20, class: gpr64, preferred-register: '' } + - { id: 21, class: gpr64, preferred-register: '' } + - { id: 22, class: gpr64, preferred-register: '' } + - { id: 23, class: gpr32, preferred-register: '' } + - { id: 24, class: gpr64, preferred-register: '' } + - { id: 25, class: gpr64, preferred-register: '' } + - { id: 26, class: gpr64, preferred-register: '' } + - { id: 27, class: gpr64, preferred-register: '' } + - { id: 28, class: gpr64, preferred-register: '' } + - { id: 29, class: gpr64, preferred-register: '' } + - { id: 30, class: gpr32, preferred-register: '' } + - { id: 31, class: gpr64, preferred-register: '' } + - { id: 32, class: gpr64, preferred-register: '' } + - { id: 33, class: gpr64, preferred-register: '' } + - { id: 34, class: gpr64, preferred-register: '' } + - { id: 35, class: gpr32, preferred-register: '' } + - { id: 36, class: gpr64, preferred-register: '' } + - { id: 37, class: gpr64, preferred-register: '' } + - { id: 38, class: gpr64, preferred-register: '' } + - { id: 39, class: gpr64, preferred-register: '' } + - { id: 40, class: gpr64, preferred-register: '' } + - { id: 41, class: gpr64, preferred-register: '' } + - { id: 42, class: gpr64, preferred-register: '' } + - { id: 43, class: gpr64, preferred-register: '' } + - { id: 44, class: gpr64, preferred-register: '' } + - { id: 45, class: gpr64, preferred-register: '' } + - { id: 46, class: gpr64, preferred-register: '' } + - { id: 47, class: gpr64, preferred-register: '' } + - { id: 48, class: gpr64, preferred-register: '' } + - { id: 49, class: gpr64, preferred-register: '' } + - { id: 50, class: gpr64, preferred-register: '' } + - { id: 51, class: gpr64, preferred-register: '' } + - { id: 52, class: gpr64, preferred-register: '' } + - { id: 53, class: gpr64, preferred-register: '' } + - { id: 54, class: gpr64, preferred-register: '' } + - { id: 55, class: gpr32, preferred-register: '' } + - { id: 56, class: gpr32, preferred-register: '' } + - { id: 57, class: gpr64, preferred-register: '' } + - { id: 58, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%5' } + - { reg: '%t9_64', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: true + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + successors: %bb.1.entry._ZTW1k.exit_crit_edge(0x7fe00000), %bb.2.init.i.i(0x00200000) + liveins: %a0_64, %t9_64 + + %57 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i + %58 = DADDu %57, %t9_64 + %6 = DADDiu %58, target-flags(mips-gpoff-lo) @_Z2k1i + %5 = COPY %a0_64 + ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp + %7 = LUi64 target-flags(mips-call-hi16) @_Z1gi + %8 = DADDu killed %7, %6 + %9 = LD killed %8, target-flags(mips-call-lo16) @_Z1gi :: (load 8 from call-entry @_Z1gi) + %a0_64 = COPY %5 + %gp_64 = COPY %6 + JALR64Pseudo killed %9, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0 + ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp + %10 = COPY %v0 + %11 = COPY %5.sub_32 + %12 = ADDu %10, killed %11 + %13 = LUi64 target-flags(mips-got-hi16) @v + %14 = DADDu killed %13, %6 + %15 = LD killed %14, target-flags(mips-got-lo16) @v :: (load 8 from got) + %16 = LW killed %15, 0 :: (dereferenceable load 4 from @v) + %0 = ADDu killed %12, killed %16 + ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp + %17 = LUi64 target-flags(mips-call-hi16) $__tls_get_addr + %18 = DADDu killed %17, %6 + %19 = LD killed %18, target-flags(mips-call-lo16) $__tls_get_addr :: (load 8 from call-entry $__tls_get_addr) + %20 = DADDiu %6, target-flags(mips-tlsldm) @__tls_guard + %a0_64 = COPY %20 + %gp_64 = COPY %6 + JALR64Pseudo killed %19, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64 + ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp + %21 = COPY %v0_64 + %22 = DADDiu %21, target-flags(mips-dtprel-hi) @__tls_guard + %23 = LBu killed %22, target-flags(mips-dtprel-lo) @__tls_guard :: (dereferenceable load 1 from @__tls_guard) + BEQ killed %23, %zero, %bb.2.init.i.i, implicit-def dead %at + B %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead %at + + bb.1.entry._ZTW1k.exit_crit_edge: + successors: %bb.3._ZTW1k.exit(0x80000000) + + ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp + %39 = LUi64 target-flags(mips-call-hi16) $__tls_get_addr + %40 = DADDu killed %39, %6 + %41 = LD killed %40, target-flags(mips-call-lo16) $__tls_get_addr :: (load 8 from call-entry $__tls_get_addr) + %42 = DADDiu %6, target-flags(mips-tlsgd) @k + %a0_64 = COPY %42 + %gp_64 = COPY %6 + JALR64Pseudo killed %41, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64 + ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp + %43 = COPY %v0_64 + %1 = LW %43, 0 :: (dereferenceable load 4 from @k) + B %bb.3._ZTW1k.exit, implicit-def dead %at + + bb.2.init.i.i: + successors: %bb.3._ZTW1k.exit(0x80000000) + + ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp + %24 = LUi64 target-flags(mips-call-hi16) $__tls_get_addr + %25 = DADDu killed %24, %6 + %26 = LD %25, target-flags(mips-call-lo16) $__tls_get_addr :: (load 8 from call-entry $__tls_get_addr) + %27 = DADDiu %6, target-flags(mips-tlsldm) @__tls_guard + %a0_64 = COPY %27 + %gp_64 = COPY %6 + JALR64Pseudo killed %26, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64 + ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp + %28 = COPY %v0_64 + %29 = DADDiu %28, target-flags(mips-dtprel-hi) @__tls_guard + %30 = ADDiu %zero, 1 + SB killed %30, killed %29, target-flags(mips-dtprel-lo) @__tls_guard :: (store 1 into @__tls_guard) + ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp + %31 = LUi64 target-flags(mips-call-hi16) @_Z1gi + %32 = DADDu killed %31, %6 + %33 = DADDiu %zero_64, 3 + %34 = LD killed %32, target-flags(mips-call-lo16) @_Z1gi :: (load 8 from call-entry @_Z1gi) + %a0_64 = COPY %33 + %gp_64 = COPY %6 + JALR64Pseudo killed %34, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0 + ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp + %35 = COPY %v0 + ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp + %36 = LD %25, target-flags(mips-call-lo16) $__tls_get_addr :: (load 8 from call-entry $__tls_get_addr) + %37 = DADDiu %6, target-flags(mips-tlsgd) @k + %a0_64 = COPY %37 + %gp_64 = COPY %6 + JALR64Pseudo killed %36, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64 + ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp + %38 = COPY %v0_64 + SW %35, %38, 0 :: (store 4 into @k) + %2 = COPY %35 + + bb.3._ZTW1k.exit: + successors: %bb.4(0x40000000), %bb.5._ZTW1j.exit(0x40000000) + + %3 = PHI %2, %bb.2.init.i.i, %1, %bb.1.entry._ZTW1k.exit_crit_edge + %4 = ADDu %0, %3 + %44 = LUi64 target-flags(mips-got-hi16) @_ZTH1j + %45 = DADDu killed %44, %6 + %46 = LD killed %45, target-flags(mips-got-lo16) @_ZTH1j :: (load 8 from got) + BEQ64 killed %46, %zero_64, %bb.5._ZTW1j.exit, implicit-def dead %at + B %bb.4, implicit-def dead %at + + bb.4 (%ir-block.2): + successors: %bb.5._ZTW1j.exit(0x80000000) + + ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp + %47 = LUi64 target-flags(mips-call-hi16) @_ZTH1j + %48 = DADDu killed %47, %6 + %49 = LD killed %48, target-flags(mips-call-lo16) @_ZTH1j :: (load 8 from call-entry @_ZTH1j) + %gp_64 = COPY %6 + JALR64Pseudo killed %49, csr_n64, implicit-def dead %ra, implicit %gp_64, implicit-def %sp + ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp + + bb.5._ZTW1j.exit: + ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp + %50 = LUi64 target-flags(mips-call-hi16) $__tls_get_addr + %51 = DADDu killed %50, %6 + %52 = LD killed %51, target-flags(mips-call-lo16) $__tls_get_addr :: (load 8 from call-entry $__tls_get_addr) + %53 = DADDiu %6, target-flags(mips-tlsgd) @j + %a0_64 = COPY %53 + %gp_64 = COPY %6 + JALR64Pseudo killed %52, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64 + ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp + %54 = COPY %v0_64 + %55 = LW %54, 0 :: (dereferenceable load 4 from @j) + %56 = ADDu %4, killed %55 + %v0 = COPY %56 + RetRA implicit %v0 + +... + diff --git a/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir b/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir new file mode 100644 index 0000000000000..55e520fe03b90 --- /dev/null +++ b/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir @@ -0,0 +1,95 @@ +# RUN: llc -march=mips -start-before=expand-isel-pseudos \ +# RUN: -stop-after=expand-isel-pseudos -relocation-model=pic \ +# RUN: -o /dev/null %s + +# A simple test to show that we can parse the target specific flags: got-call, +# got. + +--- | + @v = global i32 0, align 4 + @j = external global i32, align 4 + + define i32 @_Z2k1i(i32 signext %asd) { + entry: + %call = tail call i32 @_Z1gi(i32 signext %asd) + %add = add nsw i32 %call, %asd + %0 = load i32, i32* @v, align 4 + %add1 = add nsw i32 %add, %0 + %1 = load i32, i32* @j, align 4 + %add2 = add nsw i32 %add1, %1 + ret i32 %add2 + } + + declare i32 @_Z1gi(i32 signext) +... +--- +name: _Z2k1i +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } + - { id: 2, class: gpr32, preferred-register: '' } + - { id: 3, class: gpr32, preferred-register: '' } + - { id: 4, class: gpr32, preferred-register: '' } + - { id: 5, class: gpr32, preferred-register: '' } + - { id: 6, class: gpr32, preferred-register: '' } + - { id: 7, class: gpr32, preferred-register: '' } + - { id: 8, class: gpr32, preferred-register: '' } + - { id: 9, class: gpr32, preferred-register: '' } + - { id: 10, class: gpr32, preferred-register: '' } + - { id: 11, class: gpr32, preferred-register: '' } + - { id: 12, class: gpr32, preferred-register: '' } +liveins: + - { reg: '%a0', virtual-reg: '%0' } + - { reg: '%t9', virtual-reg: '' } + - { reg: '%v0', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: true + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0, %t9, %v0 + + %1 = ADDu %v0, %t9 + %0 = COPY %a0 + ADJCALLSTACKDOWN 16, 0, implicit-def dead %sp, implicit %sp + %2 = LW %1, target-flags(mips-got-call) @_Z1gi :: (load 4 from call-entry @_Z1gi) + %a0 = COPY %0 + %gp = COPY %1 + JALRPseudo killed %2, csr_o32_fpxx, implicit-def dead %ra, implicit %a0, implicit %gp, implicit-def %sp, implicit-def %v0 + ADJCALLSTACKUP 16, 0, implicit-def dead %sp, implicit %sp + %3 = COPY %v0 + %4 = ADDu %3, %0 + %5 = LW %1, target-flags(mips-got) @v :: (load 4 from got) + %6 = LW killed %5, 0 :: (dereferenceable load 4 from @v) + %7 = ADDu killed %4, killed %6 + %8 = LW %1, target-flags(mips-got) @j :: (load 4 from got) + %9 = LW killed %8, 0 :: (dereferenceable load 4 from @j) + %10 = ADDu killed %7, killed %9 + %v0 = COPY %10 + RetRA implicit %v0 + +... + diff --git a/test/CodeGen/Mips/mirparser/target-flags-pic.mir b/test/CodeGen/Mips/mirparser/target-flags-pic.mir new file mode 100644 index 0000000000000..2092406e38f1b --- /dev/null +++ b/test/CodeGen/Mips/mirparser/target-flags-pic.mir @@ -0,0 +1,98 @@ +# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \ +# RUN: -stop-after=expand-isel-pseudos -relocation-model=pic \ +# RUN: -o /dev/null %s + +# A simple test to show that we can parse the target specific flags: gpoff-hi, +#Â gpoff-lo, got-call, got-disp. + +--- | + @v = global i32 0, align 4 + @j = external global i32, align 4 + + define i32 @_Z2k1i(i32 signext %asd) { + entry: + %call = tail call i32 @_Z1gi(i32 signext %asd) + %add = add nsw i32 %call, %asd + %0 = load i32, i32* @v, align 4 + %add1 = add nsw i32 %add, %0 + %1 = load i32, i32* @j, align 4 + %add2 = add nsw i32 %add1, %1 + ret i32 %add2 + } + + declare i32 @_Z1gi(i32 signext) +... +--- +name: _Z2k1i +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } + - { id: 2, class: gpr64, preferred-register: '' } + - { id: 3, class: gpr32, preferred-register: '' } + - { id: 4, class: gpr32, preferred-register: '' } + - { id: 5, class: gpr32, preferred-register: '' } + - { id: 6, class: gpr64, preferred-register: '' } + - { id: 7, class: gpr32, preferred-register: '' } + - { id: 8, class: gpr32, preferred-register: '' } + - { id: 9, class: gpr64, preferred-register: '' } + - { id: 10, class: gpr32, preferred-register: '' } + - { id: 11, class: gpr32, preferred-register: '' } + - { id: 12, class: gpr64, preferred-register: '' } + - { id: 13, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '%t9_64', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: true + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64, %t9_64 + + %12 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i + %13 = DADDu %12, %t9_64 + %1 = DADDiu %13, target-flags(mips-gpoff-lo) @_Z2k1i + %0 = COPY %a0_64 + ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp + %2 = LD %1, target-flags(mips-got-call) @_Z1gi :: (load 8 from call-entry @_Z1gi) + %a0_64 = COPY %0 + %gp_64 = COPY %1 + JALR64Pseudo killed %2, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0 + ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp + %3 = COPY %v0 + %4 = COPY %0.sub_32 + %5 = ADDu %3, killed %4 + %6 = LD %1, target-flags(mips-got-disp) @v :: (load 8 from got) + %7 = LW killed %6, 0 :: (dereferenceable load 4 from @v) + %8 = ADDu killed %5, killed %7 + %9 = LD %1, target-flags(mips-got-disp) @j :: (load 8 from got) + %10 = LW killed %9, 0 :: (dereferenceable load 4 from @j) + %11 = ADDu killed %8, killed %10 + %v0 = COPY %11 + RetRA implicit %v0 + +... + diff --git a/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir b/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir new file mode 100644 index 0000000000000..ba0da2f178ce6 --- /dev/null +++ b/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir @@ -0,0 +1,236 @@ +# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \ +# RUN: -stop-after=expand-isel-pseudos -relocation-model=static -o /dev/null %s + +# A simple test to show that we can parse the target specific flags: highest, +# higher, hi, lo, tprel-lo, tprel-hi, gpoff-hi, gpoff-lo, gottprel. + +--- | + @v = global i32 0, align 4 + @k = thread_local global i32 0, align 4 + @j = external thread_local global i32, align 4 + @__tls_guard = internal thread_local global i1 false, align 1 + + declare i32 @_Z1gi(i32 signext) + + declare extern_weak void @_ZTH1j() + + define i32 @_Z2k1i(i32 signext %asd) { + entry: + %call = tail call i32 @_Z1gi(i32 signext %asd) + %add = add nsw i32 %call, %asd + %0 = load i32, i32* @v, align 4 + %add1 = add nsw i32 %add, %0 + %.b.i.i = load i1, i1* @__tls_guard, align 1 + br i1 %.b.i.i, label %entry._ZTW1k.exit_crit_edge, label %init.i.i + + entry._ZTW1k.exit_crit_edge: + %.pre = load i32, i32* @k, align 4 + br label %_ZTW1k.exit + + init.i.i: + store i1 true, i1* @__tls_guard, align 1 + %call.i.i.i = tail call i32 @_Z1gi(i32 signext 3) + store i32 %call.i.i.i, i32* @k, align 4 + br label %_ZTW1k.exit + + _ZTW1k.exit: + %1 = phi i32 [ %.pre, %entry._ZTW1k.exit_crit_edge ], [ %call.i.i.i, %init.i.i ] + %add2 = add nsw i32 %add1, %1 + br i1 icmp ne (void ()* @_ZTH1j, void ()* null), label %2, label %_ZTW1j.exit + + ; <label>:2: + tail call void @_ZTH1j() + br label %_ZTW1j.exit + + _ZTW1j.exit: + %3 = load i32, i32* @j, align 4 + %add3 = add nsw i32 %add2, %3 + ret i32 %add3 + } +... +--- +name: _Z2k1i +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } + - { id: 2, class: gpr32, preferred-register: '' } + - { id: 3, class: gpr32, preferred-register: '' } + - { id: 4, class: gpr32, preferred-register: '' } + - { id: 5, class: gpr64, preferred-register: '' } + - { id: 6, class: gpr32, preferred-register: '' } + - { id: 7, class: gpr32, preferred-register: '' } + - { id: 8, class: gpr32, preferred-register: '' } + - { id: 9, class: gpr64, preferred-register: '' } + - { id: 10, class: gpr64, preferred-register: '' } + - { id: 11, class: gpr64, preferred-register: '' } + - { id: 12, class: gpr64, preferred-register: '' } + - { id: 13, class: gpr64, preferred-register: '' } + - { id: 14, class: gpr32, preferred-register: '' } + - { id: 15, class: gpr64, preferred-register: '' } + - { id: 16, class: gpr64, preferred-register: '' } + - { id: 17, class: gpr64, preferred-register: '' } + - { id: 18, class: gpr64, preferred-register: '' } + - { id: 19, class: gpr64, preferred-register: '' } + - { id: 20, class: gpr32, preferred-register: '' } + - { id: 21, class: gpr64, preferred-register: '' } + - { id: 22, class: gpr64, preferred-register: '' } + - { id: 23, class: gpr64, preferred-register: '' } + - { id: 24, class: gpr64, preferred-register: '' } + - { id: 25, class: gpr64, preferred-register: '' } + - { id: 26, class: gpr32, preferred-register: '' } + - { id: 27, class: gpr64, preferred-register: '' } + - { id: 28, class: gpr64, preferred-register: '' } + - { id: 29, class: gpr64, preferred-register: '' } + - { id: 30, class: gpr64, preferred-register: '' } + - { id: 31, class: gpr32, preferred-register: '' } + - { id: 32, class: gpr64, preferred-register: '' } + - { id: 33, class: gpr64, preferred-register: '' } + - { id: 34, class: gpr64, preferred-register: '' } + - { id: 35, class: gpr64, preferred-register: '' } + - { id: 36, class: gpr64, preferred-register: '' } + - { id: 37, class: gpr64, preferred-register: '' } + - { id: 38, class: gpr64, preferred-register: '' } + - { id: 39, class: gpr64, preferred-register: '' } + - { id: 40, class: gpr64, preferred-register: '' } + - { id: 41, class: gpr64, preferred-register: '' } + - { id: 42, class: gpr64, preferred-register: '' } + - { id: 43, class: gpr64, preferred-register: '' } + - { id: 44, class: gpr64, preferred-register: '' } + - { id: 45, class: gpr64, preferred-register: '' } + - { id: 46, class: gpr64, preferred-register: '' } + - { id: 47, class: gpr64, preferred-register: '' } + - { id: 48, class: gpr32, preferred-register: '' } + - { id: 49, class: gpr32, preferred-register: '' } + - { id: 50, class: gpr64, preferred-register: '' } + - { id: 51, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%5' } + - { reg: '%t9_64', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: true + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + successors: %bb.1.entry._ZTW1k.exit_crit_edge(0x7fe00000), %bb.2.init.i.i(0x00200000) + liveins: %a0_64, %t9_64 + + %50 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i + %51 = DADDu %50, %t9_64 + %43 = DADDiu %51, target-flags(mips-gpoff-lo) @_Z2k1i + %5 = COPY %a0_64 + ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp + %6 = COPY %5.sub_32 + %a0_64 = COPY %5 + JAL @_Z1gi, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit-def %sp, implicit-def %v0 + ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp + %7 = COPY %v0 + %8 = ADDu %7, killed %6 + %9 = LUi64 target-flags(mips-highest) @v + %10 = DADDiu killed %9, target-flags(mips-higher) @v + %11 = DSLL killed %10, 16 + %12 = DADDiu killed %11, target-flags(mips-abs-hi) @v + %13 = DSLL killed %12, 16 + %14 = LW killed %13, target-flags(mips-abs-lo) @v :: (dereferenceable load 4 from @v) + %0 = ADDu killed %8, killed %14 + %15 = LUi64 target-flags(mips-tprel-hi) @__tls_guard + %16 = DADDiu killed %15, target-flags(mips-tprel-lo) @__tls_guard + %17 = RDHWR64 %hwr29 + %v1_64 = COPY %17 + %18 = COPY %v1_64 + %19 = DADDu %18, killed %16 + %20 = LBu killed %19, 0 :: (dereferenceable load 1 from @__tls_guard) + BEQ killed %20, %zero, %bb.2.init.i.i, implicit-def dead %at + J %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead %at + + bb.1.entry._ZTW1k.exit_crit_edge: + successors: %bb.3._ZTW1k.exit(0x80000000) + + %32 = LUi64 target-flags(mips-tprel-hi) @k + %33 = DADDiu killed %32, target-flags(mips-tprel-lo) @k + %34 = RDHWR64 %hwr29 + %v1_64 = COPY %34 + %35 = COPY %v1_64 + %36 = DADDu %35, killed %33 + %1 = LW killed %36, 0 :: (dereferenceable load 4 from @k) + J %bb.3._ZTW1k.exit, implicit-def dead %at + + bb.2.init.i.i: + successors: %bb.3._ZTW1k.exit(0x80000000) + + %21 = LUi64 target-flags(mips-tprel-hi) @__tls_guard + %22 = DADDiu killed %21, target-flags(mips-tprel-lo) @__tls_guard + %23 = RDHWR64 %hwr29 + %v1_64 = COPY %23 + %24 = COPY %v1_64 + %25 = DADDu %24, killed %22 + %26 = ADDiu %zero, 1 + SB killed %26, killed %25, 0 :: (store 1 into @__tls_guard) + %27 = LUi64 target-flags(mips-tprel-hi) @k + %28 = DADDiu killed %27, target-flags(mips-tprel-lo) @k + %29 = DADDu %24, killed %28 + ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp + %30 = DADDiu %zero_64, 3 + %a0_64 = COPY %30 + JAL @_Z1gi, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit-def %sp, implicit-def %v0 + ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp + %31 = COPY %v0 + SW %31, killed %29, 0 :: (store 4 into @k) + %2 = COPY %31 + + bb.3._ZTW1k.exit: + successors: %bb.4(0x40000000), %bb.5._ZTW1j.exit(0x40000000) + + %3 = PHI %2, %bb.2.init.i.i, %1, %bb.1.entry._ZTW1k.exit_crit_edge + %4 = ADDu %0, %3 + %37 = LUi64 target-flags(mips-highest) @_ZTH1j + %38 = DADDiu killed %37, target-flags(mips-higher) @_ZTH1j + %39 = DSLL killed %38, 16 + %40 = DADDiu killed %39, target-flags(mips-abs-hi) @_ZTH1j + %41 = DSLL killed %40, 16 + %42 = DADDiu killed %41, target-flags(mips-abs-lo) @_ZTH1j + BEQ64 killed %42, %zero_64, %bb.5._ZTW1j.exit, implicit-def dead %at + J %bb.4, implicit-def dead %at + + bb.4 (%ir-block.2): + successors: %bb.5._ZTW1j.exit(0x80000000) + + ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp + JAL @_ZTH1j, csr_n64, implicit-def dead %ra, implicit-def %sp + ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp + + bb.5._ZTW1j.exit: + %44 = RDHWR64 %hwr29 + %v1_64 = COPY %44 + %45 = LD %43, target-flags(mips-gottprel) @j :: (load 8) + %46 = COPY %v1_64 + %47 = DADDu %46, killed %45 + %48 = LW killed %47, 0 :: (dereferenceable load 4 from @j) + %49 = ADDu %4, killed %48 + %v0 = COPY %49 + RetRA implicit %v0 + +... + diff --git a/test/CodeGen/Mips/nmadd.ll b/test/CodeGen/Mips/nmadd.ll new file mode 100644 index 0000000000000..857d75b3fda3a --- /dev/null +++ b/test/CodeGen/Mips/nmadd.ll @@ -0,0 +1,84 @@ +; Check whether nmadd/nmsub instructions are properly generated +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+fp64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=micromips -enable-no-nans-fp-math -asm-show-inst | FileCheck %s -check-prefixes=ALL,CHECK-NM,CHECK-MM +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64 +; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64 +; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM +; RUN: llc < %s -march=mips64el -mcpu=mips3 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM-64 +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -mattr=micromips -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM +; RUN: llc < %s -march=mipsel -mcpu=mips32r3 -mattr=micromips -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM + +define float @add1(float %f, float %g, float %h) local_unnamed_addr #0 { +entry: +; ALL-LABEL: add1 + +; CHECK-NM-64: nmadd.s $f0, $f14, $f12, $f13 +; CHECK-NM: nmadd.s $f0, $f0, $f12, $f14 +; CHECK-MM: NMADD_S_MM +; CHECK-NOT-NM-64 mul.s $f0, $f12, $f13 +; CHECK-NOT-NM-64: neg.s $f0, $f0 +; CHECK-NOT-NM: mul.s $f0, $f12, $f14 +; CHECK-NOT-NM: neg.s $f0, $f0 + + %mul = fmul nnan float %f, %g + %add = fadd nnan float %mul, %h + %sub = fsub nnan float -0.000000e+00, %add + ret float %sub +} + +define double @add2(double %f, double %g, double %h) local_unnamed_addr #0 { +entry: +; ALL-LABEL: add2 + +; CHECK-NM-64: nmadd.d $f0, $f14, $f12, $f13 +; CHECK-NM: nmadd.d $f0, $f0, $f12, $f14 +; CHECK-MM: NMADD_D32_MM +; CHECK-NOT-NM-64 mul.d $f0, $f12, $f13 +; CHECK-NOT-NM-64: neg.d $f0, $f0 +; CHECK-NOT-NM: mul.d $f0, $f12, $f14 +; CHECK-NOT-NM: neg.d $f0, $f0 + + %mul = fmul nnan double %f, %g + %add = fadd nnan double %mul, %h + %sub = fsub nnan double -0.000000e+00, %add + ret double %sub +} + +define float @sub1(float %f, float %g, float %h) local_unnamed_addr #0 { +entry: +; ALL-LABEL: sub1 + +; CHECK-NM-64: nmsub.s $f0, $f14, $f12, $f13 +; CHECK-NM: nmsub.s $f0, $f0, $f12, $f14 +; CHECK-MM: NMSUB_S_MM +; CHECK-NOT-NM-64 mul.s $f0, $f12, $f13 +; CHECK-NOT-NM-64: neg.s $f0, $f0 +; CHECK-NOT-NM: mul.s $f0, $f12, $f14 +; CHECK-NOT-NM: neg.s $f0, $f0 + + %mul = fmul nnan float %f, %g + %sub = fsub nnan float %mul, %h + %sub1 = fsub nnan float -0.000000e+00, %sub + ret float %sub1 +} + +define double @sub2(double %f, double %g, double %h) local_unnamed_addr #0 { +entry: +; ALL-LABEL: sub2 + +; CHECK-NM-64: nmsub.d $f0, $f14, $f12, $f13 +; CHECK-NM: nmsub.d $f0, $f0, $f12, $f14 +; CHECK-MM: NMSUB_D32_MM +; CHECK-NOT-NM-64 mul.d $f0, $f12, $f13 +; CHECK-NOT-NM-64: neg.d $f0, $f0 +; CHECK-NOT-NM: mul.d $f0, $f12, $f14 +; CHECK-NOT-NM: neg.d $f0, $f0 + + %mul = fmul nnan double %f, %g + %sub = fsub nnan double %mul, %h + %sub1 = fsub nnan double -0.000000e+00, %sub + ret double %sub1 +} diff --git a/test/CodeGen/Mips/octeon.ll b/test/CodeGen/Mips/octeon.ll index 7e2a81019ac44..eb16991604860 100644 --- a/test/CodeGen/Mips/octeon.ll +++ b/test/CodeGen/Mips/octeon.ll @@ -1,5 +1,6 @@ ; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON ; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64 +; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon -relocation-model=pic | FileCheck %s -check-prefixes=ALL,OCTEON-PIC define i64 @addi64(i64 %a, i64 %b) nounwind { entry: @@ -88,10 +89,12 @@ entry: ret i64 %res2 } -define i64 @bbit0(i64 %a) nounwind { +define i64 @bbit1(i64 %a) nounwind { entry: -; ALL-LABEL: bbit0: -; OCTEON: bbit0 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] +; ALL-LABEL: bbit1: +; OCTEON: bbit1 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] +; OCTEON-PIC-NOT: b {{[[:space:]].*}} +; OCTEON-NOT: j {{[[:space:]].*}} ; MIPS64: andi $[[T0:[0-9]+]], $4, 8 ; MIPS64: bnez $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]] %bit = and i64 %a, 8 @@ -104,10 +107,12 @@ endif: ret i64 12 } -define i64 @bbit032(i64 %a) nounwind { +define i64 @bbit132(i64 %a) nounwind { entry: -; ALL-LABEL: bbit032: -; OCTEON: bbit032 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] +; ALL-LABEL: bbit132: +; OCTEON: bbit132 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] +; OCTEON-PIC-NOT: b {{[[:space:]].*}} +; OCTEON-NOT: j {{[[:space:]].*}} ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1 ; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35 ; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]] @@ -122,10 +127,12 @@ endif: ret i64 12 } -define i64 @bbit1(i64 %a) nounwind { +define i64 @bbit0(i64 %a) nounwind { entry: -; ALL-LABEL: bbit1: -; OCTEON: bbit1 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] +; ALL-LABEL: bbit0: +; OCTEON: bbit0 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] +; OCTEON-PIC-NOT: b {{[[:space:]].*}} +; OCTEON-NOT: j {{[[:space:]].*}} ; MIPS64: andi $[[T0:[0-9]+]], $4, 8 ; MIPS64: beqz $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]] %bit = and i64 %a, 8 @@ -138,10 +145,12 @@ endif: ret i64 12 } -define i64 @bbit132(i64 %a) nounwind { +define i64 @bbit032(i64 %a) nounwind { entry: -; ALL-LABEL: bbit132: -; OCTEON: bbit132 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] +; ALL-LABEL: bbit032: +; OCTEON: bbit032 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] +; OCTEON-PIC-NOT: b {{[[:space:]].*}} +; OCTEON-NOT: j {{[[:space:]].*}} ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1 ; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35 ; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]] @@ -155,3 +164,59 @@ if: endif: ret i64 12 } + +; extern void foo(void); +; long long var = 7; +; void bbit0i32 () { +; if ((var & 0x2)) { +; foo(); +; } +; } +; +; void bbit1i32() { +; if (!(var & 0x2)) { +; foo(); +; } +; } + +@var = local_unnamed_addr global i64 7, align 8 + +define void @bbit0i32() local_unnamed_addr { +entry: +; ALL-LABEL: bbit0i32: +; OCTEON: bbit0 $1, 1, [[BB0:(\$|\.L)BB[0-9_]+]] +; OCTEON-PIC-NOT: b {{[[:space:]].*}} +; OCTEON-NOT: j {{[[:space:]].*}} + %0 = load i64, i64* @var, align 8 + %and = and i64 %0, 2 + %tobool = icmp eq i64 %and, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + tail call void @foo() #2 + br label %if.end + +if.end: ; preds = %entry, %if.then + ret void +} + +declare void @foo() local_unnamed_addr + +define void @bbit1i32() local_unnamed_addr { +entry: +; ALL-LABEL: bbit1i32: +; OCTEON: bbit1 $1, 1, [[BB0:(\$|\.L)BB[0-9_]+]] +; OCTEON-PIC-NOT: b {{[[:space:]].*}} +; OCTEON-NOT: j {{[[:space:]].*}} + %0 = load i64, i64* @var, align 8 + %and = and i64 %0, 2 + %tobool = icmp eq i64 %and, 0 + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @foo() #2 + br label %if.end + +if.end: ; preds = %entry, %if.then + ret void +} diff --git a/test/CodeGen/Mips/pr33682.ll b/test/CodeGen/Mips/pr33682.ll new file mode 100644 index 0000000000000..0209ac39ea8bc --- /dev/null +++ b/test/CodeGen/Mips/pr33682.ll @@ -0,0 +1,55 @@ +; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,BE +; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,LE + +; Verify visitTRUNCATE respects endianness when transforming trunc to insert_vector_elt. + +; ALL-LABEL: a: +; BE: lw $2, 4($4) +; LE: lw $2, 0($4) + +define i32 @a(<2 x i32> * %a) { +entry: +%0 = load <2 x i32>, <2 x i32> * %a +%1 = bitcast <2 x i32> %0 to i64 +%2 = trunc i64 %1 to i32 +ret i32 %2 +} + +; ALL-LABEL: b: +; BE: lw $2, 12($4) +; LE: lw $2, 0($4) + +define i32 @b(<4 x i32> * %a) { +entry: +%0 = load <4 x i32>, <4 x i32> * %a +%1 = bitcast <4 x i32> %0 to i128 +%2 = trunc i128 %1 to i32 +ret i32 %2 +} + + +; Verify visitEXTRACT_VECTOR_ELT respects endianness when transforming extract_vector_elt to a trunc. + +; ALL-LABEL: c: +; BE: lw $2, 0($4) +; LE: lw $2, 0($4) + +define i32 @c(i64 * %a) { +entry: +%0 = load i64, i64 * %a +%1 = bitcast i64 %0 to <2 x i32> +%2 = extractelement <2 x i32> %1, i32 0 +ret i32 %2 +} + +; ALL-LABEL: d: +; BE: lw $2, 4($4) +; LE: lw $2, 4($4) + +define i32 @d(i64 * %a) { +entry: +%0 = load i64, i64 * %a +%1 = bitcast i64 %0 to <2 x i32> +%2 = extractelement <2 x i32> %1, i32 1 +ret i32 %2 +} diff --git a/test/CodeGen/Mips/pr34975.ll b/test/CodeGen/Mips/pr34975.ll new file mode 100644 index 0000000000000..a77a59fc5d308 --- /dev/null +++ b/test/CodeGen/Mips/pr34975.ll @@ -0,0 +1,90 @@ +; RUN: llc -mtriple=mips64-unknown-freebsd -target-abi n64 -relocation-model pic -o /dev/null %s -O2 + +; Test that the presence of debug information does not cause the branch folder +; to rewrite branches to have negative basic block ids, which would cause the +; long branch pass to crash. + +@c = external global i32, align 4 + +define void @e() !dbg !19 { +entry: + %0 = load i32, i32* @c, align 4, !dbg !28, !tbaa !31 + %tobool8 = icmp eq i32 %0, 0, !dbg !35 + br i1 %tobool8, label %for.end, label %for.body.preheader, !dbg !35 + +for.body.preheader: ; preds = %entry + br label %for.body, !dbg !36 + +for.body: ; preds = %for.body.preheader + %1 = load i8, i8* undef, align 1, !dbg !36, !tbaa !38 + %conv = zext i8 %1 to i32, !dbg !36 + %cmp = icmp sgt i32 %0, %conv, !dbg !39 + br i1 %cmp, label %if.end, label %if.then, !dbg !40 + +if.then: ; preds = %for.body + tail call void @llvm.dbg.value(metadata i32 %conv, metadata !41, metadata !DIExpression()), !dbg !43 + %idxprom5 = zext i8 %1 to i64, !dbg !44 + %call = tail call i32 bitcast (i32 (...)* @g to i32 (i32)*)(i32 signext undef) #3, !dbg !45 + br label %if.end, !dbg !46 + +if.end: ; preds = %if.then, %for.body + unreachable + +for.end: ; preds = %entry + ret void +} + +declare i32 @g(...) + +declare void @llvm.dbg.value(metadata, metadata, metadata) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!17, !18} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 6.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, globals: !3) +!1 = !DIFile(filename: "/local/scratch/alr48/cheri/llvm/tools/clang/test/CodeGen/<stdin>", directory: "/local/scratch/alr48/cheri/llvm/cmake-build-debug/tools/clang/test/CodeGen") +!2 = !{} +!3 = !{!4, !9, !13, !15} +!4 = !DIGlobalVariableExpression(var: !5, expr: !DIExpression()) +!5 = distinct !DIGlobalVariable(name: "a", scope: !0, file: !6, line: 6, type: !7, isLocal: false, isDefinition: true) +!6 = !DIFile(filename: "/crash.c", directory: "/tmp") +!7 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !8, size: 64) +!8 = !DIBasicType(name: "unsigned char", size: 8, encoding: DW_ATE_unsigned_char) +!9 = !DIGlobalVariableExpression(var: !10, expr: !DIExpression()) +!10 = distinct !DIGlobalVariable(name: "b", scope: !0, file: !6, line: 7, type: !11, isLocal: false, isDefinition: true) +!11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 64) +!12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!13 = !DIGlobalVariableExpression(var: !14, expr: !DIExpression()) +!14 = distinct !DIGlobalVariable(name: "c", scope: !0, file: !6, line: 8, type: !12, isLocal: false, isDefinition: true) +!15 = !DIGlobalVariableExpression(var: !16, expr: !DIExpression()) +!16 = distinct !DIGlobalVariable(name: "d", scope: !0, file: !6, line: 8, type: !12, isLocal: false, isDefinition: true) +!17 = !{i32 2, !"Debug Info Version", i32 3} +!18 = !{i32 7, !"PIC Level", i32 2} +!19 = distinct !DISubprogram(name: "e", scope: !6, file: !6, line: 9, type: !20, isLocal: false, isDefinition: true, scopeLine: 9, isOptimized: true, unit: !0, variables: !22) +!20 = !DISubroutineType(types: !21) +!21 = !{!12} +!22 = !{!23} +!23 = !DILocalVariable(name: "f", scope: !24, file: !6, line: 12, type: !12) +!24 = distinct !DILexicalBlock(scope: !25, file: !6, line: 11, column: 20) +!25 = distinct !DILexicalBlock(scope: !26, file: !6, line: 11, column: 9) +!26 = distinct !DILexicalBlock(scope: !27, file: !6, line: 10, column: 3) +!27 = distinct !DILexicalBlock(scope: !19, file: !6, line: 10, column: 3) +!28 = !DILocation(line: 10, column: 10, scope: !29) +!29 = distinct !DILexicalBlock(scope: !30, file: !6, line: 10, column: 3) +!30 = distinct !DILexicalBlock(scope: !19, file: !6, line: 10, column: 3) +!31 = !{!32, !32, i64 0} +!32 = !{!"int", !33, i64 0} +!33 = !{!"omnipotent char", !34, i64 0} +!34 = !{!"Simple C/C++ TBAA"} +!35 = !DILocation(line: 10, column: 3, scope: !30) +!36 = !DILocation(line: 11, column: 9, scope: !37) +!37 = distinct !DILexicalBlock(scope: !29, file: !6, line: 11, column: 9) +!38 = !{!33, !33, i64 0} +!39 = !DILocation(line: 11, column: 14, scope: !37) +!40 = !DILocation(line: 11, column: 9, scope: !29) +!41 = !DILocalVariable(name: "f", scope: !42, file: !6, line: 12, type: !12) +!42 = distinct !DILexicalBlock(scope: !37, file: !6, line: 11, column: 20) +!43 = !DILocation(line: 12, column: 11, scope: !42) +!44 = !DILocation(line: 13, column: 9, scope: !42) +!45 = !DILocation(line: 13, column: 7, scope: !42) +!46 = !DILocation(line: 14, column: 5, scope: !42) diff --git a/test/CodeGen/Mips/pr35071.ll b/test/CodeGen/Mips/pr35071.ll new file mode 100644 index 0000000000000..ae60f69a0808a --- /dev/null +++ b/test/CodeGen/Mips/pr35071.ll @@ -0,0 +1,73 @@ +; RUN: llc -mtriple mips64-unknown-freebsd12.0 -relocation-model pic -mcpu=mips4 -target-abi n64 -O2 -o - %s + +; Test that the long branch pass does not crash due to the control flow +; optimizer producing malformed basic block operands due to the backend +; failing to handle debug information around branch instructions. + +define void @f() !dbg !5 { +entry: + %cmp = icmp eq i32 undef, 0, !dbg !16 + %conv = zext i1 %cmp to i32, !dbg !16 + tail call void @llvm.dbg.value(metadata i32 %conv, metadata !11, metadata !DIExpression()), !dbg !17 + %tobool = icmp eq i32 undef, 0, !dbg !18 + br i1 %tobool, label %if.end, label %cleanup7.critedge, !dbg !21 + +if.end: ; preds = %entry + %call6 = call i32 bitcast (i32 (...)* @j to i32 (i32)*)(i32 signext %conv) +#4, !dbg !22 + br label %cleanup7, !dbg !23 + +cleanup7.critedge: ; preds = %entry + call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull undef) #4, !dbg !24 + br label %cleanup7 + +cleanup7: ; preds = %cleanup7.critedge, + ret void +} + +declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 + +declare i32 @j(...) + +declare void @llvm.dbg.value(metadata, metadata, metadata) #3 +attributes #1 = { argmemonly nounwind } +attributes #3 = { nounwind readnone speculatable } +attributes #4 = { nounwind } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang +version 6.0.0", isOptimized: true, runtimeVersion: +0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: +"/tmp//<stdin>", directory: +"/tmp/") +!2 = !{} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 7, !"PIC Level", i32 2} +!5 = distinct !DISubprogram(name: "f", scope: !6, file: !6, line: 8, type: !7, +isLocal: false, isDefinition: true, scopeLine: 8, isOptimized: true, unit: !0, +variables: !10) +!6 = !DIFile(filename: +"/tmp/test.c", +directory: "/tmp") +!7 = !DISubroutineType(types: !8) +!8 = !{!9} +!9 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!10 = !{!11, !12, !14} +!11 = !DILocalVariable(name: "e", scope: !5, file: !6, line: 9, type: !9) +!12 = !DILocalVariable(name: "g", scope: !13, file: !6, line: 11, type: !9) +!13 = distinct !DILexicalBlock(scope: !5, file: !6, line: 10, column: 3) +!14 = !DILocalVariable(name: "d", scope: !13, file: !6, line: 12, type: !15) +!15 = !DIDerivedType(tag: DW_TAG_typedef, name: "a", file: !6, line: 2, +baseType: !9) +!16 = !DILocation(line: 9, column: 15, scope: !5) +!17 = !DILocation(line: 9, column: 7, scope: !5) +!18 = !DILocation(line: 12, column: 5, scope: !19) +!19 = distinct !DILexicalBlock(scope: !20, file: !6, line: 12, column: 5) +!20 = distinct !DILexicalBlock(scope: !5, file: !6, line: 10, column: 3) +!21 = !DILocation(line: 12, column: 5, scope: !20) +!22 = !DILocation(line: 16, column: 3, scope: !5) +!23 = !DILocation(line: 17, column: 1, scope: !5) +!24 = !DILocation(line: 15, column: 3, scope: !5) diff --git a/test/CodeGen/Mips/prevent-hoisting.ll b/test/CodeGen/Mips/prevent-hoisting.ll index ca71bf7d1af41..1fc7462811cb2 100644 --- a/test/CodeGen/Mips/prevent-hoisting.ll +++ b/test/CodeGen/Mips/prevent-hoisting.ll @@ -16,7 +16,7 @@ ; CHECK: sll ; Check that at the start of a fallthrough block there is a instruction that writes to $1. -; CHECK: {{BB[0-9_#]+}}: +; CHECK: {{%bb.[0-9]+}}: ; CHECK: sll $1, $[[R0:[0-9]+]], 4 ; CHECK: lw $[[R1:[0-9]+]], %got(assignSE2partition)($[[R2:[0-9]+]]) diff --git a/test/CodeGen/Mips/select.ll b/test/CodeGen/Mips/select.ll index 8c1b0286bb530..9d47c9b8a757e 100644 --- a/test/CodeGen/Mips/select.ll +++ b/test/CodeGen/Mips/select.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32 -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R2 -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R6 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64 -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R2 -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R6 +; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,32 +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,32R2 +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,32R6 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,64 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,64R2 +; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,64R6 @d2 = external global double @d3 = external global double diff --git a/test/CodeGen/Mips/stack-alignment.ll b/test/CodeGen/Mips/stack-alignment.ll index b18f96695ff57..af0df3eea247e 100644 --- a/test/CodeGen/Mips/stack-alignment.ll +++ b/test/CodeGen/Mips/stack-alignment.ll @@ -1,9 +1,15 @@ ; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32 +; RUN: llc -march=mipsel -stack-alignment=32 < %s | FileCheck %s -check-prefix=A32-32 ; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s -check-prefix=32 +; RUN: llc -march=mips64el -mcpu=mips3 < %s | FileCheck %s -check-prefix=64 +; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64 +; RUN: llc -march=mips64el -mcpu=mips64 -stack-alignment=32 < %s | FileCheck %s -check-prefix=A32-64 ; 32: addiu $sp, $sp, -8 -; 64: addiu $sp, $sp, -16 +; 64: daddiu $sp, $sp, -16 +; A32-32: addiu $sp, $sp, -32 +; A32-64: daddiu $sp, $sp, -32 define i32 @foo1() #0 { entry: diff --git a/test/CodeGen/Mips/tailcall/tailcall.ll b/test/CodeGen/Mips/tailcall/tailcall.ll index 3f04e1cf30531..02556fbfd3da2 100644 --- a/test/CodeGen/Mips/tailcall/tailcall.ll +++ b/test/CodeGen/Mips/tailcall/tailcall.ll @@ -27,11 +27,7 @@ ; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mattr=+micromips \ ; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32MM ; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \ -; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32 -; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6 \ -; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64R6MM -; RUN: llc -march=mips64el -relocation-model=static -mcpu=mips64r6 \ -; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=STATIC64 +; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32MMR6 @g0 = common global i32 0, align 4 @g1 = common global i32 0, align 4 @@ -51,6 +47,7 @@ entry: ; PIC32MM: jalr $25 ; PIC32R6: jalr $25 ; STATIC32: jal +; STATIC32MMR6: jal ; N64: jalr $25 ; N64R6: jalr $25 ; PIC16: jalrc @@ -68,6 +65,7 @@ entry: ; PIC32MM: jalr $25 ; PIC32R6: jalr $25 ; STATIC32: jal +; STATIC32MMR6: jal ; N64: jalr $25 ; N64R6: jalr $25 ; PIC16: jalrc @@ -85,6 +83,7 @@ entry: ; PIC32R6: jalr $25 ; PIC32MM: jalr $25 ; STATIC32: jal +; STATIC32MMR6: jal ; N64: jalr $25 ; N64R6: jalr $25 ; PIC16: jalrc @@ -102,6 +101,7 @@ entry: ; PIC32R6: jalr $25 ; PIC32MM: jalr $25 ; STATIC32: jal +; SATATIC32MMR6: jal ; PIC64: jalr $25 ; STATIC64: jal ; N64R6: jalr $25 @@ -120,6 +120,7 @@ entry: ; PIC32R6: jr $25 ; PIC32MM: jr ; STATIC32: j +; STATIC32MMR6: bc ; PIC64: jr $25 ; STATIC64: j ; PIC16: jalrc @@ -161,9 +162,9 @@ entry: ; PIC32R6: jrc $25 ; PIC32MM: jrc ; STATIC32: j +; STATIC32MMR6: bc ; PIC64: jr $25 ; PIC64R6: jrc $25 -; PIC64R6MM: jr $25 ; STATIC64: j ; PIC16: jalrc @@ -178,6 +179,7 @@ entry: ; PIC32R6: jalr $25 ; PIC32MM: jalr $25 ; STATIC32: jal +; STATIC32MMR6: jal ; PIC64: jalr $25 ; STATIC64: jal ; PIC16: jalrc @@ -199,6 +201,7 @@ entry: ; PIC32R6: jrc $25 ; PIC32MM: jrc ; STATIC32: j +; STATIC32MMR6: bc ; PIC64: jr $25 ; STATIC64: j ; PIC64R6: jrc $25 @@ -214,6 +217,7 @@ entry: ; PIC32R6: jalrc $25 ; PIC32MM: jalr $25 ; STATIC32: jal +; STATIC32MMR6: jal ; STATIC64: jal ; PIC64: jalr $25 ; PIC64R6: jalrc $25 @@ -232,6 +236,7 @@ entry: ; PIC32R6: jalr $25 ; PIC32MM: jalr $25 ; STATIC32: jal +; STATIC32MMR6: jal ; STATIC64: jal ; PIC64: jalr $25 ; PIC64R6: jalr $25 @@ -250,6 +255,7 @@ entry: ; PIC32R6: jalrc $25 ; PIC32MM: jalr $25 ; STATIC32: jal +; STATIC32MMR6: jal ; STATIC64: jal ; PIC64: jalr $25 ; PIC64R6: jalrc $25 @@ -270,6 +276,7 @@ entry: ; PIC32R6: jalrc $25 ; PIC32MM: jalr $25 ; STATIC32: jal +; STATIC32MMR6: jal ; STATIC64: jal ; PIC64: jalr $25 ; PIC64R6: jalrc $25 @@ -290,6 +297,7 @@ entry: ; PIC32R6: jalr $25 ; PIC32MM: jalr $25 ; STATIC32: jal +; STATIC32MMR6: jal ; STATIC64: jal ; PIC64R6: jalr $25 ; PIC64: jalr $25 diff --git a/test/CodeGen/Mips/v2i16tof32.ll b/test/CodeGen/Mips/v2i16tof32.ll new file mode 100644 index 0000000000000..7e5591ee9cb7b --- /dev/null +++ b/test/CodeGen/Mips/v2i16tof32.ll @@ -0,0 +1,47 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -O2 -mtriple mipsel--linux-android -mattr=+dsp -verify-machineinstrs | FileCheck %s + +; Function below generates a v2i16 to f32 bitcast. +; Test that we are able to match it. + +define float @f(<8 x i16>* %a) { +; CHECK-LABEL: f: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addiu $sp, $sp, -32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: sw $fp, 28($sp) # 4-byte Folded Spill +; CHECK-NEXT: .cfi_offset 30, -4 +; CHECK-NEXT: move $fp, $sp +; CHECK-NEXT: .cfi_def_cfa_register 30 +; CHECK-NEXT: addiu $1, $zero, -16 +; CHECK-NEXT: and $sp, $sp, $1 +; CHECK-NEXT: lw $1, 8($4) +; CHECK-NEXT: lw $2, 4($4) +; CHECK-NEXT: lw $3, 12($4) +; CHECK-NEXT: sw $3, 12($sp) +; CHECK-NEXT: sw $1, 8($sp) +; CHECK-NEXT: sw $2, 4($sp) +; CHECK-NEXT: lw $1, 0($4) +; CHECK-NEXT: sw $1, 0($sp) +; CHECK-NEXT: mtc1 $1, $f0 +; CHECK-NEXT: move $sp, $fp +; CHECK-NEXT: lw $fp, 28($sp) # 4-byte Folded Reload +; CHECK-NEXT: jr $ra +; CHECK-NEXT: addiu $sp, $sp, 32 +; CHECK-NEXT: .set at +; CHECK-NEXT: .set macro +; CHECK-NEXT: .set reorder +; CHECK-NEXT: .end f +entry: + %m = alloca <8 x i16> + %0 = load <8 x i16>, <8 x i16>* %a + store <8 x i16> %0, <8 x i16>* %m + %1 = bitcast <8 x i16> %0 to <4 x float> + %2 = shufflevector <4 x float> %1, <4 x float> undef, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> + %3 = shufflevector <8 x float> zeroinitializer, <8 x float> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7> + %4 = bitcast <8 x float> %3 to <8 x i32> + %5 = extractelement <8 x i32> %4, i32 0 + %6 = bitcast i32 %5 to float + ret float %6 +} + diff --git a/test/CodeGen/Mips/whitespace.ll b/test/CodeGen/Mips/whitespace.ll new file mode 100644 index 0000000000000..adb97e1657ff6 --- /dev/null +++ b/test/CodeGen/Mips/whitespace.ll @@ -0,0 +1,62 @@ +; Test that the instructions have the correct whitespace. +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck -strict-whitespace %s -check-prefix=16 +; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -strict-whitespace -check-prefix=32R2 + +@main.L = internal unnamed_addr constant [5 x i8*] [i8* blockaddress(@main, %L1), i8* blockaddress(@main, %L2), i8* blockaddress(@main, %L3), i8* blockaddress(@main, %L4), i8* null], align 4 +@str = private unnamed_addr constant [2 x i8] c"A\00" +@str5 = private unnamed_addr constant [2 x i8] c"B\00" +@str6 = private unnamed_addr constant [2 x i8] c"C\00" +@str7 = private unnamed_addr constant [2 x i8] c"D\00" +@str8 = private unnamed_addr constant [2 x i8] c"E\00" + +define i32 @main() nounwind { +entry: +; 16: jalrc ${{[0-9]+}} +; 16: jrc ${{[0-9]+}} +; 16: jrc $ra + %puts = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str, i32 0, i32 0)) + br label %L1 + +L1: ; preds = %entry, %L3 + %i.0 = phi i32 [ 0, %entry ], [ %inc, %L3 ] + %puts5 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str5, i32 0, i32 0)) + br label %L2 + +L2: ; preds = %L1, %L3 + %i.1 = phi i32 [ %i.0, %L1 ], [ %inc, %L3 ] + %puts6 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str6, i32 0, i32 0)) + br label %L3 + +L3: ; preds = %L2, %L3 + %i.2 = phi i32 [ %i.1, %L2 ], [ %inc, %L3 ] + %puts7 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str7, i32 0, i32 0)) + %inc = add i32 %i.2, 1 + %arrayidx = getelementptr inbounds [5 x i8*], [5 x i8*]* @main.L, i32 0, i32 %i.2 + %0 = load i8*, i8** %arrayidx, align 4 + indirectbr i8* %0, [label %L1, label %L2, label %L3, label %L4] +L4: ; preds = %L3 + %puts8 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str8, i32 0, i32 0)) + ret i32 0 +} + +declare i32 @puts(i8* nocapture) nounwind + +define i32 @ext(i32 %s, i32 %pos, i32 %sz) nounwind readnone { +entry: +; 32R2: ext ${{[0-9]+}}, $4, 5, 9 + %shr = lshr i32 %s, 5 + %and = and i32 %shr, 511 + ret i32 %and +} + +define void @ins(i32 %s, i32* nocapture %d) nounwind { +entry: +; 32R2: ins ${{[0-9]+}}, $4, 5, 9 + %and = shl i32 %s, 5 + %shl = and i32 %and, 16352 + %tmp3 = load i32, i32* %d, align 4 + %and5 = and i32 %tmp3, -16353 + %or = or i32 %and5, %shl + store i32 %or, i32* %d, align 4 + ret void +} diff --git a/test/CodeGen/Mips/xray-section-group.ll b/test/CodeGen/Mips/xray-section-group.ll index d87f178ec4bec..d295ff39e5231 100644 --- a/test/CodeGen/Mips/xray-section-group.ll +++ b/test/CodeGen/Mips/xray-section-group.ll @@ -14,7 +14,7 @@ define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always" { ; CHECK: .section .text.foo,"ax",@progbits ret i32 0 -; CHECK: .section xray_instr_map,"a",@progbits +; CHECK: .section xray_instr_map,"awo",@progbits,foo,unique,1 } ; CHECK-OBJ: Section { @@ -24,7 +24,7 @@ $bar = comdat any define i32 @bar() nounwind noinline uwtable "function-instrument"="xray-always" comdat($bar) { ; CHECK: .section .text.bar,"axG",@progbits,bar,comdat ret i32 1 -; CHECK: .section xray_instr_map,"aG",@progbits,bar,comdat +; CHECK: .section xray_instr_map,"aGwo",@progbits,bar,comdat,bar,unique,2 } ; CHECK-OBJ: Section { |