diff options
Diffstat (limited to 'test/CodeGen/X86/GlobalISel/select-sub-v512.mir')
| -rw-r--r-- | test/CodeGen/X86/GlobalISel/select-sub-v512.mir | 49 |
1 files changed, 25 insertions, 24 deletions
diff --git a/test/CodeGen/X86/GlobalISel/select-sub-v512.mir b/test/CodeGen/X86/GlobalISel/select-sub-v512.mir index 828a243b26567..67949219ba43a 100644 --- a/test/CodeGen/X86/GlobalISel/select-sub-v512.mir +++ b/test/CodeGen/X86/GlobalISel/select-sub-v512.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --- | @@ -26,23 +27,23 @@ ... --- name: test_sub_v64i8 -# ALL-LABEL: name: test_sub_v64i8 alignment: 4 legalized: true regBankSelected: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } -# ALL: %2 = VPSUBBZrr %0, %1 body: | bb.1 (%ir-block.0): liveins: %zmm0, %zmm1 + ; ALL-LABEL: name: test_sub_v64i8 + ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0 + ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1 + ; ALL: [[VPSUBBZrr:%[0-9]+]]:vr512 = VPSUBBZrr [[COPY]], [[COPY1]] + ; ALL: %zmm0 = COPY [[VPSUBBZrr]] + ; ALL: RET 0, implicit %zmm0 %0(<64 x s8>) = COPY %zmm0 %1(<64 x s8>) = COPY %zmm1 %2(<64 x s8>) = G_SUB %0, %1 @@ -52,23 +53,23 @@ body: | ... --- name: test_sub_v32i16 -# ALL-LABEL: name: test_sub_v32i16 alignment: 4 legalized: true regBankSelected: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } -# ALL: %2 = VPSUBWZrr %0, %1 body: | bb.1 (%ir-block.0): liveins: %zmm0, %zmm1 + ; ALL-LABEL: name: test_sub_v32i16 + ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0 + ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1 + ; ALL: [[VPSUBWZrr:%[0-9]+]]:vr512 = VPSUBWZrr [[COPY]], [[COPY1]] + ; ALL: %zmm0 = COPY [[VPSUBWZrr]] + ; ALL: RET 0, implicit %zmm0 %0(<32 x s16>) = COPY %zmm0 %1(<32 x s16>) = COPY %zmm1 %2(<32 x s16>) = G_SUB %0, %1 @@ -78,23 +79,23 @@ body: | ... --- name: test_sub_v16i32 -# ALL-LABEL: name: test_sub_v16i32 alignment: 4 legalized: true regBankSelected: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } -# ALL: %2 = VPSUBDZrr %0, %1 body: | bb.1 (%ir-block.0): liveins: %zmm0, %zmm1 + ; ALL-LABEL: name: test_sub_v16i32 + ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0 + ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1 + ; ALL: [[VPSUBDZrr:%[0-9]+]]:vr512 = VPSUBDZrr [[COPY]], [[COPY1]] + ; ALL: %zmm0 = COPY [[VPSUBDZrr]] + ; ALL: RET 0, implicit %zmm0 %0(<16 x s32>) = COPY %zmm0 %1(<16 x s32>) = COPY %zmm1 %2(<16 x s32>) = G_SUB %0, %1 @@ -104,23 +105,23 @@ body: | ... --- name: test_sub_v8i64 -# ALL-LABEL: name: test_sub_v8i64 alignment: 4 legalized: true regBankSelected: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } -# ALL: %2 = VPSUBQZrr %0, %1 body: | bb.1 (%ir-block.0): liveins: %zmm0, %zmm1 + ; ALL-LABEL: name: test_sub_v8i64 + ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0 + ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1 + ; ALL: [[VPSUBQZrr:%[0-9]+]]:vr512 = VPSUBQZrr [[COPY]], [[COPY1]] + ; ALL: %zmm0 = COPY [[VPSUBQZrr]] + ; ALL: RET 0, implicit %zmm0 %0(<8 x s64>) = COPY %zmm0 %1(<8 x s64>) = COPY %zmm1 %2(<8 x s64>) = G_SUB %0, %1 |