diff options
Diffstat (limited to 'test/CodeGen')
58 files changed, 893 insertions, 314 deletions
diff --git a/test/CodeGen/AMDGPU/cgp-addressing-modes.ll b/test/CodeGen/AMDGPU/cgp-addressing-modes.ll index 77f7bd01b7f0a..a68d110fdc96d 100644 --- a/test/CodeGen/AMDGPU/cgp-addressing-modes.ll +++ b/test/CodeGen/AMDGPU/cgp-addressing-modes.ll @@ -1,12 +1,15 @@ -; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown < %s | FileCheck -check-prefix=OPT %s -; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN %s +; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-CI %s +; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tonga < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-VI %s +; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s declare i32 @llvm.r600.read.tidig.x() #0 ; OPT-LABEL: @test_sink_global_small_offset_i32( -; OPT-NOT: getelementptr i32, i32 addrspace(1)* %in +; OPT-CI-NOT: getelementptr i32, i32 addrspace(1)* %in +; OPT-VI: getelementptr i32, i32 addrspace(1)* %in ; OPT: br i1 -; OPT: ptrtoint +; OPT-CI: ptrtoint ; GCN-LABEL: {{^}}test_sink_global_small_offset_i32: ; GCN: {{^}}BB0_2: @@ -214,8 +217,11 @@ done: } ; GCN-LABEL: {{^}}test_sink_global_vreg_sreg_i32: +; VI-DAG: s_movk_i32 flat_scratch_lo, 0x0 +; VI-DAG: s_movk_i32 flat_scratch_hi, 0x0 ; GCN: s_and_saveexec_b64 -; GCN: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; CI: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; VI: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}] ; GCN: {{^}}BB7_2: define void @test_sink_global_vreg_sreg_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %offset, i32 %cond) { entry: diff --git a/test/CodeGen/AMDGPU/global_atomics.ll b/test/CodeGen/AMDGPU/global_atomics.ll index 847950f6376e5..146f0a5fbf260 100644 --- a/test/CodeGen/AMDGPU/global_atomics.ll +++ b/test/CodeGen/AMDGPU/global_atomics.ll @@ -1,7 +1,9 @@ -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s +; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=SI --check-prefix=FUNC %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=VI --check-prefix=FUNC %s + ; FUNC-LABEL: {{^}}atomic_add_i32_offset: -; SI: buffer_atomic_add v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_add v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_add_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -10,8 +12,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_add_i32_ret_offset: -; SI: buffer_atomic_add [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_add [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_add_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -22,6 +24,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_add_i32_addr64_offset: ; SI: buffer_atomic_add v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} + define void @atomic_add_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -32,7 +38,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_add_i32_ret_addr64_offset: ; SI: buffer_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_add_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -43,7 +52,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_add_i32: -; SI: buffer_atomic_add v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_add v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_add_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile add i32 addrspace(1)* %out, i32 %in seq_cst @@ -51,8 +60,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_add_i32_ret: -; SI: buffer_atomic_add [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_add [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dword [[RET]] define void @atomic_add_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile add i32 addrspace(1)* %out, i32 %in seq_cst @@ -62,6 +71,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_add_i32_addr64: ; SI: buffer_atomic_add v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_add_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -71,7 +83,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_add_i32_ret_addr64: ; SI: buffer_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_add_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -81,7 +96,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_and_i32_offset: -; SI: buffer_atomic_and v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_and v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_and_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -90,8 +105,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_and_i32_ret_offset: -; SI: buffer_atomic_and [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_and [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_and_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -102,6 +117,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_and_i32_addr64_offset: ; SI: buffer_atomic_and v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_and_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -112,7 +130,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_and_i32_ret_addr64_offset: ; SI: buffer_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_and_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -123,7 +144,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_and_i32: -; SI: buffer_atomic_and v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_and v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_and_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile and i32 addrspace(1)* %out, i32 %in seq_cst @@ -131,8 +152,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_and_i32_ret: -; SI: buffer_atomic_and [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_and [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dword [[RET]] define void @atomic_and_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile and i32 addrspace(1)* %out, i32 %in seq_cst @@ -142,6 +163,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_and_i32_addr64: ; SI: buffer_atomic_and v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_and_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -151,7 +175,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_and_i32_ret_addr64: ; SI: buffer_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_and_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -161,7 +188,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_sub_i32_offset: -; SI: buffer_atomic_sub v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_sub v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_sub_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -170,8 +197,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_sub_i32_ret_offset: -; SI: buffer_atomic_sub [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_sub [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_sub_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -182,6 +209,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_sub_i32_addr64_offset: ; SI: buffer_atomic_sub v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_sub_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -192,7 +222,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_sub_i32_ret_addr64_offset: ; SI: buffer_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_sub_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -203,7 +236,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_sub_i32: -; SI: buffer_atomic_sub v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_sub v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_sub_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile sub i32 addrspace(1)* %out, i32 %in seq_cst @@ -211,8 +244,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_sub_i32_ret: -; SI: buffer_atomic_sub [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_sub [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dword [[RET]] define void @atomic_sub_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile sub i32 addrspace(1)* %out, i32 %in seq_cst @@ -222,6 +255,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_sub_i32_addr64: ; SI: buffer_atomic_sub v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_sub_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -231,7 +267,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_sub_i32_ret_addr64: ; SI: buffer_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_sub_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -241,7 +280,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_max_i32_offset: -; SI: buffer_atomic_smax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_smax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_max_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -250,8 +289,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_max_i32_ret_offset: -; SI: buffer_atomic_smax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_smax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_max_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -262,6 +301,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_max_i32_addr64_offset: ; SI: buffer_atomic_smax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_max_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -272,7 +314,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_max_i32_ret_addr64_offset: ; SI: buffer_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_max_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -283,7 +328,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_max_i32: -; SI: buffer_atomic_smax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_smax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_max_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile max i32 addrspace(1)* %out, i32 %in seq_cst @@ -291,8 +336,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_max_i32_ret: -; SI: buffer_atomic_smax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_smax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dword [[RET]] define void @atomic_max_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile max i32 addrspace(1)* %out, i32 %in seq_cst @@ -302,6 +347,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_max_i32_addr64: ; SI: buffer_atomic_smax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_max_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -311,7 +359,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_max_i32_ret_addr64: ; SI: buffer_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_max_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -321,7 +372,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umax_i32_offset: -; SI: buffer_atomic_umax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_umax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_umax_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -330,8 +381,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umax_i32_ret_offset: -; SI: buffer_atomic_umax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_umax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_umax_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -342,6 +393,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_umax_i32_addr64_offset: ; SI: buffer_atomic_umax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_umax_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -352,7 +406,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_umax_i32_ret_addr64_offset: ; SI: buffer_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_umax_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -363,7 +420,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umax_i32: -; SI: buffer_atomic_umax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_umax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_umax_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile umax i32 addrspace(1)* %out, i32 %in seq_cst @@ -371,8 +428,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umax_i32_ret: -; SI: buffer_atomic_umax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_umax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dword [[RET]] define void @atomic_umax_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile umax i32 addrspace(1)* %out, i32 %in seq_cst @@ -382,6 +439,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_umax_i32_addr64: ; SI: buffer_atomic_umax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_umax_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -391,7 +451,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_umax_i32_ret_addr64: ; SI: buffer_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_umax_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -401,7 +464,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_min_i32_offset: -; SI: buffer_atomic_smin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_smin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_min_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -410,8 +473,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_min_i32_ret_offset: -; SI: buffer_atomic_smin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_smin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_min_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -422,6 +485,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_min_i32_addr64_offset: ; SI: buffer_atomic_smin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_min_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -432,7 +498,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_min_i32_ret_addr64_offset: ; SI: buffer_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_min_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -443,7 +512,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_min_i32: -; SI: buffer_atomic_smin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_smin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_min_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile min i32 addrspace(1)* %out, i32 %in seq_cst @@ -451,8 +520,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_min_i32_ret: -; SI: buffer_atomic_smin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_smin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dword [[RET]] define void @atomic_min_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile min i32 addrspace(1)* %out, i32 %in seq_cst @@ -462,6 +531,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_min_i32_addr64: ; SI: buffer_atomic_smin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_min_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -471,7 +543,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_min_i32_ret_addr64: ; SI: buffer_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_min_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -481,7 +556,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umin_i32_offset: -; SI: buffer_atomic_umin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_umin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_umin_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -490,8 +565,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umin_i32_ret_offset: -; SI: buffer_atomic_umin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_umin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_umin_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -502,6 +577,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_umin_i32_addr64_offset: ; SI: buffer_atomic_umin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_umin_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -512,7 +590,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_umin_i32_ret_addr64_offset: ; SI: buffer_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_umin_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -523,7 +604,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_umin_i32: -; SI: buffer_atomic_umin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_umin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_umin_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile umin i32 addrspace(1)* %out, i32 %in seq_cst @@ -532,7 +613,7 @@ entry: ; FUNC-LABEL: {{^}}atomic_umin_i32_ret: ; SI: buffer_atomic_umin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: buffer_store_dword [[RET]] +; GCN: buffer_store_dword [[RET]] define void @atomic_umin_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile umin i32 addrspace(1)* %out, i32 %in seq_cst @@ -542,6 +623,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_umin_i32_addr64: ; SI: buffer_atomic_umin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_umin_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -551,7 +635,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_umin_i32_ret_addr64: ; SI: buffer_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_umin_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -561,7 +648,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_or_i32_offset: -; SI: buffer_atomic_or v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_or v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_or_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -570,8 +657,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_or_i32_ret_offset: -; SI: buffer_atomic_or [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_or [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_or_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -582,6 +669,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_or_i32_addr64_offset: ; SI: buffer_atomic_or v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_or_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -592,7 +682,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_or_i32_ret_addr64_offset: ; SI: buffer_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_or_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -603,7 +696,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_or_i32: -; SI: buffer_atomic_or v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_or v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_or_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile or i32 addrspace(1)* %out, i32 %in seq_cst @@ -611,8 +704,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_or_i32_ret: -; SI: buffer_atomic_or [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_or [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dword [[RET]] define void @atomic_or_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile or i32 addrspace(1)* %out, i32 %in seq_cst @@ -622,6 +715,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_or_i32_addr64: ; SI: buffer_atomic_or v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_or_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -631,7 +727,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_or_i32_ret_addr64: ; SI: buffer_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_or_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -641,7 +740,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xchg_i32_offset: -; SI: buffer_atomic_swap v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_swap v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_xchg_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -650,8 +749,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xchg_i32_ret_offset: -; SI: buffer_atomic_swap [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_swap [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_xchg_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -672,7 +771,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_xchg_i32_ret_addr64_offset: ; SI: buffer_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_xchg_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -683,7 +785,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xchg_i32: -; SI: buffer_atomic_swap v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_swap v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_xchg_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile xchg i32 addrspace(1)* %out, i32 %in seq_cst @@ -691,8 +793,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xchg_i32_ret: -; SI: buffer_atomic_swap [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_swap [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dword [[RET]] define void @atomic_xchg_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile xchg i32 addrspace(1)* %out, i32 %in seq_cst @@ -702,6 +804,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_xchg_i32_addr64: ; SI: buffer_atomic_swap v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_xchg_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -711,7 +816,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_xchg_i32_ret_addr64: ; SI: buffer_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_xchg_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -721,7 +829,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xor_i32_offset: -; SI: buffer_atomic_xor v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_xor v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_xor_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -730,8 +838,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xor_i32_ret_offset: -; SI: buffer_atomic_xor [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_xor [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc {{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_xor_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 @@ -742,6 +850,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_xor_i32_addr64_offset: ; SI: buffer_atomic_xor v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_xor_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -752,7 +863,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_xor_i32_ret_addr64_offset: ; SI: buffer_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_xor_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -763,7 +877,7 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xor_i32: -; SI: buffer_atomic_xor v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_xor v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_xor_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = atomicrmw volatile xor i32 addrspace(1)* %out, i32 %in seq_cst @@ -771,8 +885,8 @@ entry: } ; FUNC-LABEL: {{^}}atomic_xor_i32_ret: -; SI: buffer_atomic_xor [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc -; SI: buffer_store_dword [[RET]] +; GCN: buffer_atomic_xor [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dword [[RET]] define void @atomic_xor_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: %0 = atomicrmw volatile xor i32 addrspace(1)* %out, i32 %in seq_cst @@ -782,6 +896,9 @@ entry: ; FUNC-LABEL: {{^}}atomic_xor_i32_addr64: ; SI: buffer_atomic_xor v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_xor_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index @@ -791,7 +908,10 @@ entry: ; FUNC-LABEL: {{^}}atomic_xor_i32_ret_addr64: ; SI: buffer_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; SI: buffer_store_dword [[RET]] +; VI: s_movk_i32 flat_scratch_lo, 0x0 +; VI: s_movk_i32 flat_scratch_hi, 0x0 +; VI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: buffer_store_dword [[RET]] define void @atomic_xor_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index diff --git a/test/CodeGen/AMDGPU/gv-const-addrspace.ll b/test/CodeGen/AMDGPU/gv-const-addrspace.ll index 3c1fc6c98f749..d4d13125cfbf4 100644 --- a/test/CodeGen/AMDGPU/gv-const-addrspace.ll +++ b/test/CodeGen/AMDGPU/gv-const-addrspace.ll @@ -8,9 +8,7 @@ @float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.0, float 1.0, float 2.0, float 3.0, float 4.0], align 4 ; FUNC-LABEL: {{^}}float: -; FIXME: We should be using s_load_dword here. -; SI: buffer_load_dword -; VI: s_load_dword +; GCN: s_load_dword ; EG-DAG: MOV {{\** *}}T2.X ; EG-DAG: MOV {{\** *}}T3.X @@ -31,9 +29,7 @@ entry: ; FUNC-LABEL: {{^}}i32: -; FIXME: We should be using s_load_dword here. -; SI: buffer_load_dword -; VI: s_load_dword +; GCN: s_load_dword ; EG-DAG: MOV {{\** *}}T2.X ; EG-DAG: MOV {{\** *}}T3.X @@ -71,9 +67,7 @@ define void @struct_foo_gv_load(i32 addrspace(1)* %out, i32 %index) { <1 x i32> <i32 4> ] ; FUNC-LABEL: {{^}}array_v1_gv_load: -; FIXME: We should be using s_load_dword here. -; SI: buffer_load_dword -; VI: s_load_dword +; GCN: s_load_dword define void @array_v1_gv_load(<1 x i32> addrspace(1)* %out, i32 %index) { %gep = getelementptr inbounds [4 x <1 x i32>], [4 x <1 x i32>] addrspace(2)* @array_v1_gv, i32 0, i32 %index %load = load <1 x i32>, <1 x i32> addrspace(2)* %gep, align 4 diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.fract.f64.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.fract.f64.ll index e098dd35d6da8..6049dca04012c 100644 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.fract.f64.ll +++ b/test/CodeGen/AMDGPU/llvm.AMDGPU.fract.f64.ll @@ -11,8 +11,8 @@ declare double @llvm.AMDGPU.fract.f64(double) nounwind readnone ; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff ; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]] ; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3 -; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]] -; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]] +; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]] +; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]] ; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]] ; CI: buffer_store_dwordx2 [[FRC]] define void @fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) nounwind { @@ -28,8 +28,8 @@ define void @fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) nou ; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff ; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]] ; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3 -; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]] -; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]] +; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]] +; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]] ; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]] ; CI: buffer_store_dwordx2 [[FRC]] define void @fract_f64_neg(double addrspace(1)* %out, double addrspace(1)* %src) nounwind { @@ -46,8 +46,8 @@ define void @fract_f64_neg(double addrspace(1)* %out, double addrspace(1)* %src) ; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff ; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]] ; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3 -; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]] -; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]] +; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]] +; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]] ; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]] ; CI: buffer_store_dwordx2 [[FRC]] define void @fract_f64_neg_abs(double addrspace(1)* %out, double addrspace(1)* %src) nounwind { diff --git a/test/CodeGen/AMDGPU/private-memory.ll b/test/CodeGen/AMDGPU/private-memory.ll index 1c5629780508e..645dc04f44202 100644 --- a/test/CodeGen/AMDGPU/private-memory.ll +++ b/test/CodeGen/AMDGPU/private-memory.ll @@ -298,7 +298,7 @@ entry: ; FUNC-LABEL: ptrtoint: ; SI-NOT: ds_write ; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen -; SI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:5 +; SI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; define void @ptrtoint(i32 addrspace(1)* %out, i32 %a, i32 %b) { %alloca = alloca [16 x i32] %tmp0 = getelementptr [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a diff --git a/test/CodeGen/AMDGPU/scratch-buffer.ll b/test/CodeGen/AMDGPU/scratch-buffer.ll index 56088718ada82..268869daaa321 100644 --- a/test/CodeGen/AMDGPU/scratch-buffer.ll +++ b/test/CodeGen/AMDGPU/scratch-buffer.ll @@ -1,5 +1,7 @@ -; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck --check-prefix=GCN --check-prefix=DEFAULT-SCRATCH %s +; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=GCN --check-prefix=DEFAULT-SCRATCH %s +; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=+huge-scratch-buffer -mcpu=SI < %s | FileCheck --check-prefix=GCN --check-prefix=HUGE-SCRATCH %s +; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=+huge-scratch-buffer -mcpu=tonga < %s | FileCheck --check-prefix=GCN --check-prefix=HUGE-SCRATCH %s ; When a frame index offset is more than 12-bits, make sure we don't store ; it in mubuf's offset field. @@ -8,11 +10,11 @@ ; for both stores. This register is allocated by the register scavenger, so we ; should be able to reuse the same regiser for each scratch buffer access. -; CHECK-LABEL: {{^}}legal_offset_fi: -; CHECK: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0{{$}} -; CHECK: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen -; CHECK: v_mov_b32_e32 [[OFFSET]], 0x8000 -; CHECK: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}} +; GCN-LABEL: {{^}}legal_offset_fi: +; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0{{$}} +; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen +; GCN: v_mov_b32_e32 [[OFFSET]], 0x8000 +; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}} define void @legal_offset_fi(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) { entry: @@ -47,10 +49,10 @@ done: } -; CHECK-LABEL: {{^}}legal_offset_fi_offset -; CHECK: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen -; CHECK: v_add_i32_e32 [[OFFSET:v[0-9]+]], 0x8000 -; CHECK: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}} +; GCN-LABEL: {{^}}legal_offset_fi_offset +; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen +; GCN: v_add_i32_e32 [[OFFSET:v[0-9]+]], 0x8000 +; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}} define void @legal_offset_fi_offset(i32 addrspace(1)* %out, i32 %cond, i32 addrspace(1)* %offsets, i32 %if_offset, i32 %else_offset) { entry: @@ -85,3 +87,30 @@ done: ret void } +; GCN-LABEL: @neg_vaddr_offset +; We can't prove %offset is positive, so we must do the computation with the +; immediate in an add instruction instead of folding offset and the immediate into +; the store instruction. +; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen{{$}} +define void @neg_vaddr_offset(i32 %offset) { +entry: + %array = alloca [8192 x i32] + %ptr_offset = add i32 %offset, 4 + %ptr = getelementptr [8192 x i32], [8192 x i32]* %array, i32 0, i32 %ptr_offset + store i32 0, i32* %ptr + ret void +} + +; GCN-LABEL: @pos_vaddr_offse +; DEFAULT-SCRATCH: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:16 +; HUGE-SCRATCH: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen{{$}} +define void @pos_vaddr_offset(i32 addrspace(1)* %out, i32 %offset) { +entry: + %array = alloca [8192 x i32] + %ptr = getelementptr [8192 x i32], [8192 x i32]* %array, i32 0, i32 4 + store i32 0, i32* %ptr + %load_ptr = getelementptr [8192 x i32], [8192 x i32]* %array, i32 0, i32 %offset + %val = load i32, i32* %load_ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/smrd.ll b/test/CodeGen/AMDGPU/smrd.ll index b0c18ca5959c8..0598208e13173 100644 --- a/test/CodeGen/AMDGPU/smrd.ll +++ b/test/CodeGen/AMDGPU/smrd.ll @@ -43,13 +43,7 @@ entry: ; GCN-LABEL: {{^}}smrd3: ; FIXME: There are too many copies here because we don't fold immediates ; through REG_SEQUENCE -; SI: s_mov_b32 s[[SLO:[0-9]+]], 0 ; -; SI: s_mov_b32 s[[SHI:[0-9]+]], 4 -; SI: s_mov_b32 s[[SSLO:[0-9]+]], s[[SLO]] -; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SSLO]] -; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] -; FIXME: We should be able to use s_load_dword here -; SI: buffer_load_dword v{{[0-9]+}}, v{{\[}}[[VLO]]:[[VHI]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 +; SI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b ; TODO: Add VI checks ; GCN: s_endpgm define void @smrd3(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) { diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll index 56cdcaedf900b..5411618ed86dd 100644 --- a/test/CodeGen/ARM/ldrd.ll +++ b/test/CodeGen/ARM/ldrd.ll @@ -112,10 +112,10 @@ entry: } ; CHECK-LABEL: strd_spill_ldrd_reload: -; A8: strd r1, r0, [sp, #-8]! -; M3: strd r1, r0, [sp, #-8]! -; BASIC: strd r1, r0, [sp, #-8]! -; GREEDY: strd r0, r1, [sp, #-8]! +; A8: strd r1, r0, [sp] +; M3: strd r1, r0, [sp] +; BASIC: strd r1, r0, [sp] +; GREEDY: strd r0, r1, [sp] ; CHECK: @ InlineAsm Start ; CHECK: @ InlineAsm End ; A8: ldrd r2, r1, [sp] @@ -131,53 +131,5 @@ define void @strd_spill_ldrd_reload(i32 %v0, i32 %v1) { ret void } -declare void @extfunc2(i32*, i32, i32) - -; CHECK-LABEL: ldrd_postupdate_dec: -; CHECK: ldrd r1, r2, [r0], #-8 -; CHECK-NEXT: bl{{x?}} _extfunc -define void @ldrd_postupdate_dec(i32* %p0) { - %p0.1 = getelementptr i32, i32* %p0, i32 1 - %v0 = load i32, i32* %p0 - %v1 = load i32, i32* %p0.1 - %p1 = getelementptr i32, i32* %p0, i32 -2 - call void @extfunc2(i32* %p1, i32 %v0, i32 %v1) - ret void -} - -; CHECK-LABEL: ldrd_postupdate_inc: -; CHECK: ldrd r1, r2, [r0], #8 -; CHECK-NEXT: bl{{x?}} _extfunc -define void @ldrd_postupdate_inc(i32* %p0) { - %p0.1 = getelementptr i32, i32* %p0, i32 1 - %v0 = load i32, i32* %p0 - %v1 = load i32, i32* %p0.1 - %p1 = getelementptr i32, i32* %p0, i32 2 - call void @extfunc2(i32* %p1, i32 %v0, i32 %v1) - ret void -} - -; CHECK-LABEL: strd_postupdate_dec: -; CHECK: strd r1, r2, [r0], #-8 -; CHECK-NEXT: bx lr -define i32* @strd_postupdate_dec(i32* %p0, i32 %v0, i32 %v1) { - %p0.1 = getelementptr i32, i32* %p0, i32 1 - store i32 %v0, i32* %p0 - store i32 %v1, i32* %p0.1 - %p1 = getelementptr i32, i32* %p0, i32 -2 - ret i32* %p1 -} - -; CHECK-LABEL: strd_postupdate_inc: -; CHECK: strd r1, r2, [r0], #8 -; CHECK-NEXT: bx lr -define i32* @strd_postupdate_inc(i32* %p0, i32 %v0, i32 %v1) { - %p0.1 = getelementptr i32, i32* %p0, i32 1 - store i32 %v0, i32* %p0 - store i32 %v1, i32* %p0.1 - %p1 = getelementptr i32, i32* %p0, i32 2 - ret i32* %p1 -} - declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind diff --git a/test/CodeGen/Mips/Fast-ISel/br1.ll b/test/CodeGen/Mips/Fast-ISel/br1.ll index 11842ddc41885..a448e90187cbb 100644 --- a/test/CodeGen/Mips/Fast-ISel/br1.ll +++ b/test/CodeGen/Mips/Fast-ISel/br1.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @b = global i32 1, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/bswap1.ll b/test/CodeGen/Mips/Fast-ISel/bswap1.ll index 8ac9753fa463f..8f1f703ea0780 100644 --- a/test/CodeGen/Mips/Fast-ISel/bswap1.ll +++ b/test/CodeGen/Mips/Fast-ISel/bswap1.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s \ +; RUN: -fast-isel-abort=1 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R1 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s \ +; RUN: -fast-isel-abort=1 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R2 @a = global i16 -21829, align 2 diff --git a/test/CodeGen/Mips/Fast-ISel/callabi.ll b/test/CodeGen/Mips/Fast-ISel/callabi.ll index 8f5d68b41f668..34616a50b1a05 100644 --- a/test/CodeGen/Mips/Fast-ISel/callabi.ll +++ b/test/CodeGen/Mips/Fast-ISel/callabi.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=mipsel -mcpu=mips32 -O0 \ -; RUN: -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \ +; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \ ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 ; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 \ -; RUN: -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \ +; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \ ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 declare void @xb(i8) diff --git a/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll b/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll index df60d80718368..d6d9074c7c19a 100644 --- a/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll +++ b/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 < %s | FileCheck %s +; RUN: -fast-isel=true -fast-isel-abort=1 < %s | FileCheck %s ; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 < %s | FileCheck %s +; RUN: -fast-isel=true -fast-isel-abort=1 < %s | FileCheck %s @ARR = external global [10 x i32], align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/div1.ll b/test/CodeGen/Mips/Fast-ISel/div1.ll index 89e7f211251f6..89055aa12805f 100644 --- a/test/CodeGen/Mips/Fast-ISel/div1.ll +++ b/test/CodeGen/Mips/Fast-ISel/div1.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s +; RUN: -fast-isel-abort=1 | FileCheck %s ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s +; RUN: -fast-isel-abort=1 | FileCheck %s @sj = global i32 200000, align 4 @sk = global i32 -47, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/fastalloca.ll b/test/CodeGen/Mips/Fast-ISel/fastalloca.ll index b4a9f1ce7ab09..00bc7f485e08f 100644 --- a/test/CodeGen/Mips/Fast-ISel/fastalloca.ll +++ b/test/CodeGen/Mips/Fast-ISel/fastalloca.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s %struct.x = type { i32 } diff --git a/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll b/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll new file mode 100644 index 0000000000000..d9ce8b3964a46 --- /dev/null +++ b/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose 2>&1 | FileCheck %s + +; CHECK: FastISel missed call: +; CHECK-SAME: %call = call fastcc i32 @foo(i32 signext %a, i32 signext %b) + +define internal i32 @bar(i32 signext %a, i32 signext %b) { + %s = and i32 %a, %b + ret i32 %s +} + +define i32 @foo(i32 signext %a, i32 signext %b) { + %call = call fastcc i32 @foo(i32 signext %a, i32 signext %b) + ret i32 %call +} diff --git a/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll b/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll index 72de888b26e08..e346acfeff133 100644 --- a/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll +++ b/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @f1 = common global float 0.000000e+00, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/fpext.ll b/test/CodeGen/Mips/Fast-ISel/fpext.ll index 5ac22490ff028..f78289f40a022 100644 --- a/test/CodeGen/Mips/Fast-ISel/fpext.ll +++ b/test/CodeGen/Mips/Fast-ISel/fpext.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @f = global float 0x40147E6B80000000, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/fpintconv.ll b/test/CodeGen/Mips/Fast-ISel/fpintconv.ll index a94ef5081539a..2c022be5b3f73 100644 --- a/test/CodeGen/Mips/Fast-ISel/fpintconv.ll +++ b/test/CodeGen/Mips/Fast-ISel/fpintconv.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s diff --git a/test/CodeGen/Mips/Fast-ISel/fptrunc.ll b/test/CodeGen/Mips/Fast-ISel/fptrunc.ll index 2eec4c3ef5473..89a7bfce5b05c 100644 --- a/test/CodeGen/Mips/Fast-ISel/fptrunc.ll +++ b/test/CodeGen/Mips/Fast-ISel/fptrunc.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @d = global double 0x40147E6B74DF0446, align 8 diff --git a/test/CodeGen/Mips/Fast-ISel/icmpa.ll b/test/CodeGen/Mips/Fast-ISel/icmpa.ll index 670a8d5cfb4e2..fc37e118e7555 100644 --- a/test/CodeGen/Mips/Fast-ISel/icmpa.ll +++ b/test/CodeGen/Mips/Fast-ISel/icmpa.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @c = global i32 4, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/loadstore2.ll b/test/CodeGen/Mips/Fast-ISel/loadstore2.ll index 3daf03d681cbe..46f7a42a5fefd 100644 --- a/test/CodeGen/Mips/Fast-ISel/loadstore2.ll +++ b/test/CodeGen/Mips/Fast-ISel/loadstore2.ll @@ -4,9 +4,9 @@ target triple = "mips--linux-gnu" @c2 = common global i8 0, align 1 @c1 = common global i8 0, align 1 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @s2 = common global i16 0, align 2 diff --git a/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll b/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll index acba132b28e1e..09b56d2c87ec1 100644 --- a/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll +++ b/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32r2 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32 @b2 = global i8 0, align 1 diff --git a/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll b/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll index 9f644ecd18751..1051b2800e5b5 100644 --- a/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll +++ b/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 diff --git a/test/CodeGen/Mips/Fast-ISel/logopm.ll b/test/CodeGen/Mips/Fast-ISel/logopm.ll index 0f0c3bf9e1dc7..fec85092fffd9 100644 --- a/test/CodeGen/Mips/Fast-ISel/logopm.ll +++ b/test/CodeGen/Mips/Fast-ISel/logopm.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s @ub1 = common global i8 0, align 1 @ub2 = common global i8 0, align 1 @@ -283,8 +283,8 @@ entry: ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_Neg89:[0-9]+]], $zero, -89 -; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_Neg89]] +; CHECK-DAG: addiu $[[CONST_167:[0-9]+]], $zero, 167 +; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_167]] ; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) ; CHECK: .end andUc1 ret void @@ -345,8 +345,8 @@ entry: ; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) ; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) ; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_neg18:[0-9]+]], $zero, -18 -; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_neg18]] +; CHECK-DAG: addiu $[[CONST_238:[0-9]+]], $zero, 238 +; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_238]] ; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) ; CHECK: .end orUc1 ret void @@ -469,8 +469,8 @@ entry: ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_Neg4185:[0-9]+]], $zero, -4185 -; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_Neg4185]] +; CHECK-DAG: ori $[[CONST_61351:[0-9]+]], $zero, 61351 +; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_61351]] ; CHECK: sh $[[RES]], 0($[[US_ADDR]]) ; CHECK: .end andUs1 ret void @@ -520,8 +520,8 @@ entry: ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_neg4591:[0-9]+]], $zero, -4591 -; CHECK-DAG: or $[[RES:[0-9]+]], $[[US1]], $[[CONST_neg4591]] +; CHECK-DAG: ori $[[CONST_60945:[0-9]+]], $zero, 60945 +; CHECK-DAG: or $[[RES:[0-9]+]], $[[US1]], $[[CONST_60945]] ; CHECK: sh $[[RES]], 0($[[US_ADDR]]) ; CHECK: .end orUs1 ret void @@ -583,8 +583,8 @@ entry: ; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_Neg5512:[0-9]+]], $zero, -5512 -; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_Neg5512]] +; CHECK-DAG: ori $[[CONST_60024:[0-9]+]], $zero, 60024 +; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_60024]] ; CHECK: sh $[[RES]], 0($[[US_ADDR]]) ; CHECK: .end xorUs1 ret void diff --git a/test/CodeGen/Mips/Fast-ISel/memtest1.ll b/test/CodeGen/Mips/Fast-ISel/memtest1.ll index a3fc4a32981c0..b98200d7456d2 100644 --- a/test/CodeGen/Mips/Fast-ISel/memtest1.ll +++ b/test/CodeGen/Mips/Fast-ISel/memtest1.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s \ +; RUN: -fast-isel-abort=1 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R1 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s \ +; RUN: -fast-isel-abort=1 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R2 @str = private unnamed_addr constant [12 x i8] c"hello there\00", align 1 diff --git a/test/CodeGen/Mips/Fast-ISel/mul1.ll b/test/CodeGen/Mips/Fast-ISel/mul1.ll index 0ee044bea0a78..8713e7ef1d966 100644 --- a/test/CodeGen/Mips/Fast-ISel/mul1.ll +++ b/test/CodeGen/Mips/Fast-ISel/mul1.ll @@ -1,7 +1,5 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 \ -; RUN: -fast-isel -mips-fast-isel -relocation-model=pic -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 \ -; RUN: -fast-isel -mips-fast-isel -relocation-model=pic +; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic ; The test is just to make sure it is able to allocate ; registers for this example. There was an issue with allocating AC0 diff --git a/test/CodeGen/Mips/Fast-ISel/nullvoid.ll b/test/CodeGen/Mips/Fast-ISel/nullvoid.ll index 5fa3f13ace4c1..106015e30c35c 100644 --- a/test/CodeGen/Mips/Fast-ISel/nullvoid.ll +++ b/test/CodeGen/Mips/Fast-ISel/nullvoid.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s ; Function Attrs: nounwind diff --git a/test/CodeGen/Mips/Fast-ISel/overflt.ll b/test/CodeGen/Mips/Fast-ISel/overflt.ll index 57f991e23d95c..37e87b29c58e2 100644 --- a/test/CodeGen/Mips/Fast-ISel/overflt.ll +++ b/test/CodeGen/Mips/Fast-ISel/overflt.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @x = common global [128000 x float] zeroinitializer, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/rem1.ll b/test/CodeGen/Mips/Fast-ISel/rem1.ll index 9b5e440d0eaa2..cf709e7e49542 100644 --- a/test/CodeGen/Mips/Fast-ISel/rem1.ll +++ b/test/CodeGen/Mips/Fast-ISel/rem1.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s +; RUN: -fast-isel-abort=1 | FileCheck %s ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s +; RUN: -fast-isel-abort=1 | FileCheck %s @sj = global i32 200, align 4 @sk = global i32 -47, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/retabi.ll b/test/CodeGen/Mips/Fast-ISel/retabi.ll index 03119b827eb65..20747c4ed2060 100644 --- a/test/CodeGen/Mips/Fast-ISel/retabi.ll +++ b/test/CodeGen/Mips/Fast-ISel/retabi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s @i = global i32 75, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/sel1.ll b/test/CodeGen/Mips/Fast-ISel/sel1.ll index 47b6a895cde87..8f762b0ed088d 100644 --- a/test/CodeGen/Mips/Fast-ISel/sel1.ll +++ b/test/CodeGen/Mips/Fast-ISel/sel1.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O2 -relocation-model=pic \ -; RUN: -fast-isel -mips-fast-isel -fast-isel-abort=1 | FileCheck %s +; RUN: -fast-isel -fast-isel-abort=1 | FileCheck %s define i1 @sel_i1(i1 %j, i1 %k, i1 %l) { entry: @@ -8,7 +8,8 @@ entry: ; FIXME: The following instruction is redundant. ; CHECK: xor $[[T0:[0-9]+]], $4, $zero ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]] - ; CHECK-NEXT: movn $6, $5, $[[T1]] + ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 + ; CHECK-NEXT: movn $6, $5, $[[T2]] ; CHECK: move $2, $6 %cond = icmp ne i1 %j, 0 %res = select i1 %cond, i1 %k, i1 %l @@ -24,7 +25,8 @@ entry: ; CHECK-DAG: seb $[[T1:[0-9]+]], $zero ; CHECK: xor $[[T2:[0-9]+]], $[[T0]], $[[T1]] ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]] - ; CHECK-NEXT: movn $6, $5, $[[T3]] + ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1 + ; CHECK-NEXT: movn $6, $5, $[[T4]] ; CHECK: move $2, $6 %cond = icmp ne i8 %j, 0 %res = select i1 %cond, i8 %k, i8 %l @@ -40,7 +42,8 @@ entry: ; CHECK-DAG: seh $[[T1:[0-9]+]], $zero ; CHECK: xor $[[T2:[0-9]+]], $[[T0]], $[[T1]] ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]] - ; CHECK-NEXT: movn $6, $5, $[[T3]] + ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1 + ; CHECK-NEXT: movn $6, $5, $[[T4]] ; CHECK: move $2, $6 %cond = icmp ne i16 %j, 0 %res = select i1 %cond, i16 %k, i16 %l @@ -54,7 +57,8 @@ entry: ; FIXME: The following instruction is redundant. ; CHECK: xor $[[T0:[0-9]+]], $4, $zero ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]] - ; CHECK-NEXT: movn $6, $5, $[[T1]] + ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 + ; CHECK-NEXT: movn $6, $5, $[[T2]] ; CHECK: move $2, $6 %cond = icmp ne i32 %j, 0 %res = select i1 %cond, i32 %k, i32 %l @@ -69,7 +73,8 @@ entry: ; CHECK-DAG: mtc1 $5, $f1 ; CHECK-DAG: xor $[[T0:[0-9]+]], $4, $zero ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]] - ; CHECK: movn.s $f0, $f1, $[[T1]] + ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 + ; CHECK: movn.s $f0, $f1, $[[T2]] %cond = icmp ne i32 %j, 0 %res = select i1 %cond, float %k, float %l ret float %res @@ -84,7 +89,8 @@ entry: ; CHECK-DAG: ldc1 $f0, 16($sp) ; CHECK-DAG: xor $[[T0:[0-9]+]], $4, $zero ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]] - ; CHECK: movn.d $f0, $f2, $[[T1]] + ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 + ; CHECK: movn.d $f0, $f2, $[[T2]] %cond = icmp ne i32 %j, 0 %res = select i1 %cond, double %k, double %l ret double %res diff --git a/test/CodeGen/Mips/Fast-ISel/shftopm.ll b/test/CodeGen/Mips/Fast-ISel/shftopm.ll index 90ddd190be137..bbea9c5566c54 100644 --- a/test/CodeGen/Mips/Fast-ISel/shftopm.ll +++ b/test/CodeGen/Mips/Fast-ISel/shftopm.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 \ ; RUN: -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 \ ; RUN: -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s @s1 = global i16 -89, align 2 diff --git a/test/CodeGen/Mips/Fast-ISel/shift.ll b/test/CodeGen/Mips/Fast-ISel/shift.ll index df1c82700d59d..9fe694bb58273 100644 --- a/test/CodeGen/Mips/Fast-ISel/shift.ll +++ b/test/CodeGen/Mips/Fast-ISel/shift.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -O1 -fast-isel=true -mips-fast-isel -filetype=obj %s -o - \ +; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -fast-isel=true -filetype=obj %s -o - \ ; RUN: | llvm-objdump -arch mipsel -mcpu=mips32r2 -d - | FileCheck %s ; This test checks that encoding for srl is correct when fast-isel for mips32r2 is used. diff --git a/test/CodeGen/Mips/Fast-ISel/simplestore.ll b/test/CodeGen/Mips/Fast-ISel/simplestore.ll index bcb198b1a8238..627a383f597c2 100644 --- a/test/CodeGen/Mips/Fast-ISel/simplestore.ll +++ b/test/CodeGen/Mips/Fast-ISel/simplestore.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @abcd = external global i32 diff --git a/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll b/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll index f4b91d8502558..62101d8ef7ebf 100644 --- a/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll +++ b/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32r2 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32 @f = common global float 0.000000e+00, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/simplestorei.ll b/test/CodeGen/Mips/Fast-ISel/simplestorei.ll index 83ccae0b1de56..67541b54bae7a 100644 --- a/test/CodeGen/Mips/Fast-ISel/simplestorei.ll +++ b/test/CodeGen/Mips/Fast-ISel/simplestorei.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @ijk = external global i32 @@ -22,9 +22,10 @@ define void @si2_2() #0 { entry: store i32 -32768, i32* @ijk, align 4 ; CHECK: .ent si2_2 -; CHECK: addiu $[[REG1:[0-9]+]], $zero, -32768 -; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}}) -; CHECK: sw $[[REG1]], 0($[[REG2]]) +; CHECK: lui $[[REG1:[0-9]+]], 65535 +; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 32768 +; CHECK: lw $[[REG3:[0-9]+]], %got(ijk)(${{[0-9]+}}) +; CHECK: sw $[[REG2]], 0($[[REG3]]) ret void } diff --git a/test/CodeGen/Mips/delay-slot-kill.ll b/test/CodeGen/Mips/delay-slot-kill.ll index 57b630303c264..5e301441fd260 100644 --- a/test/CodeGen/Mips/delay-slot-kill.ll +++ b/test/CodeGen/Mips/delay-slot-kill.ll @@ -1,4 +1,6 @@ ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s +; We have to XFAIL this temporarily because of the reversion of r229675. +; XFAIL: * ; Currently, the following IR assembly generates a KILL instruction between ; the bitwise-and instruction and the return instruction. We verify that the diff --git a/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll b/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll index 779620e10128a..58dd16c9f9c8e 100644 --- a/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll +++ b/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll @@ -1,10 +1,10 @@ ; Check that register scavenging spill slot is close to $fp. -; RUN: llc -march=mipsel -O0 < %s | FileCheck %s +; RUN: llc -march=mipsel -O0 -fast-isel=false < %s | FileCheck %s -; CHECK: sw ${{.*}}, 4($sp) -; CHECK: lw ${{.*}}, 4($sp) +; CHECK: sw ${{.*}}, 8($sp) +; CHECK: lw ${{.*}}, 8($sp) -define i32 @main(i32 signext %argc, i8** %argv) "no-frame-pointer-elim"="true" { +define i32 @main(i32 signext %argc, i8** %argv) #0 { entry: %retval = alloca i32, align 4 %argc.addr = alloca i32, align 4 @@ -30,3 +30,5 @@ entry: store <16 x i8> %mul, <16 x i8>* %result, align 16 ret i32 0 } + +attributes #0 = { noinline optnone "no-frame-pointer-elim"="true" } diff --git a/test/CodeGen/Mips/llvm-ir/and.ll b/test/CodeGen/Mips/llvm-ir/and.ll index 8ebcfe4a3f640..c4121701ec153 100644 --- a/test/CodeGen/Mips/llvm-ir/and.ll +++ b/test/CodeGen/Mips/llvm-ir/and.ll @@ -59,7 +59,10 @@ define signext i32 @and_i32(i32 signext %a, i32 signext %b) { entry: ; ALL-LABEL: and_i32: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $[[T0:[0-9]+]], $4, $5 + ; GP64: sll $2, $[[T0]], 0 %r = and i32 %a, %b ret i32 %r diff --git a/test/CodeGen/Mips/llvm-ir/or.ll b/test/CodeGen/Mips/llvm-ir/or.ll index 6215e4036325a..8509d6ce93f37 100644 --- a/test/CodeGen/Mips/llvm-ir/or.ll +++ b/test/CodeGen/Mips/llvm-ir/or.ll @@ -59,7 +59,11 @@ define signext i32 @or_i32(i32 signext %a, i32 signext %b) { entry: ; ALL-LABEL: or_i32: - ; ALL: or $2, $4, $5 + ; GP32: or $2, $4, $5 + + ; GP64: or $[[T0:[0-9]+]], $4, $5 + ; FIXME: The sll instruction below is redundant. + ; GP64: sll $2, $[[T0]], 0 %r = or i32 %a, %b ret i32 %r diff --git a/test/CodeGen/Mips/llvm-ir/xor.ll b/test/CodeGen/Mips/llvm-ir/xor.ll index 89af99981a3c6..d3cc574848950 100644 --- a/test/CodeGen/Mips/llvm-ir/xor.ll +++ b/test/CodeGen/Mips/llvm-ir/xor.ll @@ -59,7 +59,10 @@ define signext i32 @xor_i32(i32 signext %a, i32 signext %b) { entry: ; ALL-LABEL: xor_i32: - ; ALL: xor $2, $4, $5 + ; GP32: xor $2, $4, $5 + + ; GP64: xor $[[T0:[0-9]+]], $4, $5 + ; GP64: sll $2, $[[T0]], 0 %r = xor i32 %a, %b ret i32 %r diff --git a/test/CodeGen/PowerPC/fp2int2fp-ppcfp128.ll b/test/CodeGen/PowerPC/fp2int2fp-ppcfp128.ll new file mode 100644 index 0000000000000..7742ffe331507 --- /dev/null +++ b/test/CodeGen/PowerPC/fp2int2fp-ppcfp128.ll @@ -0,0 +1,16 @@ +; RUN: llc -mcpu=a2 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-bgq-linux" + +define linkonce_odr double @test1() { +entry: + %conv6.i.i = fptosi ppc_fp128 undef to i64 + %conv.i = sitofp i64 %conv6.i.i to double + ret double %conv.i + +; CHECK-LABEL: @test1 +; CHECK: bl __fixtfdi +; CHECK: fcfid +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/ppc64-patchpoint.ll b/test/CodeGen/PowerPC/ppc64-patchpoint.ll index 53b737ae9a0b7..d10ea98cd1a77 100644 --- a/test/CodeGen/PowerPC/ppc64-patchpoint.ll +++ b/test/CodeGen/PowerPC/ppc64-patchpoint.ll @@ -103,6 +103,21 @@ entry: ret void } +; Trivial symbolic patchpoint codegen. + +declare i64 @foo(i64 %p1, i64 %p2) +define i64 @trivial_symbolic_patchpoint_codegen(i64 %p1, i64 %p2) { +entry: +; CHECK-LABEL: trivial_symbolic_patchpoint_codegen: +; CHECK: bl foo +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NOT: nop +; CHECK: blr + %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 9, i32 12, i8* bitcast (i64 (i64, i64)* @foo to i8*), i32 2, i64 %p1, i64 %p2) + ret i64 %result +} + declare void @llvm.experimental.stackmap(i64, i32, ...) declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...) declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...) diff --git a/test/CodeGen/PowerPC/pr24216.ll b/test/CodeGen/PowerPC/pr24216.ll new file mode 100644 index 0000000000000..4ab41985f5b16 --- /dev/null +++ b/test/CodeGen/PowerPC/pr24216.ll @@ -0,0 +1,14 @@ +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +; Test case adapted from PR24216. + +define void @foo(<16 x i8>* nocapture readonly %in, <16 x i8>* nocapture %out) { +entry: + %0 = load <16 x i8>, <16 x i8>* %in, align 16 + %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 2, i32 3, i32 4, i32 5, i32 2, i32 3, i32 4, i32 5, i32 2, i32 3, i32 4, i32 5> + store <16 x i8> %1, <16 x i8>* %out, align 16 + ret void +} + +; CHECK: vperm +; CHECK-NOT: vspltw diff --git a/test/CodeGen/PowerPC/vec_shuffle_le.ll b/test/CodeGen/PowerPC/vec_shuffle_le.ll index 46d451ff1573f..65c47ada87505 100644 --- a/test/CodeGen/PowerPC/vec_shuffle_le.ll +++ b/test/CodeGen/PowerPC/vec_shuffle_le.ll @@ -202,7 +202,7 @@ entry: ; CHECK: VSLDOI_xx: %tmp = load <16 x i8>, <16 x i8>* %A %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11> -; CHECK: vsldoi +; CHECK: vsldoi {{[0-9]+}}, [[REG1:[0-9]+]], [[REG1]], 4 store <16 x i8> %tmp2, <16 x i8>* %A ret void } diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll index f85acebeea677..dceb2516c6969 100644 --- a/test/CodeGen/PowerPC/vsx.ll +++ b/test/CodeGen/PowerPC/vsx.ll @@ -70,10 +70,10 @@ entry: ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test5 -; CHECK-FISL: vor 4, 2, 2 -; CHECK-FISL: vor 5, 3, 3 -; CHECK-FISL: xxlxor 36, 36, 37 -; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: vor +; CHECK-FISL: vor +; CHECK-FISL: xxlxor +; CHECK-FISL: vor 2 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test5 @@ -133,10 +133,10 @@ entry: ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test8 -; CHECK-FISL: vor 4, 2, 2 -; CHECK-FISL: vor 5, 3, 3 -; CHECK-FISL: xxlor 36, 36, 37 -; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: vor +; CHECK-FISL: vor +; CHECK-FISL: xxlor +; CHECK-FISL: vor 2 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test8 @@ -196,10 +196,10 @@ entry: ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test11 -; CHECK-FISL: vor 4, 2, 2 -; CHECK-FISL: vor 5, 3, 3 -; CHECK-FISL: xxland 36, 36, 37 -; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: vor +; CHECK-FISL: vor +; CHECK-FISL: xxland +; CHECK-FISL: vor 2 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test11 @@ -260,17 +260,14 @@ entry: ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test14 -; CHECK-FISL: vor 4, 2, 2 -; CHECK-FISL: vor 5, 3, 3 -; CHECK-FISL: xxlor 36, 36, 37 -; CHECK-FISL: vor 0, 4, 4 -; CHECK-FISL: vor 4, 2, 2 -; CHECK-FISL: vor 5, 3, 3 -; CHECK-FISL: xxlnor 36, 36, 37 +; CHECK-FISL: vor 4, 3, 3 +; CHECK-FISL: vor 5, 2, 2 +; CHECK-FISL: xxlor 0, 37, 36 +; CHECK-FISL: xxlnor 36, 37, 36 ; CHECK-FISL: vor 2, 4, 4 ; CHECK-FISL: lis 0, -1 ; CHECK-FISL: ori 0, 0, 65520 -; CHECK-FISL: stvx 0, 1, 0 +; CHECK-FISL: stxvd2x 0, 1, 0 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test14 @@ -347,15 +344,13 @@ entry: ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test17 -; CHECK-FISL: vspltisb 4, -1 -; CHECK-FISL: vor 5, 3, 3 -; CHECK-FISL: vor 0, 4, 4 -; CHECK-FISL: xxlxor 37, 37, 32 -; CHECK-FISL: vor 3, 5, 5 +; CHECK-FISL: vor 4, 3, 3 ; CHECK-FISL: vor 5, 2, 2 -; CHECK-FISL: vor 0, 3, 3 -; CHECK-FISL: xxland 37, 37, 32 -; CHECK-FISL: vor 2, 5, 5 +; CHECK-FISL: vspltisb 2, -1 +; CHECK-FISL: vor 0, 2, 2 +; CHECK-FISL: xxlxor 36, 36, 32 +; CHECK-FISL: xxland 36, 37, 36 +; CHECK-FISL: vor 2, 4, 4 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test17 @@ -434,12 +429,18 @@ entry: ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} ; CHECK-REG: blr +; FIXME: The fast-isel code is pretty miserable for this one. + ; CHECK-FISL-LABEL: @test20 -; CHECK-FISL: vcmpequw 4, 4, 5 -; CHECK-FISL: vor 0, 3, 3 -; CHECK-FISL: vor 1, 2, 2 -; CHECK-FISL: vor 6, 4, 4 -; CHECK-FISL: xxsel 32, 32, 33, 38 +; CHECK-FISL: vor 0, 5, 5 +; CHECK-FISL: vor 1, 4, 4 +; CHECK-FISL: vor 6, 3, 3 +; CHECK-FISL: vor 7, 2, 2 +; CHECK-FISL: vor 2, 1, 1 +; CHECK-FISL: vor 3, 0, 0 +; CHECK-FISL: vcmpequw 2, 2, 3 +; CHECK-FISL: vor 0, 2, 2 +; CHECK-FISL: xxsel 32, 38, 39, 32 ; CHECK-FISL: vor 2, 0, 0 ; CHECK-FISL: blr @@ -794,8 +795,6 @@ define <4 x i32> @test34(<4 x i32>* %a) { ; CHECK-FISL-LABEL: @test34 ; CHECK-FISL: lxvw4x 0, 0, 3 ; CHECK-FISL: xxlor 34, 0, 0 -; CHECK-FISL: vor 3, 2, 2 -; CHECK-FISL: vor 2, 3, 3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test34 diff --git a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll index 84bbdd75b0f73..6c89b1092bdfc 100644 --- a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll +++ b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll @@ -8,9 +8,9 @@ define <2 x double> @testi0(<2 x double>* %p1, double* %p2) { ; CHECK-LABEL: testi0 ; CHECK: lxvd2x 0, 0, 3 -; CHECK: lxsdx 34, 0, 4 +; CHECK: lxsdx 1, 0, 4 ; CHECK: xxswapd 0, 0 -; CHECK: xxspltd 1, 34, 0 +; CHECK: xxspltd 1, 1, 0 ; CHECK: xxpermdi 34, 0, 1, 1 } @@ -22,9 +22,9 @@ define <2 x double> @testi1(<2 x double>* %p1, double* %p2) { ; CHECK-LABEL: testi1 ; CHECK: lxvd2x 0, 0, 3 -; CHECK: lxsdx 34, 0, 4 +; CHECK: lxsdx 1, 0, 4 ; CHECK: xxswapd 0, 0 -; CHECK: xxspltd 1, 34, 0 +; CHECK: xxspltd 1, 1, 0 ; CHECK: xxmrgld 34, 1, 0 } diff --git a/test/CodeGen/PowerPC/xvcmpeqdp-v2f64.ll b/test/CodeGen/PowerPC/xvcmpeqdp-v2f64.ll new file mode 100644 index 0000000000000..ef63233e746b2 --- /dev/null +++ b/test/CodeGen/PowerPC/xvcmpeqdp-v2f64.ll @@ -0,0 +1,38 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @__fmax_double3_3D_exec() #0 { +entry: + br i1 undef, label %if.then.i, label %fmax_double3.exit + +if.then.i: ; preds = %entry + %cmp24.i.i = fcmp ord <3 x double> undef, zeroinitializer + %sext25.i.i = sext <3 x i1> %cmp24.i.i to <3 x i64> + %neg.i.i = xor <3 x i64> %sext25.i.i, <i64 -1, i64 -1, i64 -1> + %or.i.i = or <3 x i64> undef, %neg.i.i + %neg.i.i.i = select <3 x i1> undef, <3 x i64> zeroinitializer, <3 x i64> %sext25.i.i + %and.i.i.i = and <3 x i64> undef, %neg.i.i.i + %and26.i.i.i = and <3 x i64> undef, %or.i.i + %or.i.i.i = or <3 x i64> %and.i.i.i, %and26.i.i.i + %astype32.i.i.i = bitcast <3 x i64> %or.i.i.i to <3 x double> + %extractVec33.i.i.i = shufflevector <3 x double> %astype32.i.i.i, <3 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> + store <4 x double> %extractVec33.i.i.i, <4 x double>* undef, align 32 + br label %fmax_double3.exit + +; CHECK-LABEL: @__fmax_double3_3D_exec +; CHECK: xvcmpeqdp + +fmax_double3.exit: ; preds = %if.then.i, %entry + br i1 undef, label %if.then, label %do.end + +if.then: ; preds = %fmax_double3.exit + unreachable + +do.end: ; preds = %fmax_double3.exit + ret void +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/SystemZ/args-04.ll b/test/CodeGen/SystemZ/args-04.ll index 1178bb4dafdf7..48a2cf4910493 100644 --- a/test/CodeGen/SystemZ/args-04.ll +++ b/test/CodeGen/SystemZ/args-04.ll @@ -124,3 +124,17 @@ define void @f13(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2, store fp128 %y, fp128 *%r2 ret void } + +; Explicit fp128 return values are likewise passed indirectly. +define fp128 @f14(fp128 %r3) { +; CHECK-LABEL: f14: +; CHECK: ld %f0, 0(%r3) +; CHECK: ld %f2, 8(%r3) +; CHECK: axbr %f0, %f0 +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %y = fadd fp128 %r3, %r3 + ret fp128 %y +} + diff --git a/test/CodeGen/SystemZ/args-07.ll b/test/CodeGen/SystemZ/args-07.ll new file mode 100644 index 0000000000000..29d9b319ffc00 --- /dev/null +++ b/test/CodeGen/SystemZ/args-07.ll @@ -0,0 +1,60 @@ +; Test multiple return values (LLVM ABI extension) +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Up to four integer return values fit into GPRs. +define { i64, i64, i64, i64 } @f1() { +; CHECK-LABEL: f1: +; CHECK: lghi %r2, 0 +; CHECK: lghi %r3, 1 +; CHECK: lghi %r4, 2 +; CHECK: lghi %r5, 3 +; CHECK: br %r14 + ret { i64, i64, i64, i64 } { i64 0, i64 1, i64 2, i64 3 } +} + +; More than four integer return values use sret. +define { i64, i64, i64, i64, i64 } @f2() { +; CHECK-LABEL: f2: +; CHECK: mvghi 32(%r2), 4 +; CHECK: mvghi 24(%r2), 3 +; CHECK: mvghi 16(%r2), 2 +; CHECK: mvghi 8(%r2), 1 +; CHECK: mvghi 0(%r2), 0 +; CHECK: br %r14 + ret { i64, i64, i64, i64, i64 } { i64 0, i64 1, i64 2, i64 3, i64 4 } +} + +; Up to four floating-point return values fit into FPRs. +define { double, double, double, double } @f3() { +; CHECK-LABEL: f3: +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: ldeb %f0, 0([[TMP]]) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: ldeb %f2, 0([[TMP]]) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: ldeb %f4, 0([[TMP]]) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: ldeb %f6, 0([[TMP]]) +; CHECK: br %r14 + ret { double, double, double, double } + { double 1.0, double 2.0, double 3.0, double 4.0 } +} + +; More than four floating-point return values use sret. +define { double, double, double, double, double } @f4() { +; CHECK-LABEL: f4: +; CHECK: llihh [[TMP:%r[0-5]]], 16404 +; CHECK: stg [[TMP]], 32(%r2) +; CHECK: llihh [[TMP:%r[0-5]]], 16400 +; CHECK: stg [[TMP]], 24(%r2) +; CHECK: llihh [[TMP:%r[0-5]]], 16392 +; CHECK: stg [[TMP]], 16(%r2) +; CHECK: llihh [[TMP:%r[0-5]]], 16384 +; CHECK: stg [[TMP]], 8(%r2) +; CHECK: llihh [[TMP:%r[0-5]]], 16368 +; CHECK: stg [[TMP]], 0(%r2) +; CHECK: br %r14 + ret { double, double, double, double, double } + { double 1.0, double 2.0, double 3.0, double 4.0, double 5.0 } +} diff --git a/test/CodeGen/SystemZ/args-08.ll b/test/CodeGen/SystemZ/args-08.ll new file mode 100644 index 0000000000000..0bad5a8989dc0 --- /dev/null +++ b/test/CodeGen/SystemZ/args-08.ll @@ -0,0 +1,57 @@ +; Test calling functions with multiple return values (LLVM ABI extension) +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Up to four integer return values fit into GPRs. +declare { i64, i64, i64, i64 } @bar1() + +define i64 @f1() { +; CHECK-LABEL: f1: +; CHECK: brasl %r14, bar1 +; CHECK: lgr %r2, %r5 +; CHECK: br %r14 + %mret = call { i64, i64, i64, i64 } @bar1() + %ret = extractvalue { i64, i64, i64, i64 } %mret, 3 + ret i64 %ret +} + +; More than four integer return values use sret. +declare { i64, i64, i64, i64, i64 } @bar2() + +define i64 @f2() { +; CHECK-LABEL: f2: +; CHECK: la %r2, 160(%r15) +; CHECK: brasl %r14, bar2 +; CHECK: lg %r2, 192(%r15) +; CHECK: br %r14 + %mret = call { i64, i64, i64, i64, i64 } @bar2() + %ret = extractvalue { i64, i64, i64, i64, i64 } %mret, 4 + ret i64 %ret +} + +; Up to four floating-point return values fit into GPRs. +declare { double, double, double, double } @bar3() + +define double @f3() { +; CHECK-LABEL: f3: +; CHECK: brasl %r14, bar3 +; CHECK: ldr %f0, %f6 +; CHECK: br %r14 + %mret = call { double, double, double, double } @bar3() + %ret = extractvalue { double, double, double, double } %mret, 3 + ret double %ret +} + +; More than four integer return values use sret. +declare { double, double, double, double, double } @bar4() + +define double @f4() { +; CHECK-LABEL: f4: +; CHECK: la %r2, 160(%r15) +; CHECK: brasl %r14, bar4 +; CHECK: ld %f0, 192(%r15) +; CHECK: br %r14 + %mret = call { double, double, double, double, double } @bar4() + %ret = extractvalue { double, double, double, double, double } %mret, 4 + ret double %ret +} diff --git a/test/CodeGen/SystemZ/vec-args-06.ll b/test/CodeGen/SystemZ/vec-args-06.ll new file mode 100644 index 0000000000000..b26131ca1d4e5 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-06.ll @@ -0,0 +1,83 @@ +; Test multiple return values (LLVM ABI extension) +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Up to eight vector return values fit into VRs. +define { <2 x double>, <2 x double>, <2 x double>, <2 x double>, + <2 x double>, <2 x double>, <2 x double>, <2 x double> } @f1() { +; CHECK-LABEL: f1: +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl %v24, 0([[TMP]]) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl %v26, 0([[TMP]]) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl %v28, 0([[TMP]]) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl %v30, 0([[TMP]]) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl %v25, 0([[TMP]]) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl %v27, 0([[TMP]]) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl %v29, 0([[TMP]]) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl %v31, 0([[TMP]]) +; CHECK: br %r14 + ret { <2 x double>, <2 x double>, <2 x double>, <2 x double>, + <2 x double>, <2 x double>, <2 x double>, <2 x double> } + { <2 x double> <double 1.0, double 1.1>, + <2 x double> <double 2.0, double 2.1>, + <2 x double> <double 3.0, double 3.1>, + <2 x double> <double 4.0, double 4.1>, + <2 x double> <double 5.0, double 5.1>, + <2 x double> <double 6.0, double 6.1>, + <2 x double> <double 7.0, double 7.1>, + <2 x double> <double 8.0, double 8.1> } +} + +; More than eight vector return values use sret. +define { <2 x double>, <2 x double>, <2 x double>, <2 x double>, + <2 x double>, <2 x double>, <2 x double>, <2 x double>, + <2 x double> } @f2() { +; CHECK-LABEL: f2: +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) +; CHECK: vst [[VTMP]], 128(%r2) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) +; CHECK: vst [[VTMP]], 112(%r2) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) +; CHECK: vst [[VTMP]], 96(%r2) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) +; CHECK: vst [[VTMP]], 80(%r2) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) +; CHECK: vst [[VTMP]], 64(%r2) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) +; CHECK: vst [[VTMP]], 48(%r2) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) +; CHECK: vst [[VTMP]], 32(%r2) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) +; CHECK: vst [[VTMP]], 16(%r2) +; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) +; CHECK: vst [[VTMP]], 0(%r2) +; CHECK: br %r14 + ret { <2 x double>, <2 x double>, <2 x double>, <2 x double>, + <2 x double>, <2 x double>, <2 x double>, <2 x double>, + <2 x double> } + { <2 x double> <double 1.0, double 1.1>, + <2 x double> <double 2.0, double 2.1>, + <2 x double> <double 3.0, double 3.1>, + <2 x double> <double 4.0, double 4.1>, + <2 x double> <double 5.0, double 5.1>, + <2 x double> <double 6.0, double 6.1>, + <2 x double> <double 7.0, double 7.1>, + <2 x double> <double 8.0, double 8.1>, + <2 x double> <double 9.0, double 9.1> } +} diff --git a/test/CodeGen/SystemZ/vec-args-07.ll b/test/CodeGen/SystemZ/vec-args-07.ll new file mode 100644 index 0000000000000..f0b5e6835cfe5 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-07.ll @@ -0,0 +1,47 @@ +; Test calling functions with multiple return values (LLVM ABI extension) +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Up to eight vector return values fit into VRs. +declare { <2 x double>, <2 x double>, <2 x double>, <2 x double>, + <2 x double>, <2 x double>, <2 x double>, <2 x double> } @bar1() + +define <2 x double> @f1() { +; CHECK-LABEL: f1: +; CHECK: brasl %r14, bar1 +; CHECK: vlr %v24, %v31 +; CHECK: br %r14 + %mret = call { <2 x double>, <2 x double>, + <2 x double>, <2 x double>, + <2 x double>, <2 x double>, + <2 x double>, <2 x double> } @bar1() + %ret = extractvalue { <2 x double>, <2 x double>, + <2 x double>, <2 x double>, + <2 x double>, <2 x double>, + <2 x double>, <2 x double> } %mret, 7 + ret <2 x double> %ret +} + +; More than eight vector return values use sret. +declare { <2 x double>, <2 x double>, <2 x double>, <2 x double>, + <2 x double>, <2 x double>, <2 x double>, <2 x double>, + <2 x double> } @bar2() + +define <2 x double> @f2() { +; CHECK-LABEL: f2: +; CHECK: la %r2, 160(%r15) +; CHECK: brasl %r14, bar2 +; CHECK: vl %v24, 288(%r15) +; CHECK: br %r14 + %mret = call { <2 x double>, <2 x double>, + <2 x double>, <2 x double>, + <2 x double>, <2 x double>, + <2 x double>, <2 x double>, + <2 x double> } @bar2() + %ret = extractvalue { <2 x double>, <2 x double>, + <2 x double>, <2 x double>, + <2 x double>, <2 x double>, + <2 x double>, <2 x double>, + <2 x double> } %mret, 8 + ret <2 x double> %ret +} diff --git a/test/CodeGen/X86/fdiv-combine.ll b/test/CodeGen/X86/fdiv-combine.ll index 34eac62e36733..b65e9d01ab8ba 100644 --- a/test/CodeGen/X86/fdiv-combine.ll +++ b/test/CodeGen/X86/fdiv-combine.ll @@ -44,5 +44,24 @@ define double @div3_arcp(double %x, double %y, double %z) #0 { ret double %ret } +define void @PR24141() #0 { +; CHECK-LABEL: PR24141: +; CHECK: callq +; CHECK-NEXT: divsd +; CHECK-NEXT: jmp +entry: + br label %while.body + +while.body: + %x.0 = phi double [ undef, %entry ], [ %div, %while.body ] + %call = call { double, double } @g(double %x.0) + %xv0 = extractvalue { double, double } %call, 0 + %xv1 = extractvalue { double, double } %call, 1 + %div = fdiv double %xv0, %xv1 + br label %while.body +} + +declare { double, double } @g(double) + ; FIXME: If the backend understands 'arcp', then this attribute is unnecessary. attributes #0 = { "unsafe-fp-math"="true" } diff --git a/test/CodeGen/X86/machine-trace-metrics-crash.ll b/test/CodeGen/X86/machine-trace-metrics-crash.ll new file mode 100644 index 0000000000000..1d0ee79f04a96 --- /dev/null +++ b/test/CodeGen/X86/machine-trace-metrics-crash.ll @@ -0,0 +1,62 @@ +; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse -enable-unsafe-fp-math < %s | FileCheck %s + +; The debug info in this test case was causing a crash because machine trace metrics +; did not correctly ignore debug instructions. The check lines ensure that the +; machine-combiner pass has run, reassociated the add operands, and therefore +; used machine trace metrics. + +define void @PR24199() { +; CHECK-LABEL: PR24199: +; CHECK: addss %xmm1, %xmm0 +; CHECK: addss %xmm2, %xmm0 + +entry: + %i = alloca %struct.A, align 8 + %tobool = icmp ne i32 undef, 0 + br i1 undef, label %if.end, label %if.then + +if.then: + br label %if.end + +if.end: + %h = phi float [ 0.0, %if.then ], [ 4.0, %entry ] + call void @foo(%struct.A* nonnull undef) + tail call void @llvm.dbg.value(metadata %struct.A* undef, i64 0, metadata !5, metadata !4), !dbg !6 + tail call void @llvm.dbg.value(metadata float %h, i64 0, metadata !5, metadata !4), !dbg !6 + %n0 = load float, float* undef, align 4 + %mul = fmul fast float %n0, %h + %add = fadd fast float %mul, 1.0 + tail call void @llvm.dbg.value(metadata %struct.A* undef, i64 0, metadata !5, metadata !4), !dbg !6 + tail call void @llvm.dbg.value(metadata float %add, i64 0, metadata !5, metadata !4), !dbg !6 + %add.i = fadd fast float %add, %n0 + store float %add.i, float* undef, align 4 + %n1 = bitcast %struct.A* %i to i8* + call void @llvm.lifetime.start(i64 16, i8* %n1) + %n2 = load <2 x float>, <2 x float>* undef, align 8 + %conv = uitofp i1 %tobool to float + %bitcast = extractelement <2 x float> %n2, i32 0 + %factor = fmul fast float %bitcast, 2.0 + %add3 = fadd fast float %factor, %conv + call void @bar(float %add3) + ret void +} + +%struct.A = type { float, float } + +declare void @bar(float) +declare void @foo(%struct.A*) +declare void @llvm.lifetime.start(i64, i8* nocapture) +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: 1) +!1 = !DIFile(filename: "24199.cpp", directory: "/bin") +!2 = !{i32 2, !"Debug Info Version", i32 3} +!3 = !DISubprogram(linkageName: "foo", file: !1, line: 18, isLocal: false, isDefinition: true, scopeLine: 18, function: void (%struct.A*)* @foo) +!4 = !DIExpression() +!5 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "this", arg: 1, scope: !3, flags: DIFlagArtificial | DIFlagObjectPointer) +!6 = !DILocation(line: 0, scope: !3) + + diff --git a/test/CodeGen/X86/pr2656.ll b/test/CodeGen/X86/pr2656.ll index 9a162d77ef48c..095ab831d48d7 100644 --- a/test/CodeGen/X86/pr2656.ll +++ b/test/CodeGen/X86/pr2656.ll @@ -1,15 +1,24 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s ; PR2656 -; CHECK: {{xorps.*sp}} -; CHECK-NOT: {{xorps.*sp}} - target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i686-apple-darwin9.4.0" %struct.anon = type <{ float, float }> @.str = internal constant [17 x i8] c"pt: %.0f, %.0f\0A\00\00" ; <[17 x i8]*> [#uses=1] +; We can not fold either stack load into an 'xor' instruction because that +; would change what should be a 4-byte load into a 16-byte load. +; We can fold the 16-byte constant load into either 'xor' instruction, +; but we do not. It has more than one use, so it gets loaded into a register. + define void @foo(%struct.anon* byval %p) nounwind { +; CHECK-LABEL: foo: +; CHECK: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; CHECK-NEXT: movaps {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] +; CHECK-NEXT: xorps %xmm2, %xmm0 +; CHECK-NEXT: cvtss2sd %xmm0, %xmm0 +; CHECK-NEXT: xorps %xmm2, %xmm1 entry: %tmp = getelementptr %struct.anon, %struct.anon* %p, i32 0, i32 0 ; <float*> [#uses=1] %tmp1 = load float, float* %tmp ; <float> [#uses=1] @@ -24,3 +33,20 @@ entry: } declare i32 @printf(...) + +; We can not fold the load from the stack into the 'and' instruction because +; that changes an 8-byte load into a 16-byte load (illegal memory access). +; We can fold the load of the constant because it is a 16-byte vector constant. + +define double @PR22371(double %x) { +; CHECK-LABEL: PR22371: +; CHECK: movsd 16(%esp), %xmm0 +; CHECK-NEXT: andpd LCPI1_0, %xmm0 +; CHECK-NEXT: movlpd %xmm0, (%esp) + %call = tail call double @fabs(double %x) #0 + ret double %call +} + +declare double @fabs(double) #0 +attributes #0 = { readnone } + diff --git a/test/CodeGen/X86/sse-fcopysign.ll b/test/CodeGen/X86/sse-fcopysign.ll index 25634b5472aa9..8a5462bea82d0 100644 --- a/test/CodeGen/X86/sse-fcopysign.ll +++ b/test/CodeGen/X86/sse-fcopysign.ll @@ -55,12 +55,12 @@ declare double @copysign(double, double) define float @int1(float %a, float %b) { ; X32-LABEL: @int1 -; X32: movss 12(%esp), %xmm0 {{.*#+}} xmm0 = mem[0],zero,zero,zero -; X32-NEXT: movss 8(%esp), %xmm1 {{.*#+}} xmm1 = mem[0],zero,zero,zero -; X32-NEXT: andps .LCPI2_0, %xmm1 -; X32-NEXT: andps .LCPI2_1, %xmm0 -; X32-NEXT: orps %xmm1, %xmm0 -; X32-NEXT: movss %xmm0, (%esp) +; X32: movss 8(%esp), %xmm0 {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X32-NEXT: andps .LCPI2_0, %xmm0 +; X32-NEXT: movss 12(%esp), %xmm1 {{.*#+}} xmm1 = mem[0],zero,zero,zero +; X32-NEXT: andps .LCPI2_1, %xmm1 +; X32-NEXT: orps %xmm0, %xmm1 +; X32-NEXT: movss %xmm1, (%esp) ; X32-NEXT: flds (%esp) ; X32-NEXT: popl %eax ; X32-NEXT: retl @@ -76,14 +76,14 @@ define float @int1(float %a, float %b) { define double @int2(double %a, float %b, float %c) { ; X32-LABEL: @int2 -; X32: movsd 8(%ebp), %xmm0 {{.*#+}} xmm0 = mem[0],zero -; X32-NEXT: movss 16(%ebp), %xmm1 {{.*#+}} xmm1 = mem[0],zero,zero,zero -; X32-NEXT: addss 20(%ebp), %xmm1 -; X32-NEXT: andpd .LCPI3_0, %xmm0 -; X32-NEXT: cvtss2sd %xmm1, %xmm1 -; X32-NEXT: andpd .LCPI3_1, %xmm1 -; X32-NEXT: orpd %xmm0, %xmm1 -; X32-NEXT: movsd %xmm1, (%esp) +; X32: movss 16(%ebp), %xmm0 {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X32-NEXT: addss 20(%ebp), %xmm0 +; X32-NEXT: movsd 8(%ebp), %xmm1 {{.*#+}} xmm1 = mem[0],zero +; X32-NEXT: andpd .LCPI3_0, %xmm1 +; X32-NEXT: cvtss2sd %xmm0, %xmm0 +; X32-NEXT: andpd .LCPI3_1, %xmm0 +; X32-NEXT: orpd %xmm1, %xmm0 +; X32-NEXT: movlpd %xmm0, (%esp) ; X32-NEXT: fldl (%esp) ; X32-NEXT: movl %ebp, %esp ; X32-NEXT: popl %ebp @@ -91,9 +91,9 @@ define double @int2(double %a, float %b, float %c) { ; ; X64-LABEL: @int2 ; X64: addss %xmm2, %xmm1 -; X64-NEXT: andpd .LCPI3_0(%rip), %xmm0 ; X64-NEXT: cvtss2sd %xmm1, %xmm1 -; X64-NEXT: andpd .LCPI3_1(%rip), %xmm1 +; X64-NEXT: andpd .LCPI3_0(%rip), %xmm1 +; X64-NEXT: andpd .LCPI3_1(%rip), %xmm0 ; X64-NEXT: orpd %xmm1, %xmm0 ; X64-NEXT: retq %tmp1 = fadd float %b, %c diff --git a/test/CodeGen/X86/vec_fabs.ll b/test/CodeGen/X86/vec_fabs.ll index bfefbcf5ebd3c..960b5f27cf535 100644 --- a/test/CodeGen/X86/vec_fabs.ll +++ b/test/CodeGen/X86/vec_fabs.ll @@ -4,7 +4,7 @@ define <2 x double> @fabs_v2f64(<2 x double> %p) { ; CHECK-LABEL: fabs_v2f64 - ; CHECK: vandps + ; CHECK: vandpd %t = call <2 x double> @llvm.fabs.v2f64(<2 x double> %p) ret <2 x double> %t } @@ -22,7 +22,7 @@ declare <4 x float> @llvm.fabs.v4f32(<4 x float> %p) define <4 x double> @fabs_v4f64(<4 x double> %p) { ; CHECK-LABEL: fabs_v4f64 - ; CHECK: vandps + ; CHECK: vandpd %t = call <4 x double> @llvm.fabs.v4f64(<4 x double> %p) ret <4 x double> %t } |