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* Expand generic subword atomic primitivesConrad Meyer2020-03-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The goal of this change is to make the atomic_load_acq_{8,16}, atomic_testandset{,_acq}_long, and atomic_testandclear_long primitives available in MI-namespace. The second goal is to get this draft out of my local tree, as anything that requires a full tinderbox is a big burden out of tree. MD specifics can be refined individually afterwards. The generic implementations may not be ideal for your architecture; feel free to implement better versions. If no subword_atomic definitions are needed, the include can be removed from your arch's machine/atomic.h. Generic definitions are guarded by defined macros of the same name. To avoid picking up conflicting generic definitions, some macro defines are added to various MD machine/atomic.h to register an existing implementation. Include _atomic_subword.h in arm and arm64 machine/atomic.h. For some odd reason, KCSAN only generates some versions of primitives. Generate the _acq variants of atomic_load.*_8, atomic_load.*_16, and atomic_testandset.*_long. There are other questionably disabled primitives, but I didn't run into them, so I left them alone. KCSAN is only built for amd64 in tinderbox for now. Add atomic_subword implementations of atomic_load_acq_{8,16} implemented using masking and atomic_load_acq_32. Add generic atomic_subword implementations of atomic_testandset_long(), atomic_testandclear_long(), and atomic_testandset_acq_long(), using atomic_fcmpset_long() and atomic_fcmpset_acq_long(). On x86, add atomic_testandset_acq_long as an alias for atomic_testandset_long. Reviewed by: kevans, rlibby (previous versions both) Differential Revision: https://reviews.freebsd.org/D22963 Notes: svn path=/head/; revision=359311
* amd64 atomic.h: minor codegen optimization in flag accessRyan Libby2020-02-281-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously the pattern to extract status flags from inline assembly blocks was to use setcc in the block to write the flag to a register. This was suboptimal in a few ways: - It would lead to code like: sete %cl; test %cl; jne, i.e. a flag would just be loaded into a register and then reloaded to a flag. - The setcc would force the block to use an additional register. - If the client code didn't care for the flag value then the setcc would be entirely pointless but could not be eliminated by the optimizer. A more modern inline asm construct (since gcc 6 and clang 9) allows for "flag output operands", where a C variable can be written directly from a flag. The optimizer can then use this to produce direct code where the flag does not take a trip through a register. In practice this makes each affected operation sequence shorter by five bytes of instructions. It's unlikely this has a measurable performance impact. Reviewed by: kib, markj, mjg Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D23869 Notes: svn path=/head/; revision=358439
* Port the NetBSD KCSAN runtime to FreeBSD.Andrew Turner2019-11-211-9/+16
| | | | | | | | | | | | | | | | Update the NetBSD Kernel Concurrency Sanitizer (KCSAN) runtime to work in the FreeBSD kernel. It is a useful tool for finding data races between threads executing on different CPUs. This can be enabled by enabling KCSAN in the kernel config, or by using the GENERIC-KCSAN amd64 kernel. It works on amd64 and arm64, however the later needs a compiler change to allow -fsanitize=thread that KCSAN uses. Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D22315 Notes: svn path=/head/; revision=354942
* Make sure kernel modules built by default are portable between UP andHans Petter Selasky2018-07-061-2/+2
| | | | | | | | | | | | SMP systems by extending defined(SMP) to include defined(KLD_MODULE). This is a regression issue after r335873 . Discussed with: mmacy@ Sponsored by: Mellanox Technologies Notes: svn path=/head/; revision=336025
* Use 'e' instead of 'i' constraints with 64-bit atomic operations on amd64.John Baldwin2018-07-031-4/+4
| | | | | | | | | | | | | | | | | | The ADD, AND, OR, and SUB instructions take at most a 32-bit sign-extended immediate operand. 64-bit constants that do not fit into that constraint need to be loaded into a register. The 'i' constraint tells the compiler it can pass any integer constant to the assembler, whereas the 'e' constrain only permits constants that fit into a 32-bit sign-extended value. This fixes using atomic_add/clear/set/subtract_long/64 with constants that do not fit into a 32-bit sign-extended immediate. Reported by: several folks Tested by: Pete Wright <pete@nomadlogic.org> MFC after: 2 weeks Notes: svn path=/head/; revision=335913
* inline atomics and allow tied modules to inline locksMatt Macy2018-07-021-1/+1
| | | | | | | | | | | | | | - inline atomics in modules on i386 and amd64 (they were always inline on other arches) - allow modules to opt in to inlining locks by specifying MODULE_TIED=1 in the makefile Reviewed by: kib Sponsored by: Limelight Networks Differential Revision: https://reviews.freebsd.org/D16079 Notes: svn path=/head/; revision=335873
* Add atomic_load(9) and atomic_store(9) operations.Konstantin Belousov2017-12-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | They provide relaxed-ordered atomic access semantic. Due to the FreeBSD memory model, the operations are syntaxical wrappers around the volatile accesses. The volatile qualifier is used to ensure that the access not optimized out and in turn depends on the volatile semantic as implemented by supported compilers. The motivation for adding the operation is to help people coming from other systems or knowing the C11/C++ standards where atomics have special type and require use of the special access operations. It is still the case that FreeBSD requires plain load and stores of aligned integer types to be atomic. Suggested by: jhb Reviewed by: alc, jhb Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D13534 Notes: svn path=/head/; revision=326971
* sys/amd64: further adoption of SPDX licensing ID tags.Pedro F. Giffuni2017-11-271-0/+2
| | | | | | | | | | | | | | | Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts. Notes: svn path=/head/; revision=326257
* - Remove 'struct vmmeter' from 'struct pcpu', leaving only global vmmeterGleb Smirnoff2017-04-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | in place. To do per-cpu stats, convert all fields that previously were maintained in the vmmeters that sit in pcpus to counter(9). - Since some vmmeter stats may be touched at very early stages of boot, before we have set up UMA and we can do counter_u64_alloc(), provide an early counter mechanism: o Leave one spare uint64_t in struct pcpu, named pc_early_dummy_counter. o Point counter(9) fields of vmmeter to pcpu[0].pc_early_dummy_counter, so that at early stages of boot, before counters are allocated we already point to a counter that can be safely written to. o For sparc64 that required a whole dummy pcpu[MAXCPU] array. Further related changes: - Don't include vmmeter.h into pcpu.h. - vm.stats.vm.v_swappgsout and vm.stats.vm.v_swappgsin changed to 64-bit, to match kernel representation. - struct vmmeter hidden under _KERNEL, and only vmstat(1) is an exclusion. This is based on benno@'s 4-year old patch: https://lists.freebsd.org/pipermail/freebsd-arch/2013-July/014471.html Reviewed by: kib, gallatin, marius, lidl Differential Revision: https://reviews.freebsd.org/D10156 Notes: svn path=/head/; revision=317061
* Add support for 8- and 16-bit atomic_(f)cmpset to x86.Mark Johnston2017-03-221-77/+79
| | | | | | | | | Reviewed by: kib MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D10068 Notes: svn path=/head/; revision=315718
* amd64: add atomic_fcmpsetMateusz Guzik2017-01-031-0/+51
| | | | | | | Reviewed by: kib, jhb Notes: svn path=/head/; revision=311169
* atomic: Add testandclear on i386/amd64Sepherosa Ziehau2016-05-161-0/+38
| | | | | | | | | Reviewed by: kib Sponsored by: Microsoft OSTC Differential Revision: https://reviews.freebsd.org/D6381 Notes: svn path=/head/; revision=299912
* Add missing atomic wrapper macro.Hans Petter Selasky2016-01-211-0/+1
| | | | | | | | | Reviewed by: alfred @ Sponsored by: Mellanox Technologies MFC after: 1 week Notes: svn path=/head/; revision=294526
* Improve comments.Konstantin Belousov2015-07-301-4/+4
| | | | | | | | Submitted by: bde MFC after: 2 weeks Notes: svn path=/head/; revision=286078
* Remove full barrier from the amd64 atomic_load_acq_*(). StrongKonstantin Belousov2015-07-281-17/+7
| | | | | | | | | | | | | | | | | | | | ordering semantic of x86 CPUs makes only the compiler barrier neccessary to give the acquire behaviour. Existing implementation ensured sequentially consistent semantic for load_acq, making much stronger guarantee than required by standard's definition of the load acquire. Consumers which depend on the barrier are believed to be identified and already fixed to use proper operations. Noted by: alc (long time ago) Reviewed by: alc, bde Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Notes: svn path=/head/; revision=285934
* Add a comment discussing the appropriate use of the atomic_*() functionsAlan Cox2015-07-241-0/+19
| | | | | | | | | | | with acquire and release semantics versus the *mb() functions on amd64 processors. Reviewed by: bde (an earlier version), kib Sponsored by: EMC / Isilon Storage Division Notes: svn path=/head/; revision=285854
* Add the atomic_thread_fence() family of functions with intent toKonstantin Belousov2015-07-081-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | provide a semantic defined by the C11 fences with corresponding memory_order. atomic_thread_fence_acq() gives r | r, w, where r and w are read and write accesses, and | denotes the fence itself. atomic_thread_fence_rel() is r, w | w. atomic_thread_fence_acq_rel() is the combination of the acquire and release in single operation. Note that reads after the acq+rel fence could be made visible before writes preceeding the fence. atomic_thread_fence_seq_cst() orders all accesses before/after the fence, and the fence itself is globally ordered against other sequentially consistent atomic operations. Reviewed by: alc Discussed with: bde Sponsored by: The FreeBSD Foundation MFC after: 3 weeks Notes: svn path=/head/; revision=285283
* Add a comment about too strong semantic of atomic_load_acq() on x86.Konstantin Belousov2015-06-291-0/+9
| | | | | | | | Submitted by: bde MFC after: 2 weeks Notes: svn path=/head/; revision=284922
* Remove unneeded data dependency, currently imposed byKonstantin Belousov2015-06-281-50/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | atomic_load_acq(9), on it source, for x86. Right now, atomic_load_acq() on x86 is sequentially consistent with other atomics, code ensures this by doing store/load barrier by performing locked nop on the source. Provide separate primitive __storeload_barrier(), which is implemented as the locked nop done on a cpu-private variable, and put __storeload_barrier() before load, to keep seq_cst semantic but avoid introducing false dependency on the no-modification of the source for its later use. Note that seq_cst property of x86 atomic_load_acq() is not documented and not carried by atomics implementations on other architectures, although some kernel code relies on the behaviour. This commit does not intend to change this. Reviewed by: alc Discussed with: bde Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Notes: svn path=/head/; revision=284901
* Remove empty lines before return statements for style consistency.Jung-uk Kim2013-08-211-5/+0
| | | | Notes: svn path=/head/; revision=254618
* Implement atomic_swap() and atomic_testandset().Jung-uk Kim2013-08-211-15/+57
| | | | | | | Reviewed by: arch, bde, jilles, kib Notes: svn path=/head/; revision=254617
* - Remove the "a" constraint from main output operand for atomic_cmpset().Jung-uk Kim2013-08-211-10/+10
| | | | | | | - Use "+" modifier for the "expect" because it is also an output (unused). Notes: svn path=/head/; revision=254614
* Use '+' modifier for a memory operand that is both an input and an output.Jung-uk Kim2013-08-211-23/+16
| | | | | | | | | It was actually done in r86301 but reverted in r150182 because GCC 3.x was not able to handle it for a memory operand. Apparently, this problem was fixed in GCC 4.1+ and several contrib sources already rely on this feature. Notes: svn path=/head/; revision=254612
* Remove bogus labels. No functional change.Jung-uk Kim2013-08-211-2/+0
| | | | Notes: svn path=/head/; revision=254611
* Use consistent style. No functional change.Jung-uk Kim2013-08-211-12/+12
| | | | Notes: svn path=/head/; revision=254610
* Add an unified macro to deny ability from the compiler to reorderAttilio Rao2012-10-091-2/+2
| | | | | | | | | | | | | instruction loads/stores at its will. The macro __compiler_membar() is currently supported for both gcc and clang, but kernel compilation will fail otherwise. Reviewed by: bde, kib Discussed with: dim, theraven MFC after: 2 weeks Notes: svn path=/head/; revision=241374
* Use plain store for atomic_store_rel on x86, instead of implicitlyKonstantin Belousov2012-06-021-37/+37
| | | | | | | | | | | | locked xchg instruction. IA32 memory model guarantees that store has release semantic, since stores cannot pass loads or stores. Reviewed by: bde, jhb Tested by: pho MFC after: 2 weeks Notes: svn path=/head/; revision=236456
* Inform a compiler which asm statements in the x86 implementation ofKonstantin Belousov2010-12-181-9/+10
| | | | | | | | | | atomics change eflags. Reviewed by: jhb MFC after: 2 weeks Notes: svn path=/head/; revision=216524
* Rename an argument from "exp" to "expect" since the former makes FlexeLintPoul-Henning Kamp2010-05-201-7/+7
| | | | | | | | | uneasy, in case anybody think it might be exp(3) in libm. This also makes it consistent with other archs. Notes: svn path=/head/; revision=208332
* atomic_cmpset_barr_* was added in order to cope with compilers willing toAttilio Rao2009-10-091-32/+44
| | | | | | | | | | | | | | | | | | | | specify their own version of atomic_cmpset_* which could have been different than the membar version. Right now, however, FreeBSD is bound mostly to GCC-like compilers and it is desired to add new support and compat shim mostly when there is a real necessity, in order to avoid too much compatibility bloats. In this optic, bring back atomic_cmpset_{acq, rel}_* to be the same as atomic_cmpset_* and unwind the atomic_cmpset_barr_* introduction. Requested by: jhb Reviewed by: jhb Tested by: Giovanni Trematerra <giovanni dot trematerra at gmail dot com> Notes: svn path=/head/; revision=197910
* - All the functions in atomic.h needs to be in "physical" form (likeAttilio Rao2009-10-061-46/+29
| | | | | | | | | | | | | | | not defined through macros or similar) in order to be later compiled in the kernel and offer this way the support for modules (and compatibility among the UP case and SMP case). Fix this for the newly introduced atomic_cmpset_barr_* cases by defining and specifying a template. Note that the new DEFINE_CMPSET_GEN() template save more typing on amd64 than the current code. [1] - Fix the style for memory barriers on amd64. [1] Reported by: Paul B. Mahol <onemda at gmail dot com> Notes: svn path=/head/; revision=197824
* Per their definition, atomic instructions used in conjuction withAttilio Rao2009-10-061-43/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | memory barriers should also ensure that the compiler doesn't reorder paths where they are used. GCC, however, does that aggressively, even in presence of volatile operands. The most reliable way GCC offers for avoid instructions reordering is clobbering "memory" even if that is theoretically an heavy-weight operation, flushing the content of all the registers and forcing reload of them (We could rely, however, on gcc DTRT by just understanding the purpose as this is a well-known pattern for many modern operating-systems). Not all our memory barriers, right now, clobber memory for GCC-like compilers. The most notable cases are IA32 and amd64 where the memory barrier are treacted the same as normal atomic instructions. Fix this by offering the possibility to implement atomic instructions with memory barriers separately from the normal version and implement the GCC-like specific one using memory clobbering. Thanks to Chris Lattner (@apple) for his discussion on llvm specifics. Reported by: jhb Reviewed by: jhb Tested by: rdivacky, Giovanni Trematerra <giovanni dot trematerra at gmail dot com> Notes: svn path=/head/; revision=197803
* - bump __FreeBSD version to reflect added buf_ring, memory barriers,Kip Macy2008-11-221-0/+4
| | | | | | | | | | | | | | | | | | | | and ifnet functions - add memory barriers to <machine/atomic.h> - update drivers to only conditionally define their own - add lockless producer / consumer ring buffer - remove ring buffer implementation from cxgb and update its callers - add if_transmit(struct ifnet *ifp, struct mbuf *m) to ifnet to allow drivers to efficiently manage multiple hardware queues (i.e. not serialize all packets through one ifq) - expose if_qflush to allow drivers to flush any driver managed queues This work was supported by Bitgravity Inc. and Chelsio Inc. Notes: svn path=/head/; revision=185162
* Implement atomic_fetchadd_long() for all architectures and document it.Pawel Jakub Dawidek2008-03-161-0/+20
| | | | | | | Reviewed by: attilio, jhb, jeff, kris (as a part of the uidinfo_waitfree.patch) Notes: svn path=/head/; revision=177276
* Fixed some style bugs (mainly assorted errors in comments, and inconsistentBruce Evans2006-12-291-23/+23
| | | | | | | spelling of `result'). Notes: svn path=/head/; revision=165635
* Fixed some style bugs (whitespace only).Bruce Evans2006-12-291-30/+31
| | | | Notes: svn path=/head/; revision=165633
* Try harder to garbage-collect the "LOCORE" (really asm) version ofBruce Evans2006-12-291-6/+6
| | | | | | | | | | | | | MPLOCKED. The cleaning in rev.1.25 was supposed to have been undone by rev.1.26, but 1.26 could never have actually affected asm files since atomic.h is full of C declarations so including it in asm files would just give syntax errors. The asm MPLOCKED is even less needed than when misplaced definitions of it were first removed, and is now unused in any asm file in the src tree except in anachronismns in sys/i386/i386/support.s. Notes: svn path=/head/; revision=165630
* Removed gratuitous cosmetic differences with the i386 version. ThisBruce Evans2006-12-281-7/+7
| | | | | | | | | | | | | | mainly involves removing all __CC_SUPPORTS___INLINE__ ifdefs. These ifdefs are even less needed for amd64 than for i386, but the i386 atomic.h never had them. The ifdefs here were just an optimization of obsolescent compatibility cruft (__inline) for a null set of compilers. I think null sets of compilers should only be supported in cases where this is more than an optimization, doesn't require extensive ifdefs, and only involves not-so-obsolescent compatibility cruft (plain inline here). Notes: svn path=/head/; revision=165578
* Avoid an instruction in atomic_cmpset_{int_long)() in most cases.Bruce Evans2006-12-271-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions are used a lot for mutexes, so this reduces the text size of an average kernel by about 0.75%. This wasn't intended to be a significant optimization, but it somehow increased the maximum number of packets per second that can be transmitted by my bge hardware from 320000 to 460000 (this benchmark is CPU-bound and remarkably sensitive to changes in the text section). Details: we would prefer to leave the result of the cmpxchg in %al, but cannot tell gcc that it is there, so we have to convert it to an integer register. We converted to %al, then to %[re]ax, but the latter step is usually wasted since gcc usually only wants the condition code and can recover it from %al just as easily as from %[re]ax. Let gcc promote %al in the few cases where this is needed. Nearby style fixes; - let gcc manage the load of `res', and don't abuse `res' for a copy of `exp' - don't echo `res's name in comments - consistently spell the condition code as 'e' after comparison for equality - don't hard-code %al anywhere except in constraints - for the version that doesn't use cmpxchg, there is no requirement to use %al anywhere, so don't hard-code it in the constraints either. Style non-fix: - for the versions that use cmpxchg, keep using "a" (was %[re]ax, now %al) for the main output operand, although this is not required. The input and output operands that use the "a" constraint are now decoupled, and this makes things clearer except for the reason that the output register is hard-coded. It is now just a hack to tell gcc that the input "a" has been clobbered without increasing the number of operands. Notes: svn path=/head/; revision=165572
* Add a new atomic_fetchadd() primitive that atomically adds a value to aJohn Baldwin2005-09-271-0/+21
| | | | | | | | | | | | variable and returns the previous value of the variable. Tested on: i386, alpha, sparc64, arm (cognet) Reviewed by: arch@ Submitted by: cognet (arm) MFC after: 1 week Notes: svn path=/head/; revision=150627
* Stop using the '+' constraint modifier with inline assembly. The '+'John Baldwin2005-09-151-22/+27
| | | | | | | | | | | | | constraint is actually only allowed for register operands. Instead, use separate input and output memory constraints. Education from: alc Reviewed by: alc Tested on: i386, alpha MFC after: 1 week Notes: svn path=/head/; revision=150182
* Add aliases for atomic operations on 64-bit integers just like otherJohn Baldwin2005-08-181-0/+20
| | | | | | | | | 64-bit platforms. MFC after: 1 week Notes: svn path=/head/; revision=149233
* Like on i386, bypass lock prefix for atomic ops on !SMP kernels.Peter Wemm2005-07-211-0/+27
| | | | Notes: svn path=/head/; revision=148267
* Convert the atomic_ptr() operations over to operating on uintptr_tJohn Baldwin2005-07-151-52/+18
| | | | | | | | | | | | | variables rather than void * variables. This makes it easier and simpler to get asm constraints and volatile keywords correct. MFC after: 3 days Tested on: i386, alpha, sparc64 Compiled on: ia64, powerpc, amd64 Kernel toolchain busted on: arm Notes: svn path=/head/; revision=148067
* Some cleanups and tweaks to some of the atomic.h files in preparation forJohn Baldwin2005-07-091-79/+63
| | | | | | | | | | | | | | | | | | further changes and fixes in the future: - Use aliases via macros rather than duplicated inlines wherever possible. - Move all the aliases to the bottom of these files and the inline functions to the top. - Add various comments. - On alpha, drop atomic_{load_acq,store_rel}_{8,char,16,short}(). - On i386 and amd64, don't duplicate the extern declarations for functions in the two non-inline cases (KLD_MODULE and compiler doesn't do inlines), instead, consolidate those two cases. - Some whitespace fixes. Approved by: re (scottl) Notes: svn path=/head/; revision=147855
* netchild's mega-patch to isolate compiler dependencies into a centralJoerg Wunsch2005-03-021-11/+15
| | | | | | | | | | | | | | | | | | | place. This moves the dependency on GCC's and other compiler's features into the central sys/cdefs.h file, while the individual source files can then refer to #ifdef __COMPILER_FEATURE_FOO where they by now used to refer to #if __GNUC__ > 3.1415 && __BARC__ <= 42. By now, GCC and ICC (the Intel compiler) have been actively tested on IA32 platforms by netchild. Extension to other compilers is supposed to be possible, of course. Submitted by: netchild Reviewed by: various developers on arch@, some time ago Notes: svn path=/head/; revision=143063
* Cosmetic and/or trivial sync up with i386.Peter Wemm2003-11-211-4/+10
| | | | | | | Approved by: re (rwatson) Notes: svn path=/head/; revision=122940
* Initial landing of SMP support for FreeBSD/amd64.Peter Wemm2003-11-171-1/+1
| | | | | | | | | | | | | | | | | | | - This is heavily derived from John Baldwin's apic/pci cleanup on i386. - I have completely rewritten or drastically cleaned up some other parts. (in particular, bootstrap) - This is still a WIP. It seems that there are some highly bogus bioses on nVidia nForce3-150 boards. I can't stress how broken these boards are. I have a workaround in mind, but right now the Asus SK8N is broken. The Gigabyte K8NPro (nVidia based) is also mind-numbingly hosed. - Most of my testing has been with SCHED_ULE. SCHED_4BSD works. - the apic and acpi components are 'standard'. - If you have an nVidia nForce3-150 board, you are stuck with 'device atpic' in addition, because they somehow managed to forget to connect the 8254 timer to the apic, even though its in the same silicon! ARGH! This directly violates the ACPI spec. Notes: svn path=/head/; revision=122849
* Commit MD parts of a loosely functional AMD64 port. This is based onPeter Wemm2003-05-011-67/+29
| | | | | | | | | | | | | | | | | | | | | | | | | a heavily stripped down FreeBSD/i386 (brutally stripped down actually) to attempt to get a stable base to start from. There is a lot missing still. Worth noting: - The kernel runs at 1GB in order to cheat with the pmap code. pmap uses a variation of the PAE code in order to avoid having to worry about 4 levels of page tables yet. - It boots in 64 bit "long mode" with a tiny trampoline embedded in the i386 loader. This simplifies locore.s greatly. - There are still quite a few fragments of i386-specific code that have not been translated yet, and some that I cheated and wrote dumb C versions of (bcopy etc). - It has both int 0x80 for syscalls (but using registers for argument passing, as is native on the amd64 ABI), and the 'syscall' instruction for syscalls. int 0x80 preserves all registers, 'syscall' does not. - I have tried to minimize looking at the NetBSD code, except in a couple of places (eg: to find which register they use to replace the trashed %rcx register in the syscall instruction). As a result, there is not a lot of similarity. I did look at NetBSD a few times while debugging to get some ideas about what I might have done wrong in my first attempt. Notes: svn path=/head/; revision=114349
* Add a knob to turn on and off the CMPXCHG instruction on > i386 IA32 systems.Jim Pirzyk2002-10-141-1/+1
| | | | | | | | | | This is most beneficial for vmware client os installs. Reviewed by: jmallet, iedowse, tlambert2@mindspring.com MFC After: never, -STABLE does not currently use this instruction Notes: svn path=/head/; revision=105117
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