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* Add CFI start/end proc directives to arm64, i386, and ppcConrad Meyer2020-12-053-0/+5
| | | | | | | | | | | | | | Follow-up to r353959 and r368070: do the same for other architectures. arm32 already seems to use its own .fnstart/.fnend directives, which appear to be ARM-specific variants of the same thing. Likewise, MIPS uses .frame directives. Reviewed by: arichardson Differential Revision: https://reviews.freebsd.org/D27387 Notes: svn path=/head/; revision=368354
* vm_phys: Try to clean up NUMA KPIsMark Johnston2020-11-192-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | It can useful for code outside the VM system to look up the NUMA domain of a page backing a virtual or physical address, specifically when creating NUMA-aware data structures. We have _vm_phys_domain() for this, but the leading underscore implies that it's an internal function, and vm_phys.h has dependencies on a number of other headers. Rename vm_phys_domain() to vm_page_domain(), and _vm_phys_domain() to vm_phys_domain(). Make the latter an inline function. Add _vm_phys.h and define struct vm_phys_seg there so that it's easier to use in other headers. Include it from vm_page.h so that vm_page_domain() can be defined there. Include machine/vmparam.h from _vm_phys.h since it depends directly on some constants defined there. Reviewed by: alc Reviewed by: dougm, kib (earlier versions) Differential Revision: https://reviews.freebsd.org/D27207 Notes: svn path=/head/; revision=367828
* [PowerPC] Don't overwrite vm.pmap sysctl nodeLeandro Lupori2020-11-172-13/+9
| | | | | | | | | | | | | | | | | | After r367417, both mmu_oea64 and mmu_radix were defining the vm.pmap sysctl node, resulting in the later definition hiding the properties of the previous one. Avoid this issue by defining vm.pmap in a common source file and declaring it where needed. This change also standardizes the tunable name used to enable superpages and change its default to disabled on radix MMU, because it still has some issues with superpages. Reviewed by: bdragon, jhibbits Sponsored by: Eldorado Research Institute (eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D27156 Notes: svn path=/head/; revision=367758
* [PowerPC64LE] Radix MMU fixes for LE.Brandon Bergren2020-11-131-199/+222
| | | | | | | | | | | | | | | | There were many, many endianness fixes needed for Radix MMU. The Radix pagetable is stored in BE (as it is read and written to by the MMU hw), so we need to convert back and forth every time we interact with it when running in LE. With these changes, I can successfully boot with radix enabled on POWER9 hw. Reviewed by: luporl, jhibbits Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D27181 Notes: svn path=/head/; revision=367644
* [PowerPC] Fix powerpc64le boot after HPT superpages additionBrandon Bergren2020-11-081-7/+9
| | | | | | | | | | | | | | | The HPT is always stored in big-endian, as it is accessed directly by the hardware as well as the kernel. As such, it is necessary to convert values to and from native endian when running on LE. Some unconverted accesses snuck in accidentally with r367417. Apply the appropriate conversions to fix boot hanging on powerpc64le. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=367496
* Fix powerpc and LINT buildsLeandro Lupori2020-11-062-1/+4
| | | | | | | | | | | | Fix build errors introduced by r367417 and r367390: - Guard label reached only by powerpc64 - Guard vm_reserv_level_iffullpop call, that is not defined on powerpc variants that don't support superpages - Add missing hwpmc file, for when hwpmc is built into kernel Notes: svn path=/head/; revision=367427
* Implement superpages for PowerPC64 (HPT)Leandro Lupori2020-11-063-109/+1375
| | | | | | | | | | | | | | | | | | | | | | | | | | This change adds support for transparent superpages for PowerPC64 systems using Hashed Page Tables (HPT). All pmap operations are supported. The changes were inspired by RISC-V implementation of superpages, by @markj (r344106), but heavily adapted to fit PPC64 HPT architecture and existing MMU OEA64 code. While these changes are not better tested, superpages support is disabled by default. To enable it, use vm.pmap.superpages_enabled=1. In this initial implementation, when superpages are disabled, system performance stays at the same level as without these changes. When superpages are enabled, buildworld time increases a bit (~2%). However, for workloads that put a heavy pressure on the TLB the performance boost is much bigger (see HPC Challenge and pgbench on D25237). Reviewed by: jhibbits Sponsored by: Eldorado Research Institute (eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D25237 Notes: svn path=/head/; revision=367417
* Avoid dump_avail[] redefinition.Konstantin Belousov2020-10-142-0/+2
| | | | | | | | | | | | | Move dump_avail[] extern declaration and inlines into a new header vm/vm_dumpset.h. This fixes default gcc build for mips. Reviewed by: alc, scottph Tested by: kevans (previous version) Sponsored by: The FreeBSD Foundation Differential revision: https://reviews.freebsd.org/D26741 Notes: svn path=/head/; revision=366711
* [PowerPC64LE] Fix AP spinup on powernv.Brandon Bergren2020-09-231-0/+13
| | | | | | | | | | | | | | | | | | | | OPAL unconditionally enters secondary CPUs with only HV and SF set. I tried writing a secondary entry point instead, but OPAL rejected it and I am unsure why, so I resorted to making the system reset interrupt endian-flexible. This means we take a slight performance hit on wakeup on LE, but it is a good stopgap until we can figure out a reliable way to make OPAL enter where we want it to. It probably makes sense to have it around anyway, because I can imagine scenarios where the cpu resets itself to BE and does a software reset. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366053
* [PowerPC64LE] Implement endian-independent dword atomic PTE lock.Brandon Bergren2020-09-231-1/+33
| | | | | | | | | | | | | | | It's much easier to implement this in an endian-independent way when we don't also have to worry about masking half of the dword off. Given that this code ran on a machine that ran a poudriere bulk with no kernel oddities, I am relatively certain it is correctly implemented. ;) This should be a minor performance boost on BE as well. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366046
* [PowerPC64LE] Fix endian conversion bugs in moea64.Brandon Bergren2020-09-231-4/+4
| | | | | | | | | | | | For a body of code that had its endian conversion bits written blind without the ability to test, moea64 was VERY close to being correct. There were only four instances where the existing code was getting it wrong. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366045
* [PowerPC64LE] LE bringup work: locore / machdep / platformBrandon Bergren2020-09-222-1/+11
| | | | | | | | | | This is the initial LE changes required in the machdep code to get as far as platform attachment on qemu pseries. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=366033
* [PowerPC64LE] Set up the powernv partition table correctly.Brandon Bergren2020-09-151-2/+2
| | | | | | | | | The partition table is always big endian. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=365768
* [PowerPC] Implement pmap_mincore() for moeaBrandon Bergren2020-09-131-1/+49
| | | | | | | | | Do the same as previous for moea. Tested on G4. Notes: svn path=/head/; revision=365691
* [PowerPC64] Implement pmap_mincore() for moea64Brandon Bergren2020-09-131-0/+49
| | | | | | | | | | | | | Implement pmap_mincore() for moea64. This will need some slight tweaks when large page support in HPT lands. Submitted by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br> Reviewed by: bdragon Differential Revision: https://reviews.freebsd.org/D26314 Notes: svn path=/head/; revision=365690
* [PowerPC] Add PVO_PADDR macro to mmu_oea.c to match mmu_oea64.c changesBrandon Bergren2020-09-121-7/+9
| | | | | | | | | | Use a PVO_PADDR macro on 32 bit as well, to reduce the difference between mmu_oea.c and mmu_oea64.c. Equivilent to the changes in r363222. Notes: svn path=/head/; revision=365678
* [PowerPC64] Hide dssall instruction from llvm assemblerBrandon Bergren2020-09-081-1/+2
| | | | | | | | | | | | | | | | When doing a build for a modern CPUTYPE, llvm will throw errors if obsolete instructions are used, even if they will never run due to runtime checks. Hiding the dssall instruction from the assembler fixes kernel build when overriding CPUTYPE, without having any effect on the generated binary. This has been in my local tree for over a year and is well tested across a variety of machines. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=365481
* Include the psind in data returned by mincore(2).Mark Johnston2020-09-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Currently we use a single bit to indicate whether the virtual page is part of a superpage. To support a forthcoming implementation of non-transparent 1GB superpages, it is useful to provide more detailed information about large page sizes. The change converts MINCORE_SUPER into a mask for MINCORE_PSIND(psind) values, indicating a mapping of size psind, where psind is an index into the pagesizes array returned by getpagesizes(3), which in turn comes from the hw.pagesizes sysctl. MINCORE_PSIND(1) is equal to the old value of MINCORE_SUPER. For now, two bits are used to record the page size, permitting values of MAXPAGESIZES up to 4. Reviewed by: alc, kib Sponsored by: Juniper Networks, Inc. Sponsored by: Klara, Inc. Differential Revision: https://reviews.freebsd.org/D26238 Notes: svn path=/head/; revision=365267
* powerpc: clean up empty lines in .c and .h filesMateusz Guzik2020-09-018-38/+7
| | | | Notes: svn path=/head/; revision=365073
* [PowerPC] Fix translation-related crashes during startupBrandon Bergren2020-08-212-29/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After spending a lot of time trying to track down what was going on, I have isolated the "black screen" failures when using boot1 to boot a G4 machine. It turns out we were replacing the traps before installing the temporary BAT entry for the bottom of physical memory. That meant that until the MMU was bootstrapped, the cached translations were the only thing keeping us from losing. Throwing boot1 into the mix was affecting execution flow enough to cause us to hit an uncached page and crash. Fix this by properly setting up the initial BAT entry at the same time we are replacing the OpenFirmware traps, so we can continue executing in segment 0 until the rest of the DMAP has been set up. A second thing discovered while researching this is that we were entering a BAT region for segment 16. It turns out this range was a) considered part of KVA, and b) has firmware mappings with varying attributes. If we ever accessed an unmapped page in segment 16, it would cause a BAT entry to be installed for the whole segment, which would bypass the existing mappings until it was flushed out again. Instead, translate the OFW memory attributes into VM memory attributes and install the ranges into the kernel address space properly. Reviewed by: adalava MFC after: 3 weeks Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D25547 Notes: svn path=/head/; revision=364447
* Fix clang 11 inline asm constraint error when building powerpc GENERIC64Dimitry Andric2020-08-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | kernels: sys/powerpc/aim/mmu_radix.c:728:19: error: invalid operand for inline asm constraint 'i' __asm __volatile(PPC_TLBIEL(%0, %1, %2, %3, 1) ^ sys/powerpc/aim/mmu_radix.c:149:3: note: expanded from macro 'PPC_TLBIEL' __XSTRING(.long PPC_INST_TLBIEL | \ ^ sys/sys/cdefs.h:161:22: note: expanded from macro '__XSTRING' #define __XSTRING(x) __STRING(x) /* expand x, then stringify */ ^ sys/sys/cdefs.h:160:21: note: expanded from macro '__STRING' #define __STRING(x) #x /* stringify without expanding x */ ^ <scratch space>:112:1: note: expanded from here ".long 0x7c000224 | (((%0) & 0x1f) << 11) | (((%1) & 0x1f) << 21) | (((%2) & 0x3) << 18) | (((%3) & 0x1) << 17) | (((1) & 0x1) << 16)" ^ This is solved by making the affected inline functions __always_inline. Suggested by: jhibbits MFC after: 3 days Notes: svn path=/head/; revision=364040
* Revert r240317 to prevent leaking pmap entriesConrad Meyer2020-07-163-1/+5
| | | | | | | | | | | | | | | | | | | | | | | Subsequent to r240317, kmem_free() was replaced with kva_free() (r254025). kva_free() releases the KVA allocation for the mapped region, but no longer clears the pmap (pagetable) entries. An affected pmap_unmapdev operation would leave the still-pmap'd VA space free for allocation by other KVA consumers. However, this bug easily avoided notice for ~7 years because most devices (1) never call pmap_unmapdev and (2) on amd64, mostly fit within the DMAP and do not need KVA allocations. Other affected arch are less popular: i386, MIPS, and PowerPC. Arm64, arm32, and riscv are not affected. Reported by: Don Morris <dgmorris AT earthlink.net> Submitted by: Don Morris (amd64 part) Reviewed by: kib, markj, Don (!amd64 parts) MFC after: I don't intend to, but you might want to Sponsored by: Dell Isilon Differential Revision: https://reviews.freebsd.org/D25689 Notes: svn path=/head/; revision=363266
* [PowerPC] Use PVO_PADDR to get the PA from PVOLeandro Lupori2020-07-151-14/+17
| | | | | | | | | | | | | | Use PVO_PADDR macro to get the physical address from a PVO, instead of explicitly ANDing pvo_pte.pa with LPTE_RPGN where it is needed. Besides improving readability, this is needed to support superpages (D25237), where the steps to get the PA from a PVO are different. Reviewed by: markj Sponsored by: Eldorado Research Institute (eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D25654 Notes: svn path=/head/; revision=363222
* Revert r362998, r326999 while a better compatibility strategy is devised.Scott Long2020-07-091-1/+1
| | | | Notes: svn path=/head/; revision=363060
* Migrate the feature of excluding RAM pages to use "excludelist"Scott Long2020-07-071-1/+1
| | | | | | | | | as its nomenclature. MFC after: 1 week Notes: svn path=/head/; revision=362998
* powerpc: Use IFUNCs for copyin/copyout/etcJustin Hibbits2020-06-061-17/+0
| | | | | | | | | | | | | | | | Summary: Radix on AIM, and all of Book-E (currently), can do direct addressing of user space, instead of needing to map user addresses into kernel space. Take advantage of this to optimize the copy(9) functions for this behavior, and avoid effectively NOP translations. Test Plan: Tested on powerpcspe, powerpc64/booke, powerpc64/AIM Reviewed by: bdragon Differential Revision: https://reviews.freebsd.org/D25129 Notes: svn path=/head/; revision=361861
* powerpc: Add a (CPU/runtime features) flags set to pcpu structJustin Hibbits2020-06-062-0/+8
| | | | | | | | | | | | | | | | | | Summary: The point of this addition is to cache CPU behavior 'features', to avoid having to recompute based on CPU, etc. The first such use case is to avoid the unnecessary manipulation of the SLBs (Segment Lookaside Buffers) when using the Radix pmap on POWER9. Since we already get the PCPU pointer wherever we swap the SLB entries, we can use a cached flag to check if it's necessary to perform the operation anyway, and skip it when not. Reviewed by: bdragon Differential Revision: https://reviews.freebsd.org/D24908 Notes: svn path=/head/; revision=361859
* [PowerPC] Fix radix crash when passing -1 from userspaceBrandon Bergren2020-05-281-1/+2
| | | | | | | | | | | | | Found by running libc tests with radix enabled. Detect unsigned integer wrapping with a postcondition. Note: Radix MMU is not enabled by default yet. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=361568
* powerpc/mmu: Convert PowerPC pmap drivers to ifunc from kobjJustin Hibbits2020-05-276-823/+752
| | | | | | | | | | | | | With IFUNC support in the kernel, we can finally get rid of our poor-man's ifunc for pmap, utilizing kobj. Since moea64 uses a second tier kobj as well, for its own private methods, this adds a second pmap install function (pmap_mmu_init()) to perform pmap 'post-install pre-bootstrap' initialization, before the IFUNCs get initialized. Reviewed by: bdragon Notes: svn path=/head/; revision=361544
* [PowerPC] Fix invalid asm in trap codeBrandon Bergren2020-05-271-1/+1
| | | | | | | | | | | | | | In this context, 0 actually means 0 (i.e. this is a li instruction). While most assemblers will ignore this, I did have a compile failure at one point when using an external toolchain. In the future, we should use the li syntax to make this clearer. Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=361542
* [PowerPC] Fix kernel boot on powerpcBrandon Bergren2020-05-211-1/+0
| | | | | | | | | | | | | | Recent changes have caused the vmspace objects to start coming from KVA instead of direct-mapped memory on powerpc. As far as I can tell, this is not actually a problem, so we should stop arbitrarily asserting that it is. I do not know why this was not being triggered before. Approved by: jhibbits Sponsored by: Tag1 Consulting, Inc. Notes: svn path=/head/; revision=361336
* powerpc: Handle machine checks caused by D-ERAT multihitJustin Hibbits2020-05-212-0/+14
| | | | | | | | | | | | Instead of crashing the user process when a D-ERAT multihit is detected, try to flush the ERAT, and continue. This machine check indicates a likely PMAP invalidation shortcoming that will need to be addressed, but it's recoverable, so just recover. The recovery is pmap-specific to flush the ERAT, so add a pmap function to do so, currently only implemented by the POWER9 radix pmap. Notes: svn path=/head/; revision=361317
* powerpc/radix mmu: No need for delayed TLB invalidationJustin Hibbits2020-05-201-93/+4
| | | | | | | | | x86 needs delayed TLB invalidation because invalidation requires an expensive IPI. PowerPC has had a TLB invalidation instruction since the POWER1 in 1990, so there's no need to delay anything. Notes: svn path=/head/; revision=361271
* powerpc/mmu: Don't use the cache instructions to zero pagesJustin Hibbits2020-05-191-3/+1
| | | | | | | | | | | | | | | | A page (even physmem) can be marked as cache-inhibited. Attempting to use 'dcbz' to zero a page mapped cache-inhibited triggers an alignment exception, which is fatal in kernel. This was seen when testing hardware acceleration with X on POWER9. At some point in the future, this should be changed to a more straight forward zero loop instead of bzero(), and a similar change be made to the other pmaps. Reported by: pkubaj@ Notes: svn path=/head/; revision=361232
* [PowerPC64] Minor correctness fix in rstcode.Brandon Bergren2020-05-121-1/+1
| | | | | | | | | | | | | TRAP_ENTRY(0) should be TRAP_GENTRAP(0) here. However, in practice, it doesn't matter, as the only time TRAP_ENTRY and TRAP_GENTRAP can differ is when bridge mode is active, which is impossible on the 64 bit kernel. Fix it anyway in case we ever need to add a trap preamble on PPC64. Notes: svn path=/head/; revision=360948
* powerpc64: Implement Radix MMU for POWER9 CPUsJustin Hibbits2020-05-114-5/+6535
| | | | | | | | | | | | | | | | Summary: POWER9 supports two MMU formats: traditional hashed page tables, and Radix page tables, similar to what's presesnt on most other architectures. The PowerISA also specifies a process table -- a table of page table pointers-- which on the POWER9 is only available with the Radix MMU, so we can take advantage of it with the Radix MMU driver. Written by Matt Macy. Differential Revision: https://reviews.freebsd.org/D19516 Notes: svn path=/head/; revision=360887
* powerpc: Add a CPU-custom machine check handlerJustin Hibbits2020-05-102-0/+28
| | | | | | | | | | | | | | | | | Summary: Some machine checks are process-recoverable, others are not. Let a CPU-specific handler decide what to do. This works around a machine check error hit while building www/firefox and mail/thunderbird, which would otherwise cause the build to fail. More work is needed to handle all possible machine check conditions, but this is sufficient to unblock some ports building. Differential Revision: https://reviews.freebsd.org/D23731 Notes: svn path=/head/; revision=360881
* [PowerPC] kernel ifunc support for powerpc*, fix ppc64 relocation oddities.Brandon Bergren2020-05-072-5/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a general cleanup of the relocatable kernel support on powerpc, needed to enable kernel ifuncs. * Fix some relocatable issues in the kernel linker, and change to using a RELOCATABLE_KERNEL #define instead of #ifdef __powerpc__ for parts that other platforms can use in the future if they wish to have ET_DYN kernels. * Get rid of the DB_STOFFS hack now that the kernel is relocated to the DMAP properly across the board on powerpc64. * Add powerpc64 and powerpc32 ifunc functionality. * Allow AIM64 virtual mode OF kernels to run from the DMAP like other AIM64 by implementing a virtual mode restart. This fixes the runtime address on PowerMac G5. * Fix symbol relocation problems on post-relocation kernels by relocating the symbol table. * Add an undocumented method for supplying kernel symbols on powernv and other powerpc machines using linux-style kernel/initrd loading -- If you pass the kernel in as the initrd as well, the copy resident in initrd will be used as a source for symbols when initializing the debugger. This method is subject to removal once we have a better way of doing this. Approved by: jhibbits Relnotes: yes Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D23156 Notes: svn path=/head/; revision=360794
* Use %zu to print a size_t value instead of %ju.John Baldwin2020-04-161-1/+1
| | | | | | | This fixes the build for 32-bit kernels. Notes: svn path=/head/; revision=360023
* powerpc: autosize bpvo based on physical memoryAlfredo Dal'Ava Junior2020-04-151-1/+18
| | | | | | | | | | | | | | | Default moea64_bpvo_pool_size 327680 was insufficient for initial memory mapping at boot time on systems with, for example, 64G and no huge pages enabled. Submitted by: Andre Silva <afscoelho@gmail.com> Reviewed by: jhibbits, alfredo Approved by: jhibbits (mentor) Sponsored by: Eldorado Research Institute (eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D24102 Notes: svn path=/head/; revision=359992
* powerpc: unconditionally mark SLB zones UMA_ZONE_CONTIGRyan Libby2020-02-191-8/+2
| | | | | | | | | | | | PR: 244118 Reported by: Francis Little <oggy at farscape.co.uk> Tested by: Francis Little, Mark Millard <marklmi at yahoo.com> Reviewed by: markj Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D23729 Notes: svn path=/head/; revision=358094
* uma: convert mbuf_jumbo_alloc to UMA_ZONE_CONTIG & tag othersRyan Libby2020-02-041-2/+8
| | | | | | | | | | | | | | Remove mbuf_jumbo_alloc and let large mbuf zones use the new uma default contig allocator (a copy of mbuf_jumbo_alloc). Tag other zones which require contiguous objects, even if they don't use the new default contig allocator, so that uma knows about their constraints. Reviewed by: jeff, markj Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D23238 Notes: svn path=/head/; revision=357548
* [PowerPC] Fix VSX context handlingBrandon Bergren2020-02-041-2/+19
| | | | | | | | | | | | | | | | | | | | | | In r356767, memcpy/memmove/bcopy optimizations were added to libc to improve performance. This exposed an existing kernel issue in VSX handling. The PSL_VSX flag was not being excluded from the psl_userstatic set, which meant that any thread that used these and then called swapcontext(3) would get an EINVAL error. Fixing this exposed a second issue - in r344123, the FPU was being forced off in set_mcontext(). However, this was neglecting to ensure VSX was turned off at the same time. While here, add some code comments to explain what's going on. Reviewed by: jhibbits, luporl (earlier rev), pkubaj (earlier rev) Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D23497 Notes: svn path=/head/; revision=357529
* [PowerPC64] fix crash when using machdep.moea64_bpvo_pool_size tunableJustin Hibbits2020-01-191-4/+6
| | | | | | | | | | | | | | | | | | | | | | Summary: This fixes kernel crashing when tunable "machdep.moea64_bpvo_pool_size" is set to a value higher then 327680 (default value). Function moea64_mid_bootstrap() relies on moea64_bpvo_pool_size, but at time of the use the variable wan't yet updated with the new value provided by user. Problem was detected after trying to use a VM with 64GB of RAM, and default moea64_bpvo_pool_size is insufficient (kernel boot used more than 470000) . I think default value must be discussed to address this use case, or find a way to calculate pool size automatically based on amount of memory detected. Test Plan: Tested on QEMU VM with 64GB of RAM using "set machdep.moea64_bpvo_pool_size=655360" on loader prompt Submitted by: Alfredo Dal'Ava Júnior (alfredo.junior_eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D23233 Notes: svn path=/head/; revision=356896
* D23057: [PowerPC] Fix offset calculations in bridge modeBrandon Bergren2020-01-183-9/+11
| | | | | | | | | | | | | | | | | | | | | | In rS354701, I replaced text relocations with offsets from &generictrap. Unfortunately, the magic variable I was using doesn't actually mean the address of &generictrap, in bridge mode it actually means &generictrap64. So, for bridge mode to work, it is necessary to differentiate between "where do we need to branch to to handle a trap" and "where is &generictrap for purposes of doing relative math". Introduce a new TRAP_ENTRY and use it instead of TRAP_GENTRAP for doing actual calls to the generic trap handler. Reported by: Mark Millard <marklmi@yahoo.com> Reviewed by: jhibbits Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D23057 Notes: svn path=/head/; revision=356862
* Add a 'SINGLETON' directive to kobj interface definitionJustin Hibbits2020-01-181-0/+1
| | | | | | | | | | | | | | | | Summary: This makes the interface described in the definition file act like a pseudo-IFUNC service, by caching the found method locally. Applying this to the PowerPC MMU definitions, it yields a significant (15-20%) performance improvement, seen in both a 'make buildworld' and a parallel build of LLVM, on a POWER9 system. Reviewed By: imp Differential Revision: https://reviews.freebsd.org/D23245 Notes: svn path=/head/; revision=356860
* powerpc: Prevent infinite loop in moea_sync_icache()Justin Hibbits2020-01-101-1/+1
| | | | | | | | | This applies r344049 to the 32-bit pmap. Reported by: Mark Millard <marklmi_yahoo.com> Notes: svn path=/head/; revision=356595
* [PowerPC] Fix powerpc 32 bit build in mmu_oea64.cBrandon Bergren2019-12-121-0/+6
| | | | | | | | | | | | Due to ppc32 building mmu_oea64.c (for use when in bridge mode on a G5), we need to guard the new moea64_page_array_startup code behind __powerpc64__ to avoid a compile error, since vm_offset_t is not 64-bit on ppc32. Reviewed by: jhibbits Differential Revision: https://reviews.freebsd.org/D22782 Notes: svn path=/head/; revision=355655
* Introduce vm_page_astate.Mark Johnston2019-12-102-4/+5
| | | | | | | | | | | | | | | | | This is a 32-bit structure embedded in each vm_page, consisting mostly of page queue state. The use of a structure makes it easy to store a snapshot of a page's queue state in a stack variable and use cmpset loops to update that state without requiring the page lock. This change merely adds the structure and updates references to atomic state fields. No functional change intended. Reviewed by: alc, jeff, kib Sponsored by: Netflix, Intel Differential Revision: https://reviews.freebsd.org/D22650 Notes: svn path=/head/; revision=355586
* powerpc64/pmap: micro-optimize some PVO-PTE logicJustin Hibbits2019-12-083-12/+14
| | | | | | | | | | | | | | Summary: moea64_pte_sync_native() and moea64_pte_unset_native() don't need the full PTE created, they only need to check that the PVO has a matching PTE to the PTE in the page table. Don't waste time creating the full PTE in this case. Reviewed by: luporl Differential Revision: https://reviews.freebsd.org/D22341 Notes: svn path=/head/; revision=355519
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