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* Add VT driver for VBE framebuffer deviceToomas Soome2020-11-301-0/+14
* Limit workaround for errata E400 to appropriate AMD cpus.Konstantin Belousov2020-10-142-0/+5
* Move ctx_switch_xsave declaration to amd64 md_var.h.Konstantin Belousov2020-10-031-1/+0
* Add missing declarations of 64-bit variants of bus_peek/bus_poke on amd64.Michal Meloun2020-09-241-0/+6
* Move vm_page_dump bitset array definition to MI codeD Scott Phillips2020-09-211-3/+0
* Add missing assignment forgotten in r365899Michal Meloun2020-09-201-0/+1
* Add NetBSD compatible bus_space_peek_N() and bus_space_poke_N() functions.Michal Meloun2020-09-191-0/+25
* Add constant for the DE_CFG MSR on AMD CPUs.John Baldwin2020-09-111-0/+1
* x86: clean up empty lines in .c and .h filesMateusz Guzik2020-09-017-11/+1
* Add amd64 procctl(2) ops to manage forced LA48/LA57 VA after exec.Konstantin Belousov2020-08-231-1/+10
* Add definition for CR4.LA57 bit.Konstantin Belousov2020-08-231-0/+1
* Export a routine to provide the TSC_AUX MSR value and use this in vmm.Peter Grehan2020-08-181-0/+1
* o Add machine/iommu.h and include MD iommu headers from it,Ruslan Bukin2020-08-051-0/+13
* o Move iommu_set_buswide_ctx, iommu_is_buswide_ctx toRuslan Bukin2020-07-291-6/+0
* o Move the buswide_ctxs bitmap to iommu_unit and rename related functions.Ruslan Bukin2020-07-281-2/+2
* Add initial driver for ACPI Platform Error Interfaces.Alexander Motin2020-07-271-0/+1
* Allow swi_sched() to be called from NMI context.Alexander Motin2020-07-252-1/+4
* Introduce ipi_self_from_nmi().Alexander Motin2020-07-241-0/+1
* Use APIC_IPI_DEST_OTHERS for bitmapped IPIs too.Alexander Motin2020-07-241-1/+0
* hwpmc: Always set pmc_cpuid to somethingRyan Moeller2020-07-141-0/+1
* amd64: allow parallel shootdown IPIsKonstantin Belousov2020-07-142-9/+2
* Control for Special Register Buffer Data Sampling mitigation.Konstantin Belousov2020-06-121-0/+2
* x86: add bits definitions for SRBDS mitigation control.Konstantin Belousov2020-06-121-0/+5
* amd64 pmap: reorder IPI send and local TLB flush in TLB invalidations.Konstantin Belousov2020-06-101-4/+9
* x86: Detect new feature bitsConrad Meyer2020-05-261-0/+4
* amd64: Add a knob to flush RSB on context switches if machine has SMEP.Konstantin Belousov2020-05-201-0/+1
* Fix IBRS for machines with IBRS_ALL capability.Konstantin Belousov2020-02-251-2/+2
* hwpstate_intel(4): Add fallback EPP using PERF_BIAS MSRConrad Meyer2020-02-011-0/+3
* x86: Add/amend some power-management comments/macrosConrad Meyer2020-02-011-0/+1
* Reimplement stack capture of running threads on i386 and amd64.Mark Johnston2020-01-312-5/+5
* Add support for Hygon Dhyana Family 18h processor.Konstantin Belousov2020-01-212-0/+2
* bus_dma_dmar_load_ident(9): load identity mapping into the map.Konstantin Belousov2019-11-271-0/+2
* Limit bus_dma_dmar_set_buswide() definition to kernel only.Konstantin Belousov2019-11-251-0/+2
* Port the NetBSD KCSAN runtime to FreeBSD.Andrew Turner2019-11-211-5/+10
* bus_dma_dmar_set_buswide(9): KPI to indicate that the whole dmarKonstantin Belousov2019-11-181-0/+2
* Add x86 msr tweak KPI.Konstantin Belousov2019-11-181-0/+8
* TSX Asynchronous Abort mitigation for Intel CVE-2019-11135.Scott Long2019-11-161-0/+2
* Add new bit definitions for TSX, related to the TAA issue. The actualScott Long2019-11-121-0/+7
* Workaround for Intel SKL002/SKL012S errata.Konstantin Belousov2019-11-121-0/+1
* amd64: Fix typo: RDPRU bit is 0x10, not 0x04Conrad Meyer2019-10-301-1/+1
* amd64: Define and decode new AMD64 feature bitsConrad Meyer2019-10-301-0/+5
* x86: Fetch and save standard CPUID leaf 6 in identcpuConrad Meyer2019-10-182-19/+32
* x86: Use canonical spelling of MOVDIR64B feature/instructionConrad Meyer2019-10-141-1/+1
* amd64: plug spurious cld instructionsMateusz Guzik2019-10-081-18/+0
* Add a constant for the LS config MSR on AMD CPUs.John Baldwin2019-05-231-0/+1
* Decode and name additional x86 feature bitsConrad Meyer2019-05-221-18/+30
* x86 MCA: introduce MCA hooks for different vendor implementationsAndrew Gallatin2019-05-221-0/+10
* Instead of individual conditional statements to look for each hypervisorStephen J. Kiernan2019-05-171-0/+1
* Remove resolver_qual from DEFINE_IFUNC/DEFINE_UIFUNC macros.Konstantin Belousov2019-05-161-7/+7
* Allow loading the same DMA address multiple times without any priorTycho Nightingale2019-05-162-0/+13
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