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authorPeter Wemm <peter@FreeBSD.org>2001-09-04 11:05:33 +0000
committerPeter Wemm <peter@FreeBSD.org>2001-09-04 11:05:33 +0000
commit25ea330aecf8a80c0740f3d58d23047f868cf315 (patch)
tree3d87e0e032f89b14405c4102e9026634bcaaffe6
parent63462b0c3a16dfec9129ba5e85a7022922c94f43 (diff)
Notes
-rw-r--r--sys/amd64/amd64/initcpu.c8
-rw-r--r--sys/amd64/amd64/locore.S11
-rw-r--r--sys/amd64/amd64/locore.s11
-rw-r--r--sys/i386/i386/initcpu.c8
-rw-r--r--sys/i386/i386/locore.s11
5 files changed, 17 insertions, 32 deletions
diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c
index eae6d32f1445..b32c786851b9 100644
--- a/sys/amd64/amd64/initcpu.c
+++ b/sys/amd64/amd64/initcpu.c
@@ -70,9 +70,15 @@ SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
&hw_instruction_sse, 0,
"SIMD/MMX2 instructions available in CPU");
+/* Must *NOT* be BSS or locore will bzero these after setting them */
+int cpu = 0; /* Are we 386, 386sx, 486, etc? */
+u_int cpu_id = 0; /* Stepping ID */
+u_int cpu_feature = 0; /* Feature flags */
+u_int cpu_high = 0; /* Highest arg to CPUID */
#ifdef CPU_ENABLE_SSE
-u_int cpu_fxsr; /* SSE enabled */
+u_int cpu_fxsr = 0; /* SSE enabled */
#endif
+char cpu_vendor[20] = ""; /* CPU Origin code */
#ifdef I486_CPU
/*
diff --git a/sys/amd64/amd64/locore.S b/sys/amd64/amd64/locore.S
index c2a2092dcf86..97a1e1646a33 100644
--- a/sys/amd64/amd64/locore.S
+++ b/sys/amd64/amd64/locore.S
@@ -123,16 +123,7 @@
.space 0x2000 /* space for tmpstk - temporary stack */
HIDENAME(tmpstk):
- .globl boothowto,bootdev
-
- .globl cpu,cpu_vendor,cpu_id,bootinfo
- .globl cpu_high, cpu_feature
-
-cpu: .long 0 /* are we 386, 386sx, or 486 */
-cpu_id: .long 0 /* stepping ID */
-cpu_high: .long 0 /* highest arg to CPUID */
-cpu_feature: .long 0 /* features */
-cpu_vendor: .space 20 /* CPU origin code */
+ .globl bootinfo
bootinfo: .space BOOTINFO_SIZE /* bootinfo that we can handle */
KERNend: .long 0 /* phys addr end of kernel (just after bss) */
diff --git a/sys/amd64/amd64/locore.s b/sys/amd64/amd64/locore.s
index c2a2092dcf86..97a1e1646a33 100644
--- a/sys/amd64/amd64/locore.s
+++ b/sys/amd64/amd64/locore.s
@@ -123,16 +123,7 @@
.space 0x2000 /* space for tmpstk - temporary stack */
HIDENAME(tmpstk):
- .globl boothowto,bootdev
-
- .globl cpu,cpu_vendor,cpu_id,bootinfo
- .globl cpu_high, cpu_feature
-
-cpu: .long 0 /* are we 386, 386sx, or 486 */
-cpu_id: .long 0 /* stepping ID */
-cpu_high: .long 0 /* highest arg to CPUID */
-cpu_feature: .long 0 /* features */
-cpu_vendor: .space 20 /* CPU origin code */
+ .globl bootinfo
bootinfo: .space BOOTINFO_SIZE /* bootinfo that we can handle */
KERNend: .long 0 /* phys addr end of kernel (just after bss) */
diff --git a/sys/i386/i386/initcpu.c b/sys/i386/i386/initcpu.c
index eae6d32f1445..b32c786851b9 100644
--- a/sys/i386/i386/initcpu.c
+++ b/sys/i386/i386/initcpu.c
@@ -70,9 +70,15 @@ SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
&hw_instruction_sse, 0,
"SIMD/MMX2 instructions available in CPU");
+/* Must *NOT* be BSS or locore will bzero these after setting them */
+int cpu = 0; /* Are we 386, 386sx, 486, etc? */
+u_int cpu_id = 0; /* Stepping ID */
+u_int cpu_feature = 0; /* Feature flags */
+u_int cpu_high = 0; /* Highest arg to CPUID */
#ifdef CPU_ENABLE_SSE
-u_int cpu_fxsr; /* SSE enabled */
+u_int cpu_fxsr = 0; /* SSE enabled */
#endif
+char cpu_vendor[20] = ""; /* CPU Origin code */
#ifdef I486_CPU
/*
diff --git a/sys/i386/i386/locore.s b/sys/i386/i386/locore.s
index c2a2092dcf86..97a1e1646a33 100644
--- a/sys/i386/i386/locore.s
+++ b/sys/i386/i386/locore.s
@@ -123,16 +123,7 @@
.space 0x2000 /* space for tmpstk - temporary stack */
HIDENAME(tmpstk):
- .globl boothowto,bootdev
-
- .globl cpu,cpu_vendor,cpu_id,bootinfo
- .globl cpu_high, cpu_feature
-
-cpu: .long 0 /* are we 386, 386sx, or 486 */
-cpu_id: .long 0 /* stepping ID */
-cpu_high: .long 0 /* highest arg to CPUID */
-cpu_feature: .long 0 /* features */
-cpu_vendor: .space 20 /* CPU origin code */
+ .globl bootinfo
bootinfo: .space BOOTINFO_SIZE /* bootinfo that we can handle */
KERNend: .long 0 /* phys addr end of kernel (just after bss) */