diff options
| author | Jung-uk Kim <jkim@FreeBSD.org> | 2008-12-12 23:17:00 +0000 |
|---|---|---|
| committer | Jung-uk Kim <jkim@FreeBSD.org> | 2008-12-12 23:17:00 +0000 |
| commit | 39e52304e04e2f040e36fddcaac27b423fd7a905 (patch) | |
| tree | 3cabd879115041c9697fc93c22d23bb2f36fd5a4 | |
| parent | 366eaf1e2da426c46105c76307c74631f756d6a9 (diff) | |
Notes
| -rw-r--r-- | sys/amd64/amd64/identcpu.c | 16 | ||||
| -rw-r--r-- | sys/amd64/include/specialreg.h | 8 | ||||
| -rw-r--r-- | sys/i386/i386/identcpu.c | 16 | ||||
| -rw-r--r-- | sys/i386/include/specialreg.h | 8 |
4 files changed, 32 insertions, 16 deletions
diff --git a/sys/amd64/amd64/identcpu.c b/sys/amd64/amd64/identcpu.c index c63339d096cd..f417e0fa503c 100644 --- a/sys/amd64/amd64/identcpu.c +++ b/sys/amd64/amd64/identcpu.c @@ -322,15 +322,15 @@ printcpuinfo(void) "\003SVM" /* Secure Virtual Mode */ "\004ExtAPIC" /* Extended APIC register */ "\005CR8" /* CR8 in legacy mode */ - "\006<b5>" - "\007<b6>" - "\010<b7>" + "\006ABM" /* LZCNT instruction */ + "\007SSE4A" /* SSE4A */ + "\010MAS" /* Misaligned SSE mode */ "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ - "\012<b9>" - "\013<b10>" - "\014<b11>" - "\015<b12>" - "\016<b13>" + "\012OSVW" /* OS visible workaround */ + "\013IBS" /* Instruction based sampling */ + "\014SSE5" /* SSE5 */ + "\015SKINIT" /* SKINIT/STGI */ + "\016WDT" /* Watchdog timer */ "\017<b14>" "\020<b15>" "\021<b16>" diff --git a/sys/amd64/include/specialreg.h b/sys/amd64/include/specialreg.h index cd9da86d483e..674638c5c851 100644 --- a/sys/amd64/include/specialreg.h +++ b/sys/amd64/include/specialreg.h @@ -150,7 +150,15 @@ #define AMDID2_SVM 0x00000004 #define AMDID2_EXT_APIC 0x00000008 #define AMDID2_CR8 0x00000010 +#define AMDID2_ABM 0x00000020 +#define AMDID2_SSE4A 0x00000040 +#define AMDID2_MAS 0x00000080 #define AMDID2_PREFETCH 0x00000100 +#define AMDID2_OSVW 0x00000200 +#define AMDID2_IBS 0x00000400 +#define AMDID2_SSE5 0x00000800 +#define AMDID2_SKINIT 0x00001000 +#define AMDID2_WDT 0x00002000 /* * CPUID instruction 1 eax info diff --git a/sys/i386/i386/identcpu.c b/sys/i386/i386/identcpu.c index 67ff94397566..cf70af7aab63 100644 --- a/sys/i386/i386/identcpu.c +++ b/sys/i386/i386/identcpu.c @@ -826,15 +826,15 @@ printcpuinfo(void) "\003SVM" /* Secure Virtual Mode */ "\004ExtAPIC" /* Extended APIC register */ "\005CR8" /* CR8 in legacy mode */ - "\006<b5>" - "\007<b6>" - "\010<b7>" + "\006ABM" /* LZCNT instruction */ + "\007SSE4A" /* SSE4A */ + "\010MAS" /* Misaligned SSE mode */ "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ - "\012<b9>" - "\013<b10>" - "\014<b11>" - "\015<b12>" - "\016<b13>" + "\012OSVW" /* OS visible workaround */ + "\013IBS" /* Instruction based sampling */ + "\014SSE5" /* SSE5 */ + "\015SKINIT" /* SKINIT/STGI */ + "\016WDT" /* Watchdog timer */ "\017<b14>" "\020<b15>" "\021<b16>" diff --git a/sys/i386/include/specialreg.h b/sys/i386/include/specialreg.h index b4842e9d414c..c3cbec72abd4 100644 --- a/sys/i386/include/specialreg.h +++ b/sys/i386/include/specialreg.h @@ -147,7 +147,15 @@ #define AMDID2_SVM 0x00000004 #define AMDID2_EXT_APIC 0x00000008 #define AMDID2_CR8 0x00000010 +#define AMDID2_ABM 0x00000020 +#define AMDID2_SSE4A 0x00000040 +#define AMDID2_MAS 0x00000080 #define AMDID2_PREFETCH 0x00000100 +#define AMDID2_OSVW 0x00000200 +#define AMDID2_IBS 0x00000400 +#define AMDID2_SSE5 0x00000800 +#define AMDID2_SKINIT 0x00001000 +#define AMDID2_WDT 0x00002000 /* * CPUID instruction 1 eax info |