9 files changed, 33 insertions, 33 deletions

diff --git a/sys/dev/iommu/busdma_iommu.c b/sys/dev/iommu/busdma_iommu.c
index a4fe8ee9d063..0fd54e8b641a 100644
--- a/sys/dev/iommu/busdma_iommu.c
+++ b/sys/dev/iommu/busdma_iommu.c
@@ -299,7 +299,7 @@ acpi_iommu_get_dma_tag(device_t dev, device_t child)
 }
 
 bool
-bus_dma_dmar_set_buswide(device_t dev)
+bus_dma_iommu_set_buswide(device_t dev)
 {
 	struct iommu_unit *unit;
 	device_t parent;
@@ -317,12 +317,12 @@ bus_dma_dmar_set_buswide(device_t dev)
 	if (slot != 0 || func != 0) {
 		if (bootverbose) {
 			device_printf(dev,
-			    "dmar%d pci%d:%d:%d requested buswide busdma\n",
+			    "iommu%d pci%d:%d:%d requested buswide busdma\n",
 			    unit->unit, busno, slot, func);
 		}
 		return (false);
 	}
-	dmar_set_buswide_ctx(unit, busno);
+	iommu_set_buswide_ctx(unit, busno);
 	return (true);
 }
 
@@ -987,7 +987,7 @@ iommu_fini_busdma(struct iommu_unit *unit)
 }
 
 int
-bus_dma_dmar_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map1,
+bus_dma_iommu_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map1,
     vm_paddr_t start, vm_size_t length, int flags)
 {
 	struct bus_dma_tag_common *tc;
diff --git a/sys/dev/iommu/iommu.h b/sys/dev/iommu/iommu.h
index c3bc3d26b765..380f4cdfe5f6 100644
--- a/sys/dev/iommu/iommu.h
+++ b/sys/dev/iommu/iommu.h
@@ -34,11 +34,13 @@
 #ifndef _SYS_IOMMU_H_
 #define _SYS_IOMMU_H_
 
+#include <sys/types.h>
 #include <sys/queue.h>
 #include <sys/sysctl.h>
 #include <sys/taskqueue.h>
 #include <sys/tree.h>
-#include <sys/types.h>
+
+#include <dev/pci/pcireg.h>
 
 /* Host or physical memory address, after translation. */
 typedef uint64_t iommu_haddr_t;
@@ -96,6 +98,14 @@ struct iommu_unit {
 	struct task dmamap_load_task;
 	TAILQ_HEAD(, bus_dmamap_iommu) delayed_maps;
 	struct taskqueue *delayed_taskqueue;
+
+	/*
+	 * Bitmap of buses for which context must ignore slot:func,
+	 * duplicating the page table pointer into all context table
+	 * entries.  This is a client-controlled quirk to support some
+	 * NTBs.
+	 */
+	uint32_t buswide_ctxs[(PCI_BUSMAX + 1) / NBBY / sizeof(uint32_t)];
 };
 
 /*
diff --git a/sys/dev/ntb/ntb_hw/ntb_hw_intel.c b/sys/dev/ntb/ntb_hw/ntb_hw_intel.c
index 9182461fe9a5..ba61fdc9ffcd 100644
--- a/sys/dev/ntb/ntb_hw/ntb_hw_intel.c
+++ b/sys/dev/ntb/ntb_hw/ntb_hw_intel.c
@@ -811,7 +811,7 @@ intel_ntb_map_pci_bars(struct ntb_softc *ntb)
 		device_printf(ntb->device, "Unable to create BAR0 map\n");
 		return (ENOMEM);
 	}
-	if (bus_dma_dmar_load_ident(ntb->bar0_dma_tag, ntb->bar0_dma_map,
+	if (bus_dma_iommu_load_ident(ntb->bar0_dma_tag, ntb->bar0_dma_map,
 	    bar->pbase, bar->size, 0)) {
 		device_printf(ntb->device, "Unable to load BAR0 map\n");
 		return (ENOMEM);
diff --git a/sys/dev/ntb/ntb_hw/ntb_hw_plx.c b/sys/dev/ntb/ntb_hw/ntb_hw_plx.c
index 97df9ce3a4cc..a9654e7f6725 100644
--- a/sys/dev/ntb/ntb_hw/ntb_hw_plx.c
+++ b/sys/dev/ntb/ntb_hw/ntb_hw_plx.c
@@ -343,7 +343,7 @@ ntb_plx_attach(device_t dev)
 	 * The device occupies whole bus.  In translated TLP slot field
 	 * keeps LUT index (original bus/slot), function is passed through.
 	 */
-	bus_dma_dmar_set_buswide(dev);
+	bus_dma_iommu_set_buswide(dev);
 
 	/* Identify chip port we are connected to. */
 	val = bus_read_4(sc->conf_res, 0x360);
diff --git a/sys/x86/include/bus_dma.h b/sys/x86/include/bus_dma.h
index 5bb70419726a..a87143609259 100644
--- a/sys/x86/include/bus_dma.h
+++ b/sys/x86/include/bus_dma.h
@@ -192,8 +192,8 @@ _bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map,
 }
 
 #ifdef _KERNEL
-bool bus_dma_dmar_set_buswide(device_t dev);
-int bus_dma_dmar_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map,
+bool bus_dma_iommu_set_buswide(device_t dev);
+int bus_dma_iommu_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map,
     vm_paddr_t start, vm_size_t length, int flags);
 #endif
 
diff --git a/sys/x86/iommu/intel_ctx.c b/sys/x86/iommu/intel_ctx.c
index 45151c8dd355..edd59e5f2477 100644
--- a/sys/x86/iommu/intel_ctx.c
+++ b/sys/x86/iommu/intel_ctx.c
@@ -196,7 +196,7 @@ ctx_id_entry_init(struct dmar_ctx *ctx, dmar_ctx_entry_t *ctxp, bool move,
 		    IOMMU_PGF_NOALLOC);
 	}
 
-	if (dmar_is_buswide_ctx(unit, busno)) {
+	if (iommu_is_buswide_ctx((struct iommu_unit *)unit, busno)) {
 		MPASS(!move);
 		for (i = 0; i <= PCI_BUSMAX; i++) {
 			ctx_id_entry_init_one(&ctxp[i], domain, ctx_root);
@@ -464,6 +464,7 @@ dmar_get_ctx_for_dev1(struct dmar_unit *dmar, device_t dev, uint16_t rid,
 {
 	struct dmar_domain *domain, *domain1;
 	struct dmar_ctx *ctx, *ctx1;
+	struct iommu_unit *unit;
 	dmar_ctx_entry_t *ctxp;
 	struct sf_buf *sf;
 	int bus, slot, func, error;
@@ -480,9 +481,10 @@ dmar_get_ctx_for_dev1(struct dmar_unit *dmar, device_t dev, uint16_t rid,
 	}
 	enable = false;
 	TD_PREP_PINNED_ASSERT;
+	unit = (struct iommu_unit *)dmar;
 	DMAR_LOCK(dmar);
-	KASSERT(!dmar_is_buswide_ctx(dmar, bus) || (slot == 0 && func == 0),
-	    ("dmar%d pci%d:%d:%d get_ctx for buswide", dmar->iommu.unit, bus,
+	KASSERT(!iommu_is_buswide_ctx(unit, bus) || (slot == 0 && func == 0),
+	    ("iommu%d pci%d:%d:%d get_ctx for buswide", dmar->iommu.unit, bus,
 	    slot, func));
 	ctx = dmar_find_ctx_locked(dmar, rid);
 	error = 0;
diff --git a/sys/x86/iommu/intel_dmar.h b/sys/x86/iommu/intel_dmar.h
index fba5e36f95cd..49a94190b496 100644
--- a/sys/x86/iommu/intel_dmar.h
+++ b/sys/x86/iommu/intel_dmar.h
@@ -167,15 +167,6 @@ struct dmar_unit {
 	struct iommu_map_entries_tailq tlb_flush_entries;
 	struct task qi_task;
 	struct taskqueue *qi_taskqueue;
-
-	/*
-	 * Bitmap of buses for which context must ignore slot:func,
-	 * duplicating the page table pointer into all context table
-	 * entries.  This is a client-controlled quirk to support some
-	 * NTBs.
-	 */
-	uint32_t buswide_ctxs[(PCI_BUSMAX + 1) / NBBY / sizeof(uint32_t)];
-
 };
 
 #define	DMAR_LOCK(dmar)		mtx_lock(&(dmar)->iommu.lock)
@@ -290,8 +281,8 @@ void dmar_quirks_pre_use(struct iommu_unit *dmar);
 int dmar_init_irt(struct dmar_unit *unit);
 void dmar_fini_irt(struct dmar_unit *unit);
 
-void dmar_set_buswide_ctx(struct iommu_unit *unit, u_int busno);
-bool dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno);
+void iommu_set_buswide_ctx(struct iommu_unit *unit, u_int busno);
+bool iommu_is_buswide_ctx(struct iommu_unit *unit, u_int busno);
 
 extern iommu_haddr_t dmar_high;
 extern int haw;
diff --git a/sys/x86/iommu/intel_drv.c b/sys/x86/iommu/intel_drv.c
index a8a2bc7cf770..4af5da538840 100644
--- a/sys/x86/iommu/intel_drv.c
+++ b/sys/x86/iommu/intel_drv.c
@@ -593,21 +593,18 @@ DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
 
 void
-dmar_set_buswide_ctx(struct iommu_unit *unit, u_int busno)
+iommu_set_buswide_ctx(struct iommu_unit *unit, u_int busno)
 {
-	struct dmar_unit *dmar;
-
-	dmar = (struct dmar_unit *)unit;
 
 	MPASS(busno <= PCI_BUSMAX);
-	DMAR_LOCK(dmar);
-	dmar->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] |=
+	IOMMU_LOCK(unit);
+	unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] |=
 	    1 << (busno % (NBBY * sizeof(uint32_t)));
-	DMAR_UNLOCK(dmar);
+	IOMMU_UNLOCK(unit);
 }
 
 bool
-dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno)
+iommu_is_buswide_ctx(struct iommu_unit *unit, u_int busno)
 {
 
 	MPASS(busno <= PCI_BUSMAX);
diff --git a/sys/x86/x86/busdma_machdep.c b/sys/x86/x86/busdma_machdep.c
index 3442313f55c8..3dade64692d6 100644
--- a/sys/x86/x86/busdma_machdep.c
+++ b/sys/x86/x86/busdma_machdep.c
@@ -301,13 +301,13 @@ bus_dma_tag_destroy(bus_dma_tag_t dmat)
 
 #ifndef ACPI_DMAR
 bool
-bus_dma_dmar_set_buswide(device_t dev)
+bus_dma_iommu_set_buswide(device_t dev)
 {
 	return (false);
 }
 
 int
-bus_dma_dmar_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map,
+bus_dma_iommu_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map,
     vm_paddr_t start, vm_size_t length, int flags)
 {
 	return (0);