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| author | Emmanuel Vadot <manu@FreeBSD.org> | 2017-06-20 02:28:15 +0000 |
|---|---|---|
| committer | Emmanuel Vadot <manu@FreeBSD.org> | 2017-06-20 02:28:15 +0000 |
| commit | 8fdc67f730291b64de002bf95d19ae75e058b8ce (patch) | |
| tree | 7168a4d1758594b7d9d103004964d3ab4a44d2a3 /Bindings/devfreq | |
| parent | ff018dbf5bb142aa83bd955e5b6c55d66e9e9c1e (diff) | |
| download | src-8fdc67f730291b64de002bf95d19ae75e058b8ce.tar.gz src-8fdc67f730291b64de002bf95d19ae75e058b8ce.zip | |
Notes
Diffstat (limited to 'Bindings/devfreq')
| -rw-r--r-- | Bindings/devfreq/exynos-bus.txt | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/Bindings/devfreq/exynos-bus.txt b/Bindings/devfreq/exynos-bus.txt index d3ec8e676b6b..d085ef90d27c 100644 --- a/Bindings/devfreq/exynos-bus.txt +++ b/Bindings/devfreq/exynos-bus.txt @@ -123,6 +123,20 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC: |--- FSYS |--- FSYS2 +- In case of Exynos5433, there is VDD_INT power line as following: + VDD_INT |--- G2D (parent device) + |--- MSCL + |--- GSCL + |--- JPEG + |--- MFC + |--- HEVC + |--- BUS0 + |--- BUS1 + |--- BUS2 + |--- PERIS (Fixed clock rate) + |--- PERIC (Fixed clock rate) + |--- FSYS (Fixed clock rate) + Example1: Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to power line (regulator). The MIF (Memory Interface) AXI bus is used to |