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| author | Dimitry Andric <dim@FreeBSD.org> | 2022-07-27 20:11:54 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2023-02-08 19:04:48 +0000 |
| commit | 972a253a57b6f144b0e4a3e2080a2a0076ec55a0 (patch) | |
| tree | a8aeeb0997a0a52500f1fa0644244206cf71df94 /contrib/llvm-project/clang/utils/TableGen/TableGen.cpp | |
| parent | fcaf7f8644a9988098ac6be2165bce3ea4786e91 (diff) | |
| parent | 08e8dd7b9db7bb4a9de26d44c1cbfd24e869c014 (diff) | |
Diffstat (limited to 'contrib/llvm-project/clang/utils/TableGen/TableGen.cpp')
| -rw-r--r-- | contrib/llvm-project/clang/utils/TableGen/TableGen.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/contrib/llvm-project/clang/utils/TableGen/TableGen.cpp b/contrib/llvm-project/clang/utils/TableGen/TableGen.cpp index bb9366e2b7fc..d18a31226e80 100644 --- a/contrib/llvm-project/clang/utils/TableGen/TableGen.cpp +++ b/contrib/llvm-project/clang/utils/TableGen/TableGen.cpp @@ -88,6 +88,7 @@ enum ActionType { GenRISCVVectorHeader, GenRISCVVectorBuiltins, GenRISCVVectorBuiltinCG, + GenRISCVVectorBuiltinSema, GenAttrDocs, GenDiagDocs, GenOptDocs, @@ -243,6 +244,8 @@ cl::opt<ActionType> Action( "Generate riscv_vector_builtins.inc for clang"), clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen", "Generate riscv_vector_builtin_cg.inc for clang"), + clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema", + "Generate riscv_vector_builtin_sema.inc for clang"), clEnumValN(GenAttrDocs, "gen-attr-docs", "Generate attribute documentation"), clEnumValN(GenDiagDocs, "gen-diag-docs", @@ -458,6 +461,9 @@ bool ClangTableGenMain(raw_ostream &OS, RecordKeeper &Records) { case GenRISCVVectorBuiltinCG: EmitRVVBuiltinCG(Records, OS); break; + case GenRISCVVectorBuiltinSema: + EmitRVVBuiltinSema(Records, OS); + break; case GenAttrDocs: EmitClangAttrDocs(Records, OS); break; |