diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2023-12-18 20:30:12 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2024-04-06 20:11:55 +0000 |
| commit | 5f757f3ff9144b609b3c433dfd370cc6bdc191ad (patch) | |
| tree | 1b4e980b866cd26a00af34c0a653eb640bd09caf /contrib/llvm-project/llvm/lib/CodeGen/MachineCSE.cpp | |
| parent | 3e1c8a35f741a5d114d0ba670b15191355711fe9 (diff) | |
| parent | 312c0ed19cc5276a17bacf2120097bec4515b0f1 (diff) | |
Diffstat (limited to 'contrib/llvm-project/llvm/lib/CodeGen/MachineCSE.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/CodeGen/MachineCSE.cpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/contrib/llvm-project/llvm/lib/CodeGen/MachineCSE.cpp b/contrib/llvm-project/llvm/lib/CodeGen/MachineCSE.cpp index f879c5fcf20c..26a8d00e6626 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/MachineCSE.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/MachineCSE.cpp @@ -44,7 +44,6 @@ #include <cassert> #include <iterator> #include <utility> -#include <vector> using namespace llvm; @@ -65,6 +64,10 @@ static cl::opt<int> CSUsesThreshold("csuses-threshold", cl::Hidden, cl::init(1024), cl::desc("Threshold for the size of CSUses")); +static cl::opt<bool> AggressiveMachineCSE( + "aggressive-machine-cse", cl::Hidden, cl::init(false), + cl::desc("Override the profitability heuristics for Machine CSE")); + namespace { class MachineCSE : public MachineFunctionPass { @@ -403,7 +406,7 @@ bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI, bool MachineCSE::isCSECandidate(MachineInstr *MI) { if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() || MI->isKill() || - MI->isInlineAsm() || MI->isDebugInstr()) + MI->isInlineAsm() || MI->isDebugInstr() || MI->isJumpTableDebugInfo()) return false; // Ignore copies. @@ -439,6 +442,9 @@ bool MachineCSE::isCSECandidate(MachineInstr *MI) { /// defined. bool MachineCSE::isProfitableToCSE(Register CSReg, Register Reg, MachineBasicBlock *CSBB, MachineInstr *MI) { + if (AggressiveMachineCSE) + return true; + // FIXME: Heuristics that works around the lack the live range splitting. // If CSReg is used at all uses of Reg, CSE should not increase register |