diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2022-03-20 11:40:34 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2022-05-14 11:43:05 +0000 |
| commit | 349cc55c9796c4596a5b9904cd3281af295f878f (patch) | |
| tree | 410c5a785075730a35f1272ca6a7adf72222ad03 /contrib/llvm-project/llvm/lib/CodeGen/MachineOutliner.cpp | |
| parent | cb2ae6163174b90e999326ecec3699ee093a5d43 (diff) | |
| parent | c0981da47d5696fe36474fcf86b4ce03ae3ff818 (diff) | |
Diffstat (limited to 'contrib/llvm-project/llvm/lib/CodeGen/MachineOutliner.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/CodeGen/MachineOutliner.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/contrib/llvm-project/llvm/lib/CodeGen/MachineOutliner.cpp b/contrib/llvm-project/llvm/lib/CodeGen/MachineOutliner.cpp index 1d55bd00e033..cfbccebaff3e 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/MachineOutliner.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/MachineOutliner.cpp @@ -798,6 +798,7 @@ bool MachineOutliner::outline(Module &M, Last = std::next(CallInst.getReverse()); Iter != Last; Iter++) { MachineInstr *MI = &*Iter; + SmallSet<Register, 2> InstrUseRegs; for (MachineOperand &MOP : MI->operands()) { // Skip over anything that isn't a register. if (!MOP.isReg()) @@ -806,7 +807,8 @@ bool MachineOutliner::outline(Module &M, if (MOP.isDef()) { // Introduce DefRegs set to skip the redundant register. DefRegs.insert(MOP.getReg()); - if (!MOP.isDead() && UseRegs.count(MOP.getReg())) + if (UseRegs.count(MOP.getReg()) && + !InstrUseRegs.count(MOP.getReg())) // Since the regiester is modeled as defined, // it is not necessary to be put in use register set. UseRegs.erase(MOP.getReg()); @@ -814,6 +816,7 @@ bool MachineOutliner::outline(Module &M, // Any register which is not undefined should // be put in the use register set. UseRegs.insert(MOP.getReg()); + InstrUseRegs.insert(MOP.getReg()); } } if (MI->isCandidateForCallSiteEntry()) |