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author | Dimitry Andric <dim@FreeBSD.org> | 2024-01-09 20:00:28 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2024-04-06 20:13:28 +0000 |
commit | 1db9f3b21e39176dd5b67cf8ac378633b172463e (patch) | |
tree | 71bca5bd62db6368f0738c961b2d87e14c8cb602 /contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | |
parent | 412fa3436f0d1fe4a7e5e3b66783aa40f599125e (diff) | |
parent | aca2e42c67292825f835f094eb0c4df5ce6013db (diff) | |
download | src-1db9f3b21e39176dd5b67cf8ac378633b172463e.tar.gz src-1db9f3b21e39176dd5b67cf8ac378633b172463e.zip |
Diffstat (limited to 'contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp')
-rw-r--r-- | contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 66461b26468f..ec74d2940099 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -1442,7 +1442,7 @@ void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0)); Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); - uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); + uint64_t IdxVal = Idx->getAsZExtVal(); Hi = DAG.getNode( ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, DAG.getVectorIdxConstant(IdxVal + LoVT.getVectorMinNumElements(), dl)); @@ -1466,7 +1466,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo, // If we know the index is in the first half, and we know the subvector // doesn't cross the boundary between the halves, we can avoid spilling the // vector, and insert into the lower half of the split vector directly. - unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); + unsigned IdxVal = Idx->getAsZExtVal(); if (IdxVal + SubElems <= LoElems) { Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); return; @@ -3279,7 +3279,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_INSERT_SUBVECTOR(SDNode *N, SDValue Lo, Hi; GetSplitVector(SubVec, Lo, Hi); - uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); + uint64_t IdxVal = Idx->getAsZExtVal(); uint64_t LoElts = Lo.getValueType().getVectorMinNumElements(); SDValue FirstInsertion = @@ -3301,7 +3301,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { GetSplitVector(N->getOperand(0), Lo, Hi); uint64_t LoEltsMin = Lo.getValueType().getVectorMinNumElements(); - uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); + uint64_t IdxVal = Idx->getAsZExtVal(); if (IdxVal < LoEltsMin) { assert(IdxVal + SubVT.getVectorMinNumElements() <= LoEltsMin && @@ -5257,7 +5257,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { EVT InVT = InOp.getValueType(); // Check if we can just return the input vector after widening. - uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); + uint64_t IdxVal = Idx->getAsZExtVal(); if (IdxVal == 0 && InVT == WidenVT) return InOp; |