diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2023-09-02 21:17:18 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2023-12-08 17:34:50 +0000 |
| commit | 06c3fb2749bda94cb5201f81ffdb8fa6c3161b2e (patch) | |
| tree | 62f873df87c7c675557a179e0c4c83fe9f3087bc /contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp | |
| parent | cf037972ea8863e2bab7461d77345367d2c1e054 (diff) | |
| parent | 7fa27ce4a07f19b07799a767fc29416f3b625afb (diff) | |
Diffstat (limited to 'contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp index a41d5999d961..77d2dfcf2323 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/MachineValueType.h" #include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" @@ -33,7 +34,6 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" -#include "llvm/Support/MachineValueType.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Printable.h" #include "llvm/Support/raw_ostream.h" @@ -79,8 +79,8 @@ bool TargetRegisterInfo::shouldRegionSplitForVirtReg( void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const { - for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI) - RegisterSet.set(*AI); + for (MCPhysReg SR : superregs_inclusive(Reg)) + RegisterSet.set(SR); } bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet, @@ -90,9 +90,9 @@ bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet, for (unsigned Reg : RegisterSet.set_bits()) { if (Checked[Reg]) continue; - for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) { - if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) { - dbgs() << "Error: Super register " << printReg(*SR, this) + for (MCPhysReg SR : superregs(Reg)) { + if (!RegisterSet[SR] && !is_contained(Exceptions, Reg)) { + dbgs() << "Error: Super register " << printReg(SR, this) << " of reserved register " << printReg(Reg, this) << " is not reserved.\n"; return false; @@ -100,7 +100,7 @@ bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet, // We transitively check superregs. So we can remember this for later // to avoid compiletime explosion in deep register hierarchies. - Checked.set(*SR); + Checked.set(SR); } } return true; @@ -281,7 +281,7 @@ const TargetRegisterClass *firstCommonClass(const uint32_t *A, const TargetRegisterInfo *TRI) { for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32) if (unsigned Common = *A++ & *B++) - return TRI->getRegClass(I + countTrailingZeros(Common)); + return TRI->getRegClass(I + llvm::countr_zero(Common)); return nullptr; } @@ -424,8 +424,8 @@ bool TargetRegisterInfo::getRegAllocationHints( SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const { const MachineRegisterInfo &MRI = MF.getRegInfo(); - const std::pair<Register, SmallVector<Register, 4>> &Hints_MRI = - MRI.getRegAllocationHints(VirtReg); + const std::pair<unsigned, SmallVector<Register, 4>> &Hints_MRI = + MRI.getRegAllocationHints(VirtReg); SmallSet<Register, 32> HintedRegs; // First hint may be a target hint. |