diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2021-12-25 22:36:56 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2022-05-14 11:44:01 +0000 |
| commit | 0eae32dcef82f6f06de6419a0d623d7def0cc8f6 (patch) | |
| tree | 55b7e05be47b835fd137915bee1e64026c35e71c /contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp | |
| parent | 4824e7fd18a1223177218d4aec1b3c6c5c4a444e (diff) | |
| parent | 77fc4c146f0870ffb09c1afb823ccbe742c5e6ff (diff) | |
Diffstat (limited to 'contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp index f4bb71535f7f..f5cb518fce3e 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp @@ -248,8 +248,8 @@ static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R){ assert(RC->isAllocatable() && "invalid for nonallocatable sets"); ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); - for (unsigned i = 0; i != Order.size(); ++i) - R.set(Order[i]); + for (MCPhysReg PR : Order) + R.set(PR); } BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, |