diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2020-01-22 20:31:01 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2020-01-22 20:31:01 +0000 |
| commit | 8bcb0991864975618c09697b1aca10683346d9f0 (patch) | |
| tree | 0afab28faa50e5f27698f8dd6c1921fff8d25e39 /contrib/llvm-project/llvm/lib/CodeGen/TargetSchedule.cpp | |
| parent | b14637d118e110006a149a79b649c5695e7f419a (diff) | |
| parent | 1d5ae1026e831016fc29fd927877c86af904481f (diff) | |
Notes
Diffstat (limited to 'contrib/llvm-project/llvm/lib/CodeGen/TargetSchedule.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/CodeGen/TargetSchedule.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/contrib/llvm-project/llvm/lib/CodeGen/TargetSchedule.cpp b/contrib/llvm-project/llvm/lib/CodeGen/TargetSchedule.cpp index 195279719ad4..ce59452fd1b8 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/TargetSchedule.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/TargetSchedule.cpp @@ -300,7 +300,7 @@ computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, // TODO: The following hack exists because predication passes do not // correctly append imp-use operands, and readsReg() strangely returns false // for predicated defs. - unsigned Reg = DefMI->getOperand(DefOperIdx).getReg(); + Register Reg = DefMI->getOperand(DefOperIdx).getReg(); const MachineFunction &MF = *DefMI->getMF(); const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI)) |