diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2021-08-22 19:00:43 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2021-11-13 20:39:49 +0000 |
| commit | fe6060f10f634930ff71b7c50291ddc610da2475 (patch) | |
| tree | 1483580c790bd4d27b6500a7542b5ee00534d3cc /contrib/llvm-project/llvm/lib/Target/ARM/ARMInstructionSelector.cpp | |
| parent | b61bce17f346d79cecfd8f195a64b10f77be43b1 (diff) | |
| parent | 344a3780b2e33f6ca763666c380202b18aab72a3 (diff) | |
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/ARM/ARMInstructionSelector.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/ARM/ARMInstructionSelector.cpp | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/contrib/llvm-project/llvm/lib/Target/ARM/ARMInstructionSelector.cpp index 09a94cc3a8e8..8be4e3f160e3 100644 --- a/contrib/llvm-project/llvm/lib/Target/ARM/ARMInstructionSelector.cpp +++ b/contrib/llvm-project/llvm/lib/Target/ARM/ARMInstructionSelector.cpp @@ -1096,24 +1096,6 @@ bool ARMInstructionSelector::select(MachineInstr &I) { if (NewOpc == G_LOAD || NewOpc == G_STORE) return false; - if (ValSize == 1 && NewOpc == Opcodes.STORE8) { - // Before storing a 1-bit value, make sure to clear out any unneeded bits. - Register OriginalValue = I.getOperand(0).getReg(); - - Register ValueToStore = MRI.createVirtualRegister(&ARM::GPRRegClass); - I.getOperand(0).setReg(ValueToStore); - - auto InsertBefore = I.getIterator(); - auto AndI = BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.AND)) - .addDef(ValueToStore) - .addUse(OriginalValue) - .addImm(1) - .add(predOps(ARMCC::AL)) - .add(condCodeOp()); - if (!constrainSelectedInstRegOperands(*AndI, TII, TRI, RBI)) - return false; - } - I.setDesc(TII.get(NewOpc)); if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH) |