diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2021-12-02 21:49:08 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2022-06-04 11:59:04 +0000 |
| commit | 574b7079b96703a748f89ef5adb7dc3e26b8f7fc (patch) | |
| tree | 195000196b1e0cc13dea43258fa240e006f48184 /contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp | |
| parent | 1f6fd64fe9c996b4795ee4a6c66b8f9216747560 (diff) | |
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp | 23 |
1 files changed, 9 insertions, 14 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp index d8d2025c5d27..1a66394e9757 100644 --- a/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp @@ -205,16 +205,14 @@ bool HexagonGenPredicate::isConvertibleToPredForm(const MachineInstr *MI) { } void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) { - for (MachineFunction::iterator A = MF.begin(), Z = MF.end(); A != Z; ++A) { - MachineBasicBlock &B = *A; - for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) { - MachineInstr *MI = &*I; - unsigned Opc = MI->getOpcode(); + for (MachineBasicBlock &B : MF) { + for (MachineInstr &MI : B) { + unsigned Opc = MI.getOpcode(); switch (Opc) { case Hexagon::C2_tfrpr: case TargetOpcode::COPY: - if (isPredReg(MI->getOperand(1).getReg())) { - RegisterSubReg RD = MI->getOperand(0); + if (isPredReg(MI.getOperand(1).getReg())) { + RegisterSubReg RD = MI.getOperand(0); if (RD.R.isVirtual()) PredGPRs.insert(RD); } @@ -411,7 +409,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { NumOps = 2; } - // Some sanity: check that def is in operand #0. + // Check that def is in operand #0. MachineOperand &Op0 = MI->getOperand(0); assert(Op0.isDef()); RegisterSubReg OutR(Op0); @@ -488,8 +486,8 @@ bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) { } } - for (VectOfInst::iterator I = Erase.begin(), E = Erase.end(); I != E; ++I) - (*I)->eraseFromParent(); + for (MachineInstr *MI : Erase) + MI->eraseFromParent(); return Changed; } @@ -515,11 +513,8 @@ bool HexagonGenPredicate::runOnMachineFunction(MachineFunction &MF) { Again = false; VectOfInst Processed, Copy; - using iterator = VectOfInst::iterator; - Copy = PUsers; - for (iterator I = Copy.begin(), E = Copy.end(); I != E; ++I) { - MachineInstr *MI = *I; + for (MachineInstr *MI : Copy) { bool Done = convertToPredForm(MI); if (Done) { Processed.insert(MI); |
