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author | Dimitry Andric <dim@FreeBSD.org> | 2022-03-20 11:40:34 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2022-05-14 11:43:05 +0000 |
commit | 349cc55c9796c4596a5b9904cd3281af295f878f (patch) | |
tree | 410c5a785075730a35f1272ca6a7adf72222ad03 /contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | |
parent | cb2ae6163174b90e999326ecec3699ee093a5d43 (diff) | |
parent | c0981da47d5696fe36474fcf86b4ce03ae3ff818 (diff) | |
download | src-349cc55c9796c4596a5b9904cd3281af295f878f.tar.gz src-349cc55c9796c4596a5b9904cd3281af295f878f.zip |
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp')
-rw-r--r-- | contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index f14eaacbf071..76220eff4d51 100644 --- a/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -169,13 +169,13 @@ MachineInstr *HexagonInstrInfo::findLoopInstr(MachineBasicBlock *BB, continue; if (PB == BB) continue; - for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) { - unsigned Opc = I->getOpcode(); + for (MachineInstr &I : llvm::reverse(PB->instrs())) { + unsigned Opc = I.getOpcode(); if (Opc == LOOPi || Opc == LOOPr) - return &*I; + return &I; // We've reached a different loop, which means the loop01 has been // removed. - if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB) + if (Opc == EndLoopOp && I.getOperand(0).getMBB() != TargetBB) return nullptr; } // Check the predecessors for the LOOP instruction. @@ -1791,8 +1791,8 @@ HexagonInstrInfo::CreateTargetPostRAHazardRecognizer( /// compares against in CmpValue. Return true if the comparison instruction /// can be analyzed. bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg, - Register &SrcReg2, int &Mask, - int &Value) const { + Register &SrcReg2, int64_t &Mask, + int64_t &Value) const { unsigned Opc = MI.getOpcode(); // Set mask and the first source register. @@ -3627,8 +3627,8 @@ int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const { switch (MI.getOpcode()) { default: - report_fatal_error(std::string("Unknown .new type: ") + - std::to_string(MI.getOpcode())); + report_fatal_error(Twine("Unknown .new type: ") + + std::to_string(MI.getOpcode())); case Hexagon::S4_storerb_ur: return Hexagon::S4_storerbnew_ur; |