diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2021-12-02 21:49:08 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2022-06-04 11:59:04 +0000 |
| commit | 574b7079b96703a748f89ef5adb7dc3e26b8f7fc (patch) | |
| tree | 195000196b1e0cc13dea43258fa240e006f48184 /contrib/llvm-project/llvm/lib/Target/X86/X86DomainReassignment.cpp | |
| parent | 1f6fd64fe9c996b4795ee4a6c66b8f9216747560 (diff) | |
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/X86/X86DomainReassignment.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/X86/X86DomainReassignment.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/X86/X86DomainReassignment.cpp b/contrib/llvm-project/llvm/lib/Target/X86/X86DomainReassignment.cpp index a2ae6345c006..9826bf4bf861 100644 --- a/contrib/llvm-project/llvm/lib/Target/X86/X86DomainReassignment.cpp +++ b/contrib/llvm-project/llvm/lib/Target/X86/X86DomainReassignment.cpp @@ -186,8 +186,8 @@ public: TII->getRegClass(TII->get(DstOpcode), 0, MRI->getTargetRegisterInfo(), *MBB->getParent())); MachineInstrBuilder Bld = BuildMI(*MBB, MI, DL, TII->get(DstOpcode), Reg); - for (unsigned Idx = 1, End = MI->getNumOperands(); Idx < End; ++Idx) - Bld.add(MI->getOperand(Idx)); + for (const MachineOperand &MO : llvm::drop_begin(MI->operands())) + Bld.add(MO); BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY)) .add(MI->getOperand(0)) |