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authorDimitry Andric <dim@FreeBSD.org>2018-07-30 16:33:32 +0000
committerDimitry Andric <dim@FreeBSD.org>2018-07-30 16:33:32 +0000
commit51315c45ff5643a27f9c84b816db54ee870ba29b (patch)
tree1d87443fa0e53d3e6b315ce25787e64be0906bf7 /contrib/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
parent6dfd050075216be8538ae375a22d30db72916f7e (diff)
parenteb11fae6d08f479c0799db45860a98af528fa6e7 (diff)
Notes
Diffstat (limited to 'contrib/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h')
-rw-r--r--contrib/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h15
1 files changed, 13 insertions, 2 deletions
diff --git a/contrib/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h b/contrib/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
index a9b6073106ea..b14bbad2039a 100644
--- a/contrib/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
+++ b/contrib/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
@@ -45,6 +45,11 @@ class PPCFunctionInfo : public MachineFunctionInfo {
/// PEI.
bool MustSaveLR;
+ /// Do we have to disable shrink-wrapping? This has to be set if we emit any
+ /// instructions that clobber LR in the entry block because discovering this
+ /// in PEI is too late (happens after shrink-wrapping);
+ bool ShrinkWrapDisabled = false;
+
/// Does this function have any stack spills.
bool HasSpills = false;
@@ -147,6 +152,12 @@ public:
void setMustSaveLR(bool U) { MustSaveLR = U; }
bool mustSaveLR() const { return MustSaveLR; }
+ /// We certainly don't want to shrink wrap functions if we've emitted a
+ /// MovePCtoLR8 as that has to go into the entry, so the prologue definitely
+ /// has to go into the entry block.
+ void setShrinkWrapDisabled(bool U) { ShrinkWrapDisabled = U; }
+ bool shrinkWrapDisabled() const { return ShrinkWrapDisabled; }
+
void setHasSpills() { HasSpills = true; }
bool hasSpills() const { return HasSpills; }
@@ -185,11 +196,11 @@ public:
LiveInAttrs.push_back(std::make_pair(VReg, Flags));
}
- /// This function returns true if the spesified vreg is
+ /// This function returns true if the specified vreg is
/// a live-in register and sign-extended.
bool isLiveInSExt(unsigned VReg) const;
- /// This function returns true if the spesified vreg is
+ /// This function returns true if the specified vreg is
/// a live-in register and zero-extended.
bool isLiveInZExt(unsigned VReg) const;