Backport SSSE3 instruction set support to base binutils - src

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author	Martin Matuska <mm@FreeBSD.org>	2011-07-14 14:23:48 +0000
committer	Martin Matuska <mm@FreeBSD.org>	2011-07-14 14:23:48 +0000
commit	9576b4bf678e131a21b0dc2ab8e3f82510487b8f (patch)
tree	469f8843604d09b440825c32fcaa2864ba738f81 /contrib
parent	f873379c49734df2d0da55c8d2c416163048d3d3 (diff)

Notes

Diffstat (limited to 'contrib')

-rw-r--r--

contrib/binutils/gas/ChangeLog

-rw-r--r--

contrib/binutils/gas/config/tc-i386.c

-rw-r--r--

contrib/binutils/gas/config/tc-i386.h

-rw-r--r--

contrib/binutils/include/opcode/ChangeLog

-rw-r--r--

contrib/binutils/include/opcode/i386.h

-rw-r--r--

contrib/binutils/opcodes/ChangeLog

-rw-r--r--

contrib/binutils/opcodes/i386-dis.c

7 files changed, 209 insertions, 29 deletions

diff --git a/contrib/binutils/gas/ChangeLog b/contrib/binutils/gas/ChangeLog
index df93f2a88f32..457cb87403e4 100644
--- a/contrib/binutils/gas/ChangeLog
+++ b/contrib/binutils/gas/ChangeLog

@@ -1,3 +1,23 @@

+2006-09-28 H.J. Lu <hongjiu.lu@intel.com>

+ * config/tc-i386.h (CpuMNI): Renamed to ...

+ (CpuSSSE3): This.

+ (CpuUnknownFlags): Updated.

+ * config/tc-i386.c: Updated.

+2006-02-27 H.J. Lu <hongjiu.lu@intel.com>

+ * gas/config/tc-i386.c (output_insn): Support Intel Merom New

+ Instructions.

+ * gas/config/tc-i386.h (CpuMNI): New.

+ (CpuUnknownFlags): Add CpuMNI.

+2005-04-12 Mark Kettenis <kettenis@gnu.org>

+ * config/tc-i386.c (output_insn): Handle VIA PadLock instructions

+ similar to other instructions now that they're marked as ImmExt.

2004-05-23 Alan Modra <amodra@bigpond.net.au>

* expr.c (operand, operator): Don't reject '++' and '--'.

diff --git a/contrib/binutils/gas/config/tc-i386.c b/contrib/binutils/gas/config/tc-i386.c
index 5de6a55d2f51..5e6ebf0ea6bd 100644
--- a/contrib/binutils/gas/config/tc-i386.c
+++ b/contrib/binutils/gas/config/tc-i386.c

@@ -3150,24 +3150,33 @@ output_insn ()

/* Output normal instructions here. */

char *p;

unsigned char *q;

+ unsigned int prefix;

- /* All opcodes on i386 have either 1 or 2 bytes, PadLock instructions

- have 3 bytes. We may use one more higher byte to specify a prefix

- the instruction requires. */

- if ((i.tm.cpu_flags & CpuPadLock) != 0

- && (i.tm.base_opcode & 0xff000000) != 0)

- {

- unsigned int prefix;

- prefix = (i.tm.base_opcode >> 24) & 0xff;

- if (prefix != REPE_PREFIX_OPCODE

- || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)

+ /* All opcodes on i386 have either 1 or 2 bytes. Supplemental

+ Streaming SIMD extensions 3 Instructions have 3 bytes. We may

+ use one more higher byte to specify a prefix the instruction

+ requires. */

+ if ((i.tm.cpu_flags & CpuSSSE3) != 0)

+ {

+ if (i.tm.base_opcode & 0xff000000)

+ {

+ prefix = (i.tm.base_opcode >> 24) & 0xff;

+ goto check_prefix;

+ }

+ else if ((i.tm.base_opcode & 0xff0000) != 0)

+ {

+ prefix = (i.tm.base_opcode >> 16) & 0xff;

+ if ((i.tm.cpu_flags & CpuPadLock) != 0)

+ {

+check_prefix:

+ if (prefix != REPE_PREFIX_OPCODE

+ || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)

+ add_prefix (prefix);

+ }

+ else

add_prefix (prefix);

}

- else

- if ((i.tm.cpu_flags & CpuPadLock) == 0

- && (i.tm.base_opcode & 0xff0000) != 0)

- add_prefix ((i.tm.base_opcode >> 16) & 0xff);

/* The prefix bytes. */

for (q = i.prefix;

@@ -3188,7 +3197,7 @@ output_insn ()

}

else

{

- if ((i.tm.cpu_flags & CpuPadLock) != 0)

+ if ((i.tm.cpu_flags & CpuSSSE3) != 0)

{

p = frag_more (3);

*p++ = (i.tm.base_opcode >> 16) & 0xff;

diff --git a/contrib/binutils/gas/config/tc-i386.h b/contrib/binutils/gas/config/tc-i386.h
index 14b522b56495..3354d7f0fe54 100644
--- a/contrib/binutils/gas/config/tc-i386.h
+++ b/contrib/binutils/gas/config/tc-i386.h

@@ -195,13 +195,14 @@ typedef struct

#define Cpu3dnow 0x4000 /* 3dnow! support required */

#define CpuPNI 0x8000 /* Prescott New Instructions required */

#define CpuPadLock 0x10000 /* VIA PadLock required */

+#define CpuSSSE3 0x80000 /* Supplemental Streaming SIMD extensions 3 required */

/* These flags are set by gas depending on the flag_code. */

#define Cpu64 0x4000000 /* 64bit support required */

#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */

/* The default value for unknown CPUs - enable all features to avoid problems. */

/* the bits in opcode_modifier are used to generate the final opcode from

the base_opcode. These bits also are used to detect alternate forms of

diff --git a/contrib/binutils/include/opcode/ChangeLog b/contrib/binutils/include/opcode/ChangeLog
index 6c50775ea1c4..af2996eba3ac 100644
--- a/contrib/binutils/include/opcode/ChangeLog
+++ b/contrib/binutils/include/opcode/ChangeLog

@@ -1,3 +1,16 @@

+2006-09-28 H.J. Lu <hongjiu.lu@intel.com>

+ * i386.h: Replace CpuMNI with CpuSSSE3.

+2006-02-27 H.J. Lu <hongjiu.lu@intel.com>

+ * i386.h (i386_optab): Support Intel Merom New Instructions.

+2005-04-12 Mark Kettenis <kettenis@gnu.org>

+ * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and

+ adjust them accordingly.

2004-04-08 Alan Modra <amodra@bigpond.net.au>

Apply from mainline.

diff --git a/contrib/binutils/include/opcode/i386.h b/contrib/binutils/include/opcode/i386.h
index 5e3673e2b041..b396c872f682 100644
--- a/contrib/binutils/include/opcode/i386.h
+++ b/contrib/binutils/include/opcode/i386.h

@@ -1326,6 +1326,41 @@ static const template i386_optab[] = {

/* Need to ensure only "mwait %eax,%ecx" is accepted. */

{"mwait", 2, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { Reg32, Reg32, 0} },

+/* Supplemental Streaming SIMD extensions 3 Instructions. */

+{"phaddw", 2, 0x0f3801,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"phaddw", 2, 0x660f3801,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

+{"phaddd", 2, 0x0f3802,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"phaddd", 2, 0x660f3802,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

+{"phaddsw", 2, 0x0f3803,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"phaddsw", 2, 0x660f3803,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

+{"phsubw", 2, 0x0f3805,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"phsubw", 2, 0x660f3805,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

+{"phsubd", 2, 0x0f3806,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"phsubd", 2, 0x660f3806,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

+{"phsubsw", 2, 0x0f3807,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"phsubsw", 2, 0x660f3807,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

+{"pmaddubsw", 2, 0x0f3804,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"pmaddubsw", 2, 0x660f3804,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

+{"pmulhrsw", 2, 0x0f380b,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"pmulhrsw", 2, 0x660f380b,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

+{"pshufb", 2, 0x0f3800,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"pshufb", 2, 0x660f3800,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

+{"psignb", 2, 0x0f3808,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"psignb", 2, 0x660f3808,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

+{"psignw", 2, 0x0f3809,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"psignw", 2, 0x660f3809,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

+{"psignd", 2, 0x0f380a,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"psignd", 2, 0x660f380a,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

+{"palignr", 3, 0x0f3a0f,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LongMem, RegMMX } },

+{"palignr", 3, 0x660f3a0f,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },

+{"pabsb", 2, 0x0f381c,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"pabsb", 2, 0x660f381c,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

+{"pabsw", 2, 0x0f381d,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"pabsw", 2, 0x660f381d,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

+{"pabsd", 2, 0x0f381e,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },

+{"pabsd", 2, 0x660f381e,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },

/* AMD 3DNow! instructions. */

{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } },

@@ -1362,13 +1397,16 @@ static const template i386_optab[] = {

{"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} },

/* VIA PadLock extensions. */

-{"xstorerng", 0, 0x0fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },

-{"xcryptecb", 0, 0xf30fa7c8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },

-{"xcryptcbc", 0, 0xf30fa7d0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },

-{"xcryptcfb", 0, 0xf30fa7e0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },

-{"xcryptofb", 0, 0xf30fa7e8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },

-/* alias for xstorerng */

-{"xstore", 0, 0x0fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} },

+{"xstorerng", 0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },

+{"xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },

+{"xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },

+{"xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },

+{"xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },

+{"montmul", 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },

+{"xsha1", 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },

+{"xsha256", 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },

+/* Alias for xstorerng. */

+{"xstore", 0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },

/* sentinel */

{NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }

diff --git a/contrib/binutils/opcodes/ChangeLog b/contrib/binutils/opcodes/ChangeLog
index 88c6b3e549fe..b82ae12c8b83 100644
--- a/contrib/binutils/opcodes/ChangeLog
+++ b/contrib/binutils/opcodes/ChangeLog

@@ -1,3 +1,17 @@

+2006-02-27 H.J. Lu <hongjiu.lu@intel.com>

+ * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by

+ Intel Merom New Instructions.

+ (THREE_BYTE_0): Likewise.

+ (THREE_BYTE_1): Likewise.

+ (three_byte_table): Likewise.

+ (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use

+ THREE_BYTE_1 for entry 0x3a.

+ (twobyte_has_modrm): Updated.

+ (twobyte_uses_SSE_prefix): Likewise.

+ (print_insn): Handle 3-byte opcodes used by Intel Merom New

+ Instructions.

2004-05-13 Nick Clifton <nickc@redhat.com>

* po/fr.po: Updated French translation.

diff --git a/contrib/binutils/opcodes/i386-dis.c b/contrib/binutils/opcodes/i386-dis.c
index a71eb0c9105a..07f5adb010a9 100644
--- a/contrib/binutils/opcodes/i386-dis.c
+++ b/contrib/binutils/opcodes/i386-dis.c

@@ -367,6 +367,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)

#define USE_GROUPS 2

#define USE_PREFIX_USER_TABLE 3

#define X86_64_SPECIAL 4

+#define IS_3BYTE_OPCODE 5

#define FLOAT NULL, NULL, FLOATCODE, NULL, 0, NULL, 0

@@ -431,6 +432,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)

#define X86_64_0 NULL, NULL, X86_64_SPECIAL, NULL, 0, NULL, 0

+#define THREE_BYTE_0 NULL, NULL, IS_3BYTE_OPCODE, NULL, 0, NULL, 0

+#define THREE_BYTE_1 NULL, NULL, IS_3BYTE_OPCODE, NULL, 1, NULL, 0

typedef void (*op_rtn) (int bytemode, int sizeflag);

struct dis386 {

@@ -829,9 +833,9 @@ static const struct dis386 dis386_twobyte[] = {

{ "(bad)", XX, XX, XX },

/* 38 */

+ { THREE_BYTE_0 },

{ "(bad)", XX, XX, XX },

- { "(bad)", XX, XX, XX },

+ { THREE_BYTE_1 },

{ "(bad)", XX, XX, XX },

@@ -1084,7 +1088,7 @@ static const unsigned char twobyte_has_modrm[256] = {

/* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */

/* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0, /* 1f */

/* 20 */ 1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 2f */

- /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */

+ /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */

/* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */

/* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */

/* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */

@@ -1107,7 +1111,7 @@ static const unsigned char twobyte_uses_SSE_prefix[256] = {

/* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */

/* 10 */ 1,1,1,0,0,0,1,0,0,0,0,0,0,0,0,0, /* 1f */

/* 20 */ 0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,0, /* 2f */

- /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */

+ /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */

/* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */

/* 50 */ 0,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* 5f */

/* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,1, /* 6f */

@@ -1709,6 +1713,79 @@ static const struct dis386 x86_64_table[][2] = {

};

+static const struct dis386 three_byte_table[][32] = {

+ /* THREE_BYTE_0 */

+ {

+ { "pshufb", MX, EM, XX },

+ { "phaddw", MX, EM, XX },

+ { "phaddd", MX, EM, XX },

+ { "phaddsw", MX, EM, XX },

+ { "pmaddubsw", MX, EM, XX },

+ { "phsubw", MX, EM, XX },

+ { "phsubd", MX, EM, XX },

+ { "phsubsw", MX, EM, XX },

+ { "psignb", MX, EM, XX },

+ { "psignw", MX, EM, XX },

+ { "psignd", MX, EM, XX },

+ { "pmulhrsw", MX, EM, XX },

+ { "(bad)", XX, XX, XX },

+ { "pabsb", MX, EM, XX },

+ { "pabsw", MX, EM, XX },

+ { "pabsd", MX, EM, XX },

+ { "(bad)", XX, XX, XX }

+ },

+ /* THREE_BYTE_1 */

+ {

+ { "(bad)", XX, XX, XX },

+ { "palignr", MX, EM, Ib },

+ { "(bad)", XX, XX, XX },

+ { "(bad)", XX, XX, XX }

+ },

+};

#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")

static void

@@ -2160,7 +2237,15 @@ print_insn (bfd_vma pc, disassemble_info *info)

}

- if (need_modrm)

+ if (dp->name == NULL && dp->bytemode1 == IS_3BYTE_OPCODE)

+ {

+ FETCH_DATA (info, codep + 2);

+ dp = &three_byte_table[dp->bytemode2][*codep++];

+ mod = (*codep >> 6) & 3;

+ reg = (*codep >> 3) & 7;

+ rm = *codep & 7;

+ }

+ else if (need_modrm)

{

FETCH_DATA (info, codep + 1);

mod = (*codep >> 6) & 3;