diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2012-05-03 16:50:55 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2012-05-03 16:50:55 +0000 |
| commit | b61ab53cb789e568acbb2952fbead20ab853a696 (patch) | |
| tree | 8575c732129e272992ac5d7b4c2519238fff4735 /lib/Target/Hexagon/HexagonMCInstLower.cpp | |
| parent | 63faed5b8e4f2755f127fcb8aa440480c0649327 (diff) | |
Notes
Diffstat (limited to 'lib/Target/Hexagon/HexagonMCInstLower.cpp')
| -rw-r--r-- | lib/Target/Hexagon/HexagonMCInstLower.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Hexagon/HexagonMCInstLower.cpp b/lib/Target/Hexagon/HexagonMCInstLower.cpp index 70bddcc76a59..fbb331bdd8bf 100644 --- a/lib/Target/Hexagon/HexagonMCInstLower.cpp +++ b/lib/Target/Hexagon/HexagonMCInstLower.cpp @@ -49,7 +49,7 @@ void llvm::HexagonLowerToMC(const MachineInstr* MI, MCInst& MCI, switch (MO.getType()) { default: MI->dump(); - llvm_unreachable("unknown operand type"); + assert(0 && "unknown operand type"); case MachineOperand::MO_Register: // Ignore all implicit register operands. if (MO.isImplicit()) continue; |