1 files changed, 49 insertions, 39 deletions

diff --git a/lib/libpmc/pmc.ivybridge.3 b/lib/libpmc/pmc.ivybridge.3
index b693b30ca73b..d86199b4d407 100644
--- a/lib/libpmc/pmc.ivybridge.3
+++ b/lib/libpmc/pmc.ivybridge.3
@@ -91,12 +91,12 @@ Configure the Off-core Response bits.
 .Bl -tag -width indent
 .It Li REQ_DMND_DATA_RD
 Counts the number of demand and DCU prefetch data reads of full and partial
-cachelines as well as demand data page table entry cacheline reads. Does not
-count L2 data read prefetches or instruction fetches.
+cachelines as well as demand data page table entry cacheline reads.
+Does not count L2 data read prefetches or instruction fetches.
 .It Li REQ_DMND_RFO
 Counts the number of demand and DCU prefetch reads for ownership (RFO)
-requests generated by a write to data cacheline. Does not count L2 RFO
-prefetches.
+requests generated by a write to data cacheline.
+Does not count L2 RFO prefetches.
 .It Li REQ_DMND_IFETCH
 Counts the number of demand and DCU prefetch instruction cacheline reads.
 Does not count L2 code read prefetches.
@@ -144,8 +144,9 @@ A snoop was needed and it missed all snooped caches:
 -For LLC Miss, Rspl was returned by all sockets and data was returned from
 DRAM.
 .It Li RES_SNOOP_HIT_NO_FWD
-A snoop was needed and it hits in at least one snooped cache. Hit denotes a
-cache-line was valid before snoop effect. This includes:
+A snoop was needed and it hits in at least one snooped cache.
+Hit denotes a cache-line was valid before snoop effect.
+This includes:
 -Snoop Hit w/ Invalidation (LLC Hit, RFO)
 -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD)
 -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S)
@@ -155,14 +156,15 @@ A snoop was needed and data was forwarded from a remote socket.
 This includes:
 -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
 .It Li RES_SNOOP_HITM
-A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a
-cache-line was in modified state before effect as a results of snoop. This
-includes:
+A snoop was needed and it HitM-ed in local or remote cache.
+HitM denotes a cache-line was in modified state before effect as a results of snoop.
+This includes:
 -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD)
 -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO)
 -Snoop MtoS (LLC Hit, IFetch/Data_RD).
 .It Li RES_NON_DRAM
-Target was non-DRAM system address. This includes MMIO transactions.
+Target was non-DRAM system address.
+This includes MMIO transactions.
 .El
 .It Li cmask= Ns Ar value
 Configure the PMC to increment only if the number of configured
@@ -225,18 +227,19 @@ Set Cmask = 1, Inv = 1to count stalled cycles.
 Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.
 .It Li UOPS_ISSUED.FLAGS_MERGE
 .Pq Event 0EH , Umask 10H
-Number of flags-merge uops allocated. Such uops adds delay.
+Number of flags-merge uops allocated.
+Such uops adds delay.
 .It Li UOPS_ISSUED.SLOW_LEA
 .Pq Event 0EH , Umask 20H
-Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2
-sources + immediate) regardless if as a result of LEA instruction or not.
+Number of slow LEA or similar uops allocated.
+Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
 .It Li UOPS_ISSUED.SINGLE_MUL
 .Pq Event 0EH , Umask 40H
 Number of multiply packed/scalar single precision uops allocated.
 .It Li ARITH.FPU_DIV_ACTIVE
 .Pq Event 14H , Umask 01H
-Cycles that the divider is active, includes INT and FP. Set 'edge =1,
-cmask=1' to count the number of divides.
+Cycles that the divider is active, includes INT and FP.
+Set 'edge =1, cmask=1' to count the number of divides.
 .It Li L2_RQSTS.DEMAND_DATA_RD_HIT
 .Pq Event 24H , Umask 01H
 Demand Data Read requests that hit L2 cache.
@@ -302,16 +305,16 @@ cache.
 .It Li CPU_CLK_UNHALTED.THREAD_P
 .Pq Event 3CH , Umask 00H
 Counts the number of thread cycles while the thread is not in a halt state.
-The thread enters the halt state when it is running the HLT instruction. The
-core frequency may change from time to time due to power or thermal
+The thread enters the halt state when it is running the HLT instruction.
+The core frequency may change from time to time due to power or thermal
 throttling.
 .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK
 .Pq Event 3CH , Umask 01H
 Increments at the frequency of XCLK (100 MHz) when not halted.
 .It Li L1D_PEND_MISS.PENDING
 .Pq Event 48H , Umask 01H
-Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1
-and Edge =1 to count occurrences.
+Increments the number of outstanding L1D misses every cycle.
+Set Cmaks = 1 and Edge =1 to count occurrences.
 Counter 2 only.
 Set Cmask = 1 to count cycles.
 .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
@@ -364,20 +367,20 @@ Cycles the RS is empty for the thread.
 Counts load operations that missed 1st level DTLB but hit the 2nd level.
 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
 .Pq Event 60H , Umask 01H
-Offcore outstanding Demand Data Read transactions in SQ to uncore. Set
-Cmask=1 to count cycles.
+Offcore outstanding Demand Data Read transactions in SQ to uncore.
+Set Cmask=1 to count cycles.
 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD
 .Pq Event 60H , Umask 02H
-Offcore outstanding Demand Code Read transactions in SQ to uncore. Set
-Cmask=1 to count cycles.
+Offcore outstanding Demand Code Read transactions in SQ to uncore.
+Set Cmask=1 to count cycles.
 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
 .Pq Event 60H , Umask 04H
-Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to
-count cycles.
+Offcore outstanding RFO store transactions in SQ to uncore.
+Set Cmask=1 to count cycles.
 .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
 .Pq Event 60H , Umask 08H
-Offcore outstanding cacheable data read transactions in SQ to uncore. Set
-Cmask=1 to count cycles.
+Offcore outstanding cacheable data read transactions in SQ to uncore.
+Set Cmask=1 to count cycles.
 .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
 .Pq Event 63H , Umask 01H
 Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.
@@ -399,31 +402,37 @@ Can combine Umask 08H and 10H
 Set Cmask = 1 to count cycles.
 .It Li IDQ.MS_DSB_UOPS
 .Pq Event 79H , Umask 10H
-Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set
-Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.
+Increment each cycle # of uops delivered to IDQ when MS_busy by DSB.
+Set Cmask = 1 to count cycles.
+Add Edge=1 to count # of delivery.
 Can combine Umask 04H, 08H.
 .It Li IDQ.MS_MITE_UOPS
 .Pq Event 79H , Umask 20H
-Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set
-Cmask = 1 to count cycles.
+Increment each cycle # of uops delivered to IDQ when MS_busy by MITE.
+Set Cmask = 1 to count cycles.
 Can combine Umask 04H, 08H.
 .It Li IDQ.MS_UOPS
 .Pq Event 79H , Umask 30H
 Increment each cycle # of uops delivered to IDQ from MS by either DSB or
-MITE. Set Cmask = 1 to count cycles.
+MITE.
+Set Cmask = 1 to count cycles.
 Can combine Umask 04H, 08H.
 .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS
 .Pq Event 79H , Umask 18H
-Counts cycles DSB is delivered at least one uops. Set Cmask = 1.
+Counts cycles DSB is delivered at least one uops.
+Set Cmask = 1.
 .It Li IDQ.ALL_DSB_CYCLES_4_UOPS
 .Pq Event 79H , Umask 18H
-Counts cycles DSB is delivered four uops. Set Cmask = 4.
+Counts cycles DSB is delivered four uops.
+Set Cmask = 4.
 .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS
 .Pq Event 79H , Umask 24H
-Counts cycles MITE is delivered at least one uops. Set Cmask = 1.
+Counts cycles MITE is delivered at least one uops.
+Set Cmask = 1.
 .It Li IDQ.ALL_MITE_CYCLES_4_UOPS
 .Pq Event 79H , Umask 24H
-Counts cycles MITE is delivered four uops. Set Cmask = 4.
+Counts cycles MITE is delivered four uops.
+Set Cmask = 4.
 .It Li IDQ.MITE_ALL_UOPS
 .Pq Event 79H , Umask 3CH
 # of uops delivered to IDQ from any path.
@@ -442,7 +451,8 @@ Misses in all ITLB levels that cause completed page walks.
 Cycle PMH is busy with a walk.
 .It Li ITLB_MISSES.STLB_HIT
 .Pq Event 85H , Umask 10H
-Number of cache load STLB hits. No page walk.
+Number of cache load STLB hits.
+No page walk.
 .It Li ILD_STALL.LCP
 .Pq Event 87H , Umask 01H
 Stalls caused by changing prefix length of the instruction.
@@ -577,8 +587,8 @@ ItoM.
 Data read requests sent to uncore (demand and prefetch).
 .It Li UOPS_EXECUTED.THREAD
 .Pq Event B1H , Umask 01H
-Counts total number of uops to be executed per-thread each cycle. Set Cmask
-= 1, INV =1 to count stall cycles.
+Counts total number of uops to be executed per-thread each cycle.
+Set Cmask = 1, INV =1 to count stall cycles.
 .It Li UOPS_EXECUTED.CORE
 .Pq Event B1H , Umask 02H
 Counts total number of uops to be executed per-core each cycle.