diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2021-12-02 21:02:54 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2021-12-02 21:02:54 +0000 |
| commit | f65dcba83ce5035ab88a85fe17628b447eb56e1b (patch) | |
| tree | 35f37bb72b3cfc6060193e66c76ee7c9478969b0 /llvm/lib/CodeGen/MachineInstr.cpp | |
| parent | 846a2208a8ab099f595fe7e8b2e6d54a7b5e67fb (diff) | |
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MachineInstr.cpp | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 5c4f75e9ceb9..aaa80432d2f2 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -1490,12 +1490,10 @@ bool MachineInstr::allDefsAreDead() const { /// instruction to this instruction. void MachineInstr::copyImplicitOps(MachineFunction &MF, const MachineInstr &MI) { - for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands(); - i != e; ++i) { - const MachineOperand &MO = MI.getOperand(i); + for (const MachineOperand &MO : + llvm::drop_begin(MI.operands(), MI.getDesc().getNumOperands())) if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) addOperand(MF, MO); - } } bool MachineInstr::hasComplexRegisterTies() const { |