diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2023-07-26 19:03:47 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2023-07-26 19:04:23 +0000 |
| commit | 7fa27ce4a07f19b07799a767fc29416f3b625afb (patch) | |
| tree | 27825c83636c4de341eb09a74f49f5d38a15d165 /llvm/lib/CodeGen/MachineRegisterInfo.cpp | |
| parent | e3b557809604d036af6e00c60f012c2025b59a5e (diff) | |
Diffstat (limited to 'llvm/lib/CodeGen/MachineRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MachineRegisterInfo.cpp | 22 |
1 files changed, 7 insertions, 15 deletions
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp index 1ad08e19feae..0048918fc53b 100644 --- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp @@ -101,13 +101,13 @@ MachineRegisterInfo::constrainRegAttrs(Register Reg, const auto RegCB = getRegClassOrRegBank(Reg); if (RegCB.isNull()) setRegClassOrRegBank(Reg, ConstrainingRegCB); - else if (RegCB.is<const TargetRegisterClass *>() != - ConstrainingRegCB.is<const TargetRegisterClass *>()) + else if (isa<const TargetRegisterClass *>(RegCB) != + isa<const TargetRegisterClass *>(ConstrainingRegCB)) return false; - else if (RegCB.is<const TargetRegisterClass *>()) { + else if (isa<const TargetRegisterClass *>(RegCB)) { if (!::constrainRegClass( - *this, Reg, RegCB.get<const TargetRegisterClass *>(), - ConstrainingRegCB.get<const TargetRegisterClass *>(), MinNumRegs)) + *this, Reg, cast<const TargetRegisterClass *>(RegCB), + cast<const TargetRegisterClass *>(ConstrainingRegCB), MinNumRegs)) return false; } else if (RegCB != ConstrainingRegCB) return false; @@ -644,16 +644,8 @@ void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) { bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const { const TargetRegisterInfo *TRI = getTargetRegisterInfo(); for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) { - bool IsRootReserved = true; - for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true); - Super.isValid(); ++Super) { - MCRegister Reg = *Super; - if (!isReserved(Reg)) { - IsRootReserved = false; - break; - } - } - if (IsRootReserved) + if (all_of(TRI->superregs_inclusive(*Root), + [&](MCPhysReg Super) { return isReserved(Super); })) return true; } return false; |