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authorDimitry Andric <dim@FreeBSD.org>2023-07-26 19:03:47 +0000
committerDimitry Andric <dim@FreeBSD.org>2023-07-26 19:04:23 +0000
commit7fa27ce4a07f19b07799a767fc29416f3b625afb (patch)
tree27825c83636c4de341eb09a74f49f5d38a15d165 /llvm/lib/CodeGen/MachineSSAContext.cpp
parente3b557809604d036af6e00c60f012c2025b59a5e (diff)
Diffstat (limited to 'llvm/lib/CodeGen/MachineSSAContext.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineSSAContext.cpp10
1 files changed, 3 insertions, 7 deletions
diff --git a/llvm/lib/CodeGen/MachineSSAContext.cpp b/llvm/lib/CodeGen/MachineSSAContext.cpp
index 6de8f8da9254..324084fb9c32 100644
--- a/llvm/lib/CodeGen/MachineSSAContext.cpp
+++ b/llvm/lib/CodeGen/MachineSSAContext.cpp
@@ -21,8 +21,6 @@
using namespace llvm;
-const Register MachineSSAContext::ValueRefNull{};
-
void MachineSSAContext::setFunction(MachineFunction &Fn) {
MF = &Fn;
RegInfo = &MF->getRegInfo();
@@ -42,10 +40,8 @@ void MachineSSAContext::appendBlockTerms(
void MachineSSAContext::appendBlockDefs(SmallVectorImpl<Register> &defs,
const MachineBasicBlock &block) {
for (const MachineInstr &instr : block.instrs()) {
- for (const MachineOperand &op : instr.operands()) {
- if (op.isReg() && op.isDef())
- defs.push_back(op.getReg());
- }
+ for (const MachineOperand &op : instr.all_defs())
+ defs.push_back(op.getReg());
}
}
@@ -56,7 +52,7 @@ MachineBasicBlock *MachineSSAContext::getDefBlock(Register value) const {
return RegInfo->getVRegDef(value)->getParent();
}
-bool MachineSSAContext::isConstantValuePhi(const MachineInstr &Phi) {
+bool MachineSSAContext::isConstantOrUndefValuePhi(const MachineInstr &Phi) {
return Phi.isConstantValuePHI();
}