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| author | Dimitry Andric <dim@FreeBSD.org> | 2023-12-17 20:41:09 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2023-12-17 20:41:09 +0000 |
| commit | 312c0ed19cc5276a17bacf2120097bec4515b0f1 (patch) | |
| tree | e6e4a4163840b73ba54bb0d3b70ee4899e4b7434 /llvm/lib/Target/AMDGPU/AMDGPU.td | |
| parent | b1c73532ee8997fe5dfbeb7d223027bdf99758a0 (diff) | |
| download | src-312c0ed19cc5276a17bacf2120097bec4515b0f1.tar.gz src-312c0ed19cc5276a17bacf2120097bec4515b0f1.zip | |
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPU.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPU.td | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td index 799e102d5617..060fb66d38f7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -411,6 +411,12 @@ def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode", "Has VGPR mode register indexing" >; +def FeatureScalarDwordx3Loads : SubtargetFeature<"scalar-dwordx3-loads", + "HasScalarDwordx3Loads", + "true", + "Has 96-bit scalar load instructions" +>; + def FeatureScalarStores : SubtargetFeature<"scalar-stores", "HasScalarStores", "true", @@ -816,6 +822,18 @@ def FeatureVGPRSingleUseHintInsts : SubtargetFeature<"vgpr-singleuse-hint", "Has single-use VGPR hint instructions" >; +def FeaturePseudoScalarTrans : SubtargetFeature<"pseudo-scalar-trans", + "HasPseudoScalarTrans", + "true", + "Has Pseudo Scalar Transcendental instructions" +>; + +def FeatureHasRestrictedSOffset : SubtargetFeature<"restricted-soffset", + "HasRestrictedSOffset", + "true", + "Has restricted SOffset (immediate not supported)." +>; + //===------------------------------------------------------------===// // Subtarget Features (options and debugging) //===------------------------------------------------------------===// @@ -1461,8 +1479,11 @@ def FeatureISAVersion12 : FeatureSet< FeaturePackedTID, FeatureVcmpxPermlaneHazard, FeatureSALUFloatInsts, + FeaturePseudoScalarTrans, + FeatureHasRestrictedSOffset, FeatureVGPRSingleUseHintInsts, - FeatureMADIntraFwdBug]>; + FeatureMADIntraFwdBug, + FeatureScalarDwordx3Loads]>; //===----------------------------------------------------------------------===// @@ -1773,6 +1794,11 @@ def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">, def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">, AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>; +def HasRestrictedSOffset : Predicate<"Subtarget->hasRestrictedSOffset()">, + AssemblerPredicate<(all_of FeatureHasRestrictedSOffset)>; +def HasUnrestrictedSOffset : Predicate<"!Subtarget->hasRestrictedSOffset()">, + AssemblerPredicate<(all_of (not FeatureHasRestrictedSOffset))>; + def D16PreservesUnusedBits : Predicate<"Subtarget->d16PreservesUnusedBits()">, AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>; @@ -2002,6 +2028,9 @@ def HasSALUFloatInsts : Predicate<"Subtarget->hasSALUFloatInsts()">, def HasVGPRSingleUseHintInsts : Predicate<"Subtarget->hasVGPRSingleUseHintInsts()">, AssemblerPredicate<(all_of FeatureVGPRSingleUseHintInsts)>; +def HasPseudoScalarTrans : Predicate<"Subtarget->hasPseudoScalarTrans()">, + AssemblerPredicate<(all_of FeaturePseudoScalarTrans)>; + def HasGDS : Predicate<"Subtarget->hasGDS()">; def HasGWS : Predicate<"Subtarget->hasGWS()">; @@ -2011,6 +2040,8 @@ def HasNoCvtFP8VOP1Bug : Predicate<"!Subtarget->hasCvtFP8VOP1Bug()">; def HasAtomicCSubNoRtnInsts : Predicate<"Subtarget->hasAtomicCSubNoRtnInsts()">; +def HasScalarDwordx3Loads : Predicate<"Subtarget->hasScalarDwordx3Loads()">; + // Include AMDGPU TD files include "SISchedule.td" include "GCNProcessors.td" |