diff options
author | Dimitry Andric <dim@FreeBSD.org> | 2023-02-11 12:38:04 +0000 |
---|---|---|
committer | Dimitry Andric <dim@FreeBSD.org> | 2023-02-11 12:38:11 +0000 |
commit | e3b557809604d036af6e00c60f012c2025b59a5e (patch) | |
tree | 8a11ba2269a3b669601e2fd41145b174008f4da8 /llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp | |
parent | 08e8dd7b9db7bb4a9de26d44c1cbfd24e869c014 (diff) |
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp | 129 |
1 files changed, 59 insertions, 70 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp index 6b93769949bc..5f2707317984 100644 --- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp +++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp @@ -172,13 +172,13 @@ public: } /// \returns The address spaces be accessed by the machine - /// instruction used to create this SiMemOpInfo. + /// instruction used to create this SIMemOpInfo. SIAtomicAddrSpace getInstrAddrSpace() const { return InstrAddrSpace; } /// \returns The address spaces that must be ordered by the machine - /// instruction used to create this SiMemOpInfo. + /// instruction used to create this SIMemOpInfo. SIAtomicAddrSpace getOrderingAddrSpace() const { return OrderingAddrSpace; } @@ -221,7 +221,7 @@ private: /// the SI atomic scope it corresponds to, the address spaces it /// covers, and whether the memory ordering applies between address /// spaces. - Optional<std::tuple<SIAtomicScope, SIAtomicAddrSpace, bool>> + std::optional<std::tuple<SIAtomicScope, SIAtomicAddrSpace, bool>> toSIAtomicScope(SyncScope::ID SSID, SIAtomicAddrSpace InstrAddrSpace) const; /// \return Return a bit set of the address spaces accessed by \p AS. @@ -229,31 +229,32 @@ private: /// \returns Info constructed from \p MI, which has at least machine memory /// operand. - Optional<SIMemOpInfo> constructFromMIWithMMO( - const MachineBasicBlock::iterator &MI) const; + std::optional<SIMemOpInfo> + constructFromMIWithMMO(const MachineBasicBlock::iterator &MI) const; public: /// Construct class to support accessing the machine memory operands /// of instructions in the machine function \p MF. SIMemOpAccess(MachineFunction &MF); - /// \returns Load info if \p MI is a load operation, "None" otherwise. - Optional<SIMemOpInfo> getLoadInfo( - const MachineBasicBlock::iterator &MI) const; + /// \returns Load info if \p MI is a load operation, "std::nullopt" otherwise. + std::optional<SIMemOpInfo> + getLoadInfo(const MachineBasicBlock::iterator &MI) const; - /// \returns Store info if \p MI is a store operation, "None" otherwise. - Optional<SIMemOpInfo> getStoreInfo( - const MachineBasicBlock::iterator &MI) const; + /// \returns Store info if \p MI is a store operation, "std::nullopt" + /// otherwise. + std::optional<SIMemOpInfo> + getStoreInfo(const MachineBasicBlock::iterator &MI) const; /// \returns Atomic fence info if \p MI is an atomic fence operation, - /// "None" otherwise. - Optional<SIMemOpInfo> getAtomicFenceInfo( - const MachineBasicBlock::iterator &MI) const; + /// "std::nullopt" otherwise. + std::optional<SIMemOpInfo> + getAtomicFenceInfo(const MachineBasicBlock::iterator &MI) const; /// \returns Atomic cmpxchg/rmw info if \p MI is an atomic cmpxchg or - /// rmw operation, "None" otherwise. - Optional<SIMemOpInfo> getAtomicCmpxchgOrRmwInfo( - const MachineBasicBlock::iterator &MI) const; + /// rmw operation, "std::nullopt" otherwise. + std::optional<SIMemOpInfo> + getAtomicCmpxchgOrRmwInfo(const MachineBasicBlock::iterator &MI) const; }; class SICacheControl { @@ -621,50 +622,38 @@ void SIMemOpAccess::reportUnsupported(const MachineBasicBlock::iterator &MI, Func.getContext().diagnose(Diag); } -Optional<std::tuple<SIAtomicScope, SIAtomicAddrSpace, bool>> +std::optional<std::tuple<SIAtomicScope, SIAtomicAddrSpace, bool>> SIMemOpAccess::toSIAtomicScope(SyncScope::ID SSID, SIAtomicAddrSpace InstrAddrSpace) const { if (SSID == SyncScope::System) - return std::make_tuple(SIAtomicScope::SYSTEM, - SIAtomicAddrSpace::ATOMIC, - true); + return std::tuple(SIAtomicScope::SYSTEM, SIAtomicAddrSpace::ATOMIC, true); if (SSID == MMI->getAgentSSID()) - return std::make_tuple(SIAtomicScope::AGENT, - SIAtomicAddrSpace::ATOMIC, - true); + return std::tuple(SIAtomicScope::AGENT, SIAtomicAddrSpace::ATOMIC, true); if (SSID == MMI->getWorkgroupSSID()) - return std::make_tuple(SIAtomicScope::WORKGROUP, - SIAtomicAddrSpace::ATOMIC, - true); + return std::tuple(SIAtomicScope::WORKGROUP, SIAtomicAddrSpace::ATOMIC, + true); if (SSID == MMI->getWavefrontSSID()) - return std::make_tuple(SIAtomicScope::WAVEFRONT, - SIAtomicAddrSpace::ATOMIC, - true); + return std::tuple(SIAtomicScope::WAVEFRONT, SIAtomicAddrSpace::ATOMIC, + true); if (SSID == SyncScope::SingleThread) - return std::make_tuple(SIAtomicScope::SINGLETHREAD, - SIAtomicAddrSpace::ATOMIC, - true); + return std::tuple(SIAtomicScope::SINGLETHREAD, SIAtomicAddrSpace::ATOMIC, + true); if (SSID == MMI->getSystemOneAddressSpaceSSID()) - return std::make_tuple(SIAtomicScope::SYSTEM, - SIAtomicAddrSpace::ATOMIC & InstrAddrSpace, - false); + return std::tuple(SIAtomicScope::SYSTEM, + SIAtomicAddrSpace::ATOMIC & InstrAddrSpace, false); if (SSID == MMI->getAgentOneAddressSpaceSSID()) - return std::make_tuple(SIAtomicScope::AGENT, - SIAtomicAddrSpace::ATOMIC & InstrAddrSpace, - false); + return std::tuple(SIAtomicScope::AGENT, + SIAtomicAddrSpace::ATOMIC & InstrAddrSpace, false); if (SSID == MMI->getWorkgroupOneAddressSpaceSSID()) - return std::make_tuple(SIAtomicScope::WORKGROUP, - SIAtomicAddrSpace::ATOMIC & InstrAddrSpace, - false); + return std::tuple(SIAtomicScope::WORKGROUP, + SIAtomicAddrSpace::ATOMIC & InstrAddrSpace, false); if (SSID == MMI->getWavefrontOneAddressSpaceSSID()) - return std::make_tuple(SIAtomicScope::WAVEFRONT, - SIAtomicAddrSpace::ATOMIC & InstrAddrSpace, - false); + return std::tuple(SIAtomicScope::WAVEFRONT, + SIAtomicAddrSpace::ATOMIC & InstrAddrSpace, false); if (SSID == MMI->getSingleThreadOneAddressSpaceSSID()) - return std::make_tuple(SIAtomicScope::SINGLETHREAD, - SIAtomicAddrSpace::ATOMIC & InstrAddrSpace, - false); - return None; + return std::tuple(SIAtomicScope::SINGLETHREAD, + SIAtomicAddrSpace::ATOMIC & InstrAddrSpace, false); + return std::nullopt; } SIAtomicAddrSpace SIMemOpAccess::toSIAtomicAddrSpace(unsigned AS) const { @@ -686,7 +675,7 @@ SIMemOpAccess::SIMemOpAccess(MachineFunction &MF) { MMI = &MF.getMMI().getObjFileInfo<AMDGPUMachineModuleInfo>(); } -Optional<SIMemOpInfo> SIMemOpAccess::constructFromMIWithMMO( +std::optional<SIMemOpInfo> SIMemOpAccess::constructFromMIWithMMO( const MachineBasicBlock::iterator &MI) const { assert(MI->getNumMemOperands() > 0); @@ -711,7 +700,7 @@ Optional<SIMemOpInfo> SIMemOpAccess::constructFromMIWithMMO( if (!IsSyncScopeInclusion) { reportUnsupported(MI, "Unsupported non-inclusive atomic synchronization scope"); - return None; + return std::nullopt; } SSID = *IsSyncScopeInclusion ? SSID : MMO->getSyncScopeID(); @@ -730,7 +719,7 @@ Optional<SIMemOpInfo> SIMemOpAccess::constructFromMIWithMMO( auto ScopeOrNone = toSIAtomicScope(SSID, InstrAddrSpace); if (!ScopeOrNone) { reportUnsupported(MI, "Unsupported atomic synchronization scope"); - return None; + return std::nullopt; } std::tie(Scope, OrderingAddrSpace, IsCrossAddressSpaceOrdering) = *ScopeOrNone; @@ -738,7 +727,7 @@ Optional<SIMemOpInfo> SIMemOpAccess::constructFromMIWithMMO( ((OrderingAddrSpace & SIAtomicAddrSpace::ATOMIC) != OrderingAddrSpace) || ((InstrAddrSpace & SIAtomicAddrSpace::ATOMIC) == SIAtomicAddrSpace::NONE)) { reportUnsupported(MI, "Unsupported atomic address space"); - return None; + return std::nullopt; } } return SIMemOpInfo(Ordering, Scope, OrderingAddrSpace, InstrAddrSpace, @@ -746,12 +735,12 @@ Optional<SIMemOpInfo> SIMemOpAccess::constructFromMIWithMMO( IsNonTemporal); } -Optional<SIMemOpInfo> SIMemOpAccess::getLoadInfo( - const MachineBasicBlock::iterator &MI) const { +std::optional<SIMemOpInfo> +SIMemOpAccess::getLoadInfo(const MachineBasicBlock::iterator &MI) const { assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic); if (!(MI->mayLoad() && !MI->mayStore())) - return None; + return std::nullopt; // Be conservative if there are no memory operands. if (MI->getNumMemOperands() == 0) @@ -760,12 +749,12 @@ Optional<SIMemOpInfo> SIMemOpAccess::getLoadInfo( return constructFromMIWithMMO(MI); } -Optional<SIMemOpInfo> SIMemOpAccess::getStoreInfo( - const MachineBasicBlock::iterator &MI) const { +std::optional<SIMemOpInfo> +SIMemOpAccess::getStoreInfo(const MachineBasicBlock::iterator &MI) const { assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic); if (!(!MI->mayLoad() && MI->mayStore())) - return None; + return std::nullopt; // Be conservative if there are no memory operands. if (MI->getNumMemOperands() == 0) @@ -774,12 +763,12 @@ Optional<SIMemOpInfo> SIMemOpAccess::getStoreInfo( return constructFromMIWithMMO(MI); } -Optional<SIMemOpInfo> SIMemOpAccess::getAtomicFenceInfo( - const MachineBasicBlock::iterator &MI) const { +std::optional<SIMemOpInfo> +SIMemOpAccess::getAtomicFenceInfo(const MachineBasicBlock::iterator &MI) const { assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic); if (MI->getOpcode() != AMDGPU::ATOMIC_FENCE) - return None; + return std::nullopt; AtomicOrdering Ordering = static_cast<AtomicOrdering>(MI->getOperand(0).getImm()); @@ -788,7 +777,7 @@ Optional<SIMemOpInfo> SIMemOpAccess::getAtomicFenceInfo( auto ScopeOrNone = toSIAtomicScope(SSID, SIAtomicAddrSpace::ATOMIC); if (!ScopeOrNone) { reportUnsupported(MI, "Unsupported atomic synchronization scope"); - return None; + return std::nullopt; } SIAtomicScope Scope = SIAtomicScope::NONE; @@ -800,19 +789,19 @@ Optional<SIMemOpInfo> SIMemOpAccess::getAtomicFenceInfo( if ((OrderingAddrSpace == SIAtomicAddrSpace::NONE) || ((OrderingAddrSpace & SIAtomicAddrSpace::ATOMIC) != OrderingAddrSpace)) { reportUnsupported(MI, "Unsupported atomic address space"); - return None; + return std::nullopt; } return SIMemOpInfo(Ordering, Scope, OrderingAddrSpace, SIAtomicAddrSpace::ATOMIC, IsCrossAddressSpaceOrdering, AtomicOrdering::NotAtomic); } -Optional<SIMemOpInfo> SIMemOpAccess::getAtomicCmpxchgOrRmwInfo( +std::optional<SIMemOpInfo> SIMemOpAccess::getAtomicCmpxchgOrRmwInfo( const MachineBasicBlock::iterator &MI) const { assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic); if (!(MI->mayLoad() && MI->mayStore())) - return None; + return std::nullopt; // Be conservative if there are no memory operands. if (MI->getNumMemOperands() == 0) @@ -2329,13 +2318,13 @@ bool SIMemoryLegalizer::runOnMachineFunction(MachineFunction &MF) { continue; if (const auto &MOI = MOA.getLoadInfo(MI)) - Changed |= expandLoad(MOI.value(), MI); + Changed |= expandLoad(*MOI, MI); else if (const auto &MOI = MOA.getStoreInfo(MI)) - Changed |= expandStore(MOI.value(), MI); + Changed |= expandStore(*MOI, MI); else if (const auto &MOI = MOA.getAtomicFenceInfo(MI)) - Changed |= expandAtomicFence(MOI.value(), MI); + Changed |= expandAtomicFence(*MOI, MI); else if (const auto &MOI = MOA.getAtomicCmpxchgOrRmwInfo(MI)) - Changed |= expandAtomicCmpxchgOrRmw(MOI.value(), MI); + Changed |= expandAtomicCmpxchgOrRmw(*MOI, MI); } } |