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authorDimitry Andric <dim@FreeBSD.org>2023-02-11 12:38:04 +0000
committerDimitry Andric <dim@FreeBSD.org>2023-02-11 12:38:11 +0000
commite3b557809604d036af6e00c60f012c2025b59a5e (patch)
tree8a11ba2269a3b669601e2fd41145b174008f4da8 /llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
parent08e8dd7b9db7bb4a9de26d44c1cbfd24e869c014 (diff)
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
index aed84437b890..85de3a548411 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
@@ -226,7 +226,7 @@ bool SIOptimizeExecMaskingPreRA::optimizeVcndVcmpPair(MachineBasicBlock &MBB) {
auto DefSegment = SelLI->FindSegmentContaining(SelIdx.getRegSlot());
assert(DefSegment != SelLI->end() &&
"No live interval segment covering definition?");
- for (auto I = DefSegment; I != SelLI->end(); ++I) {
+ for (auto I = DefSegment; I != SelLI->end() && I->start <= AndIdx; ++I) {
SlotIndex Start = I->start < SelIdx.getRegSlot() ?
SelIdx.getRegSlot() : I->start;
SlotIndex End = I->end < AndIdx.getRegSlot() || I->end.isBlock() ?