diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
| commit | cfca06d7963fa0909f90483b42a6d7d194d01e08 (patch) | |
| tree | 209fb2a2d68f8f277793fc8df46c753d31bc853b /llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp | |
| parent | 706b4fc47bbc608932d3b491ae19a3b9cde9497b (diff) | |
Notes
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp | 114 |
1 files changed, 82 insertions, 32 deletions
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp index 207e4232e829..ef010a7ac157 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp @@ -397,6 +397,39 @@ static const char *getRegisterName(unsigned RegNum) { {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"}, {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"}, + {0x2c8c, "SPI_SHADER_USER_DATA_GS_0"}, + {0x2c8d, "SPI_SHADER_USER_DATA_GS_1"}, + {0x2c8e, "SPI_SHADER_USER_DATA_GS_2"}, + {0x2c8f, "SPI_SHADER_USER_DATA_GS_3"}, + {0x2c90, "SPI_SHADER_USER_DATA_GS_4"}, + {0x2c91, "SPI_SHADER_USER_DATA_GS_5"}, + {0x2c92, "SPI_SHADER_USER_DATA_GS_6"}, + {0x2c93, "SPI_SHADER_USER_DATA_GS_7"}, + {0x2c94, "SPI_SHADER_USER_DATA_GS_8"}, + {0x2c95, "SPI_SHADER_USER_DATA_GS_9"}, + {0x2c96, "SPI_SHADER_USER_DATA_GS_10"}, + {0x2c97, "SPI_SHADER_USER_DATA_GS_11"}, + {0x2c98, "SPI_SHADER_USER_DATA_GS_12"}, + {0x2c99, "SPI_SHADER_USER_DATA_GS_13"}, + {0x2c9a, "SPI_SHADER_USER_DATA_GS_14"}, + {0x2c9b, "SPI_SHADER_USER_DATA_GS_15"}, + {0x2c9c, "SPI_SHADER_USER_DATA_GS_16"}, + {0x2c9d, "SPI_SHADER_USER_DATA_GS_17"}, + {0x2c9e, "SPI_SHADER_USER_DATA_GS_18"}, + {0x2c9f, "SPI_SHADER_USER_DATA_GS_19"}, + {0x2ca0, "SPI_SHADER_USER_DATA_GS_20"}, + {0x2ca1, "SPI_SHADER_USER_DATA_GS_21"}, + {0x2ca2, "SPI_SHADER_USER_DATA_GS_22"}, + {0x2ca3, "SPI_SHADER_USER_DATA_GS_23"}, + {0x2ca4, "SPI_SHADER_USER_DATA_GS_24"}, + {0x2ca5, "SPI_SHADER_USER_DATA_GS_25"}, + {0x2ca6, "SPI_SHADER_USER_DATA_GS_26"}, + {0x2ca7, "SPI_SHADER_USER_DATA_GS_27"}, + {0x2ca8, "SPI_SHADER_USER_DATA_GS_28"}, + {0x2ca9, "SPI_SHADER_USER_DATA_GS_29"}, + {0x2caa, "SPI_SHADER_USER_DATA_GS_30"}, + {0x2cab, "SPI_SHADER_USER_DATA_GS_31"}, + {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"}, {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"}, {0x2cce, "SPI_SHADER_USER_DATA_ES_2"}, @@ -491,38 +524,55 @@ static const char *getRegisterName(unsigned RegNum) { {0xa310, "PA_SC_SHADER_CONTROL"}, {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"}, - {0x2d0c, "SPI_SHADER_USER_DATA_LS_0"}, - {0x2d0d, "SPI_SHADER_USER_DATA_LS_1"}, - {0x2d0e, "SPI_SHADER_USER_DATA_LS_2"}, - {0x2d0f, "SPI_SHADER_USER_DATA_LS_3"}, - {0x2d10, "SPI_SHADER_USER_DATA_LS_4"}, - {0x2d11, "SPI_SHADER_USER_DATA_LS_5"}, - {0x2d12, "SPI_SHADER_USER_DATA_LS_6"}, - {0x2d13, "SPI_SHADER_USER_DATA_LS_7"}, - {0x2d14, "SPI_SHADER_USER_DATA_LS_8"}, - {0x2d15, "SPI_SHADER_USER_DATA_LS_9"}, - {0x2d16, "SPI_SHADER_USER_DATA_LS_10"}, - {0x2d17, "SPI_SHADER_USER_DATA_LS_11"}, - {0x2d18, "SPI_SHADER_USER_DATA_LS_12"}, - {0x2d19, "SPI_SHADER_USER_DATA_LS_13"}, - {0x2d1a, "SPI_SHADER_USER_DATA_LS_14"}, - {0x2d1b, "SPI_SHADER_USER_DATA_LS_15"}, - {0x2d1c, "SPI_SHADER_USER_DATA_LS_16"}, - {0x2d1d, "SPI_SHADER_USER_DATA_LS_17"}, - {0x2d1e, "SPI_SHADER_USER_DATA_LS_18"}, - {0x2d1f, "SPI_SHADER_USER_DATA_LS_19"}, - {0x2d20, "SPI_SHADER_USER_DATA_LS_20"}, - {0x2d21, "SPI_SHADER_USER_DATA_LS_21"}, - {0x2d22, "SPI_SHADER_USER_DATA_LS_22"}, - {0x2d23, "SPI_SHADER_USER_DATA_LS_23"}, - {0x2d24, "SPI_SHADER_USER_DATA_LS_24"}, - {0x2d25, "SPI_SHADER_USER_DATA_LS_25"}, - {0x2d26, "SPI_SHADER_USER_DATA_LS_26"}, - {0x2d27, "SPI_SHADER_USER_DATA_LS_27"}, - {0x2d28, "SPI_SHADER_USER_DATA_LS_28"}, - {0x2d29, "SPI_SHADER_USER_DATA_LS_29"}, - {0x2d2a, "SPI_SHADER_USER_DATA_LS_30"}, - {0x2d2b, "SPI_SHADER_USER_DATA_LS_31"}, + {0x2d0c, "SPI_SHADER_USER_DATA_HS_0"}, + {0x2d0d, "SPI_SHADER_USER_DATA_HS_1"}, + {0x2d0e, "SPI_SHADER_USER_DATA_HS_2"}, + {0x2d0f, "SPI_SHADER_USER_DATA_HS_3"}, + {0x2d10, "SPI_SHADER_USER_DATA_HS_4"}, + {0x2d11, "SPI_SHADER_USER_DATA_HS_5"}, + {0x2d12, "SPI_SHADER_USER_DATA_HS_6"}, + {0x2d13, "SPI_SHADER_USER_DATA_HS_7"}, + {0x2d14, "SPI_SHADER_USER_DATA_HS_8"}, + {0x2d15, "SPI_SHADER_USER_DATA_HS_9"}, + {0x2d16, "SPI_SHADER_USER_DATA_HS_10"}, + {0x2d17, "SPI_SHADER_USER_DATA_HS_11"}, + {0x2d18, "SPI_SHADER_USER_DATA_HS_12"}, + {0x2d19, "SPI_SHADER_USER_DATA_HS_13"}, + {0x2d1a, "SPI_SHADER_USER_DATA_HS_14"}, + {0x2d1b, "SPI_SHADER_USER_DATA_HS_15"}, + {0x2d1c, "SPI_SHADER_USER_DATA_HS_16"}, + {0x2d1d, "SPI_SHADER_USER_DATA_HS_17"}, + {0x2d1e, "SPI_SHADER_USER_DATA_HS_18"}, + {0x2d1f, "SPI_SHADER_USER_DATA_HS_19"}, + {0x2d20, "SPI_SHADER_USER_DATA_HS_20"}, + {0x2d21, "SPI_SHADER_USER_DATA_HS_21"}, + {0x2d22, "SPI_SHADER_USER_DATA_HS_22"}, + {0x2d23, "SPI_SHADER_USER_DATA_HS_23"}, + {0x2d24, "SPI_SHADER_USER_DATA_HS_24"}, + {0x2d25, "SPI_SHADER_USER_DATA_HS_25"}, + {0x2d26, "SPI_SHADER_USER_DATA_HS_26"}, + {0x2d27, "SPI_SHADER_USER_DATA_HS_27"}, + {0x2d28, "SPI_SHADER_USER_DATA_HS_28"}, + {0x2d29, "SPI_SHADER_USER_DATA_HS_29"}, + {0x2d2a, "SPI_SHADER_USER_DATA_HS_30"}, + {0x2d2b, "SPI_SHADER_USER_DATA_HS_31"}, + + {0x2d4c, "SPI_SHADER_USER_DATA_LS_0"}, + {0x2d4d, "SPI_SHADER_USER_DATA_LS_1"}, + {0x2d4e, "SPI_SHADER_USER_DATA_LS_2"}, + {0x2d4f, "SPI_SHADER_USER_DATA_LS_3"}, + {0x2d50, "SPI_SHADER_USER_DATA_LS_4"}, + {0x2d51, "SPI_SHADER_USER_DATA_LS_5"}, + {0x2d52, "SPI_SHADER_USER_DATA_LS_6"}, + {0x2d53, "SPI_SHADER_USER_DATA_LS_7"}, + {0x2d54, "SPI_SHADER_USER_DATA_LS_8"}, + {0x2d55, "SPI_SHADER_USER_DATA_LS_9"}, + {0x2d56, "SPI_SHADER_USER_DATA_LS_10"}, + {0x2d57, "SPI_SHADER_USER_DATA_LS_11"}, + {0x2d58, "SPI_SHADER_USER_DATA_LS_12"}, + {0x2d59, "SPI_SHADER_USER_DATA_LS_13"}, + {0x2d5a, "SPI_SHADER_USER_DATA_LS_14"}, + {0x2d5b, "SPI_SHADER_USER_DATA_LS_15"}, {0xa2aa, "IA_MULTI_VGT_PARAM"}, {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"}, |