diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2021-11-19 20:06:13 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2021-11-19 20:06:13 +0000 |
| commit | c0981da47d5696fe36474fcf86b4ce03ae3ff818 (patch) | |
| tree | f42add1021b9f2ac6a69ac7cf6c4499962739a45 /llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp | |
| parent | 344a3780b2e33f6ca763666c380202b18aab72a3 (diff) | |
Diffstat (limited to 'llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp | 33 |
1 files changed, 31 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp b/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp index b7033d0972b9..bb5336931932 100644 --- a/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp +++ b/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp @@ -21,7 +21,7 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Support/TargetRegistry.h" +#include "llvm/MC/TargetRegistry.h" using namespace llvm; @@ -107,6 +107,12 @@ static DecodeStatus DecodeStLImmInstruction(MCInst &, uint64_t, uint64_t, static DecodeStatus DecodeLdRLImmInstruction(MCInst &, uint64_t, uint64_t, const void *); +static DecodeStatus DecodeSOPwithRS12(MCInst &, uint64_t, uint64_t, + const void *); + +static DecodeStatus DecodeSOPwithRU6(MCInst &, uint64_t, uint64_t, + const void *); + static DecodeStatus DecodeCCRU6Instruction(MCInst &, uint64_t, uint64_t, const void *); @@ -304,13 +310,36 @@ static DecodeStatus DecodeCCRU6Instruction(MCInst &Inst, uint64_t Insn, DstB = decodeBField(Insn); DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder); using Field = decltype(Insn); - Field U6Field = fieldFromInstruction(Insn, 6, 11); + Field U6Field = fieldFromInstruction(Insn, 6, 6); Inst.addOperand(MCOperand::createImm(U6Field)); Field CCField = fieldFromInstruction(Insn, 0, 4); Inst.addOperand(MCOperand::createImm(CCField)); return MCDisassembler::Success; } +static DecodeStatus DecodeSOPwithRU6(MCInst &Inst, uint64_t Insn, + uint64_t Address, const void *Decoder) { + unsigned DstB = decodeBField(Insn); + DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder); + using Field = decltype(Insn); + Field U6 = fieldFromInstruction(Insn, 6, 6); + Inst.addOperand(MCOperand::createImm(U6)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeSOPwithRS12(MCInst &Inst, uint64_t Insn, + uint64_t Address, const void *Decoder) { + unsigned DstB = decodeBField(Insn); + DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder); + using Field = decltype(Insn); + Field Lower = fieldFromInstruction(Insn, 6, 6); + Field Upper = fieldFromInstruction(Insn, 0, 5); + Field Sign = fieldFromInstruction(Insn, 5, 1) ? -1 : 1; + Field Result = Sign * ((Upper << 6) + Lower); + Inst.addOperand(MCOperand::createImm(Result)); + return MCDisassembler::Success; +} + DecodeStatus ARCDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, |