vendor/llvm-project/llvmorg-15-init-15358-g53dc0f107877

1 files changed, 26 insertions, 19 deletions

diff --git a/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp b/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
index 57343784237d..e9fecef4ac5b 100644
--- a/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
+++ b/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
@@ -16,7 +16,7 @@
 #include "LanaiCondCode.h"
 #include "LanaiInstrInfo.h"
 #include "TargetInfo/LanaiTargetInfo.h"
-#include "llvm/MC/MCFixedLenDisassembler.h"
+#include "llvm/MC/MCDecoderOps.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/TargetRegistry.h"
@@ -45,26 +45,30 @@ LanaiDisassembler::LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
 // Definition is further down.
 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 
 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder);
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
 
 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder);
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder);
 
 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder);
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder);
 
 static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
-                                 const void *Decoder);
+                                 const MCDisassembler *Decoder);
 
 static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val,
                                            uint64_t Address,
-                                           const void *Decoder);
+                                           const MCDisassembler *Decoder);
 
 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address, const void *Decoder);
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder);
 
 #include "LanaiGenDisassemblerTables.inc"
 
@@ -158,7 +162,7 @@ static const unsigned GPRDecoderTable[] = {
 
 DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                     uint64_t /*Address*/,
-                                    const void * /*Decoder*/) {
+                                    const MCDisassembler * /*Decoder*/) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
@@ -168,7 +172,8 @@ DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
 }
 
 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   // RI memory values encoded using 23 bits:
   //   5 bit register, 16 bit constant
   unsigned Register = (Insn >> 18) & 0x1f;
@@ -180,7 +185,8 @@ static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
 }
 
 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
-                                        uint64_t Address, const void *Decoder) {
+                                        uint64_t Address,
+                                        const MCDisassembler *Decoder) {
   // RR memory values encoded using 20 bits:
   //   5 bit register, 5 bit register, 2 bit PQ, 3 bit ALU operator, 5 bit JJJJJ
   unsigned Register = (Insn >> 15) & 0x1f;
@@ -192,7 +198,8 @@ static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
 }
 
 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address, const void *Decoder) {
+                                    uint64_t Address,
+                                    const MCDisassembler *Decoder) {
   // RI memory values encoded using 17 bits:
   //   5 bit register, 10 bit constant
   unsigned Register = (Insn >> 12) & 0x1f;
@@ -206,14 +213,13 @@ static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
 static bool tryAddingSymbolicOperand(int64_t Value, bool IsBranch,
                                      uint64_t Address, uint64_t Offset,
                                      uint64_t Width, MCInst &MI,
-                                     const void *Decoder) {
-  const MCDisassembler *Dis = static_cast<const MCDisassembler *>(Decoder);
-  return Dis->tryAddingSymbolicOperand(MI, Value, Address, IsBranch, Offset,
-                                       Width);
+                                     const MCDisassembler *Decoder) {
+  return Decoder->tryAddingSymbolicOperand(MI, Value, Address, IsBranch, Offset,
+                                           Width, /*InstSize=*/0);
 }
 
 static DecodeStatus decodeBranch(MCInst &MI, unsigned Insn, uint64_t Address,
-                                 const void *Decoder) {
+                                 const MCDisassembler *Decoder) {
   if (!tryAddingSymbolicOperand(Insn + Address, false, Address, 2, 23, MI,
                                 Decoder))
     MI.addOperand(MCOperand::createImm(Insn));
@@ -221,7 +227,8 @@ static DecodeStatus decodeBranch(MCInst &MI, unsigned Insn, uint64_t Address,
 }
 
 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
-                                   uint64_t Address, const void *Decoder) {
+                                   uint64_t Address,
+                                   const MCDisassembler *Decoder) {
   unsigned Offset = (Insn & 0xffff);
   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));
 
@@ -230,7 +237,7 @@ static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
 
 static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val,
                                            uint64_t Address,
-                                           const void *Decoder) {
+                                           const MCDisassembler *Decoder) {
   if (Val >= LPCC::UNKNOWN)
     return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(Val));